Host controller interface using multiple circular queue, and operating method thereof

Abstract

A host controller interface configured to provide interfacing between a host device and a storage device is disclosed. A host controller interface according to an exemplary embodiment of the technical concept of the present disclosure may include a doorbell register configured to store a head pointer and a tail pointer of at least one queue, an entry buffer configured to store a first command or a first response included in the at least one queue, an arbitrator configured to arbitrate the order of the at least one queue, a first router configured to route the first command so that it can be stored in the entry buffer according to the order, and a second router configured to route the first response so that it can be stored in the doorbell register.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a host controller interface for transmitting commands to a storage device, and more specifically, to a host controller interface having a bitmap-based doorbell structure and capable of utilizing multiple circular queues. Background Technology

[0002] Interfaces such as SATA (Serial ATA), PCIe (Peripheral Component Interconnect Express), SAS (Serial Attached SCSI), eMMC (embedded MMC), and UFS (Universal Flash Storage) are used in storage systems based on storage devices (e.g., Solid State Drives; SSDs). Storage devices are gradually improving, and the amount of data processed simultaneously is also gradually increasing. However, interfaces such as SATA have fundamental limitations because they are not interfaces specialized for storage devices such as SSDs.

[0003] Recently, NVMe (Non-Volatile Memory Express) and UFS were created as part of efforts to develop standardized interfaces applicable to data storage devices. NVMe can provide direct memory access capabilities for storage devices (or non-volatile memories) connected via the PCIe bus, and UFS is a structure that adopts the M-PHY and UniPro of MIPI (Mobile Industry Processor Interface).

[0004] When multiple cores share a single bitmap doorbell, resource overhead occurs, which can degrade the overall system performance. For example, under the UFS standard, if one of the multiple cores accesses the bitmap doorbell, the other cores cannot access it. The problem to be solved

[0005] The problem that the technical concept of the present disclosure aims to solve is to provide a host controller interface having a bitmap-based doorbell structure and capable of utilizing multiple circular queues, and a method of operation thereof. means of solving the problem

[0006] To achieve the above objectives, a host controller interface configured to provide interfacing between a host device and a storage device according to an exemplary embodiment of the present disclosure may include a doorbell register configured to store a head pointer and a tail pointer of at least one queue, an entry buffer configured to store a first command or a first response included in the at least one queue, an arbitrator configured to arbitrate the order of the at least one queue, a first router configured to route the first command so that it can be stored in the entry buffer according to the order, and a second router configured to route the first response so that it can be stored in the doorbell register.

[0007] A storage system according to an exemplary embodiment of the present disclosure may include a host device and a storage device, wherein the host device transmitting a command to the storage device includes a host memory storing at least one queue, at least one core configured to process the at least one queue, and a host controller interface configured to provide interfacing with the host memory, and the storage device provides a response to the host device which is the result of performing a memory operation based on the command, and the host controller interface may include a doorbell register storing a head pointer and a tail pointer for the at least one queue.

[0008] A method of operation of a host controller interface configured to provide interfacing between a host device and a storage device using at least one queue including at least one command according to an exemplary embodiment of the present disclosure may include the steps of: mediating the order of a plurality of commands including a first command included in a first queue; storing the first command in an entry buffer; updating a first head pointer of the first queue; storing a second command in the entry buffer; updating a second head pointer of a second queue including the second command; and providing the first command and the second command sequentially to the storage device. Effects of the invention

[0009] The host controller interface according to the technical concept of the present disclosure can utilize multiple circular queues, thereby resolving the overhead caused by the problem of shared resource occupation among multiple cores and maximizing performance.

[0010] In addition, the host controller interface according to the technical concept of the present disclosure, when using multiple circular queues, maintains the bitmap-based doorbell structure applied to UFS while additionally using an arbitrator and a router, thereby minimizing structural changes to the interface between HCI and storage and maintaining compatibility with conventional devices.

[0011] In addition, according to the host controller interface according to the technical concept of the present disclosure, the overhead caused by multiple cores occupying resources can be reduced and data processing performance can be improved. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram showing a storage system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing an example of an implementation of the host device illustrated in FIG. 1. FIG. 3 is a block diagram showing an example of an implementation of the storage controller illustrated in FIG. 1. Figure 4 is a block diagram showing an example of an implementation of a storage system with a UFS interface applied. FIG. 5 is a drawing illustrating the operation of a storage system according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart illustrating a method of operation of a host device according to an exemplary embodiment of the present disclosure. FIG. 7 is a block diagram illustrating a storage system in which a command is written according to an exemplary embodiment of the present disclosure. FIG. 8 is a block diagram illustrating a storage system in which a response is written according to an exemplary embodiment of the present disclosure. FIG. 9 is a diagram illustrating the process of a command being entered into a circular queue according to an exemplary embodiment of the present disclosure. FIG. 10 is a flowchart illustrating a method of operation of a storage system according to an exemplary embodiment of the present disclosure. FIGS. 11 and FIGS. 12 are block diagrams illustrating examples of various information stored in registers within a host memory and a host controller. Figure 13 is a diagram showing an example of a data read operation and packet implementation according to the UFS interface. FIGS. 14a and FIGS. 14b are drawings showing the structure of a packet according to an exemplary embodiment of the present disclosure. FIG. 15 is a drawing illustrating a system to which a storage device according to an exemplary embodiment of the present disclosure is applied. FIG. 16 is a drawing for illustrating a UFS system according to an exemplary embodiment of the present disclosure. FIGS. 17a to 17c are drawings for explaining the form factor of a UFS card according to an exemplary embodiment of the present disclosure. FIG. 18a is a block diagram showing a host-storage system according to an exemplary embodiment of the present disclosure, and FIG. 18b to 18e are detailed block diagrams of the configurations of FIG. 18a. FIG. 19 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 20 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 21 is a block diagram showing a memory device according to an exemplary embodiment of the present disclosure. FIG. 22 is a drawing for explaining a 3D V-NAND structure that can be applied to a UFS device according to an exemplary embodiment of the present disclosure. FIG. 23 is a cross-sectional view showing a memory device according to an exemplary embodiment of the present disclosure. FIG. 24 is a drawing showing a data center to which a host storage system according to an exemplary embodiment of the present disclosure is applied. Specific details for implementing the invention

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0014] FIG. 1 is a block diagram showing a storage system (10) according to an exemplary embodiment of the present disclosure.

[0015] The storage system (10) may include a host device (100) and a storage device (200).

[0016] Many standard specifications are being developed or are currently under development to ensure seamless data transfer between a host device (100) and a storage device (200). As one of these standard specifications, Universal Flash Storage (UFS) was developed by JEDEC (Joint Electron Device Engineering Council) for flash memory-based storage in mobile devices such as smartphones and tablet computers. UFS adopts a command protocol and SCSI (Small Computer System Interface) architecture model that supports multiple commands with the characteristics of a command queue, thereby enabling a multi-threaded programming paradigm.

[0017] Another standard developed by JEDEC is the eMMC (embedded MultiMediaCard) standard. eMMC can provide a simplified application interface design, a small package size, and low power consumption. eMMC flash memory-based storage devices are currently one of the major forms of storage in mobile devices.

[0018] A storage system (10) according to the technical concept of the present disclosure may use standard specifications for flash memory-based storage devices such as UFS and eMMC. However, the present embodiment is not limited thereto.

[0019] The storage system (10) may be implemented as a personal computer (PC), including, for example, a desktop computer and a laptop computer, a data server, a network-attached storage (NAS), an Internet of Things (IoT) device, a workstation, a server, an electric vehicle, or a portable electronic device. The portable electronic device may include a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book and / or a wearable device.

[0020] The storage system (10) can store or retrieve data in the storage device (200) according to a command (CMD) of the host device (100). In an exemplary embodiment, the host device (100) can provide data to be written to the storage device (200) and can read data by receiving a response (RESP) from the storage device (200). According to an exemplary embodiment, the host device (100) can issue a command (CMD) and transmit it to the storage device (200), and the storage device (200) can read, erase, or write data according to the command (CMD), and can generate a response (RESP) as a result and provide it to the host device (100).

[0021] A command (CMD) can be managed by being included in a command packet (PACKET_C), and a response (RESP) can be managed by being included in a response packet (PACKET_R). The configuration of the packets is described in detail with reference to FIGS. 14a and FIGS. 14b.

[0022] The host device (100) may include a host controller (110) and a host memory (130).

[0023] A host device (100) may provide various services to a user of the host device (100) according to the operations of one or more electronic circuits, chips, and devices. According to an exemplary embodiment, the host device (100) may perform various operations to process commands received from a user of the host device (100) and may provide the results of the operations to the user of the host device (100). The host device (100) according to an exemplary embodiment may include an operating system, an application, etc. The host device (100) according to an exemplary embodiment of the present disclosure may include a UFS host control driver for supporting the Universal Flash Storage (UFS) protocol. However, the present disclosure is not limited thereto, and the host device (100) may include a driver for supporting the embedded Multi-Media Card (eMMC) protocol or the Non-Volatile Memory Express (NVMe) protocol.

[0024] The host controller (110) can control the overall operation of the host device (100), more specifically, the operation of other components that make up the host device (100). In an exemplary embodiment, the host controller (110) may be implemented as a general-purpose processor, a dedicated processor, or an application processor. In addition, the host controller (110) may be implemented as a computational processor (e.g., a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), an AP (Application Processor), etc.) including a dedicated logic circuit (e.g., a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuits (ASIC), etc.), but is not limited thereto.

[0025] The host controller (110) can execute various software loaded into the host memory (130). For example, the host controller (110) can execute an operating system (OS) and applications (Application Program).

[0026] The host controller (110) can generate a command (CMD) in response to a user's request and determine whether to send the command (CMD) to the storage device (200). Additionally, the host controller (110) can receive a response (RESP). In an exemplary embodiment, the host controller (110) can write the command (CMD) and / or response (RESP) to a queue, which is a processing queue, or remove it from the queue.

[0027] The host controller (110) may include one or more cores and may further include other Intellectual Properties (IPs) for controlling memory and / or storage devices (200). According to an exemplary embodiment, the core may execute a queue, which is a processing queue for commands (CMDs) and responses (RESPs) processed by the host device (100). According to an exemplary embodiment, the host controller (110) may further include an accelerator, which is a dedicated circuit for high-speed data processing such as artificial intelligence (AI) data processing, and the accelerator may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the host controller (110).

[0028] The host controller (110) may include a host controller interface (hereinafter HCI), and the host controller interface may manage operations to store data (e.g., write data) of the host memory (130) in the non-volatile memory (230) or to store data (e.g., read data) of the non-volatile memory (230) in the host memory (130). Additionally, the storage controller (210) may include a device controller interface (not shown) for interfacing with the host controller (110).

[0029] A submission queue (SQ) may refer to a column waiting to be processed for various types of events, including requests and commands (CMDs) from a host device (100). Commands (CMDs) stored in the submission queue (SQ) may be transmitted to a storage device (200) by being fetched by a host controller (110). A completion queue (CQ) may refer to a column for processing various types of events, including requests and responses (RESPs) from a storage device (200). Responses (RESPs) stored in the completion queue (CQ) may be fetched by a host controller (110) to direct the updating of metadata to be processed by the host after a memory operation (e.g., writing, reading, or erasing data) is completed. The submission queue (SQ) and the completion queue (CQ) may be created in the host memory (130) of the host device (100). In the present disclosure, for convenience of explanation, the submission queue and the completion queue are exemplified as being implemented as circular queues, but are not limited thereto.

[0030] According to an exemplary embodiment of the present disclosure, a host controller (110) may include a doorbell register. The doorbell register is a register allocated to manage a submission queue (SQ) and a completion queue (CQ). For example, the host controller (110) may perform interface operations with the submission queue (SQ) and the completion queue (CQ) with the host memory (130) by accessing the submission queue (SQ) and the completion queue (CQ) through the doorbell register. According to an exemplary embodiment, the doorbell register may be included in the host controller interface.

[0031] A doorbell register according to an exemplary embodiment of the present disclosure may manage or control a queue pair generated by a host device (100). A doorbell register may correspond to a single queue pair. According to an exemplary embodiment, a head pointer (HP) and a tail pointer (TP) of a doorbell register queue may be stored. For example, a doorbell register may store a tail pointer (TP) pointing to the tail of a submission queue and a head pointer (HP) pointing to the head of a completion queue.

[0032] In the present disclosure, a doorbell register associated with a submission queue (SQ) is referred to as the SQ doorbell register, and a doorbell register associated with a completion queue (CQ) is referred to as the CQ doorbell register. Additionally, a data structure in which a doorbell corresponding to a single queue pair is represented as a bitmap, which is a set of 1-bit data spaces, is referred to as a bitmap doorbell. According to an exemplary embodiment of the present disclosure, the SQ doorbell register, the CQ doorbell register, and the bitmap doorbell, etc., may be managed by a host controller interface. The host controller interface is described in more detail in FIG. 5.

[0033] The host memory (130) can be used as main memory or cache memory. Additionally, the host memory (130) can be used as driving memory for running software, applications, or firmware. Programs or data to be processed by the host controller (110) can be loaded into the host memory (130). For example, the host memory (130) can be loaded with a file system, applications, and device drivers. The file system can provide logical addresses to the storage device (200) according to commands (e.g., write commands or read commands). The file system can be used according to a specific operating system running on the host device (200). The file system can be implemented through software, applications, or firmware. For example, the host device (200) can run Windows, Linux, Unix, etc.

[0034] The host memory (130) can load a submission queue (SQ) and a completion queue (CQ) used for interfacing operations between the host device (100) and the storage device (200). The submission queue (SQ) can store a command (CMD) to be provided to the storage device (200), and the completion queue (CQ) can store a response (RESP), which is completion information for an operation completed in the storage device (200).

[0035] According to an exemplary embodiment of the present disclosure, the submission queue (SQ) and completion queue (CQ) loaded by the host memory (130) can be referenced by the host controller (110). For example, the host controller (110) can write a command (CMD) or a response (RESP) to the submission queue (SQ) by referencing the tail pointer (TP), and can read a command (CMD) or a response (RESP) from the completion queue (CQ) by referencing the head pointer (HP). For example, after a command (CMD) or a response (RESP) is written to the submission queue (SQ) or the completion queue (CQ), the host controller (110) can increase the tail (TAIL) value to indicate the next empty space. The operation of writing or reading a command (CMD) or a response (RESP) to the queue is described in more detail in FIG. 9.

[0036] According to exemplary embodiments, the host controller (110) and the host memory (130) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (110) and the host memory (130) may be integrated on the same semiconductor chip. As an example, the host controller (110) may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (130) may be an embedded memory provided within the application processor, or a memory device or memory module placed outside the application processor.

[0037] The host device (100) may further include various devices related to the operation of the storage device (200). As an example, software modules (not shown), such as a host application and a device driver, may be further provided, and said software modules may be loaded into the host memory (130) and executed by a processor (not shown).

[0038] The storage device (200) may include a storage controller (210) and a non-volatile memory device (NVM) (230). The non-volatile memory (230) may include a non-volatile memory core (NVM Core).

[0039] The storage device (200) may include storage media for storing data upon request from the host device (100). As an example, the storage device (200) may include one or more solid state drives (SSDs). If the storage device (200) includes solid state drives, the storage device (200) may include a plurality of flash memory chips (e.g., NAND memory chips) for storing data non-volatilely.

[0040] According to an exemplary embodiment, the storage device (200) may correspond to a flash memory device comprising one or more flash memory chips. The flash memory device may be a non-volatile data storage medium in which data can be electrically written and erased. In an exemplary embodiment, the storage device (200) may be an embedded memory built into the storage system (10). For example, the storage device (200) may be an EMMC or an embedded UFS memory device. In an exemplary embodiment, the storage device (200) may be an external memory that is detachable from the storage system (10). For example, the storage device (200) may include various flash memory-based storage devices, including UFS memory cards, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital) or Memory Stick, Solid State Drive (SSD) and Universal Serial Bus (USB) flash drives.

[0041] When the storage device (200) includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. The 3D memory array is formed monolithically at at least one physical level of a circuit formed on or within the substrate as an array of memory cells having an active region disposed on a silicon substrate, or as a circuit related to the operation of said memory cells. The term "monolithic" means that the layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array.

[0042] In an exemplary embodiment, the 3D memory array includes vertical NAND strings arranged vertically such that at least one memory cell is positioned above another memory cell. The at least one memory cell may include a charge trap layer.

[0043] U.S. Patent Publication No. 7,679,133, No. 8,553,466, No. 8,654,587, No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 describe suitable configurations for a 3D memory array in which the 3D memory array is composed of multiple levels and word lines and / or bit lines are shared between the levels, and are incorporated herein by reference.

[0044] As another example, the storage device (200) may include various other types of non-volatile memories. For example, the storage device (200) may include Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, and various other types of memory.

[0045] The storage controller (210) can control the overall operations of the storage device (200). For example, the storage controller (210) can schedule the operations of the non-volatile memory (230) or encode and decode signals / data processed in the storage device (200). In an exemplary embodiment, the storage controller (210) can control the non-volatile memory (230) so that the non-volatile memory (230) writes, reads, or erases data.

[0046] The non-volatile memory (230) may include storage media for storing data upon request from the host device (100). In an exemplary embodiment, the non-volatile memory (230) may include at least one flash memory chip for non-volatile storage of data, as previously described, and may include a NAND or VNAND memory array.

[0047] The host device (100) and the storage device (200) can communicate with each other through various types of interfaces. As an example, the host device (100) and the storage device (200) can be connected through standard interfaces such as UFS (universal flash storage), SATA (serial ATA), SCSI (small computer small interface), SAS (serial attached SCSI), eMMC (embedded Multi Media Card), etc. The host device (100) and the storage device (200) can each generate and transmit packets according to the protocol of the interface adopted. In the example of FIG. 1, a command packet (PACKET_C) generated by the host device (100) and transmitted to the storage device (200), and a response packet (PACKET_R) generated by the storage device (200) and transmitted to the host device (100) are exemplified.

[0048] According to the technical concept of the present disclosure, the host device (100) can resolve the problem of occupying computing resources of the host device (100) and maximize performance by directly controlling the SQ doorbell register, CQ doorbell register, bitmap doorbell, and the arbitration and pathing of SQ and CQ.

[0049] FIG. 2 is a block diagram showing an example of an implementation of a host device (100) illustrated in FIG. 1. In the example of FIG. 2, an application processor (AP) including a host controller (110) is illustrated. Although the host device (100) is described below using an application processor (AP), it should be understood that the technical concept of the present disclosure is not limited to implementations using an application processor (AP) and can be applied to various host devices (100) capable of providing host-slave functions.

[0050] Referring to FIG. 2 together with FIG. 1, the host device (100) includes an application processor (AP) and a host memory (130), and the application processor (AP) may include one or more modules as Intellectual Property (IP). In an exemplary embodiment, the application processor (AP) may include a host controller (110), at least one core (120), a host memory controller (140), a modem (150), an embedded memory (160), a camera interface (170), and a display interface (170). The host controller (110), at least one core (120), the host memory controller (140), the modem (150), the embedded memory (160), the camera interface (170), and the display interface (170) may transmit and receive signals to and from each other via an internal bus. The host controller (110) may include a register (111) and a host controller interface (HCI) (190).

[0051] In FIG. 2, the host memory (130) is depicted as corresponding to memory outside the application processor (AP), but the embodiments of the present disclosure are not limited thereto. For example, an embedded memory (160) inside the application processor (AP) may be used as the host memory (130) in the aforementioned embodiment. Meanwhile, the configurations shown in FIG. 2 are merely one embodiment, and the application processor (AP) may include other configurations in addition to those shown in FIG. 2, or some of the configurations shown in FIG. 2 may not be provided in the application processor (AP).

[0052] At least one core (120) can control the overall operation of the application processor (AP). As an example, software (e.g., an application processor and a device driver) for managing data write / read operations, etc. for a storage system (10) is loaded into the host memory (130) or embedded memory (160), and the core (120) can manage data write / read operations, etc. by executing the software. The host memory (130) may be implemented as volatile memory or non-volatile memory, and according to one embodiment, the host memory (130) may include volatile memory such as dynamic random access memory (DRAM) and / or static random access memory (SRAM).

[0053] At least one core (120) may be a homogeneous multi-core processor or a heterogeneous multi-core processor.

[0054] According to an exemplary embodiment of the present disclosure, if at least one core (120) includes a plurality of cores, different cores can perform tasks, which are processing units of work, by running different software. For example, a first core can perform a first task, and a second core, which is of the same type or different from the first core, can perform a second task. The plurality of cores may each have a dedicated queue. For example, different tasks can be performed in parallel by the first core using a first submission queue and a first completion queue, and the second core using a second submission queue and a second completion queue, respectively.

[0055] According to an exemplary embodiment, the application processor (AP) can perform camera control operations, display control operations, and modem operations. As the modem (150) is included in the application processor (AP), the application processor (AP) may be referred to as ModAP.

[0056] The host controller (110) can transmit and receive a packet (PACKET) including a command (CMD) or a response (RESP) with the storage device (200) according to the above-described embodiment. The host controller (110) may include a register (111) that stores one or more transmission requests.

[0057] According to an exemplary embodiment, transfer requests related to writing and / or reading to a storage device may be stored in a register (111) based on the control of the core (120). Additionally, various information for generating packets corresponding to the transfer requests may be stored in the host memory (130) based on the control of the core (120), and as an example, table information including information regarding the type of packet and an address may be stored in the host memory (130). Additionally, in the case of a data write request, the write data may be stored in a plurality of data buffers of the host memory (130) based on the control of the core (120). The host controller (110) may check the transfer requests stored in the internal register (111) and interface with the storage device based thereon.

[0058] As in the above-described embodiment, the host controller (110) receives a response packet (PACKET_R) containing a response (RESP) from a storage device (Fig. 1, 200), parses the response (RESP) from the received packet (PACKET), and can determine whether to process the memory operation according to the parsed response (RESP).

[0059] The host controller interface (190) can connect the host device (100) to the storage device (200) by converting the format of data such as commands (e.g., read commands, write commands, etc.) corresponding to various access requests issued by the host device (100), logical addresses, and data, or by converting the format of the exchanged commands. The protocols applied to the host controller interface (190) may include, in addition to the aforementioned UFS and eMMC, USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCIe (Personal Component Interconnect Express), ATA (Advanced Technology Attachment), PATA (Parallel ATA), SATA (Serial ATA), and SAS (Serial Attached SCSI). However, they are not limited to these, and various standard specifications that support interfacing between different devices may be applied.

[0060] According to an exemplary embodiment of the present disclosure, the host controller interface (190) may include an SQ doorbell register, an SQ arbitrator, a bitmap doorbell router, a bitmap doorbell entry, a CQ router, and a CQ doorbell register. The detailed configuration included in the host controller interface (190) is described in more detail in FIG. 5.

[0061] FIG. 3 is a block diagram showing an example of an implementation of the storage controller (210) illustrated in FIG. 1.

[0062] Referring to FIGS. 1 and 3, the storage controller (210) may include a host interface (211), a central processing unit (CPU) (212) as a processor, and a memory interface (216). Additionally, the storage controller (210) may further include a Flash Translation Layer (FTL) (213), a packet manager (214), and a buffer manager (215). The storage controller (210) may further include a working memory (not shown) on which the Flash Translation Layer (213) is loaded. Data writing and reading operations for the memory core may be controlled by the central processing unit (212) executing the Flash Translation Layer (213).

[0063] The host interface (211) can transmit and receive packets with the host device (100), and according to the above-described embodiment, the packet transmitted and received by the host interface (211) may include a buffer address indicating the location of a data buffer in a buffer area within the host device (100). Additionally, the memory interface (216) can perform operations to write or read data by interfacing with a memory core.

[0064] The packet manager (214) can generate a packet according to the protocol of the interface agreed upon with the host device (100) or parse various information from the received packet. Additionally, the buffer manager (215) can manage the operation of storing various information parsed from the packet in a buffer, and as an example, can manage the operation of storing a command (CMD) or response (RESP) parsed from the packet.

[0065] The buffer manager (215) can manage the operation of storing data parsed from a packet in a buffer, and can manage the operation of storing data read from a memory core in a buffer. According to one embodiment, the buffer manager (215) may be a buffer memory (215) provided within a storage controller (210). According to one embodiment, the buffer manager (215) may manage a buffer provided outside the storage controller (210).

[0066] For example, during a data write operation, a write command (CMD) and a corresponding first buffer address may be parsed from a packet (PACKET) received from a host device (100), and the first buffer address may be stored in a buffer of a storage device (200). The storage device (200) may generate a packet (PACKET) containing a response (RESP) requesting the transmission of write data in units of a predetermined size as a response to the write command. At this time, the first buffer address corresponding to the write command may be included in the packet (PACKET), and additionally, the host device (100) may refer to the response (RESP) and the first buffer address included in the packet (PACKET) to transmit the write data stored in the data buffer at the location indicated by the first buffer address to the storage device (200).

[0067] Similarly, taking a data read operation as an example, a read command (CMD) and a corresponding second buffer address are parsed from a packet (PACKET) received from a host device (100), and the second buffer address can be stored in a buffer of a storage device (200). The storage device (200) generates a packet (PACKET) containing read data in response to the read command (CMD), and the second buffer address corresponding to the read command can be included in the packet (PACKET) along with a response (RESP). Additionally, the host device (100) can store the read data in a data buffer at a location indicated by the second buffer address by referring to the response (RESP) and the second buffer address included in the packet (PACKET).

[0068] The host interface (211), central processing unit (212), flash conversion layer (213), packet manager (214), buffer manager (215), and memory interface (216) in FIG. 3 are described again in FIG. 18a.

[0069] FIG. 4 is a block diagram showing an example of an implementation of a storage system (20) with a UFS interface applied. The storage system (10) of FIG. 1 can be applied to the storage system (20) of FIG. 4.

[0070] Referring to FIG. 4 together with FIG. 1, the UFS host and the UFS storage device of the storage system (20) can communicate according to the UFS interface, and the UFS host may include, as its components, a host memory (21), a software module (23), and a UFS host controller (25) corresponding to a hardware module. Since the host memory (21) can provide functions similar to the host memory (130) described in FIG. 1 and FIG. 2, a redundant description is omitted. In FIG. 4, a host device (100 in FIG. 1) that interfaces by adopting the UFS standard is abbreviated as the UFS host, and a storage device (200 in FIG. 1) that interfaces by adopting the UFS standard is abbreviated as the UFS device.

[0071] The software module (23) may include software (e.g., an application) and a UFS host controller driver. The software may be various applications running on the UFS host, and the UFS host controller driver is intended to manage the operation of peripheral devices connected to and used on the UFS host, and data management operations such as writing and reading data to and from storage devices may be performed by executing the UFS host controller driver. The application software and the UFS host controller driver may be loaded into the host memory (21) or loaded into another operational memory within the UFS host and executed by the processor.

[0072] The UFS host controller (25) may be an example of an implementation of the host controller (110) of FIG. 2. The UFS host controller (25) may include a UFS host controller interface (UFS HCI), a UTP protocol engine, and a UFS interconnect layer (UFS Interconnect Layer (UIC)).

[0073] The UFS Host Controller Interface (UFS HCI) can receive requests generated through the UFS Host Controller Driver and forward them to the UTP Protocol Engine, or provide data access results received from the UTP Protocol Engine to the UFS Host Controller Driver.

[0074] The UTP protocol engine can provide services for the upper layer (or application layer), and, for example, can generate packets or release packets to parse the information inside them.

[0075] The UFS interconnect layer can communicate with the UFS storage device (27), and as an example, the UFS interconnect layer may include a link layer and a physical layer (PHY layer). The link layer may be MIPI (Mobile Industry Processor Interface) UniPro, and the physical layer (PHY layer) may be MIPI M-PHY. Additionally, depending on the UFS interface, the UFS host may provide a reference clock (Ref Clock) and a reset signal (Reset) to the UFS storage device (27).

[0076] Meanwhile, the UFS storage device (27) may include a storage controller and a memory core. According to one embodiment, the storage controller in FIG. 4 may include a UFS interconnect layer, a UTP protocol engine, and a UFS storage device interface. Additionally, the memory core may be a core (NVM Core) that includes non-volatile memory.

[0077] In a structure where a UFS host controller (25) and a UFS storage device (27) communicate, data transmission and reception in response to a request from a UFS host controller driver can be performed through a UFS host controller interface. For example, during a data write operation, the write data is stored in a data buffer of the host memory (21) by a software module (23), the UFS host controller interface accesses the data buffer of the host memory (21), and the accessed write data can be transmitted to the UFS storage device (27). A command (CMD) for the data transmission and reception operation can be stored in a queue. In an exemplary embodiment, when a circular queue is used, the head pointer (HP) and tail pointer (TP) in which the command is stored can be stored in the host memory (21). For example, the head pointer (HP) and tail pointer (TP) can be stored in the doorbell register of the host memory (21).

[0078] According to an exemplary embodiment of the present disclosure, a command packet (PACKET_C) transmitted by a UFS host to a UFS storage device (27) and / or a response packet (PACKET_R) transmitted by a storage device (200) to a host device (100) may include a buffer address indicating the location of a data buffer within the host memory (21). The buffer address may correspond to a physical address indicating the location of the data buffer. As an example, a table information (e.g., a Physical Region Description Table (PRDT)) containing buffer addresses may be stored in a region of the host memory (21), and the UTP protocol engine of the UFS host may identify the buffer address through the PRDT and generate a command packet (PACKET_C) containing the identified buffer address. Additionally, the UTP protocol engine of the storage device (200) can generate a response packet (PACKET_R) containing a buffer address that is stored and managed inside the storage device (200).

[0079] Additionally, the UFS host controller (25) and the UFS storage device (27) are connected in a port-mapped I / O manner, and write and read operations can be processed in a multi-task manner. Accordingly, the UFS storage device (27) can store and manage multiple commands parsed from multiple packets and corresponding buffer addresses.

[0080] As the UFS interface is applied, various types of packets may be defined, and embodiments of the present disclosure may be applied to at least some of the various types of packets.

[0081] In an exemplary embodiment, packets according to the UFS interface may be defined as UFS Protocol information units (UPIUs), and as types thereof, packets such as Command UPIUs for write and read requests, Response UPIUs, Data_In UPIUs containing read data, Data_Out UPIUs containing write data, Task Management Request UPIUs (TM Request UPIUs), and Data Transfer Request UPIUs (Ready To Transfer (RTT) UPIUs) may be defined.

[0082] Additionally, according to an exemplary embodiment of the present disclosure, the aforementioned buffer address may be included in at least some types of packets among the packets defined in the UFS interface. For example, the aforementioned buffer address may be included in a packet requesting access to a data buffer of the host memory (21). According to the technical concept of the present disclosure, among the packets communicated between the host device (100) and the storage device (200), the command packet (PACKET_C) may include a command (CMD), a submission queue ID (SQ_ID), and a completion queue ID (CQ_ID), and the response packet (PACKET_R) may include a response (RESP), a submission queue ID (SQ_ID), and a completion queue ID (CQ_ID). The configuration of each packet is described with reference to FIG. 14a and FIG. 14b.

[0083] Hereinafter, specific operational examples of an interface between a host and a storage device according to embodiments of the present disclosure are described. In the following embodiments, a host and a storage device employing a UFS interface will be exemplified; however, as previously mentioned, the embodiments of the present disclosure may be applied to various other types of interfaces in addition to the UFS interface.

[0084] FIG. 5 is a drawing illustrating the operation of a storage system (10) according to an exemplary embodiment of the present disclosure. FIG. 1 and FIG. 2 are referenced together.

[0085] The host device (100) may include multiple processors or multiple cores (120) in a single processor. For convenience of explanation, it is assumed that one or more processors include multiple cores (120). Additionally, it is assumed that the UFS standard is applied for interfacing between the host device (100) and the storage device (200).

[0086] At least one core (120) can perform an interfacing operation with a storage device (200) based on at least one submission queue (SQ) and at least one completion queue (CQ). The interface operation can be performed in units of queue pairs consisting of a submission queue (SQ) for inputting a requested command (CMD) and a completion queue (CQ) for writing the processing result of the command.

[0087] According to an exemplary embodiment of the present disclosure, at least one core (120) can process memory operations using a submission queue (SQ) and a completion queue (CQ). Additionally, the submission queue (SQ) can store processing addresses of a command (CMD) or response (RESP) in the submission queue head pointer (SHP) and the submission queue tail pointer (STP), and the completion queue (CQ) can store processing addresses of a command (CMD) or response (RESP) in the completion queue head pointer (CHP) and the completion queue tail pointer (CTP).

[0088] The host controller interface (190) may include an SQ doorbell register (191), an SQ arbitrator (192), a bitmap doorbell router (193), a bitmap doorbell register (194), an entry buffer (195), a CQ router (196), and a CQ doorbell register (197).

[0089] The SQ doorbell register (191) may be a pointer storage space that stores the order or location of the submission queue (SQ). The SQ doorbell register (191) may store a pointer indicating the tail or the head. According to an exemplary embodiment, the SQ doorbell register (191) may include a register indicating the base address of the submission queue (SQ) entry space and a register indicating the size of the submission queue (SQ) entry. According to an exemplary embodiment, the SQ doorbell register (191) may store a submission queue head pointer (SHP) and a submission queue tail pointer (STP).

[0090] The address (SQ ENTRY ADDR) where an entry of the submission queue (SQ) is stored on the host controller interface (190) can be calculated as in Equation 1.

[0091] [Mathematical Formula 1]

[0092]

[0093] That is, the submission queue entry address (SQ ENTRY ADDR) may be the location obtained by adding the size of the submission queue entry by multiplying the submission queue head pointer (SHP) by the submission queue entry size to the submission queue entry base address (SQ ENTRY BASE ADDR).

[0094] Pointers stored in the SQ doorbell register (191) may be updated for each doorbell notification that occurs according to the input of a command (CMD) or the input / output of data. According to an exemplary embodiment of the present disclosure, the core (120) may write a command (CMD) to the submission queue (SQ). After the command (CMD) is written to the submission queue (SQ), the submission queue tail pointer (STP) may be changed. The command (CMD) may be transmitted to the storage device (200) sequentially or all at once by being fetched by the core (120). For example, the core (120) may fetch the submission queue (SQ) and transmit the command (CMD) stored in the submission queue to the storage device (200). After a command (CMD) written in the submission queue (SQ) is transmitted to the host controller interface (190), the submission queue head pointer (SHP) may be changed.

[0095] Based on the submission queue head pointer (SHP) and submission queue tail pointer (STP) stored in the SQ doorbell register (191), a command (CMD) written to the submission queue can be transmitted to the SQ arbitrator (192). Since the submission queue (SQ) can be utilized in host memory (Fig. 1, 130), it can be understood that a command or signal is provided from the SQ doorbell register (191) in which the head pointer (SHP) or tail pointer (STP) of the submission queue (SQ) is stored. According to an exemplary embodiment of the present disclosure, since the core (120) may be multiple, there may be multiple submission queues (SQ), and the SQ arbitrator (192) may receive multiple submission queues (SQ).

[0096] The SQ arbitrator (192) can mediate the processing order according to changes in the submission queue (SQ) by selecting one of the multiple submission queues (SQ) according to a criterion. For example, the SQ arbitrator (192) can determine the order of commands (CMD) to be processed among the multiple submission queues (SQ), and each of the multiple submission queues (SQ) can execute commands stored in a circular queue in a First In, First Out manner according to the determined order. In addition, as a method for the SQ arbitrator (192) to select one of the submission queues, various algorithms used for non-preemptive scheduling or preemptive scheduling based on the timing of scheduling application, static scheduling based on whether the priority of scheduling changes, and dynamic scheduling may be used. For example, the SQ arbiter (192) may apply a round robin method in which processing times between submission queues are uniform by selecting submission queues sequentially (or cyclically), a weighted round robin method in which processing times between submission queues are non-uniformly allocated by weighting relatively important submission queues and processing queues in order of increasing weight, and a fixed priority method in which fixed priorities are assigned to submission queues as part of static scheduling, but is not limited to the methods described above.

[0097] The SQ arbitrator (192) can arbitrate the order of multiple submission queues (SQ) by comparing the differences between multiple submission queues (SQ). According to an exemplary embodiment of the present disclosure, the SQ arbitrator (192) can compare the tail and the head of a submission queue (SQ). The SQ arbitrator (192) can refer to the SQ head pointer (SHP) and SQ tail pointer (STP) stored in the SQ doorbell register (191) to obtain submission queue (SQ) information.

[0098] An SQ arbitrator (192) according to an exemplary embodiment of the present disclosure can refer to the head and tail of a submission queue (SQ) processed by at least one core (120) by accessing an SQ doorbell register (191) existing within a host controller interface (190), and can arbitrate to process submission queues (SQ) that lack space first.

[0099] According to an exemplary embodiment of the present disclosure, the SQ arbitrator (192) can arbitrate the order of submission queues (SQ) so that they are processed starting from the submission queue (SQ) that has a flag attached requiring priority processing.

[0100] According to an exemplary embodiment of the present disclosure, the SQ arbitrator (192) can determine a selected submission queue (SQ) among a plurality of submission queues, or a submission queue (SQ) that has priority as a result of comparison. The SQ arbitrator (192) can transmit a command (CMD) written in the determined submission queue (SQ) to a bitmap doorbell router (193).

[0101] The bitmap doorbell router (193) can specify (i.e., path) a space where a command (CMD) is to be stored in the entry buffer (195). According to an exemplary embodiment of the present disclosure, the bitmap doorbell router (193) can search a bitmap doorbell register (194) containing information about the occupied space and idle space of the entry buffer (195), and path or provide address information so that a command (CMD) can be written to the idle space. According to an exemplary embodiment, the bitmap doorbell router (193) can specify a space where a command selected from the SQ arbitrator (192) is to be stored in the entry buffer (195).

[0102] The bitmap doorbell register (194) may be a bit storage space capable of representing the state of the storage space of the entry buffer (195). The bitmap doorbell is a data structure represented as a bitmap, which is a set of 1-bit data spaces. Since the bitmap doorbell register (194) represents whether the data space is occupied by bits "0" and "1", the bitmap doorbell router (193) can write a selected command (CMD) (or action) to an idle space where no data is stored by searching for bit "0".

[0103] In an exemplary embodiment, when a command (CMD) or response (RESP) is written to an idle space of the bitmap doorbell register (194), the bitmap for that space may be changed to bit "1". In an exemplary embodiment, when a command (CMD) or response (RESP) written to an occupied space of the bitmap doorbell register (194) is processed, the bitmap for that space may be changed to bit "0".

[0104] The entry buffer (195) may include submission queue (SQ) and completion queue (CQ) entries to be exchanged with the storage device (Fig. 1, 200). In addition to the data storage space indicating whether data is occupied, the entry buffer (195) may further include a buffer for storing other information required for data transmission (UTRD (UTP Transfer Request Descriptor), PRDT, submission queue ID (SQ_ID), completion queue ID (CQ_ID)).

[0105] According to an exemplary embodiment, the entry buffer (195) may provide to the storage controller (Fig. 1, 210) a submission queue ID (SQ_ID) indicating which submission queue the transmitted command (CMD) is written to, and a completion queue ID (CQ_ID) indicating which completion queue the transmitted command (CMD) is associated with. Similarly, the entry buffer (195) may receive from the storage controller (210) a submission queue ID (SQ_ID) indicating which submission queue the provided response (RESP) is associated with, and a completion queue ID (CQ_ID) indicating which completion queue the transmitted response (RESP) is associated with.

[0106] The host device (100) may refer to the entry buffer (195) to provide a command (CMD) to the storage device (200) in which data is stored (i.e., "1" is stored in the bitmap doorbell register (194)). The storage device (200) may perform a certain operation on the command (CMD) and, as a result, provide a response (RESP) to the host device (100). The response (RESP) may be stored back into the entry buffer (195). Data may be communicated between the host device (100) and the storage device (200) in packets (PACKET), and the command (CMD) may be included in the command packet (PACKET_C), and the response (RESP) may be included in the response packet (PACKET_R), respectively.

[0107] According to an exemplary embodiment of the present disclosure, the entry buffer (195) may buffer a plurality of submission queue (SQ) entries and / or completion queue (CQ) entries. For example, the entry buffer (195) may buffer UTRD, PRDT, command (CMD), response (RESP), submission queue ID (SQ_ID), completion queue ID (CQ_ID), etc.

[0108] The CQ router (196) can specify (i.e., route) the completion queue (CQ) to which the response (RESP) stored in the entry buffer (195) will be processed. The response (RESP) can be buffered in the entry buffer (195) after being provided from the storage device (200) and before processing.

[0109] According to an exemplary embodiment of the present disclosure, a CQ router (196) can search for a core where a response (RESP) can be processed and can route the response (RESP) to be written to a completion queue (CQ) processed by the searched core. According to an exemplary embodiment, as a result of the CQ router (196) assigning the response (RESP) to the completion queue (CQ), the head pointer or tail pointer (e.g., CHP, CTP) of the completion queue (CQ) in the CQ doorbell register (197) can be updated.

[0110] In an exemplary embodiment, the CQ router (196) can determine which of the multiple cores a response (RESP) will be written to the completion queue loaded by referring to the completion queue ID (CQ_ID) provided by the storage device (200). For example, the CQ router (196) can write the response (RESP) to the first completion queue by receiving the first completion queue ID (CQ_ID) loaded to the first core. Various selection algorithms may be applied to the method by which the CQ router (196) searches for the completion queue, similar to the submission queue selection method described above.

[0111] Additionally, according to an exemplary embodiment of the present disclosure, the CQ router (196) can control data input / output between the completion queue (CQ) and the entry buffer (195) so that the completion queue (CQ) does not overflow. For example, the CQ router (196) can control the data flow between the completion queue (CQ) and the entry buffer (195) so that the completion queue (CQ) does not overflow, which is a state where it is full and unable to store a response (RESP).

[0112] The CQ doorbell register (197) may be a pointer storage space that stores the order or location of the completion queue (CQ). The CQ doorbell register (197) may store a pointer indicating the tail or the head. According to an exemplary embodiment, the CQ doorbell register (197) may include a register indicating the base address of the completion queue (CQ) entry space and a register indicating the size of the completion queue (CQ) entry. According to an exemplary embodiment, the CQ doorbell register (197) may store the completion queue head pointer (CHP) and the completion queue tail pointer (CTP).

[0113] The address (CQ ENTRY ADDR) where an entry of the completion queue (CQ) is stored on the host controller interface (190) can be calculated as in Equation 2.

[0114] [Mathematical Formula 2]

[0115]

[0116] That is, the completion queue entry address (CQ ENTRY ADDR) may be the location obtained by adding the size of the completion queue head pointer (CHP) multiplied by the completion queue entry size to the completion queue entry base address (CQ ENTRY BASE ADDR).

[0117] Pointers stored in the CQ doorbell register (197) may be updated for each doorbell notification that occurs according to the input of a command (CMD) or the input / output of data. According to an exemplary embodiment of the present disclosure, the core (120) may write a response (RESP) received from the host controller interface (190) into the completion queue (CQ). After the response (RESP) is written into the completion queue (CQ), the completion queue tail pointer (CTP) may be changed. The response (RESP) may be processed sequentially or all at once by being fetched by the core (120). For example, the core (120) may fetch the completion queue (CQ) and perform a processing operation corresponding to the response (RESP) stored in the completion queue. After the response (RESP) written into the completion queue (CQ) is processed, the completion queue head pointer (CHP) may be changed.

[0118] The SQ arbiter (192), bitmap doorbell router (193), and CQ router (196) may be implemented as a processing circuit such as hardware including logic circuits, or as a combination of hardware and software such as a processor running software that performs arbitration operations and / or routing operations. In particular, the processing circuit may be implemented as a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU) that performs arithmetic and logical operations, bit shifts, etc., a Digital Signal Processor (DSP), a microprocessor, an Application Specific Integrated Circuit (ASIC), but is not limited thereto.

[0119] When multiple cores share a single bitmap doorbell, resource overhead occurs, which can degrade the overall system performance. For example, under the UFS standard, if one of the multiple cores accesses the bitmap doorbell, the other cores cannot access it.

[0120] A storage system (Fig. 1, 10) according to the technical concept of the present disclosure includes an SQ arbitrator (192) and a CQ router (196) to prevent resource occupation by multiple queues, thereby enabling smooth interfacing between a host device adopting the UFS standard and a storage device even in a multi-queue environment.

[0121] According to the technical concept of the present disclosure, a dedicated submission queue (SQ) and a dedicated completion queue (CQ) suitable for each of the plurality of cores, and a queue doorbell for each (i.e., SQ doorbell and CQ doorbell) can be directly utilized in the host controller interface (190). That is, according to the technical concept of the present disclosure, the structure of the storage system (10) can be minimized and compatibility with other devices adopting the UFS standard can be maintained by maintaining the bitmap doorbell structure applied to UFS as is, while additionally utilizing an SQ arbitrator (192), a bitmap doorbell router (193), and a CQ router (196).

[0122] Ultimately, the storage system (10) according to the technical concept of the present disclosure can utilize multiple circular queues (e.g., submission queue (SQ) and completion queue (CQ)) when the host controller interface (190) directly transmits a command (CMD) to the storage device (200), thereby resolving the overhead caused by the occupation of shared resources among multiple cores and maximizing performance.

[0123] FIG. 6 is a flowchart illustrating a method of operation of a host device (Fig. 1, 100) according to an exemplary embodiment of the present disclosure. FIG. 1 and FIG. 5 are referenced together with FIG. 6.

[0124] In step S110, the host device (100) can mediate a plurality of commands (CMDs) written in a plurality of submission queues (SQ). According to an exemplary embodiment, there may be a plurality of cores, and one core may process commands (CMDs) and / or responses (RESPs) using at least one submission queue (SQ) and at least one completion queue (CQ). For example, the SQ arbitrator (192) can mediate the priority between commands (CMDs) by referring to the head pointer (SHP) and tail pointer (STP) of the submission queue entry stored in the SQ doorbell register (191).

[0125] In step S120, the host device (100) can write a submission queue (SQ) entry to the entry buffer (195). In an exemplary embodiment, the host device (100) can store only the command (CMD) included in the submission queue (SQ) in the entry buffer (195), rather than the entire submission queue (SQ) entry.

[0126] In step S130, the host device (100) can set the bitmap doorbell. In an exemplary embodiment, a command (CMD) is stored in the entry buffer (195), and a specific value of the bitmap doorbell can be set.

[0127] For example, the SQ arbitrator (192) can transmit any one selected command (CMD) to the bitmap doorbell router (193), and the bitmap doorbell router (193) can store the command (CMD) in the entry buffer (195) by designating an idle space where the command (CMD) of the bitmap doorbell register (194) will be written. As the command (CMD) is written to the entry buffer (195), the data area corresponding to the entry buffer of the bitmap doorbell register (194) can be changed from bit "0" to bit "1".

[0128] In step S140, the host device (100) can update the submission queue doorbell. According to an exemplary embodiment, the host device (100) can update the head pointer (SHP) among the SQ doorbell registers (191) as a command (CMD) is written to the entry buffer (195).

[0129] According to an exemplary embodiment of the present disclosure, once a command (CMD) to be processed is written to the entry buffer (195), the command (CMD) is to be transmitted to a storage device (Fig. 1, 200) and is not to be processed by the host device (100). Accordingly, the host device (100) can optimize the space of the submission queue (SQ) by updating the submission queue head pointer (SHP).

[0130] In step S150, the host device (100) can transmit a command (CMD) and receive a response (RESP). According to an exemplary embodiment, the host device (100) can transmit the command (CMD) to a storage device (200). The storage device (200) can perform a specific memory operation based on the command (CMD) and provide the response (RESP), which is metadata about the result of the operation, back to the host device (100). In step S160, the host device (100) can store the received response (RESP) in an entry buffer (195). According to an exemplary embodiment of the present disclosure, the entry buffer (195) can buffer the command (CMD) and the response (RESP).

[0131] In step S170, the host device (100) may designate (path) the response (RESP) to be stored in one of the completion queues (CQ). For example, the CQ router (196) may refer to the written response (RESP) by referring to the bitmap doorbell register (194), select one of the response (RESP) according to a certain criterion (e.g., priority), and store the response (RESP) in the CQ doorbell register (197).

[0132] In step S180, the host device (100) can update the completion queue doorbell. According to an exemplary embodiment, as a result of the CQ router (196) assigning a response (RESP) to the completion queue (CQ), the tail pointer (e.g., CTP) of the completion queue (CQ) in the CQ doorbell register (197) can be updated.

[0133] According to an exemplary embodiment of the present disclosure, a host controller interface (191) can arbitrate the order of a plurality of submission queues (SQs). The host controller interface (191) can determine the priority and store a command included in a selected submission queue entry in an entry buffer (195). For example, a first command stored in a first submission queue can be stored in the entry buffer (195). After the first command is stored in the entry buffer (195), the host controller interface (191) can update the head pointer of the first submission queue.

[0134] The host controller interface (191) can select the next order among a plurality of submission queues (SQs). The host controller interface (191) can store a second command stored in the second submission queue in the entry buffer (195). After the second command is stored in the entry buffer (195), the host controller interface (191) can update the head pointer of the second submission queue. This is repeated sequentially. Meanwhile, the first command and the second command stored in the entry buffer (195) can be transmitted to the storage device (200) in the order in which they were entered.

[0135] FIG. 7 is a block diagram illustrating a storage system (10) in which a command (CMD) is written according to an exemplary embodiment of the present disclosure. FIG. 5 and FIG. 6 are referenced together with FIG. 7.

[0136] The storage system (10) may include a host device (100) and a storage device (200). The host device (100) and the storage device (200) of FIG. 1 may be applied to the host device (100) and the storage device (200) of FIG. 7, respectively, and redundant descriptions are omitted to the extent that they do not conflict.

[0137] The host device (100) may include a first core (121) and a second core (123).

[0138] The first core (121) can write a command (CMD) to the first submission queue (SQ1) and can refer to the first submission queue head pointer (SHP1) and the first submission queue tail pointer (STP1). The first submission queue head pointer (SHP1) and the first submission queue tail pointer (STP1) may be included in the first submission queue doorbell. Additionally, the first core (121) can process a response (RESP) written to the first completion queue (CQ1) by referring to the first completion queue head pointer (CHP1) and the first completion queue tail pointer (CTP1).

[0139] The second core (123) can write a command (CMD) to the second submission queue (SQ2) and can reference the second submission queue head pointer (SHP2) and the second submission queue tail pointer (STP2). Additionally, the second core (123) can include the second completion queue head pointer (CHP2) and the second completion queue tail pointer (CTP2) of the second completion queue (CQ2), respectively.

[0140] According to an exemplary embodiment of the present disclosure, a host device (100) may provide a first command (CMD1) to an entry buffer (195) as a result of fetching a first submission queue (SQ1) executed in a first core (112). For example, a bitmap doorbell router (193) may search for an empty space by referring to a bit stored in a bitmap doorbell register (135). The entry buffer (195) may write the first command (CMD1) to a data space for buffering, and the bitmap value corresponding to the space where the first command (CMD1) of the bitmap doorbell register (194) is written may be changed from bit "0" to bit "1".

[0141] According to an exemplary embodiment, along with the transmission of the first command (CMD1), a submission queue ID (SQ_ID) indicating which submission queue, among the first submission queue (SQ1) and the second submission queue (SQ2), the command (CMD) was transmitted may be stored in the entry buffer (195). Additionally, a completion queue ID (CQ_ID) indicating the completion queue (CQ) among the first completion queue (CQ1) and the second completion queue (CQ2) where computing resources are sufficient or the data space of the queue is empty may be transmitted to the entry buffer (195). The first command (CMD1), the submission queue ID (SQ_ID), and the completion queue ID (CQ_ID) may be transmitted in the form of a packet.

[0142] In an exemplary embodiment of the present disclosure, after the first command (CMD1) is transmitted, the submission queue head pointer (SHP1) of the first submission queue (SQ1) may be updated (HP update). For example, the write space indicated by the head of the first submission queue (SQ1) may be changed by increasing the value of the head of the submission queue head pointer (SHP1) by 1 (++HEAD). By increasing the first submission queue head pointer (SHP1) by 1, the first command (CMD1) that was written to the first submission queue (SQ1) may be deleted. That is, the first command (CMD1) may be removed from the queue (CMD1 dequeue).

[0143] According to an exemplary embodiment of the present disclosure, once a command (CMD) to be processed is written to the entry buffer (195), the command (CMD) is not to be processed by the host device (100). For example, as the storage space for the first command (CMD1) moves from the first submission queue (SQ1) to the entry buffer (195), the first submission queue (SQ1) no longer needs to store the first command (CMD1). Due to the nature of a circular queue with limited writing space, unnecessary commands must be removed so that new commands can be written. Therefore, after the first command (CMD1) is stored in the entry buffer (195), the first command (CMD1) that was written to the first submission queue (SQ1) can be removed from the queue by updating the submission queue head pointer (SHP1) of the writing space (i.e., by increasing the head value by 1). Accordingly, the host device (100) can optimize input / output by removing the first command (CMD1) from the first submission queue (SQ1).

[0144] The host device (100) can provide a first command (CMD1) to the storage device (200) through the entry buffer (195). After the first command (CMD1) is transmitted, the bitmap doorbell register (194) can change the value of the bitmap corresponding to the space where the first command (CMD1) was written from bit "1" to bit "0".

[0145] FIG. 8 is a block diagram illustrating a storage system (10) in which a response (RESP) is written according to an exemplary embodiment of the present disclosure. Since FIG. 8 illustrates the operation after the first command (CMD1) according to FIG. 7 is written, descriptions that overlap with FIG. 7 are omitted. FIG. 5 to 7 are referenced together with FIG. 8.

[0146] According to an exemplary embodiment of the present disclosure, the storage device (200) may generate a second response (RESP2) as a result of executing a first command (CMD) and transmit the second response (RESP2) back to the host device (100).

[0147] According to an exemplary embodiment of the present disclosure, the entry buffer (195) may store a response (RESP). For example, the entry buffer (195) may write a second response (RESP2) to a data space for buffering, and the value of the bitmap corresponding to the space where the second response (RESP2) of the bitmap doorbell register (194) is written may be changed from bit "0" to bit "1".

[0148] Along with the transmission of the second response (RESP2), a submission queue ID (SQ_ID) indicating which submission queue (e.g., the first command (CMD1)) associated with the first submission queue (SQ1) and the second submission queue (SQ2) has been processed, and a completion queue ID (CQ_ID) indicating which completion queue (CQ1) and the second completion queue (CQ2) associated with the command has been transmitted may be transmitted to the host device (100). The second response (RESP2), the submission queue ID (SQ_ID), and the completion queue ID (CQ_ID) may be transmitted in the form of a packet.

[0149] In an exemplary embodiment, a response (RESP) may be written to a completion queue (CQ) corresponding to the referenced completion queue ID (CQ_ID) among the first core (121) and the second core (123), based on a completion queue ID (CQ_ID) provided by the storage device (200). For example, a response (RESP) may be written to a second completion queue (CQ2) according to a completion queue ID (CQ_ID) indicating a second completion queue (CQ2) loaded into the second core (113).

[0150] According to an exemplary embodiment of the present disclosure, a CQ router (196) may assign (i.e., route) a response (RESP) to a completion queue (CQ). According to an exemplary embodiment, a second response (RESP2) may be temporarily stored in an entry buffer (195) until it is determined whether the host device (100) can access the second completion queue (CQ2).

[0151] In an exemplary embodiment, after the second response (RESP2) is written, the second completion queue tail pointer (CTP2) of the second completion queue (CQ2) may be updated (CP update). For example, by increasing the tail value of the second completion queue tail pointer (CTP2) by 1 (++TAIL), the write space indicated by the tail of the second completion queue (CQ2) may be changed. That is, by increasing the tail pointer by 1, the second response (RESP2) may be additionally written to the second completion queue (CQ2) (RESP2 enqueue).

[0152] The bitmap doorbell register (194) can change the state of the space where the second response (RESP2) was written from bit "1" to bit "0" after the second response (RESP2) is written to the second completion queue (CQ2).

[0153] FIG. 9 is a diagram illustrating the process of a command being entered into a circular queue according to an exemplary embodiment of the present disclosure. The circular queue illustrated in FIG. 9 may be applied to the submission queue (SQ) and / or completion queue (CQ) disclosed in FIG. 1 through 8. FIG. 1 and FIG. 2 are referenced together.

[0154] A circular queue is a data structure that allows data to be inserted and deleted, consisting of an array with the beginning and end connected. The initial values ​​of the head and tail of a circular queue are 0, and if the head value and the tail value are the same, the circular queue is interpreted as empty. In the initial state where the values ​​of the head and tail are both 0, new data (e.g., commands) can be written. New data (e.g., commands) can be written to the space indicated by the tail.

[0155] Referring to Fig. 9, it is assumed that there are 8 writeable spaces in the circular queue, and that the first command (CMD1), the second command (CMD2), and the third command (CMD3) have been written.

[0156] A command can be written in the space indicated by the TAIL, and the value of the pointer can be increased by 1 each time a command is written. For example, the initial value of the HEAD can be 0, and the value of the TAIL can be 3 after the first to third commands (CMD1~CMD3) are written. That is, the TAIL indicates the space where the command is to be written, and after data is written, the value can be increased to indicate the space immediately following the space where the data was written. According to an exemplary embodiment, as the first command (CMD1), the second command (CMD2), and the third command (CMD3) are written sequentially, the TAIL can be increased by 1, and as the third command (CMD3) is written, the TAIL can indicate the space immediately following the third command (CMD3).

[0157] In an exemplary embodiment, a fourth command (CMD4) can be written to a circular queue (Enqueue CMD4). The head (HEAD) can maintain an initial value of 0, and the tail (TAIL) can increase its value by 1 upon writing a new command (++TAIL). Thus, the tail (TAIL) can indicate the space immediately following the fourth command (CMD4).

[0158] As commands are sequentially entered into the circular queue as described above, the head remains the same, while the tail value increases by 1 (++TAIL). If the tail value + 1 equals the head value, the circular queue is interpreted as being full. In an exemplary embodiment, since the queue depth, which is the data capacity of the circular queue, is limited, the tail value can be allocated using a wrap-around method that reuses existing addresses. For example, if the queue depth of the circular queue is N, the tail can have a value of 0 corresponding to the address again as the increased tail value is N. As such, since the circular queue has the characteristic that the address following the last address becomes the first address, it is advantageous in environments with limited data space allocation and is easy to implement.

[0159] According to exemplary embodiments of the present disclosure, the submission queue (SQ) and / or completion queue (CQ) of FIGS. 1 through 8 may be implemented as a circular queue. If a circular queue structure is used, a command (or response) can be easily written to the submission queue and / or completion queue simply by incrementing the tail pointer, which is the address of the write space indicated by the tail (++TAIL), by 1. Similarly, a command (or response) written to the submission queue and / or completion queue can be easily erased by incrementing the head pointer by 1 (++HEAD).

[0160] FIG. 10 is a flowchart illustrating a method of operation of a storage system (10) according to an exemplary embodiment of the present disclosure. FIG. 10 is referenced together with FIG. 1 and FIG. 5.

[0161] In step S205, the core (120) can issue a command (CMD). The command (CMD) can be entered into a submission queue (SQ) entry.

[0162] In step S210, the core (120) can write a command (CMD) issued to the submission queue (SQ) and update the SQ doorbell. For example, the core (120) can perform processing based on the writing of data by updating the tail pointer (STP) of the SQ doorbell.

[0163] In step S215, the core (120) can transmit a submission queue (SQ) entry to the host controller interface (190). The submission queue (SQ) itself is substantially stored in host memory (Fig. 1, 130) and can be managed by the core (120). Thus, the core (120) can transmit the entry information of the submission queue (SQ) to the host controller interface (190).

[0164] In step S220, the host controller interface (190) can store a submission queue (SQ) entry in the entry buffer (195). According to an exemplary embodiment, the host controller interface (190) can mediate a plurality of commands (CMDs) written in a plurality of submission queues (SQ), and the SQ arbitrator (192) can mediate the priority between the commands (CMDs) by referring to the head pointer (SHP) and tail pointer (STP) of the submission queue entry stored in the SQ doorbell register (191). As a result of the mediation, the host controller interface (190) can store the commands (CMDs) included in the submission queue (SQ) in the entry buffer (195).

[0165] In step S225, the host controller interface (190) can set the bitmap doorbell. For example, the entry buffer (195) can write a command (CMD) to a data space for buffering, and the value of the bitmap corresponding to the space where the command (CMD) of the bitmap doorbell register (194) is written can be changed from bit "0" to bit "1".

[0166] In step S230, the host controller interface (190) can update the submission queue doorbell. According to an exemplary embodiment, the host controller interface (190) can update the submission queue head pointer (SHP) in the SQ doorbell register (191) as a command (CMD) is written to the entry buffer (195).

[0167] According to an exemplary embodiment of the present disclosure, when a command (CMD) to be processed is written to the entry buffer (195), the host controller interface (190) can optimize the space of the submission queue (SQ) by updating the submission queue head pointer (SHP).

[0168] In step S235, the host controller interface (190) can transmit a command (CMD) and receive a response (RESP). According to an exemplary embodiment, the host controller interface (190) can transmit the command (CMD) to the storage device (200). The storage device (200) can perform a specific memory operation based on the command (CMD) and provide the response (RESP), which is metadata about the result of the operation, back to the host controller interface (190).

[0169] In step S240, the host controller interface (190) may store the received response (RESP) in an entry buffer (195). According to an exemplary embodiment of the present disclosure, the entry buffer (195) may buffer the response (RESP) until the path of the response (RESP) is established.

[0170] At step S245, the host controller interface (190) can transmit the response (RESP) to a completion queue (CQ) entry. According to an exemplary embodiment of the present disclosure, the CQ router (196) can designate (path) the response (RESP) to be stored in one of the completion queues (CQ). For example, the CQ router (196) can select one of the response (RESP) among the response (RESP) according to a certain criterion (e.g., priority) by referring to the bitmap doorbell register (194), and store a pointer to the response (RESP) in the CQ doorbell register (197). Then, the response (RESP) can be written to the completion queue (CQ). The completion queue (CQ) itself is substantially stored in the host memory (130), and the host controller interface (190) can transmit entry information of the completion queue (CQ) to the core (120).

[0171] In step S250, the host controller interface (190) can ROD the completion queue doorbell. According to an exemplary embodiment, the host controller interface (190) can update the completion queue tail pointer (CTP) in the CQ doorbell register (197) as a response (RESP) is written to the completion queue (CQ).

[0172] In step S255, the host controller interface (190) can clear the bitmap doorbell. According to an exemplary embodiment, the host controller interface (190) can save the bitmap doorbell idle space by storing the response (RESP) according to the command (CMD) in the CQ doorbell register (197) to assign it to a specific completion queue (CQ), and then removing the bitmaps associated with the submission queue (SQ) associated with the command (CMD) and the completion queue (CQ) associated with the response (RESP).

[0173] For example, referring to the process of FIGS. 7 and 8, the first command (CMD1), submission queue ID (SQ_ID), and completion queue ID (CQ_ID) written in the first submission queue (SQ1) are stored in the entry buffer (195), and the state of the memory area of ​​the bitmap doorbell register (194) can be changed (bit "0" → bit "1"). The first command (CMD1) can be provided to the storage device (200), and the second response (RESP2) according to the first command (CMD1) can be stored again in the entry buffer (195) together with the submission queue ID (SQ_ID) and the completion queue ID (CQ_ID). The second response (RESP2) can be designated as the second completion queue (CQ2) and stored in the CQ doorbell register (197). Data generated or stored during the first command (CMD1) and second response (RESP2) process (the first command (CMD1) and second response (RESP2), and the submission queue ID (SQ_ID) and completion queue ID (CQ_ID) stored in the entry buffer (195)) can be erased as the second response (RESP2) is processed. Consequently, the bitmap doorbell register (194) and the entry buffer (195) can be initialized.

[0174] In step S260, a completion queue (CQ) entry may be consumed. According to an exemplary embodiment, the completion queue (CQ) may access the location where a response (RESP) is stored by referencing a pointer to the CQ doorbell register (197). For example, a second core (Fig. 8, 123) may write a second response (RESP2) to a second completion queue (CQ2) by referencing a second completion queue tail pointer (CTP2), and the second response (RESP2) may be processed by the second core (123).

[0175] In step S265, the completion queue (CQ) doorbell can be updated. According to an exemplary embodiment, after the second response (RESP2) is processed by the second core (123), free space is created again in the second completion queue (CQ2). The CQ doorbell register (197) can increase the input / output efficiency of the second completion queue (CQ2) by updating the head pointer (CHP2) of the completion queue (CQ).

[0176] FIGS. 11 and FIGS. 12 are block diagrams illustrating examples of various information stored in registers (111) within host memory (Fig. 1, 130) and host controller (Fig. 1, 110). FIGS. 1 and FIGS. 2 are referenced together with FIGS. 11 and FIGS. 12.

[0177] Referring to FIG. 11, the host device (100) includes a host memory (130) and a register (111), the register (111) is configured to be located inside the host controller (110), and the host memory (130) may be located outside the host controller (110). Various commands and parameters defined in JEDEC UFS standards for data management of the storage system (10) may be stored in the host memory (130) and the register (111).

[0178] A UTP Transfer Request Descriptor is stored in the descriptor area of ​​the host memory (130), and UPIU information and corresponding PRDT information may be stored in another area of ​​the host memory (130). Additionally, UTP Transfer Request Descriptors may be stored in the host memory (130) or identified in the host memory (130) through the UTP Transfer Request stored in the register (111).

[0179] Additionally, write data and read data are stored in a plurality of data buffers included in the buffer area of ​​the host memory (130), and PRDT information may include a buffer address as a physical address of the data buffer. Additionally, PRDT information may not be stored for some command UPIUs, and as an example, PRDT information may not be stored for command UPIUs that are irrelevant to data buffer access.

[0180] In addition, FIG. 11 further illustrates various other information defined in JEDEC UFS standards. For example, a UTP task management request list may be further stored in a region of the host memory (130), and for example, a task management request UPIU and a task management response UPIU may be stored in a region of the host memory (130). Furthermore, the task management request list may be stored in the host memory (130) through the UTP task management request stored in the register (111). In addition, other components defined in JEDEC UFS standards are further illustrated in the register (111), such as host controller capabilities, interrupt and host status indicators, UFS interconnect (UIC) commands, and vendor specific values ​​may be stored in the register (111).

[0181] In order to store data stored in the data buffer of the host memory (130) in the operating system in the storage device (Fig. 1, 200), a UTP transmission request descriptor is created within the host memory (130), and a host controller interface (Fig. 2, 190) can be initiated by creating a UTP transmission request.

[0182] The host controller interface (190) can access a space in the host memory (130) corresponding to a UTP transmission request, read the UTP transmission request descriptor, and send the corresponding command UPIU to the storage device (200).

[0183] A storage device (200) that has received a command UPIU can transmit an RTT (Ready To Transfer) UPIU containing size and offset information to be transmitted to a host controller interface (190), and the host controller interface (190) can refer to the LUN (Logical Unit Number) and TAG (identifier) ​​information inside the HEADER (transmission information) of the RTT UPIU to access the location of the corresponding UTP transmission request descriptor, search for PRDT information, and finally know the address of the data buffer and start data transmission.

[0184] FIG. 12 is a block diagram comparing the frequency of access to host memory in a general case and according to an embodiment of the present disclosure. FIG. 12 illustrates an example in which a host performs an operation according to a packet transmitted from a storage device.

[0185] FIG. 12 illustrates an example of processing packets according to a general format. Referring to FIG. 12, one or more UTP transfer requests are stored in a register (111) within a host controller (Fig. 2, 110), and as an example, a first transfer request (Transfer Request 0) may correspond to a data write request and a third transfer request (Transfer Request 2) may correspond to a data read request. The host controller (110) may receive an RTT UPIU from a storage device (Fig. 1, 200) in response to the first transfer request (Transfer Request 0). Additionally, the host controller (110) may receive a DATA_IN UPIU from the storage device (200) in response to the third transfer request (Transfer Request 2).

[0186] A packet transmitted from a storage device (200) may include a header area in which header information is stored, and the header information of the RTT UPIU may include size and offset information of the data to be transmitted for a data writing operation. A host controller (110) may perform a processing operation using at least some of the information values ​​within the header information of the RTT UPIU. For example, the host controller (110) accesses the host memory (130) to identify a corresponding UTP transmission request descriptor by referencing the LUN (Logical Unit Number) and TAG (identifier) ​​information within the header information of the RTT UPIU. Additionally, the host controller checks the information of the PRDT by accessing the host memory (130) at a location determined by the UTP transmission request descriptor. Furthermore, the host controller can access the data buffer through the identified PRDT information (e.g., buffer address) and transmit the data stored in the data buffer to the storage device (200).

[0187] Meanwhile, when a DATA_IN UPIU is received, the host controller (110) may access the host memory (130) to identify a corresponding UTP transmission request descriptor from the header information of the DATA_IN UPIU, and may also access the host memory (130) to identify information of the corresponding PRDT. Then, the read data included in the DATA_IN UPIU may be stored in a data buffer corresponding to the identified PRDT information.

[0188] Figure 13 is a diagram showing an example of a data read operation and packet implementation according to the UFS interface.

[0189] Referring to FIG. 13, a command UPIU (CMD UPIU) for a data read request is transmitted from a host device (100) to a storage device (200), and the CMD UPIU for the data read request may include a buffer address (or a physical address (PA) of the data buffer). The storage device (200) reads data from a memory core in response to the command UPIU for the data read request and can transmit a DATA_IN UPIU containing the read data along with the physical address (PA) parsed from the command UPIU above to the host. Additionally, the storage device (200) can transmit a response UPIU (Response UPIU) to the host device (100) indicating that the operation corresponding to the command UPIU has been completed. According to the embodiments described above, the host device (100) may store read data in a data buffer at a location indicated by a physical address (PA) parsed from the DATA_IN UPIU. Meanwhile, the packet structure of the aforementioned command UPIU and DATA_IN UPIU may be implemented as shown in FIG. 14a and FIG. 14b below.

[0190] FIGS. 14a and FIGS. 14b are drawings showing the structure of a packet according to an exemplary embodiment of the present disclosure.

[0191] FIGS. 14a and FIGS. 14b illustrate an example in which a buffer address is included in the existing header area, FIG. 14a shows the structure of the command UPIU, and FIG. 14b shows the structure of the DATA_IN UPIU.

[0192] Referring to FIG. 14a, the header area of ​​the command UPIU includes a reserved area, and a portion of the reserved area may include a buffer address and related information according to embodiments of the present disclosure. As an example, along with the host memory buffer address being included in the reserved area, information (CWA) indicating that the buffer address is included in the command UPIU and information (CWA_LENGTH) indicating the size of the area where the buffer address is stored (or the size of the area where the buffer address and related information are stored) may be further included in the reserved area.

[0193] The configuration of a command packet (PACKET_C) transmitted from a host device (100) adopting the UFS standard to a storage device (200) may include a submission queue ID (SQ_ID), a completion queue ID (CQ_ID), and a response credit (CR_RESP).

[0194] A submission queue ID (SQ_ID) indicating which of the multiple submission queues a command related to has been transmitted, and a completion queue ID (CQ_ID) indicating which of the multiple completion queues a command related to has been transmitted, are transmitted from the host device (100) to the storage device (200).

[0195] In an exemplary embodiment, the initialization of the host device (100) can be performed using a Reserved Command.

[0196] Referring to FIG. 14b, the DATA_IN UPIU includes a payload area that includes a header area and a data area, and the header area may include a reserved area. Additionally, at least a portion of the reserved area may include a buffer address of the host memory (130) and related information.

[0197] The composition of the response packet (PACKET_R) transmitted from a storage device (200) adopting the UFS standard to a host device (100) may include a submission queue ID (SQ_ID), a completion queue ID (CQ_ID), and a command credit (CR_CMD).

[0198] The information included in the preliminary area shown in Fig. 14b is the same or similar as that shown in Fig. 14a, so a detailed description thereof is omitted.

[0199] FIG. 15 is a drawing illustrating a system (1000) to which a storage device according to an exemplary embodiment of the present disclosure is applied.

[0200] The system (1000) of FIG. 15 is basically a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IoT (Internet of Things) device. However, the system (1000) of FIG. 15 is not necessarily limited to a mobile system and may be a personal computer, a laptop computer, a server, a media player, or an automotive device such as a navigation system.

[0201] Referring to FIG. 15, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0202] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0203] The main processor (1100) may include one or more CPU cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0204] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0205] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a storage controller (1310a, 1310b) and a non-volatile memory (NVM) (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). The non-volatile memory (1320a, 1320b) may include a flash memory with a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0206] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a solid state device (SSD) or a memory card, and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as Universal Flash Storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but is not necessarily limited thereto.

[0207] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0208] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, keypad, keyboard, mouse and / or microphone, etc.

[0209] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope sensor, etc.

[0210] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0211] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0212] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0213] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe, IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0214] FIG. 16 is a drawing for explaining a UFS system (2000) according to an exemplary embodiment of the present disclosure.

[0215] The UFS system (2000) is a system that follows the UFS standard published by JEDEC (Joint Electron Device Engineering Council) and may include a UFS host (2100), a UFS device (2200), and a UFS interface (2300). The description of the system (1000) of FIG. 15 described above may also be applied to the UFS system (2000) of FIG. 16 to the extent that it does not conflict with the following description of FIG. 16.

[0216] Referring to FIG. 16, the UFS host (2100) and the UFS device (2200) can be interconnected via a UFS interface (2300). If the main processor (1100) of FIG. 1 is an application processor, the UFS host (2100) can be implemented as part of the application processor. The UFS host controller (2110) and the host memory (2140) can correspond to the controller (1120) and memory (1200a, 1200b) of the main processor (1100) of FIG. 1, respectively. The UFS device (2200) may correspond to the storage device (1300a, 1300b) of FIG. 1, and the UFS device controller (2210) and non-volatile memory (2220) may correspond to the storage controller (1310a, 1310b) and non-volatile memory (1320a, 1320b) of FIG. 1, respectively.

[0217] A UFS host (2100) may include a UFS host controller (2110), an application (2120), a UFS driver (2130), a host memory (2140), and a UIC (UFS interconnect) layer (2150). A UFS device (2200) may include a UFS device controller (2210), non-volatile memory (2220), a storage interface (2230), device memory (2240), a UIC layer (2250), and a regulator (2260). The non-volatile memory (2220) may be composed of a plurality of memory units (2221), and such memory units (2221) may include V-NAND flash memory of a 2D or 3D structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM. The UFS device controller (2210) and the non-volatile memory (2220) can be connected to each other through a storage interface (2230). The storage interface (2230) can be implemented to comply with standard protocols such as Toggle or ONFI.

[0218] The application (2120) may refer to a program that wishes to communicate with the UFS device (2200) in order to use the functions of the UFS device (2200). The application (2120) may send an input-output request (IOR) to the UFS driver (2130) for input / output to the UFS device (2200). The input-output request (IOR) may refer to a data read request, a write request, and / or a discard / erase request, but is not necessarily limited thereto.

[0219] The UFS driver (2130) can manage the UFS host controller (2110) through the UFS-HCI (host controller interface). The UFS driver (2130) can convert an I / O request generated by an application (2120) into a UFS command defined by the UFS standard and transmit the converted UFS command to the UFS host controller (2110). A single I / O request can be converted into multiple UFS commands. The UFS commands may be commands defined by the SCSI standard by default, but they may also be commands specific to the UFS standard.

[0220] The UFS host controller (2110) can transmit UFS commands converted by the UFS driver (2130) to the UIC layer (2250) of the UFS device (2200) through the UIC layer (2150) and the UFS interface (2300). In this process, the UFS host register (2111) of the UFS host controller (2110) can serve as a command queue (CQ).

[0221] The UIC layer (2150) on the UFS host (2100) side may include MIPI M-PHY (2151) and MIPI UniPro (2152), and the UIC layer (2250) on the UFS device (2200) side may also include MIPI M-PHY (2251) and MIPI UniPro (2252).

[0222] The UFS interface (2300) may include a line transmitting a reference clock (REF_CLK), a line transmitting a hardware reset signal (RESET_n) for the UFS device (2200), a pair of lines transmitting a differential input signal pair (DIN_t and DIN_c), and a pair of lines transmitting a differential output signal pair (DOUT_t and DOUT_c).

[0223] The frequency value of the reference clock (REF_CLK) provided from the UFS host (2100) to the UFS device (2200) may be one of four values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not necessarily limited thereto. The UFS host (2100) may change the frequency value of the reference clock (REF_CLK) even while in operation, that is, while data transmission and reception is being performed between the UFS host (2100) and the UFS device (2200). The UFS device (2200) may generate clocks of various frequencies from the reference clock (REF_CLK) provided from the UFS host (2100) using a phase-locked loop (PLL), etc. Additionally, the UFS host (2100) may set the value of the data rate between the UFS host (2100) and the UFS device (2200) through the frequency value of the reference clock (REF_CLK). That is, the value of the data rate may be determined by depending on the frequency value of the reference clock (REF_CLK).

[0224] The UFS interface (2300) may support multiple lanes, and each lane may be implemented as a differential line pair. For example, the UFS interface (2300) may include one or more receive lanes and one or more transmit lanes. In FIG. 16, a pair of lines transmitting a differential input signal pair (DIN_T and DIN_C) may each constitute a receive lane, and a pair of lines transmitting a differential output signal pair (DOUT_T and DOUT_C) may each constitute a transmit lane. Although FIG. 16 shows one transmit lane and one receive lane, the number of transmit lanes and receive lanes may be changed.

[0225] The receiving lane and the transmitting lane can transmit data in a serial communication manner, and full-duplex communication between the UFS host (2100) and the UFS device (2200) is possible due to the structure in which the receiving lane and the transmitting lane are separated. That is, the UFS device (2200) can transmit data to the UFS host (2100) through the transmitting lane even while receiving data from the UFS host (2100) through the receiving lane. In addition, control data such as commands from the UFS host (2100) to the UFS device (2200), and user data that the UFS host (2100) intends to store in the non-volatile memory (2220) of the UFS device (2200) or read from the non-volatile memory (2220) can be transmitted through the same lane. Accordingly, there is no need to provide additional lanes for data transmission between the UFS host (2100) and the UFS device (2200) in addition to a pair of receiving lanes and a pair of transmitting lanes.

[0226] The UFS device controller (2210) of the UFS device (2200) can control the overall operation of the UFS device (2200). The UFS device controller (2210) can manage non-volatile memory (2220) through a logical unit (LU) (2211), which is a logical data storage unit. The number of LUs (2211) may be eight, but is not limited thereto. The UFS device controller (2210) may include a flash translation layer (FTL) and can convert a logical data address, such as a logical block address (LBA), transmitted from the UFS host (2100) into a physical data address, such as a physical block address (PBA), using the address mapping information of the FTL. A logical block for storing user data in the UFS system (2000) may have a size within a predetermined range. For example, the minimum size of a logical block can be set to 4Kbyte.

[0227] When a command from the UFS host (2100) is input to the UFS device (2200) through the UIC layer (2250), the UFS device controller (2210) performs an operation according to the input command, and when the operation is completed, it can send a completion response to the UFS host (2100).

[0228] For example, if a UFS host (2100) intends to store user data in a UFS device (2200), the UFS host (2100) may send a data storage command to the UFS device (2200). When the UFS host (2100) receives a response from the UFS device (2200) that the user data is ready to be transferred, the UFS host (2100) may transfer the user data to the UFS device (2200). The UFS device controller (2210) may temporarily store the transferred user data in the device memory (2240) and, based on the address mapping information of the FTL, store the user data temporarily stored in the device memory (2240) in a selected location in the non-volatile memory (2220).

[0229] As another example, when a UFS host (2100) intends to read user data stored in a UFS device (2200), the UFS host (2100) may transmit a data read command to the UFS device (2200). Upon receiving the command, the UFS device controller (2210) may read user data from the non-volatile memory (2220) based on the data read command and temporarily store the read user data in the device memory (2240). During this read process, the UFS device controller (2210) may detect and correct errors in the read user data using an embedded ECC (error correction code) engine (not shown). More specifically, the ECC engine may generate parity bits for the data to be written to the non-volatile memory (2220), and the generated parity bits may be stored in the non-volatile memory (2220) together with the data to be written. When reading data from non-volatile memory (2220), the ECC engine can correct errors in the read data using parity bits read from non-volatile memory (2220) along with the read data, and output the read data with the errors corrected.

[0230] Additionally, the UFS device controller (2210) can transmit user data temporarily stored in the device memory (2240) to the UFS host (2100). Furthermore, the UFS device controller (2210) may further include an AES (advanced encryption standard) engine (not shown). The AES engine can perform at least one of encryption and decryption operations on data input to the UFS device controller (2210) using a symmetric-key algorithm.

[0231] The UFS host (2100) can store commands to be transmitted to the UFS device (2200) in order in a UFS host register (2111) that can function as a command queue, and can transmit commands to the UFS device (2200) in the said order. At this time, the UFS host (2100) can transmit the next command waiting in the command queue to the UFS device (2200) even if the previously transmitted command is still being processed by the UFS device (2200), that is, before receiving notification that the previously transmitted command has been completed by the UFS device (2200), and accordingly, the UFS device (2200) can also receive the next command from the UFS host (2100) even while processing the previously transmitted command. The maximum number of commands that can be stored in such a command queue (queue depth) may be, for example, 32. Additionally, the command queue can be implemented as a circular queue type, which indicates the start and end of the column of commands stored in the queue through a head pointer and a tail pointer, respectively.

[0232] Each of the plurality of memory units (2221) may include a memory cell array (not shown) and a control circuit (not shown) that controls the operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a single-level cell (SLC) that stores 1 bit of information, but may also be a cell that stores 2 bits or more of information, such as an MLC (multi-level cell), TLC (triple-level cell), or QLC (quadruple-level cell). The three-dimensional memory cell array may include a vertically oriented NAND string such that at least one memory cell is positioned above another memory cell.

[0233] VCC, VCCQ, VCCQ2, etc., may be input as power voltages to the UFS device (2200). VCC is the main power voltage for the UFS device (2200) and may have a value of 2.4 to 3.6 V. VCCQ is a power voltage for supplying a low range of voltage, mainly for the UFS device controller (2210), and may have a value of 1.14 to 1.26 V. VCCQ2 is a power voltage for supplying a range of voltage lower than VCC but higher than VCCQ, mainly for an input / output interface such as MIPI M-PHY (2251), and may have a value of 1.7 to 1.95 V. The above power voltages may be supplied to each component of the UFS device (2200) through a regulator (2260). The regulator (2260) may be implemented as a set of unit regulators each connected to different of the aforementioned power voltages.

[0234] FIGS. 17a to 17c are drawings for explaining the form factor of a UFS card according to an exemplary embodiment of the present disclosure.

[0235] When the UFS device (2200) described with reference to FIG. 16 is implemented in the form of a UFS card (4000), the external appearance of the UFS card (4000) may follow that shown in FIG. 17a to FIG. 17c.

[0236] FIG. 17a illustrates an exemplary top view of a UFS card (4000). Referring to FIG. 17a, it can be seen that the UFS card (4000) follows a shark-shaped design overall. In relation to FIG. 17a, the UFS card (4000) may have dimension values ​​as exemplarily described in Table 1 below.

[0237] item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0238] FIG. 17b illustrates an exemplary side view of a UFS card (4000). In relation to FIG. 17b, the UFS card (4000) may have dimension values ​​as described in Table 2 below, for example.

[0239] item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0240] FIG. 17c illustrates an exemplary bottom view of a UFS card (4000). Referring to FIG. 17c, a plurality of pins for electrical contact with a UFS slot may be formed on the bottom surface of the UFS card (4000), and the function of each pin will be described later. Based on the symmetry between the top surface and the bottom surface of the UFS card (4000), some of the information regarding dimensions described with reference to FIG. 17a and Table 1 (e.g., T1 to T5 and T9) may also be applied to the bottom view of the UFS card (4000) as shown in FIG. 17c. A plurality of pins may be formed on the bottom surface of the UFS card (4000) for electrical connection with a UFS host, and according to FIG. 17c, the number of pins may be a total of 12. Each pin may have a rectangular shape, and the signal name corresponding to the pin is as shown in FIG. 17c. For general information regarding each pin, refer to Table 3 below, and refer to the description above in relation to FIG. 16.

[0241] number Shin Ho-myeong explanation Dimensions (mm) 1 Vss Ground (GND) 3.00 × 0.72±0.05 2 DIN_C Differential input signal input from the host to the UFS card (4000) (DIN_C is the negative node, DIN_T is the positive node) 1.50 × 0.72±0.05 3 DIN_T 4 Vss Same as number 1 3.00 × 0.72±0.05 5 DOUT_C Differential output signal output from UFS card (4000) to host (DOUT_C ​​is negative node, DOUT_T is positive node) 1.50 × 0.72±0.05 6 DOUT_T 7 Vss Same as number 1 3.00 × 0.72±0.05 8 REF_CLK Reference clock provided from the host to the UFS card (4000) 1.50 × 0.72±0.05 9 VCCQ2 A power supply voltage having a relatively lower value compared to Vcc, primarily provided for PHY interfaces or controllers. 3.00 × 0.72±0.05 10 C / D(GND) Card Detection Signal 1.50 × 0.72±0.05 11 Vss Same as number 1 3.00 × 0.80±0.05 12 Vcc Main power supply voltage

[0242] FIG. 18a is a block diagram showing a host-storage system (10) according to an exemplary embodiment of the present disclosure, and FIG. 18b through 18e are detailed block diagrams of the configurations of FIG. 18a. Referring to FIG. 18a, the host-storage system (10) may include a host device (100) and a storage device (200). Additionally, the storage device (200) may include a storage controller (210) and a non-volatile memory (NVM) (230). Additionally, according to an exemplary embodiment of the present disclosure, the host device (100) may include a host controller (110) and a host memory (130). The host memory (130) may function as a buffer memory for temporarily storing data to be transmitted to the storage device (200) or data transmitted from the storage device (200).

[0243] The storage device (200) may include storage media for storing data in response to a request from the host device (100). As an example, the storage device (200) may include at least one of a Solid State Drive (SSD), embedded memory, and removable external memory. If the storage device (200) is an SSD, the storage device (200) may be a device that follows the NVMe (non-volatile memory express) standard. If the storage device (200) is embedded memory or external memory, the storage device (200) may be a device that follows the UFS (universal flash storage) or eMMC (embedded multi-media card) standard. The host device (100) and the storage device (200) may each generate and transmit packets according to the adopted standard protocol.

[0244] When the non-volatile memory (230) of the storage device (200) includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device (200) may include various other types of non-volatile memory. For example, the storage device (200) may be equipped with Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, and various other types of memory.

[0245] According to one embodiment, the host controller (110) and the host memory (130) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (110) and the host memory (130) may be integrated on the same semiconductor chip. As an example, the host controller (110) may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (130) may be an embedded memory provided within the application processor, or a non-volatile memory or memory module placed outside the application processor.

[0246] The host controller (110) can manage the operation of storing data (e.g., write data) of the buffer area of ​​the host memory (130) in the non-volatile memory (230) or storing data (e.g., read data) of the non-volatile memory (230) in the buffer area.

[0247] The storage controller (210) may include a host interface (211), a memory interface (216), and a CPU (central processing unit) (212). Additionally, the storage controller (210) may further include a Flash Translation Layer (FTL) (213), a packet manager (214), a buffer memory (215), an ECC (error correction code) (217) engine, and an AES (advanced encryption standard) engine (218). The storage controller (210) may further include a working memory (not shown) on which the Flash Translation Layer (FTL) (214) is loaded, and data writing and reading operations for the non-volatile memory (230) may be controlled by the central processing unit (212) executing the flash layer.

[0248] The host interface (211) can transmit and receive packets with the host device (100). The packet transmitted from the host device (100) to the host interface (211) may include a command or data to be written to the non-volatile memory (230), and the packet transmitted from the host interface (211) to the host device (100) may include a response to the command or data read from the non-volatile memory (230). The memory interface (216) can transmit data to be written to the non-volatile memory (230) to the non-volatile memory (230) or receive data read from the non-volatile memory (230). This memory interface (216) may be implemented to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0249] The flash conversion layer (213) can perform various functions such as address mapping, wear-leveling, and garbage collection. Address mapping is an operation that converts a logical address received from a host device (100) into a physical address used to actually store data in non-volatile memory (230). Wear-leveling is a technique to prevent excessive degradation of a specific block by ensuring that blocks in non-volatile memory (230) are used evenly, and can be implemented, for example, through firmware technology that balances the erase counts of physical blocks. Garbage collection is a technique to secure usable capacity in non-volatile memory (230) by copying the valid data of a block to a new block and then erasing the existing block.

[0250] The packet manager (214) can generate a packet according to the protocol of the interface agreed upon with the host device (100) or parse various information from a packet received from the host device (100). Additionally, the buffer manager (215) can temporarily store data to be written to the non-volatile memory (230) or data to be read from the non-volatile memory (230) in the buffer. The buffer may be a component provided within the storage controller (210), but it may be placed outside the storage controller (210).

[0251] The ECC engine (217) can perform error detection and correction functions for read data read from the non-volatile memory (230). More specifically, the ECC engine (217) can generate parity bits for the write data to be written to the non-volatile memory (230), and the generated parity bits can be stored in the non-volatile memory (230) together with the write data. When reading data from the non-volatile memory (230), the ECC engine (217) can correct errors in the read data using the parity bits read from the non-volatile memory (230) together with the read data, and output the read data with the errors corrected.

[0252] The AES engine (218) can perform at least one of the encryption and decryption operations on data input to the storage controller (210) using a symmetric-key algorithm.

[0253] FIG. 18b is a diagram for explaining the ECC engine (217) of FIG. 18a in more detail. Referring to FIG. 18b, the ECC engine (217) may include an ECC encoding circuit (510) and an ECC decoding circuit (520). The ECC encoding circuit (510) may generate parity bits (ECCP[0:7]) for write data (WData[0:63]) to be written to memory cells of a memory cell array (221) in response to an ECC control signal (ECC_CON). The parity bits (ECCP[0:7]) may be stored in the ECC cell array (223). According to an embodiment, the ECC encoding circuit (510) can generate parity bits (ECCP[0:7]) for write data (WData[0:63]) to be written to memory cells including defective cells of the memory cell array (221) in response to an ECC control signal (ECC_CON).

[0254] The ECC decoding circuit (520) can correct error bit data using read data (RData[0:63]) read from memory cells of the memory cell array (221) and parity bits (ECCP[0:7]) read from the ECC cell array (223) in response to the ECC control signal (ECC_CON), and output error-corrected data (Data[0:63]). According to an embodiment, the ECC decoding circuit (520) can correct error bit data using read data (RData[0:63]) read from memory cells including defective cells of the memory cell array (221) in response to the ECC control signal (ECC_CON), and parity bits (ECCP[0:7]) read from the ECC cell array (223), and output error-corrected data (Data[0:63]).

[0255] FIG. 18c is a diagram illustrating the ECC encoding circuit (510) of FIG. 18b.

[0256] Referring to FIG. 18c, the ECC encoding circuit (510) may include a parity generator (511) that receives 64-bit write data (WData[0:63]) and basis bits (Basis Bit, B[0:7]) in response to an ECC control signal (ECC_CON) and generates parity bits (ECCP[0:7]) using an XOR array operation. The basis bits (B[0:7]) are bits for generating parity bits (ECCP[0:7]) for the 64-bit write data (WData[0:63]) and may be composed of, for example, b'00000000 bits. The basis bits (B[0:7]) may use other specific bits instead of b'00000000 bits.

[0257] FIG. 18d is a diagram illustrating the ECC decoding circuit (520) of FIG. 18b.

[0258] Referring to FIG. 18d, the ECC decoding circuit (520) includes a syndrome generator (521), a counter calculator (522), a 1-bit error location detector (523), and an error corrector (524). The syndrome generator (521) can receive 64-bit readout data and 8-bit parity bits (ECCP[0:7]) in response to an ECC control signal (ECC_CON) and generate syndrome data (S[0:7]) using an XOR array operation. The counter calculator (522) can calculate the coefficients of an error location equation using the syndrome data (S[0:7]). The error location equation is an equation with roots in the reciprocals of the error bits. The 1-bit error location detector (523) can calculate the location of a 1-bit error using the calculated error location equation. The error corrector (524) can determine the 1-bit error location based on the detection result of the 1-bit error location detector (523). The error corrector (524) can correct the error by inverting the logic value of the bit where the error occurred in the 64-bit read data (RData[0:63]) according to the determined 1-bit error location information, and can output the error-corrected 64-bit data (Data[0:63]).

[0259] FIG. 18e is a drawing to explain the AES engine (218) of FIG. 18a in more detail.

[0260] The AES engine (218) can perform encryption and decryption of data using the AES (advanced encryption standard) algorithm and may include an encryption module (218a) and a decryption module (218b). FIG. 18e illustrates an encryption module (218a) and a decryption module (218b) implemented as separate modules, but alternatively, it is also possible to implement a single module capable of performing both encryption and decryption within the AES engine (218). The buffer memory (215) may be a volatile memory that serves as a buffer, but it may also be a non-volatile memory.

[0261] The AES engine (218) can receive first data transmitted from the buffer memory (215). The encryption module (218a) can generate second data by encrypting the first data transmitted from the buffer memory (215) using an encryption key. The second data can be transmitted from the AES engine (218) to the buffer memory (215) and stored in the buffer memory (215).

[0262] Additionally, the AES engine (218) can receive third data transmitted from the buffer memory (215). The third data may be data encrypted with the same encryption key as the encryption key used to encrypt the first data. The decryption module (218b) can generate fourth data by decrypting the third data transmitted from the buffer memory (215) with the same encryption key as the encryption key used to encrypt the first data. The fourth data may be transmitted from the AES engine (218) to the buffer memory (215) and stored in the buffer memory (215).

[0263] FIG. 19 is a block diagram showing a memory system (15) according to an exemplary embodiment of the present disclosure.

[0264] Referring to FIG. 19, the memory system (15) may include a memory device (17) and a memory controller (16). The memory system (15) may support a plurality of channels (CH1 to CHm), and the memory device (17) and the memory controller (16) may be connected through the plurality of channels (CH1 to CHm). For example, the memory system (15) may be implemented as a storage device such as a Solid State Drive (SSD).

[0265] The memory device (17) may include a plurality of non-volatile memory devices (NVM11 to NVMmn). Each of the non-volatile memory devices (NVM11 to NVMmn) may be connected to one of a plurality of channels (CH1 to CHm) through a corresponding way. For example, the non-volatile memory devices (NVM11 to NVM1n) may be connected to a first channel (CH1) through ways (W11 to W1n), and the non-volatile memory devices (NVM21 to NVM2n) may be connected to a second channel (CH2) through ways (W21 to W2n). In an exemplary embodiment, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as any memory unit capable of operating according to individual commands from the memory controller (16). For example, each of the non-volatile memory devices (NVM11–NVMmn) may be implemented as a chip or a die, but the present disclosure is not limited thereto.

[0266] The memory controller (16) can transmit and receive signals to and from the memory device (17) through multiple channels (CH1~CHm). For example, the memory controller (16) can transmit commands (CMDa~CMDm), addresses (ADDRa~ADDRm), and data (DATAa~DATAm) to the memory device (17) through the channels (CH1~CHm), or receive data (DATAa~DATAm) from the memory device (17).

[0267] The memory controller (16) can select one of the non-volatile memory devices (NVM11 to NVMmn) connected to the respective channel through each channel and transmit and receive signals with the selected non-volatile memory device. For example, the memory controller (16) can select a non-volatile memory device (NVM11) among the non-volatile memory devices (NVM11 to NVM1n) connected to the first channel (CH1). The memory controller (16) can transmit a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory device (NVM11) through the first channel (CH1), or receive data (DATAa) from the selected non-volatile memory device (NVM11).

[0268] The memory controller (16) can transmit and receive signals to and from the memory device (17) in parallel through different channels. For example, the memory controller (16) can transmit a command (CMDb) to the memory device (17) through a second channel (CH2) while transmitting a command (CMDa) to the memory device (17) through a first channel (CH1). For example, the memory controller (16) can receive data (DATAb) from the memory device (17) through a second channel (CH2) while receiving data (DATAa) from the memory device (17) through a first channel (CH1).

[0269] The memory controller (16) can control the overall operation of the memory device (17). The memory controller (16) can control each of the non-volatile memory devices (NVM11~NVMmn) connected to the channels (CH1~CHm) by transmitting signals to the channels (CH1~CHm). For example, the memory controller (16) can control one of the selected non-volatile memory devices (NVM11~NVM1n) by transmitting a command (CMDa) and an address (ADDRa) to the first channel (CH1).

[0270] Each of the non-volatile memory devices (NVM11 to NVMmn) can operate under the control of the memory controller (16). For example, the non-volatile memory device (NVM11) can program data (DATAa) according to a command (CMDa) and an address (ADDRa) provided through the first channel (CH1). For example, the non-volatile memory device (NVM21) can read data (DATAb) according to a command (CMDb) and an address (ADDRb) provided through the second channel (CH2), and transmit the read data (DATAb) to the memory controller (16).

[0271] FIG. 19 illustrates that a memory device (17) communicates with a memory controller (16) through m channels, and that the memory device (17) includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to one channel can be varied.

[0272] FIG. 20 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure.

[0273] Referring to FIG. 20, the memory system may include a memory device (300) and a memory controller (400). The storage device (200) of FIG. 1 may be applied to the memory system of FIG. 20. The memory device (300) may correspond to one of the non-volatile memory devices (NVM11~NVMmn) that communicate with the memory controller (400) based on one of the plurality of channels (CH1~CHm) of FIG. 19. The memory controller (400) may correspond to the memory controller (16) of FIG. 19.

[0274] The memory device (300) may include first to eighth pins (P11 to P18), a memory interface circuit (310), a control logic circuit (320), and a memory cell array (330).

[0275] The memory interface circuit (310) can receive a chip enable signal (nCE) from the memory controller (400) through the first pin (P11). The memory interface circuit (310) can transmit and receive signals with the memory controller (400) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface circuit (310) can transmit and receive signals with the memory controller (400) through the second to eighth pins (P12 to P18).

[0276] The memory interface circuit (310) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the memory controller (400) through the second to fourth pins (P12 to P14). The memory interface circuit (310) can receive a data signal (DQ) from the memory controller (400) or transmit a data signal (DQ) to the memory controller (400) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals (DQ).

[0277] The memory interface circuit (310) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface circuit (310) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0278] In an exemplary embodiment, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface circuit (310) may obtain a command (CMD) or an address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0279] The memory interface circuit (310) can receive a read enable signal (nRE) from the memory controller (400) through the fifth pin (P15). The memory interface circuit (310) can receive a data strobe signal (DQS) from the memory controller (400) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the memory controller (400).

[0280] In the data (DATA) output operation of the memory device (300), the memory interface circuit (310) may receive a read-enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface circuit (310) may generate a data strobe signal (DQS) that toggles based on the toggling of the read-enable signal (nRE). For example, the memory interface circuit (310) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read-enable signal (nRE). The memory interface circuit (310) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, the data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the memory controller (400).

[0281] In the data (DATA) input operation of the memory device (300), when a data signal (DQ) containing data (DATA) is received from the memory controller (400), the memory interface circuit (310) can receive a data strobe signal (DQS) that toggles along with the data (DATA) from the memory controller (400). The memory interface circuit (310) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface circuit (310) can acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0282] The memory interface circuit (310) can transmit a ready / busy output signal (nR / B) to the memory controller (400) through the eighth pin (P18). The memory interface circuit (310) can transmit status information of the memory device (300) to the memory controller (400) through the ready / busy output signal (nR / B). When the memory device (300) is in a busy state (i.e., when internal operations of the memory device (300) are being performed), the memory interface circuit (310) can transmit a ready / busy output signal (nR / B) indicating the busy state to the memory controller (400). When the memory device (300) is in a ready state (i.e., when internal operations of the memory device (300) are not being performed or have been completed), the memory interface circuit (310) can transmit a ready / busy output signal (nR / B) indicating the ready state to the memory controller (400). For example, while the memory device (300) reads data (DATA) from the memory cell array (330) in response to a page read command, the memory interface circuit (310) can transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the memory controller (400). For example, while the memory device (300) programs data (DATA) into the memory cell array (330) in response to a program command, the memory interface circuit (310) can transmit a ready / busy output signal (nR / B) indicating a busy state to the memory controller (400).

[0283] The control logic circuit (320) can control various operations of the memory device (300) overall. The control logic circuit (320) can receive a command / address (CMD / ADDR) obtained from the memory interface circuit (310). The control logic circuit (320) can generate control signals to control other components of the memory device (300) according to the received command / address (CMD / ADDR). For example, the control logic circuit (320) can generate various control signals to program data (DATA) into the memory cell array (330) or to read data (DATA) from the memory cell array (330).

[0284] The memory cell array (330) can store data (DATA) obtained from the memory interface circuit (310) under the control of the control logic circuit (320). The memory cell array (330) can output the stored data (DATA) to the memory interface circuit (310) under the control of the control logic circuit (320).

[0285] The memory cell array (330) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present disclosure is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present disclosure will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0286] The memory controller (400) may include first to eighth pins (P21 to P28) and a controller interface circuit (410). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the memory device (300).

[0287] The controller interface circuit (410) can transmit a chip enable signal (nCE) to the memory device (300) through the first pin (P21). The controller interface circuit (410) can transmit and receive signals to and from the selected memory device (300) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0288] The controller interface circuit (410) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the memory device (300) through the second to fourth pins (P22 to P24). The controller interface circuit (410) can transmit a data signal (DQ) to the memory device (300) or receive a data signal (DQ) from the memory device (300) through the seventh pin (P27).

[0289] The controller interface circuit (410) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (300) along with a toggling write enable signal (nWE). The controller interface circuit (410) can transmit a data signal (DQ) containing a command (CMD) to the memory device (300) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (300) by transmitting an address latch enable signal (ALE) having an enable state.

[0290] The controller interface circuit (410) can transmit a read-enable signal (nRE) to the memory device (300) through the fifth pin (P25). The controller interface circuit (410) can receive a data strobe signal (DQS) from the memory device (300) or transmit a data strobe signal (DQS) to the memory device (300) through the sixth pin (P26).

[0291] In the data (DATA) output operation of the memory device (300), the controller interface circuit (410) can generate a toggling read-enable signal (nRE) and transmit the read-enable signal (nRE) to the memory device (300). For example, the controller interface circuit (410) can generate a read-enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) can be generated in the memory device (300) based on the read-enable signal (nRE). The controller interface circuit (410) can receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the memory device (300). The controller interface circuit (410) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0292] In the data (DATA) input operation of the memory device (300), the controller interface circuit (410) can generate a toggling data strobe signal (DQS). For example, the controller interface circuit (410) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the controller interface circuit (410) can transmit a data signal (DQ) containing the data (DATA) to the memory device (300).

[0293] The controller interface circuit (410) can receive a ready / busy output signal (nR / B) from the memory device (300) through the eighth pin (P28). The controller interface circuit (410) can determine the status information of the memory device (300) based on the ready / busy output signal (nR / B).

[0294] FIG. 21 is a block diagram showing a memory device (300) according to an exemplary embodiment of the present disclosure.

[0295] Referring to FIG. 21, the memory device (300) may include a control logic circuit (320), a memory cell array (330), a page buffer (340), a voltage generator (350), and a row decoder (360). Although not shown in FIG. 21, the memory device (300) may further include a memory interface circuit (310) shown in FIG. 21, and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0296] The control logic circuit (320) can control various operations within the memory device (300) overall. The control logic circuit (320) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the memory interface circuit (310). For example, the control logic circuit (320) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0297] The memory cell array (330) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (330) may be connected to a page buffer (340) via bit lines (BL) and may be connected to a row decoder (360) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0298] In an exemplary embodiment, the memory cell array (330) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (330) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0299] The page buffer (340) may include a plurality of page buffers (PB1 to PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer (340) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer (340) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer (340) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer (340) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0300] The voltage generator (350) can generate various types of voltages to perform program, readout, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (350) can generate a program voltage, a readout voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0301] The row decoder (360) can select one of a plurality of word lines (WL) and one of a plurality of string selection lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (360) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0302] FIG. 22 is a drawing for explaining a 3D V-NAND structure that can be applied to a UFS device according to an exemplary embodiment of the present disclosure.

[0303] When the storage module of a UFS device is implemented as a 3D V-NAND type flash memory, each of the multiple memory blocks constituting the storage module can be represented by an equivalent circuit as shown in FIG. 22.

[0304] The memory block (BLKi) illustrated in FIG. 22 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block (BLKi) may be formed in a direction perpendicular to the substrate.

[0305] Referring to FIG. 22, a memory block (BLKi) may include a plurality of memory NAND strings (NS11 to NS33) connected between bit lines (BL1, BL2, BL3) and a common source line (CSL). Each of the plurality of memory NAND strings (NS11 to NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground select transistor (GST). FIG. 22 illustrates that each of the plurality of memory NAND strings (NS11 to NS33) includes eight memory cells (MC1, MC2, ..., MC8), but is not necessarily limited thereto.

[0306] A string select transistor (SST) can be connected to corresponding string select lines (SSL1, SSL2, SSL3). Multiple memory cells (MC1, MC2, ..., MC8) can each be connected to corresponding gate lines (GTL1, GTL2, ..., GTL8). The gate lines (GTL1, GTL2, ..., GTL8) may correspond to word lines, and some of the gate lines (GTL1, GTL2, ..., GTL8) may correspond to dummy word lines. A ground select transistor (GST) can be connected to corresponding ground select lines (GSL1, GSL2, GSL3). A string select transistor (SST) is connected to corresponding bit lines (BL1, BL2, BL3), and a ground select transistor (GST) can be connected to a common source line (CSL).

[0307] Word lines of the same height (e.g., WL1) are connected in common, and ground select lines (GSL1, GSL2, GSL3) and string select lines (SSL1, SSL2, SSL3) can be separated. FIG. 22 shows a memory block (BLK) connected to eight gate lines (GTL1, GTL2, ..., GTL8) and three bit lines (BL1, BL2, BL3), but is not necessarily limited thereto.

[0308] FIG. 23 is a cross-sectional view showing a memory device (600) according to an exemplary embodiment of the present disclosure. The non-volatile memory (230) of FIG. 1 may be applied to the memory device (600) of FIG. 23.

[0309] Referring to FIG. 23, the memory device (600) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell region (CELL) on a first wafer, fabricating a lower chip containing a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0310] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (600) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA). The peripheral circuit region (PERI) may include a first substrate (710), an interlayer insulating layer (715), a plurality of circuit elements (720a, 720b, 720c) formed on the first substrate (710), a first metal layer (730a, 730b, 730c) connected to each of the plurality of circuit elements (720a, 720b, 720c), and a second metal layer (740a, 740b, 740c) formed on the first metal layer (730a, 730b, 730c). In one embodiment, the first metal layer (730a, 730b, 730c) may be formed of tungsten, which has relatively high resistance, and the second metal layer (740a, 740b, 740c) may be formed of copper, which has relatively low resistance.

[0311] In this specification, only the first metal layer (730a, 730b, 730c) and the second metal layer (740a, 740b, 740c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (740a, 740b, 740c). At least some of the one or more metal layers formed on the upper part of the second metal layer (740a, 740b, 740c) may be formed of aluminum or the like, having a lower resistance than the copper forming the second metal layer (740a, 740b, 740c).

[0312] The interlayer insulating layer (715) is disposed on a first substrate (710) to cover a plurality of circuit elements (720a, 720b, 720c), a first metal layer (730a, 730b, 730c), and a second metal layer (740a, 740b, 740c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0313] A lower bonding metal (771b, 772b) may be formed on the second metal layer (740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (871b, 872b) of the cell region (CELL) by a bonding method, and the lower bonding metal (771b, 772b) and the upper bonding metal (871b, 872b) may be formed of aluminum, copper, or tungsten, etc. The upper bonding metal (871b, 872b) of the cell region (CELL) may be referred to as the first metal pads, and the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be referred to as the second metal pads.

[0314] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (810) and a common source line (820). On the second substrate (810), a plurality of word lines (831-838; 830) may be stacked along a direction perpendicular to the upper surface of the second substrate (810) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (830), respectively, and a plurality of word lines (830) may be disposed between the string selection lines and the ground selection lines.

[0315] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (810) and penetrate word lines (830), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (850c) and a second metal layer (860c). For example, the first metal layer (850c) may be a bitline contact, and the second metal layer (860c) may be a bitline. In one embodiment, the bitline may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (810).

[0316] In one embodiment illustrated in FIG. 23, the area where the channel structure (CH) and bitlines are placed may be defined as a bitline bonding area (BLBA). The bitlines may be electrically connected to circuit elements (720c) that provide a page buffer (893) in the peripheral circuit area (PERI) in the bitline bonding area (BLBA). As an example, the bitlines may be connected to upper bonding metals (871c, 872c) in the peripheral circuit area (PERI), and the upper bonding metals (871c, 872c) may be connected to lower bonding metals (771c, 772c) that are connected to circuit elements (720c) of the page buffer (893).

[0317] In the wordline bonding area (WLBA), wordlines (830) may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate (810) and may be connected to a plurality of cell contact plugs (841-847; 840). The wordlines (830) and the cell contact plugs (840) may be connected to each other at pads provided by extending at least some of the wordlines (830) at different lengths along the second direction (X-axis direction). A first metal layer (850b) and a second metal layer (860b) may be connected in sequence to the upper portion of the cell contact plugs (840) connected to the wordlines (830). The cell contact plugs (840) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (871b, 872b) of the cell area (CELL) and the lower bonding metal (771b, 772b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0318] Cell contact plugs (840) may be electrically connected to circuit elements (720b) ​​that provide a row decoder (894) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (720b) ​​that provide the row decoder (894) may be different from the operating voltage of the circuit elements (720c) that provide the page buffer (893). For example, the operating voltage of the circuit elements (720c) that provide the page buffer (893) may be greater than the operating voltage of the circuit elements (720b) ​​that provide the row decoder (894).

[0319] A common source line contact plug (880) may be disposed in the external pad bonding area (PA). The common source line contact plug (880) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to the common source line (820). A first metal layer (850a) and a second metal layer (860a) may be sequentially laminated on top of the common source line contact plug (880). For example, the area where the common source line contact plug (880), the first metal layer (850a), and the second metal layer (860a) are disposed may be defined as the external pad bonding area (PA).

[0320] Meanwhile, input / output pads (705, 805) may be disposed in the external pad bonding area (PA). Referring to FIG. 23, a lower insulating film (701) covering the lower surface of the first substrate (710) may be formed on the lower surface of the first substrate (710), and a first input / output pad (705) may be formed on the lower insulating film (701). The first input / output pad (705) is connected to at least one of a plurality of circuit elements (720a, 720b, 720c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (703), and may be separated from the first substrate (710) by the lower insulating film (701). Additionally, a side insulating film is disposed between the first input / output contact plug (703) and the first substrate (710) to electrically separate the first input / output contact plug (703) and the first substrate (710).

[0321] Referring to FIG. 23, an upper insulating film (801) covering the upper surface of the second substrate (810) may be formed on the upper surface of the second substrate (810), and a second input / output pad (805) may be disposed on the upper insulating film (801). The second input / output pad (805) may be connected to at least one of a plurality of circuit elements (720a, 720b, 720c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (803).

[0322] According to the embodiments, the second substrate (810) and common source line (820), etc., may not be placed in the area where the second input / output contact plug (803) is placed. Additionally, the second input / output pad (805) may not overlap with the word lines (830) in the third direction (Z-axis direction). Referring to FIG. 23, the second input / output contact plug (803) is separated from the second substrate (810) in a direction parallel to the upper surface of the second substrate (810) and may be connected to the second input / output pad (805) by penetrating the interlayer insulating layer (815) of the cell area (CELL).

[0323] According to embodiments, the first input / output pad (705) and the second input / output pad (805) may be formed optionally. For example, the memory device (600) may include only the first input / output pad (705) disposed on the upper part of the first substrate (710), or only the second input / output pad (805) disposed on the upper part of the second substrate (810). Alternatively, the memory device (600) may include both the first input / output pad (705) and the second input / output pad (805).

[0324] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0325] The memory device (600) may form a lower metal pattern (773a) of the same shape as the upper metal pattern (872a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (872a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (773a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern of the same shape as the lower metal pattern of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern formed on the upper metal layer of the peripheral circuit region (PERI).

[0326] A lower bonding metal (771b, 772b) may be formed on the second metal layer (740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (871b, 872b) of the cell region (CELL) by a bonding method.

[0327] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (892) of the same shape as the lower metal pattern (752) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (752) formed on the upper metal layer of the peripheral circuit area (PERI). In an exemplary embodiment, a contact may not be formed on the upper metal pattern (892) formed on the upper metal layer of the cell area (CELL).

[0328] In an exemplary embodiment, corresponding to a metal pattern formed on the uppermost metal layer of one of the cell region (CELL) and peripheral circuit region (PERI), a reinforced metal pattern having the same cross-sectional shape as the formed metal pattern may be formed on the uppermost metal layer of the other of the cell region (CELL) and peripheral circuit region (PERI). Contacts may not be formed in the reinforced metal pattern.

[0329] FIG. 24 is a drawing showing a data center to which a host storage system (Fig. 1, 10) according to an exemplary embodiment of the present disclosure is applied.

[0330] Referring to FIG. 24, the data center (3000) is a facility that collects various data and provides services, and may be referred to as a data storage center. The data center (3000) may be a system for operating search engines and databases, and may be a computing system used by companies such as banks or government agencies. The data center (3000) may include application servers (3100 to 3100n) and storage servers (3200 to 3200m). The number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) may be selected in various ways according to the embodiment, and the number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) may differ from each other.

[0331] The application server (3100) or storage server (3200) may include at least one of a processor (3110, 3210) and memory (3120, 3220). To describe the storage server (3200) as an example, the processor (3210) can control the overall operation of the storage server (3200) and can access the memory (3220) to execute instructions and / or data loaded in the memory (3220). The memory (3220) may be DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, and / or NVMDIMM (Non-Volatile DIMM). Depending on the embodiment, the number of processors (3210) and the number of memory (3220) included in the storage server (3200) may be selected in various ways. In one embodiment, the processor (3210) and memory (3220) may provide a processor-memory pair. In one embodiment, the number of processors (3210) and memory (3220) may differ. The processor (3210) may include a single-core processor or a multi-core processor. The above description of the storage server (3200) may similarly apply to the application server (3100). Depending on the embodiment, the application server (3100) may not include a storage device (3150). The storage server (3200) may include at least one storage device (3250). The number of storage devices (3250) included in the storage server (3200) may be selected differently depending on the embodiment.

[0332] Application servers (3100 to 3100n) and storage servers (3200 to 3200m) can communicate with each other through a network (3300). The network (3300) can be implemented using Fibre Channel (FC) or Ethernet, etc. In this case, FC is a medium used for relatively high-speed data transmission, and an optical switch providing high performance / high availability can be used. Depending on the access method of the network (3300), the storage servers (3200 to 3200m) can be provided as file storage, block storage, or object storage.

[0333] In one embodiment, the network (3300) may be a storage-dedicated network such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN that utilizes an FC network and is implemented according to the FC Protocol (FCP). As another example, the SAN may be an IP-SAN that utilizes a TCP / IP network and is implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In another embodiment, the network (3300) may be a general network such as a TCP / IP network. For example, the network (3300) may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0334] Hereinafter, the description will focus on the application server (3100) and the storage server (3200). The description of the application server (3100) may also apply to other application servers (3100n), and the description of the storage server (3200) may also apply to other storage servers (3200m).

[0335] The application server (3100) can store data requested for storage by a user or client in one of the storage servers (3200 to 3200m) via the network (3300). Additionally, the application server (3100) can obtain data requested for reading by a user or client from one of the storage servers (3200 to 3200m) via the network (3300). For example, the application server (3100) can be implemented as a web server or a DBMS (Database Management System), etc.

[0336] The application server (3100) can access memory (3120n) or storage device (3150n) contained in another application server (3100n) via the network (3300), or can access memory (3220-3220m) or storage device (3250-3250m) contained in storage servers (3200-3200m) via the network (3300). Thus, the application server (3100) can perform various operations on data stored in the application servers (3100-3100n) and / or storage servers (3200-3200m). For example, the application server (3100) can execute commands to move or copy data between the application servers (3100-3100n) and / or storage servers (3200-3200m). At this time, data may be moved from the storage devices (3250-3250m) of the storage servers (3200-3200m) through the memories (3220-3220m) of the storage servers (3200-3200m), or directly to the memories (3120-3120n) of the application servers (3100-3100n). Data moving through the network (3300) may be encrypted data for security or privacy.

[0337] To illustrate with an example of a storage server (3200), the interface (3254) can provide a physical connection between the processor (3210) and the controller (3251) and a physical connection between the Network Interconnect (NIC) (3240) and the controller (3251). For example, the interface (3254) can be implemented in a Direct Attached Storage (DAS) manner, which directly connects the storage device (3250) with a dedicated cable. Additionally, for example, the interface (3254) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), and / or CF (compact flash) card interface.

[0338] The storage server (3200) may further include a switch (3230) and a NIC (3240). The switch (3230) may selectively connect the processor (3210) and the storage device (3250) or selectively connect the NIC (3240) and the storage device (3250) under the control of the processor (3210).

[0339] In one embodiment, the NIC (3240) may include a network interface card, a network adapter, etc. The NIC (3240) may be connected to a network (3300) by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC (3240) may include internal memory, a Digital Signal Processor (DSP), a host bus interface, etc., and may be connected to a processor (3210) and / or a switch (3230), etc., through the host bus interface. The host bus interface may be implemented as one of the examples of the interface (3254) described above. In one embodiment, the NIC (3240) may be integrated with at least one of a processor (3210), a switch (3230), and a storage device (3250).

[0340] In storage servers (3200-3200m) or application servers (3100-3100n), a processor may program or read data by sending a command to a storage device (3150-3150n, 3250-3250m) or memory (3120-3120n, 3220-3220m). The data may be data that has been error-corrected through an Error Correction Code (ECC) engine. The data may be data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) processing and may include Cyclic Redundancy Code (CRC) information. The data may be data that has been encrypted for security or privacy.

[0341] The storage device (3150-3150n, 3250-3250m) can transmit a control signal and a command / address signal to the NAND flash memory device (3252-3252m) in response to a read command received from the processor. Accordingly, when reading data from the NAND flash memory device (3252-3252m), the RE (Read Enable) signal is input as a data output control signal and can serve to output data to the DQ bus. A DQS (Data Strobe) can be generated using the RE signal. The command and address signals can be latched in the page buffer according to the rising edge or falling edge of the WE (Write Enable) signal.

[0342] The controller (3251) can control the overall operation of the storage device (3250). In one embodiment, the controller (3251) may include a Static Random Access Memory (SRAM). The controller (3251) can write data to the NAND flash (3252) in response to a write command, or read data from the NAND flash (3252) in response to a read command. For example, the write command and / or read command may be provided by a processor (3210) in the storage server (3200), a processor (3210m) in another storage server (3200m), or a processor (3110, 3110n) in the application server (3100, 3100n). The DRAM (3253) may temporarily store (buffer) data to be written to the NAND flash (3252) or data read from the NAND flash (3252). Additionally, the DRAM (3253) can store metadata. Here, the metadata is data generated by the controller (3251) to manage user data or NAND flash (3252). The storage device (3250) may include a Secure Element (SE) for security or privacy.

[0343] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A device comprising: a memory including a plurality of queues; and a controller, wherein the controller comprises: a doorbell register configured to store a head pointer and a tail pointer of each of the plurality of queues; an entry buffer configured to store a first command or a first response included in the plurality of queues; an arbitrator configured to arbitrate the order of the plurality of queues; a first router configured to route the first command so that it can be stored in the entry buffer according to the order; and a second router configured to store a pointer of the first response as the tail pointer in the doorbell register. Claim 2 A device according to claim 1, characterized in that the plurality of queues are a plurality of circular queues. Claim 3 An apparatus according to claim 1, wherein the plurality of queues include a submission queue and a completion queue, and the doorbell register stores a first head pointer and a first tail pointer for the submission queue, and a second head pointer and a second tail pointer for the completion queue. Claim 4 A device according to paragraph 3, wherein the first head pointer is updated as the first command is stored in the entry buffer. Claim 5 A device according to paragraph 3, wherein the second tail pointer is updated as the first response is stored in the completion queue. Claim 6 A device according to claim 1, further comprising a bitmap doorbell register configured to indicate whether the entry buffer can be stored using a bitmap. Claim 7 A device according to claim 6, wherein the bitmap doorbell register changes bit information corresponding to the data area where the first command or the first response is stored from bit 0 to bit 1 based on the fact that the first command or the first response is stored in the entry buffer. Claim 8 The apparatus according to claim 1, wherein the controller comprises a first core for processing a first submission queue and a first completion queue, and a second core for processing a second submission queue and a second completion queue, and the arbitrator is characterized by processing the queue with the higher priority among the first submission queue and the second submission queue first. Claim 9 A device according to claim 8, wherein the priority is determined based on whether a priority processing flag is attached to the first submission queue or the second submission queue, whether it was entered first, whether there is insufficient empty space, whether the weight is high, or whether it has been predetermined as a high priority. Claim 10 A storage system comprising a host device and a storage device, wherein the host device transmitting a command to the storage device comprises: a host memory storing at least one queue; and a host controller comprising at least one core configured to process the at least one queue and a host controller interface configured to provide interfacing with the host memory, wherein the storage device provides a response to the host device which is the result of performing a memory operation based on the command, and the host controller interface comprises a doorbell register storing a head pointer and a tail pointer for the at least one queue. Claim 11 A storage system according to claim 10, wherein at least one queue comprises a submission queue and a completion queue, and the doorbell register stores a first head pointer and a first tail pointer for the submission queue, and a second head pointer and a second tail pointer for the completion queue. Claim 12 A storage system according to claim 11, wherein the first head pointer is updated as the command is stored in an entry buffer included in the host controller. Claim 13 A storage system according to claim 11, wherein the second tail pointer is updated as the response is stored in the completion queue. Claim 14 A storage system according to claim 10, wherein the host controller interface further comprises: an entry buffer configured to store the command or the response; an arbitrator configured to arbitrate the order of the at least one queue; a first router configured to route the command so that it can be stored in the entry buffer in order; and a second router configured to route the response so that it can be stored in the doorbell register. Claim 15 A storage system according to claim 14, wherein the at least one core comprises a first core for processing a first submission queue and a first completion queue, and a second core for processing a second submission queue and a second completion queue, and wherein the arbitrator processes the queue with the higher priority among the first submission queue and the second submission queue first. Claim 16 A method of operation of a host controller interface configured to provide interfacing between a host device and a storage device using at least one queue containing at least one command, comprising: a step of mediating the order of a first queue containing a first command and a second queue containing a second command; a step of storing the first command in an entry buffer; a step of updating a first head pointer of the first queue; a step of storing the second command in the entry buffer; a step of updating a second head pointer of the second queue containing the second command; and a step of providing the first command and the second command sequentially to the storage device. Claim 17 A method of operation of a host controller interface according to claim 16, wherein the above-mentioned arbitration step includes the step of processing the queue with the higher priority first among the first queue and the second queue. Claim 18 A method of operation of a host controller interface according to claim 17, wherein the step of processing a high-priority queue first comprises: a step of determining whether a priority processing flag is attached to the first queue and the second queue; a step of determining the queue that was entered first among the first queue and the second queue; and a step of determining the queue among the first queue and the second queue that has insufficient empty space. Claim 19 A method of operation of a host controller interface according to claim 17, wherein the step of processing high-priority queues first includes the step of processing queues sequentially in the order they are input for a uniform amount of time. Claim 20 A method of operation of a host controller interface according to claim 17, wherein the step of processing high-priority queues first includes: a step of checking a weight per queue assigned according to importance; and a step of processing queues in order of increasing weight.

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