Method of manufacturing semiconductor device

Abstract

The technical concept of the present invention provides a method for manufacturing a semiconductor device comprising: a step of forming a gate insulating film on a semiconductor substrate including a first region and a second region; a step of forming a polysilicon film on the gate insulating film; a step of forming a first mask pattern that covers the entire upper surface of the polysilicon film of the first region and a step of forming a second mask pattern that partially covers the upper surface of the polysilicon film of the second region; and a step of ion-implanting an impurity into the second region; wherein the first and second mask patterns are used as ion-implantation masks.

Description

Technology Field

[0001] The technical concept of the present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a gate of a DRAM semiconductor device. Background Technology

[0002] The integration density of semiconductor devices, such as DRAM, is increasing day by day. Consequently, as the integration density of semiconductor devices increases, the gate area must decrease, and the gate height must also be continuously reduced. However, if the thickness of the polysilicon film is reduced to lower the gate height, P-type impurities can penetrate into the gate insulating film during the dual polysilicon gate manufacturing process. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor device capable of preventing P-type impurities from penetrating into a gate insulating film. means of solving the problem

[0004] To solve the above-mentioned problem, the technical concept of the present invention provides a method for manufacturing a semiconductor device comprising: a step of forming a gate insulating film on a semiconductor substrate including a first region and a second region; a step of forming a polysilicon film on the gate insulating film; a step of forming a first mask pattern that covers the entire upper surface of the polysilicon film of the first region and a step of forming a second mask pattern that partially covers the upper surface of the polysilicon film of the second region; and a step of ion-implanting an impurity into the second region; wherein the first and second mask patterns are used as ion-implantation masks. Effects of the invention

[0005] In addition, the semiconductor device manufacturing method according to the technical concept of the present invention partially covers a mask pattern on a polysilicon film to prevent impurities from penetrating into the gate insulating film, thereby enabling the easy implementation of a high-performance and high-reliability logic device.

[0006] A semiconductor device manufacturing method according to the technical concept of the present invention enables the easy realization of a high-performance and high-reliability logic device by controlling the vertical movement of ions injected into each polysilicon film in a logic device having a plurality of types of MOS, such as NMOS, PMOS, and CMOS, on a substrate. Brief explanation of the drawing

[0007] FIGS. 1a to 1e are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3 is a schematic diagram showing the diffusion of ions within a second polysilicon film during an ion implantation process on a second region according to an embodiment of the present invention. FIGS. 4a to 4d are drawings showing a second mask pattern disposed on a second polysilicon film according to one embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Specific details for implementing the invention

[0008] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0009] FIGS. 1a to 1e are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0010] Hereinafter, a method for manufacturing a CMOS (Complementary-MOS) transistor will be described with reference to FIGS. 1a to 1e. However, the present invention is not limited to a method for manufacturing a CMOS transistor and may also be applied to a method for manufacturing a semiconductor device. The semiconductor device may be used in a semiconductor device such as a DRAM.

[0011] In the above semiconductor device, P-type impurities can diffuse in the vertical direction (Z direction) and horizontal direction (X direction, Y direction, diagonal direction) from the polysilicon film (130), so that the P-type impurities do not penetrate into the gate insulating film (110). Accordingly, the threshold voltage of the PMOS region can be uniformly lowered, thereby enabling the implementation of a semiconductor device capable of driving at a low voltage. Furthermore, the reduction in the defect rate caused by the dispersion of the transistor threshold voltage in the semiconductor device can be suppressed.

[0012] Referring to FIG. 1a, a gate insulating film (110) can be formed on a semiconductor substrate (100) (S110). The semiconductor substrate (100) includes a first region (R1) where an NMOS (N-channel MOS) transistor is formed and a second region (R2) where a PMOS (P-channel) transistor is formed.

[0013] That is, the first region (R1) may be an NMOS region, and the second region (R2) may be a PMOS region. Specifically, the NMOS region may be limited by a P-type well, and the PMOS region may be limited by an N-type well. In another embodiment, that is, the first region (R1) may be a PMOS region, and the second region (R2) may be an NMOS region. An isolation process may be performed on the semiconductor substrate (100). According to one embodiment of the present invention, the first region (R1) and the second region (R2) may be spaced apart in a horizontal direction (X direction, Y direction, diagonal direction). Therefore, when an impurity is injected into the first region (R1) or the second region (R2), the impurity may not spread horizontally to the other region.

[0014] The semiconductor substrate (100) may be formed from a wafer of a group IV material, such as a silicon wafer, or a wafer of a group III-V compound. Additionally, the semiconductor substrate (100) may be formed from a single-crystal wafer, such as a silicon single-crystal wafer. However, the semiconductor substrate (100) is not limited to a single-crystal wafer, and various wafers such as an epitaxial wafer, a polished wafer, an annealed wafer, and an SOI (Silicon On Insulator) wafer may be used as the semiconductor substrate (100). Here, an epitaxial wafer refers to a wafer in which a crystalline material is grown on a single-crystal silicon substrate.

[0015] In some embodiments, the semiconductor substrate (100) may comprise silicon (Si). In other embodiments, the semiconductor substrate (100) may comprise a semiconductor element such as germanium (Ge), or a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the semiconductor substrate (100) may have a Silicon On Insulator (SOI) structure. For example, the semiconductor substrate (100) may comprise a buried oxide layer. In some embodiments, the semiconductor substrate (100) may comprise a conductive region, e.g., an impurity-doped well, or an impurity-doped structure. Depending on the type of impurity ion being doped, the semiconductor substrate (100) may be a P-type substrate or an N-type substrate.

[0016] A gate insulating film (110) can be formed on a semiconductor substrate (100). Specifically, the gate insulating film (110) can be formed on the semiconductor substrate (100) using atomic layer deposition (ALD) or chemical vapor deposition (CVD), etc.

[0017] Here, the gate insulating film (110) may be a high-k material such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), lanthanum oxide (La2O3), etc. Additionally, the gate insulating film (110) may be a dielectric material such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), etc. In one embodiment of the present invention, the overall size of the semiconductor device can be reduced by using a high-k material to reduce the thickness of the gate insulating film (110).

[0018] Referring to FIG. 1b, a barrier layer (120) may be formed on a gate insulating film (110) (S120). The barrier layer (120) may contain inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride, or organic materials such as polyimide, polyester, or acrylic, and may be formed as a plurality of laminates among the materials exemplified.

[0019] The barrier layer (120) can increase the dielectric constant of the gate insulating film (110). Additionally, the barrier layer (120) can be configured to prevent impurities from penetrating into the gate insulating film (110) in the future.

[0020] Referring to FIG. 1c, a polysilicon film (130) may be formed on the barrier layer (120) (S130). The polysilicon film (130) may include a first polysilicon film (130-1) disposed on a first region (R1) and a second polysilicon film (130-2) disposed on a second region (R2). For example, the polysilicon film (130) may contain N-type impurities. The N-type impurities may include Group 5 elements such as phosphorus (P), arsenic (As), and / or antimony (Sb).

[0021] Referring to FIG. 1d, a mask pattern (140) may be formed on the polysilicon film (130) (S140). The mask pattern (140) may include a first mask pattern (140-1) placed on a first region (R1) and a second mask pattern (140-2) placed on a second region (R2). The mask pattern (140) may include, for example, a hard mask such as photoresist (PR) or a soft mask such as a silicon nitride film and / or SiO2. The mask pattern (140) may serve as an ion-implantation mask.

[0022] According to one embodiment of the present invention, the first mask pattern (140-1) can cover the entire upper surface of the polysilicon film (130) on the first region (R1). That is, the first mask pattern (140-1) can cover the entire upper surface of the first polysilicon film (130-1). Additionally, the second mask pattern (140-2) can partially cover the upper surface of the polysilicon film (130) on the second region (R2). That is, the second mask pattern (140-2) can partially cover the upper surface of the second polysilicon film (130-2). Since the first mask pattern (140-1) covers the entire upper surface of the first polysilicon film (130-1), impurities may not be injected into the first polysilicon film (130-1). Additionally, the second mask pattern (140-2) partially covers the upper surface of the second polysilicon film (130-2), so that impurities can be injected into the second polysilicon film (130-2). That is, the mask pattern (140) can be patterned in a way that only opens the polysilicon film (130) to be ion-implanted.

[0023] For example, the thickness range of the second mask pattern (140-2) may be approximately 300 nm to approximately 400 nm, but is not limited thereto. The thickness of the second mask pattern (140-2) may be substantially the same as the thickness of the first mask pattern (140-1) or thinner than the thickness of the first mask pattern (140-1). Additionally, the ratio of the horizontal area of ​​the second polysilicon film (130-2) to the horizontal area of ​​the second mask pattern (140-2) may be approximately 200% to approximately 1000%. The shape of the second mask pattern (140-2) will be described in more detail in FIGS. 4a to 4d.

[0024] Although not illustrated in the drawing, a first mask pattern (140-1) may be formed on the cell area together with the first region (R1). The first mask pattern (140-1) may be formed over the entire upper surface of the polysilicon film (130) on the cell area. That is, ion implantation may not be performed on the cell area.

[0025] Referring to FIG. 1e, after the mask pattern (140) is placed on the polysilicon film (130), impurities can be implanted into a second region (R2) (S150). The arrow in FIG. 1e indicates that ion implantation is performed in the second region (R2). For example, the impurities may be P-type impurities. For example, the impurities may be boron (B), BF, BF2, and / or indium (In). It may include group 3 elements such as the above. The impurities may be implanted into the polysilicon film (130) by ion implantation and / or plasma doping. As described above, the mask pattern (140) may be used as an ion implantation mask so that the impurities may be implanted into the second region (R2). That is, the impurities may be implanted onto the second polysilicon film (130-2).

[0026] The above mask pattern (140) can be removed by an ashing process. After that, a Rapid Thermal Annealing (RTA) process can be performed on the resulting product. After that, a first gate electrode can be formed on the first region (R1), and a second gate electrode can be formed on the second region (R2). Additionally, source / drain regions can be formed inside the semiconductor substrate (100) on the sides of each of the first and second gate electrodes. The source / drain regions may have a lightly doped drain (LDD) structure.

[0027] In another embodiment, the first region (R1) may be a PMOS region and the second region (R2) may be an NMOS region, and N-type impurities may be implanted in the second region (R2). Additionally, the ion implantation method may be modified in various ways by partially covering the upper surface of the film to be implanted with a mask pattern (140). For example, the above method may be used in the process of forming source / drain regions.

[0028] Generally, in a dual polysilicon gate formation process, P-type impurities, such as boron (B) or boron difluoride (BF2), are ion-implanted into a polysilicon film in the PMOS region to form gate electrodes with two different impurities. At this time, the ion-implanted P-type impurities penetrate toward the gate insulating film, causing a change in the impurity concentration in the transistor channel and a change in the threshold voltage. The threshold voltage has the characteristic of changing significantly even with a small change in impurity concentration in the channel region compared to the gate impurity concentration. Accordingly, the penetration of P-type impurities toward the gate insulating film results in a worsening of the dispersion of the transistor threshold voltage in the semiconductor device, which causes an increase in the defect rate during the semiconductor device manufacturing process.

[0029] On the other hand, the method for manufacturing a semiconductor device according to the present embodiment may form a second mask pattern (140-2) that partially covers a second polysilicon film (130-2) on a second region (R2) corresponding to a PMOS region. When P-type impurities are implanted on the second region (R2), due to the second mask pattern (140-2), the ion-implanted P-type impurities move in the vertical direction (Z direction) and the horizontal direction (X direction, Y direction, or diagonal direction), thereby reducing the penetration of P-type impurities into the gate insulating film (110). In addition, a semiconductor device capable of driving at a low voltage can be realized by uniformly lowering the threshold voltage of the PMOS region accordingly. Furthermore, the reduction in the failure rate caused by the dispersion of the transistor threshold voltage in the semiconductor device can be suppressed. Therefore, the reliability of the semiconductor device can be relatively increased.

[0031] FIGS. 2a and FIGS. 2b are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] Referring to FIGS. 2a and 2b, the semiconductor device may include a semiconductor substrate (100), a gate insulating film (110), a barrier layer (120), a polysilicon film (130a), and a mask pattern (140a). The semiconductor substrate (100), gate insulating film (110), and barrier layer (120) of FIGS. 2a and 2b may be substantially the same as the semiconductor substrate (100), gate insulating film (110), and barrier layer (120) of FIGS. 1a through 1e. The embodiment of FIGS. 2a and 2b differs from the embodiment described in relation to FIGS. 1a through 1e in that N-type impurities are ion-implanted into an NMOS region. Therefore, in this embodiment, only the step of ion-implanting N-type impurities into a first region (R1), which is an NMOS region, is described.

[0033] Referring to FIG. 2a, the polysilicon film (130a) may include first and second polysilicon films (130-1a, 130-2a), and the mask pattern (140a) may include first and second mask patterns (140-1a, 140-2a).

[0034] According to one embodiment of the present invention, a first mask pattern (140-1a) may partially cover the upper surface of a first polysilicon film (130-1a), and a second mask pattern (140-2a) may cover the entire upper surface of a second polysilicon film (130-2a). Since the first mask pattern (140-1a) partially covers the upper surface of the first polysilicon film (130-1a), impurities may be injected into the first polysilicon film (130-1a). Additionally, since the second mask pattern (140-2a) may cover the entire upper surface of the second polysilicon film (130-2a), impurities may not be injected into the second polysilicon film (130-2a).

[0035] Referring to FIG. 2b, after the mask pattern (140a) is placed on the polysilicon film (130a), impurities can be implanted into the second region (R2). The arrow in FIG. 2b indicates that ion implantation is performed in the first region (R1). For example, the impurities may be N-type impurities. For example, the impurities may include phosphorus (P), arsenic (As), or antimony (Sb). The impurities may be implanted into the first polysilicon film (130-1a) by ion implantation and / or plasma doping. As described above, the mask pattern (140a) is used as an ion implantation mask so that impurities can be implanted into the first region (R1). According to one embodiment of the present invention, the first region (R1) and the second region (R2) may be spaced apart in the horizontal direction (X direction, Y direction, diagonal direction). Therefore, when impurities are injected into the first region (R1) or the second region (R2), the impurities may not spread horizontally to other regions.

[0036] That is, the first mask pattern (140-1a) may be substantially identical to the second mask pattern (140-2) of FIG. 1a, and the second mask pattern (140-2a) may be substantially identical to the first mask pattern (140-1) of FIG. 1a. The shape of the second mask pattern (140-2) will be described in more detail in FIG. 4a to 4d.

[0037] The above mask pattern (140a) can be removed by an ashing process. After that, a heat treatment process can be performed on the resulting product. After that, a first gate electrode can be formed on the first region (R1), and a second gate electrode can be formed on the second region (R2). Additionally, source / drain regions can be formed inside the semiconductor substrate (100) on the sides of each of the first and second gate electrodes. The source / drain regions may have an LDD structure.

[0039] FIG. 3 is a schematic diagram illustrating the diffusion of ions within a second polysilicon film (130-2) during an ion implantation process on a second region (R2) according to an embodiment of the present invention. The arrows in FIG. 3 indicate the paths along which ions move within the second polysilicon film (130-2).

[0040] Referring together to FIGS. 1a through 1e and FIG. 3, a second mask pattern (140-2) is disposed on the upper surface of the second polysilicon film (130-2), so that a horizontal ion concentration gradient of impurities can be generated on the second polysilicon film (130-2). Accordingly, the impurities can diffuse in the vertical direction (Z direction) and the horizontal direction (X direction, Y direction, diagonal direction). Accordingly, the degree to which the impurities penetrate into the gate insulating film (110) can be reduced. That is, the impurities diffuse in the horizontal direction (X direction, Y direction, diagonal direction), and the movement of the impurities in the vertical direction (Z direction) can be reduced.

[0041] As described above, the ratio of the horizontal area of ​​the second polysilicon film (130-2) to the horizontal area of ​​the second mask pattern (140-2) may be approximately 200% to approximately 1000%. If the ratio of the horizontal area of ​​the second polysilicon film (130-2) to the horizontal area of ​​the second mask pattern (140-2) is approximately 200% or less, the amount of impurities injected onto the second polysilicon film (130-2) is reduced, and the efficiency of the semiconductor device manufacturing process may be low. In addition, if the ratio of the horizontal area of ​​the second polysilicon film (130-2) to the horizontal area of ​​the second mask pattern (140-2) is approximately 1000% or more, the efficiency of arranging the second mask pattern (140-2) may be relatively low. The shape of the second mask pattern (140-2) will be described in more detail in FIGS. 4a to 4d.

[0043] FIGS. 4a to 4d are drawings showing a second mask pattern (140-2) disposed on a second polysilicon film (130-2) according to one embodiment of the present invention.

[0044] Referring together to FIGS. 1a through 1e and FIGS. 4a through 4d, the second mask pattern (140-2) disposed on the second polysilicon film (130-2) may have various shapes. As described above, the shape of the horizontal cross-section of the second mask pattern (140-2) may be polygonal, circular, and / or elliptical. This is exemplary, and the shape of the horizontal cross-section of the second mask pattern (140-2) may be varied. Additionally, the second mask pattern (140-2) may include a plurality of sub-mask patterns (142). For example, the sub-mask patterns (142) may be spaced apart from each other in a horizontal direction (X direction, Y direction, or diagonal direction). When the above submask patterns (142) are spaced apart from each other in a horizontal direction (X direction, Y direction, or diagonal direction), a relatively large horizontal ion concentration gradient may occur at the same vertical level of the second polysilicon film (130-2).

[0046] FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0047] Referring to FIGS. 1a through 1e and FIG. 5, the semiconductor device of the present embodiment may include a semiconductor substrate (100), a gate insulating film (110), a barrier layer (120), a polysilicon film (130), a mask pattern (140), and a device isolation film (150). The embodiment related to FIG. 5 differs from the embodiment described in relation to FIGS. 1a through 1e in that the device isolation film (150) is disposed between a first region (R1) and a second region (R2). Accordingly, the present embodiment describes only the step of forming the device isolation film (150) on the semiconductor substrate (100).

[0048] A device isolation layer (150) is disposed on a semiconductor substrate (100) with a predetermined height and may be formed of an insulating material. For example, the device isolation layer (150) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the upper surface of the device isolation layer (150) may be located in substantially the same plane as the upper surface of the semiconductor substrate (100). Subsequently, a gate insulating layer (110), a barrier layer (120), and / or a polysilicon film (130) may be sequentially laminated on the device isolation layer (150). Explanation of the symbols

[0049] 100: Substrate 110: Gate insulating film 120: Barrier layer 130: Polysilicon film 140: Mask pattern 150: Device isolation layer

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a step of forming a gate insulating film on a semiconductor substrate including a first region and a second region; a step of forming a polysilicon film on the gate insulating film; a step of forming a first mask pattern that covers the entire upper surface of the polysilicon film of the first region and a step of forming a second mask pattern that partially covers the upper surface of the polysilicon film of the second region; and a step of ion-implanting an impurity into the second region; wherein the first and second mask patterns are used as ion-implantation masks, the second mask pattern includes a sub-pattern having a line shape, and the second mask pattern is configured to provide a path through which ions can diffuse in a horizontal direction. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the first or second mask pattern comprises a photoresist film, SiO2, or SiN. Claim 3 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a barrier layer between the gate insulating film and the polysilicon film to prevent the ion from being implanted into the gate insulating film; wherein the barrier layer comprises silicon oxide or silicon nitride. Claim 4 A method for manufacturing a semiconductor device according to claim 1, characterized in that the ratio of the horizontal area of ​​the polysilicon film on the second region to the horizontal area of ​​the second mask pattern is in the range of 200% to 1000%. Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the second mask pattern is equal to or thinner than the thickness of the first mask pattern. Claim 6 A method for manufacturing a semiconductor device according to claim 1, wherein the second mask pattern comprises a plurality of sub-mask patterns, and each of the sub-mask patterns is spaced apart from each other in a horizontal direction. Claim 7 A method for manufacturing a semiconductor device according to claim 1, wherein the first and second mask patterns are removed using an ashing process. Claim 8 A method for manufacturing a semiconductor device according to claim 1, wherein the impurity is boron (B), BF, or BF2. Claim 9 A method for manufacturing a semiconductor device according to claim 1, wherein the impurity is phosphorus (P), arsenic (As), or antimony (Sb). Claim 10 A method for manufacturing a semiconductor device according to claim 1, wherein the first region is an NMOS region in which an NMOS (N-channel MOS) transistor is formed, and the second region is a PMOS region in which a PMOS (P-channel) transistor is formed.

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