Display device

Abstract

A display device according to one embodiment of the present invention comprises: a first wire extending in a first direction; a second wire spaced apart from the first wire in a second direction; subpixels including light-emitting regions located between the first wire and the second wire and light-emitting elements disposed in the light-emitting regions; a bank pattern including openings corresponding to light-emitting element array regions in which the light-emitting elements are arranged and which overlap with the first wire and the second wire; and a bank surrounding the light-emitting regions and overlapping with the first wire, the second wire and the bank pattern.

Description

Technology Field

[0001] An embodiment of the present invention relates to a display device. Background Technology

[0002] Recently, interest in information displays has been rising. Accordingly, research and development on display devices is continuously being carried out. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a display device capable of preventing overflow of light-emitting element ink including light-emitting elements.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to one embodiment of the present invention may include: a first wire extending in a first direction; a second wire spaced apart from the first wire in a second direction; subpixels including light-emitting regions located between the first wire and the second wire and light-emitting elements disposed in the light-emitting regions; a bank pattern including openings corresponding to light-emitting element array regions in which the light-emitting elements are arranged and which overlap with the first wire and the second wire; and a bank surrounding the light-emitting regions and overlapping with the first wire, the second wire and the bank pattern.

[0006] In one embodiment, the second wiring may extend in the first direction. The bank pattern may include: a first pattern portion that overlaps with the first wiring and is continuously formed along the first direction around the light-emitting regions; a second pattern portion that overlaps with the second wiring and is continuously formed along the first direction around the light-emitting regions; and third pattern portions that are disposed on both sides of each of the light-emitting element array regions in the first direction and extend in the second direction.

[0007] In one embodiment, the bank may be continuously formed along the first direction in the portion overlapping with the first pattern portion and the second pattern portion of the bank pattern.

[0008] In one embodiment, the first wiring may be a scan line to which a scan signal is applied. The second wiring may be a power line to which a first power supply voltage or a second power supply voltage is applied.

[0009] In one embodiment, each of the subpixels may include a first alignment electrode located around the first ends of the light-emitting elements and extending in the second direction. The first alignment electrode may include an end located in a part of a non-light-emitting region adjacent to the light-emitting region of the corresponding subpixel in the second direction.

[0010] In one embodiment, the first alignment electrode may be electrically connected to the first ends of the light-emitting elements.

[0011] In one embodiment, each of the subpixels may further include a pixel circuit electrically connected to the first alignment electrode.

[0012] In one embodiment, each of the subpixels may further include a second alignment electrode located around the second ends of the light-emitting elements and extended in the second direction.

[0013] In one embodiment, the display device may further include a power line electrically connected to the second alignment electrode.

[0014] In one embodiment, the subpixels may include a first subpixel, a second subpixel, and a third subpixel, each constituting a pixel and including a first light-emitting region, a second light-emitting region, and a third light-emitting region. The first light-emitting region, the second light-emitting region, and the third light-emitting region may be arranged in the first direction between the first wiring and the second wiring.

[0015] In one embodiment, the first wiring, the bank pattern, and the bank may completely overlap each other in a non-luminous region immediately adjacent to the first edge regions of the first light-emitting region, the second light-emitting region, and the third light-emitting region. The second wiring, the bank pattern, and the bank may completely overlap each other in a non-luminous region immediately adjacent to the second edge regions of the first light-emitting region, the second light-emitting region, and the third light-emitting region.

[0016] In one embodiment, the first subpixel may further include a first pixel circuit electrically connected to light-emitting elements disposed in the first light-emitting region among the light-emitting elements. The second subpixel may further include a second pixel circuit electrically connected to light-emitting elements disposed in the second light-emitting region among the light-emitting elements. The third subpixel may further include a third pixel circuit electrically connected to light-emitting elements disposed in the third light-emitting region among the light-emitting elements.

[0017] In one embodiment, the first pixel circuit, the second pixel circuit, and the third pixel circuit may be arranged in the second direction.

[0018] In one embodiment, the second wiring may be positioned between the second pixel circuit and the third pixel circuit.

[0019] In one embodiment, the first pixel circuit and the third pixel circuit may be positioned between the first wiring and the second wiring.

[0020] In one embodiment, each of the subpixels may include a light-emitting part comprising at least one light-emitting element disposed in a corresponding light-emitting region among the light-emitting elements, and electrodes electrically connected to the at least one light-emitting element; and a pixel circuit comprising circuit elements electrically connected to the light-emitting part.

[0021] In one embodiment, the display device may include a circuit layer comprising pixel circuits of the subpixels, the first wiring and the second wiring; and a display layer superimposed on the circuit layer and comprising light-emitting portions of the subpixels.

[0022] In one embodiment, the circuit layer may include conductive layers sequentially arranged along a third direction intersecting the first direction and the second direction. Among the conductive layers, the conductive layer closest to the display layer may include the first wiring and the second wiring.

[0023] In one embodiment, the display device may include at least two pixels arranged in the first direction, each including a subpixel among the subpixels. The bank pattern may include individual patterns formed separately from each other, corresponding to each of the at least two pixels, or an integrated pattern formed integrally, corresponding to each of the at least two pixels.

[0024] A display device according to one embodiment of the present invention may include: a first wiring and a second wiring extending in a first direction and spaced apart from each other in a second direction; a first subpixel including a first light-emitting region located between the first wiring and the second wiring and light-emitting elements disposed in the first light-emitting region; a second subpixel including a second light-emitting region located between the first wiring and the second wiring adjacent to the first light-emitting region in the first direction and light-emitting elements disposed in the second light-emitting region; a third subpixel including a third light-emitting region located between the first wiring and the second wiring adjacent to the second light-emitting region in the first direction and light-emitting elements disposed in the third light-emitting region; a bank pattern overlapping with the first wiring and the second wiring and including openings corresponding to each light-emitting element array region located in the first light-emitting region, the second light-emitting region and the third light-emitting region; and a bank surrounding the light-emitting regions and overlapping with the first wiring, the second wiring and the bank pattern. The bank pattern and the bank may each be continuously formed along the first direction, overlapping with the first wiring and the second wiring in the portion immediately adjacent to both ends of the first light-emitting region, the second light-emitting region, and the third light-emitting region in the second direction.

[0025] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0026] According to a display device according to embodiments of the present invention, in a non-emissive region adjacent to the emitting regions of subpixels, the height of the first bank can be increased or maximized by overlapping the first or second wiring, the bank pattern, and the first bank with each other. Accordingly, the volume of the emitting regions can be increased, and the emitting element ink containing the emitting elements can be prevented or reduced from flooding into the non-emissive region during the process of supplying emitting elements to the emitting regions. Accordingly, the first alignment wiring can be stably separated into the first alignment electrodes in a subsequent process, and short circuit defects can be prevented.

[0027] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0028] FIG. 1 is a perspective view showing a light-emitting element according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing a light-emitting element according to one embodiment of the present invention. FIG. 3 is a plan view showing a display device according to one embodiment of the present invention. FIGS. 4 and FIGS. 5 are circuit diagrams showing each subpixel according to embodiments of the present invention. FIG. 6 is a plan view showing a display area according to one embodiment of the present invention. FIG. 7 is a cross-sectional view showing a display area according to one embodiment of the present invention. FIG. 8 is a plan view showing a circuit layer of a display area according to one embodiment of the present invention. FIG. 9 is a plan view showing a display layer of a display area according to one embodiment of the present invention. FIGS. 10 and FIGS. 11 are plan views showing a display layer of a display area according to embodiments of the present invention. FIG. 12 is a cross-sectional view showing a display area according to one embodiment of the present invention. Specific details for implementing the invention

[0029] The present invention is susceptible to various modifications and may take various forms; therefore, specific embodiments are illustrated in the drawings and described in detail in the text. In the following description, singular expressions include plural expressions unless the context clearly indicates that they include only the singular.

[0030] Meanwhile, the present invention is not limited to the embodiments disclosed below and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Additionally, each of the embodiments disclosed below may be carried out alone or combined with at least one other embodiment.

[0031] Throughout the drawings, the same reference numerals have been used for identical or similar elements, even if they are shown in different drawings. In describing embodiments of the present invention with reference to the drawings, redundant descriptions of identical or similar elements are omitted or simplified.

[0032] In describing embodiments of the present invention, the term "connection" may comprehensively mean physical and / or electrical connections. Additionally, it may comprehensively mean direct connections and indirect connections, and may comprehensively mean integral connections and non-integrated connections.

[0033] FIG. 1 is a perspective view showing a light-emitting element (LD) according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a light-emitting element (LD) according to an embodiment of the present invention. For example, FIG. 1 shows an example of a light-emitting element (LD) that can be used as a light source for a pixel according to an embodiment of the present invention, and FIG. 2 shows an example of a cross-section of a light-emitting element (LD) corresponding to line I-I' of FIG. 1.

[0034] Referring to FIGS. 1 and 2, a light-emitting element (LD) may comprise a first semiconductor layer (SCL1), an active layer (ACT) (also referred to as a “light-emitting layer”), and a second semiconductor layer (SCL2) sequentially arranged and / or stacked along one direction (e.g., the longitudinal direction), and an insulating film (INF) covering the outer surface (e.g., a side surface) of the first semiconductor layer (SCL1), the active layer (ACT), and the second semiconductor layer (SCL2). In one embodiment, the light-emitting element (LD) may further comprise an electrode layer (ETL) disposed on the second semiconductor layer (SCL2). The insulating film (INF) may at least partially cover or not cover the outer surface of the electrode layer (ETL). Depending on the embodiment, the light-emitting element (LD) may further comprise another electrode layer disposed on one surface (e.g., a bottom surface) of the first semiconductor layer (SCL1).

[0035] In one embodiment, the light-emitting element (LD) may be provided in a rod shape. In describing embodiments of the present invention, the term "rod shape" may include various rod-like shapes or bar-like shapes, such as cylindrical shapes or polygonal cylindrical shapes, and the shape of the cross-section is not particularly limited. In one embodiment, the length (L) of the light-emitting element (LD) may be larger than its diameter (D) (or the width of the cross-section).

[0036] A light-emitting element (LD) may include a first end (EP1) and a second end (EP2). In one embodiment, the first end (EP1) and the second end (EP2) may face each other. For example, the light-emitting element (LD) may include a first end (EP1) and a second end (EP2) at both ends in the length direction (or, thickness direction). The first end (EP1) of the light-emitting element (LD) may include a first bottom surface (e.g., top surface) of the light-emitting element (LD) and / or a surrounding area thereof. The second end (EP2) of the light-emitting element (LD) may include a second bottom surface (e.g., bottom surface) of the light-emitting element (LD) and / or a surrounding area thereof.

[0037] The first semiconductor layer (SCL1), the active layer (ACT), the second semiconductor layer (SCL2), and the electrode layer (ETL) may be arranged sequentially from the second end (EP2) of the light-emitting element (LD) toward the first end (EP1). For example, the electrode layer (ETL) (or the second semiconductor layer (SCL2)) may be arranged at the first end (EP1) of the light-emitting element (LD), and the first semiconductor layer (SCL1) (or another electrode layer adjacent to the first semiconductor layer (SCL1) and electrically connected to the first semiconductor layer (SCL1)) may be arranged at the second end (EP2) of the light-emitting element (LD).

[0038] The first semiconductor layer (SCL1) may include a first conductivity type semiconductor layer including a first conductivity type dopant. For example, the first semiconductor layer (SCL1) may be an N-type semiconductor layer including an N-type dopant.

[0039] In the embodiments, the first semiconductor layer (SCL1) may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer (SCL1) may include a nitride-based semiconductor material comprising at least one material selected from GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material comprising at least one material selected from GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. In one embodiment, the first semiconductor layer (SCL1) may include an N-type dopant such as Si, Ge, Sn, etc. The first semiconductor layer (SCL1) may also be formed using materials other than those exemplified above.

[0040] An active layer (ACT) can be disposed on a first semiconductor layer (SCL1). The active layer (ACT) may include a single or multiple quantum well (QW) structure. When a voltage greater than the threshold voltage is applied across the ends of the light-emitting device (LD), electron-hole pairs can recombine in the active layer (ACT), and accordingly, light can be emitted from the light-emitting device (LD).

[0041] In the embodiments, the active layer (ACT) may emit light in the visible light wavelength band, for example, light in the wavelength band of approximately 400 nm to 900 nm. For example, the active layer (ACT) may emit blue light having a wavelength in the range of approximately 450 nm to 480 nm, green light having a wavelength in the range of approximately 480 nm to 560 nm, or red light having a wavelength in the range of approximately 620 nm to 750 nm. The active layer (ACT) may also emit light of other colors and / or wavelength bands in addition to the colors and / or wavelength bands exemplified above.

[0042] According to an embodiment, the active layer (ACT) may include a nitride-based semiconductor material or a phosphide-based semiconductor material. As an example, the active layer (ACT) may include a nitride-based semiconductor material comprising at least one material selected from GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material comprising at least one material selected from GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The active layer (ACT) may also be formed using materials other than those exemplified above.

[0043] The second semiconductor layer (SCL2) may be disposed on the active layer (ACT). The second semiconductor layer (SCL2) may include a semiconductor layer of the second conductivity type including a dopant of the second conductivity type. For example, the second semiconductor layer (SCL2) may be a P-type semiconductor layer including a P-type dopant.

[0044] In the embodiments, the second semiconductor layer (SCL2) may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer (SCL2) may include a nitride-based semiconductor material comprising at least one material selected from GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material comprising at least one material selected from GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. In one embodiment, the second semiconductor layer (SCL2) may include a P-type dopant such as Mg. The second semiconductor layer (SCL2) may also be formed using materials other than those exemplified above.

[0045] In one embodiment, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may include the same semiconductor material but may include dopants of different conductivity types. In another embodiment, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may include different semiconductor materials and dopants of different conductivity types.

[0046] In the embodiments, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may have different lengths (or thicknesses) along the longitudinal direction of the light-emitting element (LD). For example, along the longitudinal direction of the light-emitting element (LD), the first semiconductor layer (SCL1) may have a longer length (or a thicker thickness) than the second semiconductor layer (SCL2). Accordingly, the active layer (ACT) may be located closer to the first end (EP1) (e.g., P-type end) than to the second end (EP2) (e.g., N-type end).

[0047] An electrode layer (ETL) may be disposed on a second semiconductor layer (SCL2). The electrode layer (ETL) may be an electrode that protects the second semiconductor layer (SCL2) and smoothly connects the second semiconductor layer (SCL2) to at least one circuit element, electrode, and / or wiring. For example, the electrode layer (ETL) may be an ohmic contact electrode or a Schottky contact electrode.

[0048] According to an embodiment, the electrode layer (ETL) may comprise a metal or a metal oxide. For example, the electrode layer (ETL) may be formed by using a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), its oxides or alloys, or a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), or In2O3 (Indium Oxide), either alone or in combination. The electrode layer (ETL) may also be formed using a conductive material other than those exemplified above.

[0049] According to an embodiment, the electrode layer (ETL) may be substantially transparent. Accordingly, light generated from the light-emitting element (LD) can pass through the electrode layer (ETL).

[0050] An insulating film (INF) may be provided on the surface of a light-emitting device (LD) to cover the sides of a first semiconductor layer (SCL1), an active layer (ACT), a second semiconductor layer (SCL2), and / or an electrode layer (ETL). Accordingly, electrical stability of the light-emitting device (LD) can be ensured, and short-circuit defects through the light-emitting device (LD) can be prevented.

[0051] An insulating film (INF) may expose an electrode layer (ETL) (or a second semiconductor layer (SCL2)) and a first semiconductor layer (SCL1) (or another electrode layer provided at the second end (EP2) of the light-emitting element (LD), respectively, at the first end (EP1) and the second end (EP2) of the light-emitting element (LD). For example, the insulating film (INF) may not be provided on two bottom surfaces (e.g., the top surface and bottom surface of the light-emitting element (LD)) corresponding to the first and second ends (EP1, EP2) of the light-emitting element (LD). Accordingly, the first end (EP1) and the second end (EP2) of the light-emitting element (LD) may be connected to at least one electrode, wiring and / or conductive pattern, etc., respectively, to apply an electrical signal (e.g., a driving signal and / or power supply voltage) to the light-emitting element (LD).

[0052] When an insulating film (INF) is provided on the surface of a light-emitting element (LD), surface defects of the light-emitting element (LD) can be minimized, thereby improving lifespan and efficiency. In addition, even when light-emitting elements (LDs) are adjacent to each other, short circuit defects between the light-emitting elements (LDs) can be prevented.

[0053] In one embodiment, the light-emitting element (LD) may be manufactured through a surface treatment process. For example, the light-emitting elements (LD) may be surface-treated using a hydrophobic material. Accordingly, when a plurality of light-emitting elements (LD) are mixed in a fluid solution (or ink) and supplied to each light-emitting region (e.g., the light-emitting region of each pixel and / or sub-pixel), the light-emitting elements (LD) may be uniformly dispersed within the solution without unevenly aggregating.

[0054] The insulating film (INF) may include a transparent insulating material. Accordingly, light generated in the active layer (ACT) can pass through the insulating film (INF). For example, the insulating film (INF) is silicon oxide (SiO₂). x )(for example, SiO2), silicon nitride (SiNx )(for example, Si3N4), aluminum oxide (Al x O y )(for example, Al2O3), and titanium oxide (Ti x O y It may include at least one insulating material among )(e.g., TiO2). In addition to the materials exemplified above, an insulating film (INF) may be formed using other insulating materials.

[0055] The insulating film (INF) can be a single layer or multiple layers. As an example, the insulating film (INF) can be a double film.

[0056] In one embodiment, the insulating film (INF) may be partially etched (or removed) at a portion corresponding to at least one of the first end (EP1) and the second end (EP2) of the light-emitting element (LD). For example, the insulating film (INF) may be etched obliquely at the first end (EP1) of the light-emitting element (LD).

[0057] In one embodiment, the light-emitting element (LD) may have a small size in the range of nanometers to micrometers. For example, the light-emitting element (LD) may each have a diameter (D) (or width of the cross-section) and / or length (L) in the range of nanometers to micrometers. As an example, the light-emitting element (LD) may have a diameter (D) and / or length (L) in the range of approximately tens of nanometers to tens of micrometers.

[0058] The structure, shape, size, and / or type of the light-emitting element (LD) may be changed according to the embodiments. For example, the structure, shape, size, and / or type of the light-emitting element (LD) may be varied depending on the design conditions of the light-emitting device using the light-emitting element (LD) or the light-emitting characteristics to be secured.

[0059] A light-emitting device including a light-emitting element (LD) can be used in various types of devices that require a light source. For example, light-emitting elements (LDs) can be placed in pixels of a display device and used as a light source for the pixels. Light-emitting elements (LDs) can also be used in other types of devices that require a light source, such as lighting devices.

[0060] FIG. 3 is a plan view showing a display device (DD) according to one embodiment of the present invention.

[0061] Referring to FIG. 3, a display device (DD) may include a display panel (DPN) including pixels (PXL) and at least one driving circuit (DIC) connected to the display panel (DPN). In one embodiment, the display device (DD) may include two or more driving circuits (DIC).

[0062] A display panel (DPN) may include a display area (DA) in which pixels (PXL) are arranged, and a non-display area (NA) located around the display area (DA). Wiring and / or pads electrically connected to the pixels (PXL) may be arranged in the non-display area (NA). In one embodiment, the non-display area (NA) may be arranged at the edge of the display panel (DPN) and may surround the display area (DA).

[0063] Pixels (PXL) may be arranged in a display area (DA) along at least one direction. For example, pixels (PXL) may be regularly arranged in the display area (DA) along a first direction (DR1) and a second direction (DR2). In one embodiment, the first direction (DR1) may be the horizontal direction (or horizontal direction) of the display area (DA), and the second direction (DR2) may be the vertical direction (or vertical direction) of the display area (DA). The arrangement structure and / or arrangement direction of the pixels (PXL) may be changed according to the embodiments.

[0064] Each pixel (PXL) (also referred to as a “unit pixel”) may include a subpixel (e.g., a subpixel (SPX) of FIG. 4 or FIG. 5). For example, each pixel (PXL) may include two or more subpixels (SPX) that emit light of different colors.

[0065] A driving circuit (DIC) (e.g., a driving integrated circuit) may be placed on a pad area (PA) of a display panel (DPN). For example, the driving circuit (DIC) may be placed on the pad area (PA) of the display panel (DPN) in a third direction (DR3) (e.g., the thickness or height direction of a display device (DD)) that intersects a first direction (DR1) and a second direction (DR2). The driving circuit (DIC) may be electrically connected to pads provided in the pad area (PA) and may supply driving signals to the display panel (DPN) through said pads.

[0066] The driving circuit (DIC) may include a circuit board (CB) and an integrated circuit (IC). The circuit board (CB) may be a flexible printed circuit board (FPCB), a polymer film, or other forms of substrate or film. In one embodiment, the driving circuit (DIC) may be attached to a pad area (PA) in the form of a tape-automated bonding (TAB)-IC. The TAB-IC may include a tape carrier package (TCP) in which a chip-type integrated circuit (IC) is mounted on a polymer film, and a chip on film (COF) in which a chip-type integrated circuit (IC) is mounted on a flexible printed circuit board. The driving circuit (DIC) may also be provided in other forms or structures.

[0067] The integrated circuit (IC) may include a driver for driving pixels (PXL). For example, the driver circuit (DIC) may include a scan driver (also referred to as a “gate driver”) for supplying scan signals and / or control signals to the scan lines and / or control lines of the pixels (PXL) (or subpixels (SPX) constituting the pixels (PXL)), and a data driver (also referred to as a “source driver”) for supplying data signals to the data lines of the pixels (PXL). In other embodiments, at least a portion of the scan driver and / or data driver may be provided and / or formed on a display panel (DPN), or mounted on another substrate, etc., and connected to the display panel (DPN). In one embodiment, the data driver may include a sensing circuit for sensing the characteristics of the pixels (PXL). In another embodiment, the display device (DD) may include a separate sensing circuit separated from the data driver.

[0068] In one embodiment, the display panel (DPN) may be divided into two or more parts or regions, and the display device (DD) may include two or more driving circuits (DIC) corresponding to each part or region of the display panel (DPN). Each driving circuit (DIC) may be electrically connected to pixels (PXL) located in the corresponding part or region of the display panel (DPN) to supply driving signals to said pixels (PXL).

[0069] The display device (DD) may further include additional driving elements. For example, the display device (DD) may further include a timing control unit electrically connected to integrated circuits (IC), and a power supply voltage generation unit electrically connected to pixels (PXL) and integrated circuits (IC). In one embodiment, the timing control unit and the power supply voltage generation unit may be mounted and / or formed on separate circuit boards electrically connected to driving circuits (DIC), but the embodiments are not limited thereto.

[0070] In one embodiment, the driving circuits (DIC) may be placed only on one edge area of ​​the display panel (DPN) adjacent to one side of the display area (DA). For example, the driving circuits (DIC) may be placed only on a portion of the non-display area (NA) corresponding to the bottom edge area (or top edge area) of the display panel (DPN) (for example, a portion corresponding to the pad areas (PA) and the surrounding area). In this case, the display device (DD) may be a single-side driving display device that supplies driving signals to the display panel (DPN) through pads placed in the bottom edge area (or top edge area) of the display panel (DPN) and driving circuits (DIC) electrically connected to said pads.

[0071] In the case of a single-sided driving display device, driving circuits (DIC) (or pads for connection with driving circuits (DIC)) may not be placed on the remaining areas of the non-display area (NA) of the display panel (DPN) that are adjacent to other sides of the display area (DA) (for example, the top edge area, the left edge area, and the right edge area of ​​the display panel (DPN)). Accordingly, the width and / or area of ​​the non-display area (NA) can be reduced or minimized in the remaining areas of the non-display area (NA).

[0072] FIGS. 4 and 5 are circuit diagrams showing respective subpixels (SPX) according to embodiments of the present invention. For example, FIGS. 4 and 5 show subpixels (SPX) including light-emitting units (EMU) of different structures.

[0073] The subpixel (SPX) illustrated in FIG. 4 or FIG. 5 may be one of the subpixels (SPX) placed in the display area (DA) of FIG. 3. The subpixels (SPX) placed in the display area (DA) may have substantially the same or similar structures.

[0074] Referring to FIGS. 4 and 5, a subpixel (SPX) may be connected to a scan line (SL), a data line (DL), a first power line (PL1), and a second power line (PL2). In one embodiment, the subpixel (SPX) may be further connected to other power lines and / or signal lines. For example, the subpixel (SPX) may be further connected to a sensing line (SENL) (also referred to as the "initialization power line") and / or a control line (SSL).

[0075] A subpixel (SPX) may include an emitting unit (EMU) for generating light of a luminance corresponding to each data signal. Additionally, the subpixel (SPX) may further include a pixel circuit (PXC) for driving the emitting unit (EMU).

[0076] The pixel circuit (PXC) can be connected to a scan line (SL) and a data line (DL), and can be connected between a first power line (PL1) and a light-emitting unit (EMU). For example, the pixel circuit (PXC) can be electrically connected to a scan line (SL) to which a scan signal is supplied, a data line (DL) to which a data signal is supplied, a first power line (PL1) to which a first power voltage (VDD) is applied, and a light-emitting unit (EMU).

[0077] The pixel circuit (PXC) may optionally be further connected to a control line (SSL) to which a control signal is supplied, and a sensing line (SENL) connected to a reference power supply (or initialization power supply) or a sensing circuit corresponding to a display period or a sensing period. In one embodiment, the scan signal and control signal supplied to the subpixel (SPX) (e.g., the scan signal and control signal supplied to the subpixels (SPX) and / or pixels (SPX) of the corresponding horizontal line) may be the same or different from each other. In one embodiment, if the scan signal and control signal of the subpixel (SPX) are the same signal, the scan line (SL) and control line (SSL) connected to the subpixel (SPX) may be integrated.

[0078] The pixel circuit (PXC) may include at least one transistor (M) and a capacitor (Cst). For example, the pixel circuit (PXC) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a capacitor (Cst).

[0079] The first transistor (M1) can be electrically connected between the first power line (PL1) and the second node (N2). The second node (N2) may be a node where the pixel circuit (PXC) and the light-emitting unit (EMU) are connected. For example, the second node (N2) may be a node where one electrode of the first transistor (M1) (for example, the source electrode) and the light-emitting unit (EMU) are electrically connected to each other. The gate electrode of the first transistor (M1) may be electrically connected to the first node (N1). The first transistor (M1) can control the driving current supplied to the light-emitting unit (EMU) in response to the voltage of the first node (N1). For example, the first transistor (M1) may be a driving transistor of a subpixel (SPX).

[0080] In one embodiment, the first transistor (M1) may further include a bottom metal layer (BML) (also referred to as a "back gate electrode" or a "second gate electrode"). In one embodiment, the bottom metal layer (BML) may be electrically connected to one electrode (e.g., a source electrode) of the first transistor (M1).

[0081] In an embodiment in which the first transistor (M1) includes a lower metal layer (BML), a back-biasing technique (or a sync technique) can be applied to the lower metal layer (BML) of the first transistor (M1) to shift the threshold voltage of the first transistor (M1) in a negative or positive direction. Additionally, if the lower metal layer (BML) is placed below a semiconductor pattern (e.g., the semiconductor pattern (SCP) of FIG. 7) that constitutes the channel of the first transistor (M1), light incident on the semiconductor pattern can be blocked to stabilize the operating characteristics of the first transistor (M1).

[0082] The second transistor (M2) can be electrically connected between the data line (DL) and the first node (N1). Also, the gate electrode of the second transistor (M2) can be electrically connected to the scan line (SL). The second transistor (M2) can be turned on when a scan signal of a gate-on voltage (e.g., a logic high voltage or a high level voltage) is supplied from the scan line (SL), thereby electrically connecting the data line (DL) and the first node (N1).

[0083] For each frame period, a data signal of the corresponding frame may be supplied to the data line (DL), and the data signal may be transmitted to the first node (N1) through the second transistor (M2) during the period when a scan signal of the gate-on voltage is supplied. For example, the second transistor (M2) may be a switching transistor for transmitting each data signal into the interior of the subpixel (SPX).

[0084] A capacitor (Cst) can be electrically connected between a first node (N1) and a second node (N2). The capacitor (Cst) can charge a voltage corresponding to a data signal supplied to the first node (N1) during each frame period.

[0085] The third transistor (M3) may be electrically connected between the second node (N2) and the sensing line (SENL). The gate electrode of the third transistor (M3) may be electrically connected to the control line (SSL) (or the scan line (SL)). The third transistor (M3) is turned on when a control signal (or scan signal) of a gate-on voltage (e.g., a logic high voltage or a high level voltage) is supplied from the control line (SSL), so that it can transmit a reference voltage (or initialization voltage) supplied to the sensing line (SENL) to the second node (N2) or transmit the voltage of the second node (N2) to the sensing line (SENL). In one embodiment, the voltage of the second node (N2) may be transmitted to a sensing circuit through the sensing line (SENL), and the characteristic deviation and / or change of the subpixels (SPX) may be compensated based on the sensing signal output from the sensing circuit.

[0086] In FIGS. 4 and 5, the transistors (M) included in the pixel circuit (PXC) are all depicted as N-type transistors, but the embodiments are not limited thereto. For example, at least one of the first, second, and third transistors (M1, M2, M3) may be changed to a P-type transistor. The structure and driving method of the sub-pixel (SPX) may be varied according to the embodiments.

[0087] The light-emitting unit (EMU) may include at least one light-emitting element (LD) connected between a first power line (PL1) and a second power line (PL2). In one embodiment, the light-emitting element (LD) may include a first end (EP1) electrically connected to the first power line (PL1) through a pixel circuit (PXC), and a second end (EP2) electrically connected to the second power line (PL2).

[0088] A first power supply voltage (VDD) and a second power supply voltage (VSS) can be supplied to a light-emitting unit (EMU), respectively, through a first power line (PL1) and a second power line (PL2). For example, the light-emitting unit (EMU) can be electrically connected to a power supply voltage generating unit through the first power line (PL1) and the second power line (PL2), and the first power supply voltage (VDD) and the second power supply voltage (VSS) generated by the power supply voltage generating unit can be supplied to the light-emitting unit (EMU) through the first power line (PL1) and the second power line (PL2). In one embodiment, the first power supply voltage (VDD) may be a high-potential power supply voltage, and the second power supply voltage (VSS) may be a low-potential power supply voltage.

[0089] In the embodiments, the first end (EP1) of the light-emitting element (LD) may be a P-type end, and the second end (EP2) of the light-emitting element (LD) may be an N-type end. For example, the light-emitting element (LD) may be connected in the forward direction between the first power line (PL1) and the second power line (PL2), thereby constituting an effective light source for the corresponding subpixel (SPX).

[0090] In one embodiment, the light-emitting unit (EMU) may include a single light-emitting element (LD) connected in the forward direction between the first power line (PL1) and the second power line (PL2) (for example, between the pixel circuit (PXC) and the second power line (PL2)), as shown in FIG. 4. In another embodiment, the light-emitting unit (EMU) may include two or more light-emitting elements (LDs) connected in the forward direction between the first power line (PL1) and the second power line (PL2). For example, the light-emitting unit (EMU) may include light-emitting elements (LDs) connected in series and parallel to each other between the first power line (PL1) and the second power line (PL2), as shown in FIG. 5. For example, the light-emitting unit (EMU) may include first and second serial terminals, and may include at least one first light-emitting element (LD1) disposed and / or connected to the first serial terminal and at least one second light-emitting element (LD2) disposed and / or connected to the second serial terminal. The connection structure of the light-emitting elements (LDs) constituting each light-emitting unit (EMU) may be changed according to the embodiments. For example, the light-emitting elements (LDs) may be connected only in series or in parallel between the first power line (PL1) and the second power line (PL2). The number, type, and / or connection structure of the light-emitting elements (LDs) constituting the effective light source of the subpixel (SPX) may be varied according to the embodiments.

[0091] In the embodiments, each light-emitting element (LD) may be a rod-shaped inorganic light-emitting element. Additionally, each light-emitting element (LD) may be a micro-sized light-emitting element having a size in the range of nanometers to micrometers. For example, the light-emitting element (LD) may be the light-emitting element (LD) according to the embodiment of FIGS. 1 and 2, but the embodiments are not limited thereto. For example, the type, material, structure, size and / or shape of the light-emitting element (LD) may be varied according to the embodiments.

[0092] FIG. 6 is a plan view showing a display area (DA) according to an embodiment of the present invention. FIG. 6 schematically illustrates the structure of a display area (DA) and pixels (PXL) placed in the display area (DA), centering on a first pixel (PXL1) and a second pixel (PXL2) that are adjacent to each other along a second direction (DR2) in the display area (DA). For example, the first pixel (PXL1) may be placed on the nth (n is a natural number) horizontal line (e.g., the nth pixel row) and the mth (m is a natural number) vertical line (e.g., the mth pixel column) of the display area (DA), and the second pixel (PXL2) may be placed on the n+1st horizontal line (e.g., the n+1th pixel row) and the mth vertical line of the display area (DA). In this case, the first pixel (PXL1) and the second pixel (PXL2) may be placed on the same vertical line in the display area (DA) and may be adjacent to each other vertically in the second direction (DR2).

[0093] Referring to FIGS. 3 through 6, the display area (DA) may include pixels (PXL) including a first pixel (PXL1) and a second pixel (PXL2), and scan lines (SL), data lines (DL), sensing lines (SENL), a first power line (PL1), and a second power line (PL2) electrically connected to the pixels (PXL). In one embodiment, the control line (SSL) of each horizontal line may be integrated with the scan line (SL) of the corresponding horizontal line.

[0094] In one embodiment, the display area (DA) may further include connecting lines (CL) that intersect scan lines (SL) and / or at least one dummy line. For example, the display area (DA) may include connecting lines (CL) corresponding to each scan line (SL) and may optionally further include dummy lines, etc.

[0095] For example, among the pixel columns of a display area (DA), connection lines (CL), each electrically connected to one scan line (SL), and / or dummy lines separated from said connection lines (CL) may be disposed inside and / or around some pixel columns. In one embodiment, said dummy lines may be utilized as sub-wires to lower the resistance of the first and / or second power lines (PL1, PL2). Dummy lines (or sub-power lines), each electrically connected to the first power line (PL1) or the second power line (PL2), may be disposed inside and / or around other pixel columns.

[0096] Scan lines (SL) may extend in a first direction (DR1) from a display area (DA) and may be formed for each horizontal line. For example, the scan lines (SL) may include an nth scan line (SLn) placed on or around the nth horizontal line of the display area (DA), and an n+1th scan line (SLn+1) placed on or around the n+1th horizontal line of the display area (DA). Each scan line (SL) may extend in a first direction (DR1) from the display area (DA) and may be electrically connected to pixel circuits (PXC) of subpixels (SPX) placed on the corresponding horizontal line.

[0097] In one embodiment, each scan line (SL) may be electrically connected to at least one connecting wire (CL) and may be electrically connected to a driving circuit (DIC) through the at least one connecting wire (CL). For example, the nth scan line (SLn) may be electrically connected to the nth connecting wire (CLn) and may be electrically connected to a driving circuit (DIC) through the nth connecting wire (CLn) and a pad electrically connected thereto. Similarly, the n+1th scan line (SLn+1) may be electrically connected to the n+1th connecting wire (CLn+1) and may be electrically connected to a driving circuit (DIC) through the nth connecting wire (CLn+1) and a pad electrically connected thereto.

[0098] Connecting wires (CL) may extend in a second direction (DR2) from a display area (DA) and may be formed on or around at least some of the vertical lines. Connecting wires (CL) may correspond to each scan line (SL) and may be electrically connected to each scan line (SL). For example, connecting wires (CL) may include an nth connecting wire (CLn) corresponding to an nth scan line (SLn) and electrically connected to said nth scan line (SLn), and an nth+1th connecting wire (CLn+1) corresponding to an n+1th scan line (SLn+1) and electrically connected to said n+1th scan line (SLn+1). The location, size (e.g., width and / or length) and / or arrangement order of the connecting wires (CL) may be changed according to the embodiments.

[0099] Data lines (DL) may extend along a second direction (DR2) in a display area (DA) and may be formed for each vertical line. For example, a m-th data line (DLm) may be formed on the m-th vertical line of the display area (DA). However, the embodiments are not limited thereto. For example, data lines (DL) may be formed for every two adjacent vertical lines, and the two vertical lines may share data lines (DL). In this case, the time at which a data signal is input to the pixels (PXL) can be divided by separating the scan lines (SL) connected to the pixels (PXL) of the two vertical lines.

[0100] Each data line (DL) may be connected to the pixel circuits (PXC) of the subpixels (SPX) placed on the corresponding vertical line. Additionally, each data line (DL) may include sub-data lines that are individually connected to the subpixels (SPX) constituting each pixel (PXL). For example, the m-th data line (DLm) may include a first sub-data line (D1) electrically connected to the first subpixels (SPX1) of the pixels (PXL) placed on the m-th vertical line, a second sub-data line (D2) electrically connected to the second subpixels (SPX2) of the pixels (PXL) placed on the m-th vertical line, and a third sub-data line (D3) electrically connected to the third subpixels (SPX3) of the pixels (PXL) placed on the m-th vertical line. Accordingly, data signals can be supplied individually to each subpixel (SPX).

[0101] Sensing lines (SENL) may extend along a second direction (DR2) in a display area (DA) and may be formed for at least one vertical line. In one embodiment, the sensing lines (SENL) may be formed for each vertical line and may be commonly connected to the subpixels (SPX) constituting each pixel (PXL). In this case, the characteristics of each pixel (PXL) can be detected individually. In another embodiment, the sensing lines (SENL) may be formed to be shared by a plurality of vertical lines. In this case, the characteristics of the pixels (PXL) can be detected in block units containing a plurality of pixels (PXL).

[0102] The first power line (PL1) and the second power line (PL2) can be commonly connected to pixels (PXL) of a display area (DA). For example, the first power line (PL1) can be commonly connected to pixel circuits (PXC) of subpixels (SPX), and the second power line (PL2) can be commonly connected to light-emitting units (EMU) of subpixels (SPX) (for example, second alignment electrodes (ALE2) of the light-emitting units (EMU)).

[0103] In one embodiment, the first power line (PL1) and the second power line (PL2) may each be formed as mesh-shaped wiring. Accordingly, the voltage drop (IR drop) of the first power voltage (VDD) and the second power voltage (VSS) can be prevented or reduced, and the first power voltage (VDD) and the second power voltage (VSS) at a uniform level can be delivered to the pixels (PXL).

[0104] For example, the first power line (PL1) may include at least one first horizontal power line (HPL1) (also referred to as the “first horizontal power line”) extending in a first direction (DR1) from the display area (DA), and at least one first vertical power line (VPL1) (also referred to as the “first vertical power line”) extending in a second direction (DR2) from the display area (DA) and electrically connected to the first horizontal power line (HPL1). At least one first horizontal power line (HPL1) and at least one first vertical power line (VPL1) may intersect each other and may be connected to each other at all or some of the intersection points.

[0105] Similarly, the second power line (PL2) may include at least one second horizontal power line (HPL2) (also referred to as the “second horizontal power line”) extending in a first direction (DR1) from the display area (DA), and at least one second vertical power line (VPL2) (also referred to as the “second vertical power line”) extending in a second direction (DR2) from the display area (DA) and electrically connected to the second horizontal power line (HPL2). At least one second horizontal power line (HPL2) and at least one second vertical power line (VPL2) may intersect each other and may be connected to each other at all or some of the intersection points.

[0106] In one embodiment, the first horizontal power line (HPL1) and the second horizontal power line (HPL2) may be formed for each of one horizontal line or a plurality of horizontal lines. For example, the first horizontal power line (HPL1) and the second horizontal power line (HPL2) may be arranged alternately for each horizontal line. For example, the first horizontal power line (HPL1) may be placed on odd-numbered horizontal lines (or even-numbered horizontal lines), and the second horizontal power line (HPL2) may be placed on even-numbered horizontal lines (or odd-numbered horizontal lines).

[0107] In one embodiment, the first horizontal power line (HPL1) and the second horizontal power line (HPL2) may be positioned immediately adjacent to the light-emitting regions provided to the pixels (PXL) of the corresponding horizontal line (e.g., light-emitting regions corresponding to each light-emitting unit (EMU)). For example, the first horizontal power line (HPL1) and the second horizontal power line (HPL2) may be immediately adjacent to the bottom edge regions of the light-emitting regions corresponding to the light-emitting units (EMU) of the corresponding horizontal line and may cross the pixel regions (PXA) where the pixels (PXL) of the corresponding horizontal line are positioned. For example, a first horizontal power line (HPL1) may be placed between the second and third pixel circuits (PXC2, PXC3) (pixel circuits of the second and third subpixels (SPX2, SPX3)) provided to the pixels (PXL) of the odd-numbered horizontal lines (or, even-numbered horizontal lines), and a second horizontal power line (HPL2) may be placed between the second and third pixel circuits (PXC2, PXC3) (pixel circuits of the second and third subpixels (SPX2, SPX3)) provided to the pixels (PXL) of the even-numbered horizontal lines (or, odd-numbered horizontal lines). In one embodiment, the first and third pixel circuits (PXC1, PXC3) of the pixels (PXL) provided in each horizontal line (pixel circuits of the first and third subpixels (SPX1, SPX3)) may be located between two wires that extend in a first direction (DR1) and are located on both sides of the light-emitting regions corresponding to the light-emitting parts (EMU) of the corresponding horizontal lines in a second direction (DR2). For example, the first and third pixel circuits (PXC1, PXC3) provided in the pixels (PXL) of each horizontal line may be positioned between the scan line (SL) of the corresponding horizontal line and the first or second horizontal power line (HPL1 or HPL2).

[0108] The number, location, and / or arrangement structure of the first horizontal power line (HPL1) and the second horizontal power line (HPL2) may be varied according to the embodiments.

[0109] In one embodiment, a first vertical power line (VPL1) and a second vertical power line (VPL2) may be formed for at least one vertical line. For example, the first vertical power line (VPL1) and the second vertical power line (VPL2) may be formed for each vertical line (or its vicinity) and may be spaced apart from each other with pixel circuits (PXCs) arranged in the pixel column of the corresponding vertical line in between. The number and / or location of the first vertical power line (VPL1) and the second vertical power line (VPL2), etc., may vary depending on the embodiments.

[0110] Each pixel (PXL) may include subpixels (SPX). For example, each pixel (PXL) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3).

[0111] Each subpixel (SPX) may include a pixel circuit (PXC) and a light-emitting unit (EMU). For example, a first subpixel (SPX1) may include a first pixel circuit (PXC1) and a first light-emitting unit (EMU1), and a second subpixel (SPX2) may include a second pixel circuit (PXC2) and a second light-emitting unit (EMU2). A third subpixel (SPX3) may include a third pixel circuit (PXC3) and a third light-emitting unit (EMU3).

[0112] The pixel circuits (PXC) and light-emitting units (EMU) of each pixel (PXL) may be placed on different layers and may overlap each other. For example, the pixel circuits (PXC) may be placed on the circuit layer (e.g., the circuit layer (PCL) of FIG. 7) of the corresponding pixel area (PXA) where each pixel (PXL) is placed. The light-emitting units (EMU) may be placed on the display layer (e.g., the display layer (DPL) of FIG. 7) of the corresponding pixel area (PXA) so as to overlap with at least one pixel circuit (PXC) of the corresponding pixel (PXL) (e.g., the first pixel circuit (PXC1) and the third pixel circuit (PXC3)), and / or at least one wiring (e.g., at least one scan line (SL), sensing line (SENL), data line (DL), first power line (PL1), second power line (PL2), and / or connection wiring (CL)).

[0113] In FIG. 6, the area in which each pixel circuit (PXC) is placed is indicated, centering on the area in which the main circuit elements constituting each pixel circuit (PXC) (e.g., transistors (M) and capacitors (Cst)) or at least a part of said circuit elements are placed. In some embodiments, other parts of said circuit elements may be located outside the indicated area. Also, in FIG. 6, the area in which each light-emitting unit (EMU) is placed is indicated, centering on the area in which the main elements constituting each light-emitting unit (EMU) (e.g., light-emitting elements (LD) and electrodes electrically connected to said light-emitting elements (LD)) or at least a part of said main elements are placed. In some embodiments, at least one other part of said main elements (e.g., ends of electrodes connected to said light-emitting elements (LD)) may be located outside the indicated area.

[0114] The first, second, and third pixel circuits (PXC1, PXC2, PXC3) may be arranged in a second direction (DR2) in each pixel area (PXA). For example, the first, second, and third pixel circuits (PXC1, PXC2, PXC3) of the first pixel (PXL1) may be arranged along the second direction (DR2) in a predetermined order in the first pixel area (PXA1) where the first pixel (PXL1) is provided. Similarly, the first, second, and third pixel circuits (PXC1, PXC2, PXC3) of the second pixel (PXL2) may be arranged along the second direction (DR2) in a predetermined order in the second pixel area (PXA2) where the second pixel (PXL2) is provided.

[0115] In one embodiment, the third pixel circuit (PXC3) may be located at the center of each pixel area (PXA) in the second direction (DR2), and the first and second pixel circuits (PXC1, PXC2) may be placed on both sides of the third pixel circuit (PXC3) in the second direction (DR2). For example, in each pixel area (PXA), the pixel circuits (PXC) may be arranged in the order of the first pixel circuit (PXC1), the third pixel circuit (PXC3), and the second pixel circuit (PXC2) along the second direction (DR2). The location and / or arrangement order of the first, second, and third pixel circuits (PXC1, PXC2, PXC3) may be changed according to the embodiments.

[0116] The first, second, and third pixel circuits (PXC1, PXC2, PXC3) may be commonly connected to the first power line (PL1) and the scan line (SL) of the corresponding horizontal line, and may be connected to different sub-data lines of the corresponding vertical line. For example, the first pixel circuit (PXC1) may be electrically connected to the first sub-data line (D1), and the second pixel circuit (PXC2) may be electrically connected to the second sub-data line (D2). The third pixel circuit (PXC3) may be electrically connected to the third sub-data line (D3).

[0117] In one embodiment, the first, second, and third pixel circuits (PXC1, PXC2, PXC3) may be further connected to a sensing line (SENL). For example, the first, second, and third pixel circuits (PXC1, PXC2, PXC3) may be commonly connected to the sensing line (SENL) of the corresponding vertical line.

[0118] The first, second, and third light-emitting units (EMU1, EMU2, EMU3) can be connected between the respective pixel circuits (PXC) and the second power line (PL2). For example, the first, second, and third light-emitting units (EMU1, EMU2, EMU3) can be electrically connected to the first, second, and third pixel circuits (PXC1, PXC2, PXC3) respectively through the respective first contact holes (for example, the first contact holes (CH1) of FIGS. 8 and 9). Additionally, the first, second, and third light-emitting units (EMU1, EMU2, EMU3) can be electrically connected to the second power line (PL2) through the respective second contact holes (for example, the second contact holes (CH2) of FIGS. 8 and 9).

[0119] The first, second, and third light-emitting units (EMU1, EMU2, EMU3) may be arranged in a first direction (DR1) in their respective pixel regions (PXA). For example, the first, second, and third light-emitting units (EMU1, EMU2, EMU3) of a first pixel (PXL1) may be arranged sequentially along the first direction (DR1) in a first pixel region (PXA1) corresponding to the first pixel (PXL1). Similarly, the first, second, and third light-emitting units (EMU1, EMU2, EMU3) of a second pixel (PXL2) may be arranged sequentially along the first direction (DR1) in a second pixel region (PXA2) corresponding to the second pixel (PXL2). The first, second, and third subpixels (SPX1, SPX2, SPX3) may each have respective light-emitting regions (e.g., the first, second, and third light-emitting regions (EA1, EA2, EA3) of FIG. 9) corresponding to a region (or part) of the first, second, and third light-emitting parts (EMU1, EMU2, EMU3). Accordingly, the light-emitting regions of the first, second, and third subpixels (SPX1, SPX2, SPX3) may be arranged sequentially along the second direction (DR2). In this case, based on the light-emitting regions of the first, second, and third subpixels (SPX1, SPX2, SPX3), the first, second, and third subpixels (SPX1, SPX2, SPX3) may be seen as being arranged along the second direction (DR2).

[0120] FIG. 6 discloses an embodiment in which the pixel circuits (PXC) and light-emitting units (EMU) of subpixels (SPX) are arranged along different directions in each pixel area (PXA), but the embodiments are not limited thereto. For example, the position and / or arrangement direction of the pixel circuits (PXC) and light-emitting units (EMU), etc., may be varied according to the embodiments.

[0121] FIG. 7 is a cross-sectional view showing a display area (DA) according to an embodiment of the present invention. For example, FIG. 7 schematically shows a cross-section of a display area (DA) centered on a single subpixel (SPX) that includes a light-emitting unit (EMU) having a series-parallel structure (or a series structure) including first and second light-emitting elements (LD1, LD2) as in the embodiment of FIG. 5.

[0122] Subpixels (SPX) placed in the display area (DA) may have substantially the same or similar cross-sectional structures. However, the size, location, and / or shape of the circuit elements constituting the subpixels (SPX) and the electrodes included in the circuit elements may differ depending on the subpixels (SPX). For example, when viewed in a planar view, the first transistor (M1) of the first subpixel (SPX1) may have a different shape and / or size from the first transistor (M1) of the second subpixel (SPX2).

[0123] Referring to FIGS. 1 through 7, a display device (DD) may include a base layer (BSL), a circuit layer (PCL) (also referred to as a “circuit element layer,” “pixel circuit layer,” or “backplane”), and a display layer (DPL) (also referred to as a “display element layer” or “light-emitting element layer”). The circuit layer (PCL) and the display layer (DPL) may overlap each other on the base layer (BSL). For example, the circuit layer (PCL) and the display layer (DPL) may be sequentially arranged on one side of the base layer (BSL).

[0124] The display device (DD) may further include a color filter layer (CFL) and / or an encapsulation layer (ENC) (or a protective layer) disposed on the display layer (DPL). In one embodiment, the color filter layer (CFL) and the encapsulation layer (ENC) may be formed directly on one side of the base layer (BSL) provided with the circuit layer (PCL) and the display layer (DPL). Accordingly, the thickness of the display device (DD) can be reduced.

[0125] The base layer (BSL) may be a substrate or film made of a rigid or flexible material. In one embodiment, the base layer (BSL) may include at least one insulating material and may have a single layer or a multi-layer structure.

[0126] A circuit layer (PCL) may be provided on one side of a base layer (BSL). The circuit layer (PCL) may include pixel circuits (PXC) of each pixel (PXL). For example, circuit elements (e.g., transistors (M) and capacitors (Cst)) constituting the first, second, and third pixel circuits (PXC1, PXC2, PXC3) of the corresponding pixel (PXL) may be formed in each pixel area (PXA) of the circuit layer (PCL). In FIG. 7, as an example of circuit elements that may be disposed in the circuit layer (PCL) of a display area (DA), a cross-section of one transistor (M) (e.g., a first transistor (M1) including a lower metal layer (BML)) provided in each pixel circuit (PXC) is schematically illustrated.

[0127] Additionally, the circuit layer (PCL) may include signal lines and power lines connected to pixels (PXL). For example, the circuit layer (PCL) may include scan lines (SL), data lines (DL), sensing lines (SENL), a first power line (PL1), and a second power line (PL2). In one embodiment, the circuit layer (PCL) may further include connection lines (CL) and / or dummy lines.

[0128] In the embodiments, some of the wiring (or parts of said wiring) provided in the circuit layer (PCL) may be placed on the same layer as some elements or electrodes of the transistors (M). Other parts of the wiring (or parts of said wiring) provided in the circuit layer (PCL) may be placed on the same layer as other elements or electrodes of the transistors (M).

[0129] The circuit layer (PCL) may include conductive layers, including electrodes of circuit elements, conductive patterns and / or bridge patterns, and wiring. For example, the circuit layer (PCL) may include conductive layers (e.g., first, second, and third conductive layers) sequentially disposed on a base layer (BSL) along a third direction (DR3). The conductive layers may each include electrodes, conductive patterns, bridge patterns, and / or wiring. The circuit layer (PCL) may further include a semiconductor layer including semiconductor patterns (SCP) of transistors (M).

[0130] The circuit layer (PCL) may further include insulating layers. For example, the circuit layer (PCL) may include a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (ILD), and / or a passivation layer (PSV) sequentially disposed on one side of the base layer (BSL).

[0131] The circuit layer (PCL) may include a first conductive layer disposed on the base layer (BSL). For example, the first conductive layer may be disposed between the base layer (BSL) and the buffer layer (BFL) and may include lower metal layers (BML) of the first transistors (M1) included in the subpixels (SPX). Each lower metal layer (BML) may overlap with the semiconductor pattern (SCP) of the corresponding first transistor (M1).

[0132] The first conductive layer may further include at least one additional wire. For example, the first conductive layer may include wires (or parts of said wires) extending from the display area (DA) to the second direction (DR2). As an example, the first conductive layer may include data lines (DL), sensing lines (SENL), first vertical power lines (VPL1), second vertical power lines (VPL2), and / or connecting wires (CL).

[0133] A buffer layer (BFL) may be disposed on one side of a base layer (BSL) including a first conductive layer. The buffer layer (BFL) can prevent impurities from diffusing into each circuit element.

[0134] A semiconductor layer may be disposed on the buffer layer (BFL). The semiconductor layer may include semiconductor patterns (SCPs) of transistors (M). Each semiconductor pattern (SCP) may include a channel region that overlaps with the gate electrode (GE) of the corresponding transistor (M), and first and second conductive regions (e.g., source and drain regions) disposed on both sides of the channel region.

[0135] A gate insulating layer (GI) may be disposed on the semiconductor layer. A second conductive layer may be disposed on the gate insulating layer (GI).

[0136] The second conductive layer may include the gate electrodes (GE) of the transistors (M). The second conductive layer may further include one electrode (e.g., a lower electrode) of each of the capacitors (Cst) provided in the pixel circuits (PXC). Additionally, if at least one power line (e.g., a first vertical power line (VPL1) and / or a second vertical power line (VPL2)) and / or signal line (e.g., connection lines (CL)) disposed in the display area (DA) are composed of multiple layers, the second conductive layer may further include at least one conductive pattern (e.g., the first sub-wires (SLI1) of FIG. 8) constituting the at least one power line and / or signal line.

[0137] An interlayer insulating layer (ILD) may be disposed on the second conductive layer. A third conductive layer may be disposed on the interlayer insulating layer (ILD).

[0138] The third conductive layer may include source electrodes (SE) and drain electrodes (DE) of transistors (M). Each source electrode (SE) may be connected to one region (e.g., source region) of a semiconductor pattern (SCP) included in the transistor (M) through at least one contact hole (CH), and each drain electrode (DE) may be connected to another region (e.g., drain region) of a semiconductor pattern (SCP) included in the transistor (M) through at least one other contact hole (CH).

[0139] The third conductive layer may further include one electrode (e.g., upper electrode) of each of the capacitors (Cst) provided in the pixel circuits (PXC), and at least one wiring and / or bridge pattern. For example, the third conductive layer may include wirings (or a portion of said wirings) extending in a first direction (DR1) in the display area (DA). For example, the third conductive layer may include scan lines (SL), first horizontal power lines (HPL1) and second horizontal power lines (HPL2). Additionally, if at least one power line (e.g., first vertical power line (VPL1) and / or second vertical power line (VPL2)) and / or signal line (e.g., connection wiring (CL)) disposed in the display area (DA) is composed of multiple layers, the third conductive layer may further include at least one conductive pattern (e.g., second sub-wiring (SLI2) of FIG. 8) constituting the at least one power line and / or signal line.

[0140] Each electrode, conductive pattern, and / or wiring constituting the first to third conductive layers may have conductivity by including a conductive material, and the constituent material is not particularly limited. For example, each electrode, conductive pattern, and / or wiring constituting the first to third conductive layers may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or other conductive materials.

[0141] A passivation layer (PSV) may be disposed on the third conductive layer. Each of the buffer layer (BFL), gate insulating layer (GI), interlayer insulating layer (ILD), and passivation layer (PSV) may be a single layer or multiple layers and may include an inorganic insulating material and / or an organic insulating material. For example, each of the buffer layer (BFL), gate insulating layer (GI), interlayer insulating layer (ILD), and passivation layer (PSV) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y It may include ), or other insulating materials. In FIG. 7, insulating layers disposed on the circuit layer (PCL), for example, a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (ILD), and a passivation layer (PSV), are depicted as substantially flat, but each insulating layer may have a curvature corresponding to a step caused by the underlying conductive pattern and / or insulating pattern, etc.

[0142] In one embodiment, the passivation layer (PSV) may include an organic insulating layer and can substantially flatten the surface of the circuit layer (PCL). However, the passivation layer (PSV) may have a slight curvature corresponding to patterns disposed below (e.g., electrodes, conductive patterns, and / or wiring included in the third conductive layer), and thus may have a height variation due to the patterns below.

[0143] A display layer (DPL) can be placed on the passivation layer (PSV).

[0144] The display layer (DPL) may include light-emitting parts (EMU) of each pixel (PXL). For example, in each pixel region (PXA) of the display layer (DPL), light-emitting elements (LD) constituting first, second, and third light-emitting parts (EMU1, EMU2, EMU3) and electrodes connected thereto (for example, at least one pair of alignment electrodes (ALE) and at least one pair of contact electrodes (CNE) provided in each light-emitting part (EMU)) may be formed.

[0145] In the embodiments, the display layer (DPL) may include a first alignment electrode (ALE1), a second alignment electrode (ALE2), at least one first light-emitting element (LD1), a first contact electrode (CNE1), and a second contact electrode (CNE2), which are disposed in the light-emitting region (EA) of each subpixel (SPX) and constitute a light-emitting unit (EMU) of the said subpixel (SPX). In one embodiment, each light-emitting unit (EMU) may further include a third alignment electrode (ALE3), at least one second light-emitting element (LD2), and a third contact electrode (CNE3) additionally provided in each light-emitting region (EA) of the display layer (DPL).

[0146] The display layer (DPL) may further include insulating layers and / or insulating patterns sequentially disposed on one side of the base layer (BSL) on which the circuit layer (PCL) is formed. For example, the display layer (DPL) may include bank patterns (BNP), a first insulating layer (INS1), a first bank (BNK1), a second insulating layer (INS2), a third insulating layer (INS3), and / or a fourth insulating layer (INS4) sequentially disposed on the circuit layer (PCL). In one embodiment, the display layer (DPL) may further include a second bank (BNK2) and a light conversion layer (CCL).

[0147] Bank patterns (BNP) (also referred to as “patterns” or “wall patterns”) may be provided and / or formed on the passivation layer (PSV). Bank patterns (BNP) may be placed beneath the alignment electrodes (ALE) to overlap with a portion of each alignment electrode (ALE).

[0148] In one embodiment, bank patterns (BNP) may be formed as separate patterns that are individually arranged corresponding to each pixel (PXL). For example, in each pixel region (PXA), bank patterns (BNP) corresponding to subpixels (SPX) of the corresponding pixel (PXL) may be formed integrally to form substantially one bank pattern (BNP). The bank pattern (BNP) corresponding to each pixel (PXL) may be considered as a component included in the corresponding pixel (PXL) (or the light-emitting unit (EMU) provided to the pixel (PXL)) or as an element that may be provided to the pixel (PXL) separately from the pixel (PXL).

[0149] In another embodiment, bank patterns (BNP) corresponding to at least two adjacent pixels (PXL) may be integrally formed to substantially form a single bank pattern (BNP). For example, bank patterns (BNP) corresponding to pixels (PXL) arranged in each horizontal line and aligned in a first direction (DR1) may be integrally formed. A portion of the bank pattern (BNP) corresponding to each pixel (PXL) may be considered as a component included in the corresponding pixel (PXL) (or the light-emitting unit (EMU) provided to the pixel (PXL)) or as an element that may be provided to the pixel (PXL) separately from the pixel (PXL).

[0150] Each bank pattern (BNP) may include openings (OPN) corresponding to light-emitting element array regions (AR) of subpixels (SPX) provided in the corresponding pixel(s) (PXL). For example, the bank pattern (BNP) may be a pattern including first openings (OPN1) corresponding to first light-emitting element array regions (AR1) where first light-emitting elements (LD1) of first, second, and third subpixels (SPX1, SPX2, SPX3) provided in the corresponding pixel(s) (PXL) are placed, and / or second openings (OPN2) corresponding to second light-emitting element array regions (AR2) where second light-emitting elements (LD2) of said first, second, and third subpixels (SPX1, SPX2, SPX3) are placed.

[0151] By means of bank patterns (BNP), alignment electrodes (ALE) can protrude upward (e.g., a third direction (DR3)) around the light-emitting elements (LD). The bank patterns (BNP) and alignment electrodes (ALE) can form reflective protruding patterns around the light-emitting elements (LD). Accordingly, the light efficiency of the subpixels (SPX) can be improved.

[0152] Bank patterns (BNP) may include inorganic insulating material and / or organic insulating material and may have a single-layer or multi-layer structure. In one embodiment, bank patterns (BNP) may be organic film patterns including organic insulating material and the top surface may be substantially flat. However, if the surface of the circuit layer (PCL) has curvature, the bank patterns (BNP) may have a slight curvature corresponding to the curvature of the circuit layer (PCL). For example, the bank patterns (BNP) may be formed relatively high in the portion where the surface of the circuit layer (PCL) has a maximum height.

[0153] Alignment electrodes (ALE) of light-emitting units (EMU) can be placed on bank patterns (BNP).

[0154] Alignment electrodes (ALE) may include a conductive material, and the constituent material is not particularly limited. For example, the alignment electrodes (ALE) comprise at least one metal or an alloy containing the same among various metallic materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., at least one conductive material among conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), and FTO (Fluorine-doped Tin Oxide), and conductive polymers such as PEDOT. It may include carbon nanotubes, graphene, and / or other conductive materials.

[0155] The first alignment electrode (ALE1) and the second alignment electrode (ALE2) may be adjacent to each other and spaced apart from each other. For example, the first alignment electrode (ALE1) and the second alignment electrode (ALE2) may be adjacent to each other in a first direction (DR1) and spaced apart from each other in the first direction (DR1). At least one first light-emitting element (LD1) may be disposed between the first alignment electrode (ALE1) and the second alignment electrode (ALE2) (or in the corresponding first light-emitting element array region (AR1)).

[0156] The second alignment electrode (ALE2) and the third alignment electrode (ALE3) may be adjacent to each other and spaced apart from each other. For example, the second alignment electrode (ALE2) and the third alignment electrode (ALE3) may be adjacent to each other in a first direction (DR1) and spaced apart from each other in the first direction (DR1). For example, in the light-emitting region (EA) of each subpixel (SPX), the first alignment electrode (ALE1), the second alignment electrode (ALE2), and the third alignment electrode (ALE3) may be arranged sequentially along the first direction (DR1). At least one second light-emitting element (LD2) may be arranged between the second alignment electrode (ALE2) and the third alignment electrode (ALE3) (or in the corresponding second light-emitting element array region (AR2)). The number, shape, size, and / or location of the alignment electrodes (ALE) arranged in each light-emitting region (EA) may be changed according to the embodiments.

[0157] Each of the alignment electrodes (ALE) may be a single layer or multiple layers. For example, each alignment electrode (ALE) may include a reflective electrode layer comprising a reflective conductive material (e.g., metal) and may be a single layer or multiple layers electrode.

[0158] A first insulating layer (INS1) may be disposed on the alignment electrodes (ALE). In one embodiment, the first insulating layer (INS1) may include each contact hole (e.g., the fourth and fifth contact holes (CH4, CH5) of FIG. 9) for electrically connecting at least some of the alignment electrodes (ALE) (e.g., first and second alignment electrodes (ALE1, ALE2)) to their corresponding contact electrodes (CNE) (e.g., first and third contact electrodes (CNE1, CNE3)).

[0159] The first insulating layer (INS1) may be a single layer or multiple layers and may include an inorganic insulating material and / or an organic insulating material. In one embodiment, the first insulating layer (INS1) is silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y It may include ), or other inorganic insulating materials.

[0160] As the alignment electrodes (ALE) are covered by the first insulating layer (INS1), damage to the alignment electrodes (ALE) can be prevented during subsequent processes. Additionally, it can prevent short circuit defects caused by improper connection between the alignment electrodes (ALE) and the light-emitting elements (LD).

[0161] A first bank (BNK1) may be disposed in a display area (DA) where alignment electrodes (ALE) and a first insulating layer (INS1) are formed. The first bank (BNK1) may have openings corresponding to light-emitting regions (EA) of subpixels (SPX) and may be formed in a non-light-emitting region (NEA) to surround the light-emitting regions (EA) of said subpixels (SPX). By the first bank (BNK1), each light-emitting region (EA) to which light-emitting elements (LD) are supplied may be defined (or partitioned).

[0162] In one embodiment, the first bank (BNK1) may include a black matrix material or other light-blocking and / or reflective material. The first bank (BNK1) may include an inorganic insulating material and / or an organic insulating material and may have a single-layer or multi-layer structure. In one embodiment, the first bank (BNK1) may be an organic film pattern including an organic insulating material and may have a relatively gentle curvature. In one embodiment, the first bank (BNK1) may have different heights in parts by patterns placed underneath. For example, the first bank (BNK1) may be formed relatively higher than the rest of the part overlapping with the bank patterns (BNP).

[0163] Light-emitting elements (LDs) may be supplied to each light-emitting region (EA) surrounded by the first bank (BNK1). The light-emitting elements (LDs) may be positioned and / or aligned between a pair of alignment electrodes (ALEs) by each alignment signal applied to the alignment electrodes (ALEs) (or, first, second, and / or alignment wirings prior to being separated into the first, second, and / or third alignment electrodes (ALE1, ALE2, ALE3) of each pixel (PXL) or subpixel (SPX). For example, the light-emitting elements (LDs) supplied to each light-emitting region (EA) may be positioned and / or aligned between the first alignment electrode (ALE1) and the second alignment electrode (ALE2), and between the second alignment electrode (ALE2) and the third alignment electrode (ALE3).

[0164] In one embodiment, a first light-emitting element(s) (LD1) placed and / or aligned in a first light-emitting element array region (AR1) between a first alignment electrode (ALE1) and a second alignment electrode (ALE2) may be arranged in a first direction (DR1) or a diagonal direction, etc., such that a first end (EP1) is adjacent to the first alignment electrode (ALE1) and a second end (EP2) is adjacent to the second alignment electrode (ALE2). A second light-emitting element(s) (LD2) placed and / or aligned in a second light-emitting element array region (AR2) between a second alignment electrode (ALE2) and a third alignment electrode (ALE2) may be arranged in a first direction (DR1) or a diagonal direction, etc., such that a first end (EP1) is adjacent to the third alignment electrode (ALE3) and a second end (EP2) is adjacent to the second alignment electrode (ALE2). The arrangement position and / or direction of the light-emitting elements (LD) may vary depending on the embodiments.

[0165] A second insulating layer (INS2) may be disposed on a portion of each of the light-emitting elements (LD). In one embodiment, the second insulating layer (INS2) may be formed over the entire display area (DA) and may include openings that are open at the first and second ends (EP1, EP2) of the light-emitting elements (LD) aligned with the light-emitting area (EA) of the corresponding subpixel (SPX) and the surrounding area (e.g., an area corresponding to the alignment electrodes (ALE) and / or contact electrodes (CNE)). In another embodiment, the second insulating layer (INS2) may include separate insulating patterns that are locally disposed only on a portion including the central portion of the light-emitting elements (LD) to expose the first and second ends (EP1, EP2) of the light-emitting elements (LD) aligned with each light-emitting area (EA) (or each light-emitting element array area (AR) provided in the light-emitting area (EA)). If a second insulating layer (INS2) is formed on top of the light-emitting elements (LD), the light-emitting elements (LD) can be stably fixed.

[0166] The second insulating layer (INS2) may be a single layer or multiple layers and may include an inorganic insulating material and / or an organic insulating material. For example, the second insulating layer (INS2) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (Al x O y It may include a photoresist material, or other insulating material.

[0167] Different contact electrodes (CNE) may be disposed and / or formed on the first and second ends (EP1, EP2) of the light-emitting elements (LD) that are not covered by the second insulating layer (INS2). For example, a first contact electrode (CNE1) may be disposed on the first end (EP1) of the first light-emitting element (LD1), and a portion of the second contact electrode (CNE2) (for example, the left pattern portion of the second contact electrode (CNE2)) may be disposed on the second end (EP2) of the first light-emitting element (LD1). Another portion of the second contact electrode (CNE2) (for example, the right pattern portion of the second contact electrode (CNE2)) may be disposed on the first end (EP1) of the second light-emitting element (LD2), and a third contact electrode (CNE3) may be disposed on the second end (EP2) of the second light-emitting element (LD2).

[0168] In FIG. 7, the second contact electrode (CNE2) disposed on the second end (EP2) of the first light-emitting element (LD1) and the second contact electrode (CNE2) disposed on the first end (EP1) of the second light-emitting element (LD2) are shown as being separated from each other, but the second contact electrode (CNE2) disposed on the second end (EP2) of the first light-emitting element (LD1) and the second contact electrode (CNE2) disposed on the first end (EP1) of the second light-emitting element (LD2) may be connected to each other either integrally or non-integrally to form a single second contact electrode (CNE2). For example, when viewed in a planar view, the second contact electrode (CNE2) disposed on the second end (EP2) of the first light-emitting element (LD1) and the second contact electrode (CNE2) disposed on the first end (EP1) of the second light-emitting element (LD2) may be integrally connected. The second contact electrode (CNE2) can be electrically connected to the first contact electrode (CNE1) via the first light-emitting element (LD1) and can be electrically connected to the third contact electrode (CNE3) via the second light-emitting element (LD2).

[0169] In one embodiment, a first contact electrode (CNE1) may be formed directly on a first end (EP1) of a first light-emitting element (LD1) and electrically connected to the first end (EP1) of the first light-emitting element (LD1). A second contact electrode (CNE2) may be formed directly on a second end (EP2) of the first light-emitting element (LD1) and a first end (EP1) of a second light-emitting element (LD2) and electrically connected to the second end (EP2) of the first light-emitting element (LD1) and a first end (EP1) of the second light-emitting element (LD2). A third contact electrode (CNE3) may be formed directly on a second end (EP2) of the second light-emitting element (LD2) and electrically connected to the second end (EP2) of the second light-emitting element (LD2). Meanwhile, if each subpixel (SPX) includes only a single light-emitting element (LD) as in the embodiment of FIG. 4, or includes a light-emitting unit (EMU) in a parallel structure, the subpixel (SPX) may include only a pair of contact electrodes (CNE) disposed on the first ends (EP1) and second ends (EP2) of each light-emitting element (LD).

[0170] A first contact electrode (CNE1) may be positioned on top of the first alignment electrode (ALE1) so as to overlap with the first alignment electrode (ALE1). A second contact electrode (CNE2) may be positioned on top of the second alignment electrode (ALE2) and the third alignment electrode (ALE3) so as to overlap with a part of the second alignment electrode (ALE2) and the third alignment electrode (ALE3). A third contact electrode (CNE3) may be positioned on top of the second alignment electrode (ALE2) so as to overlap with another part of the second alignment electrode (ALE2).

[0171] In one embodiment, the first alignment electrode (ALE1) and the first contact electrode (CNE1) may be electrically connected to each other through at least one contact hole (e.g., the fourth contact hole (CH4) in FIG. 9). Similarly, the second alignment electrodes (ALE2) and the third contact electrode (CNE3) may be electrically connected to each other through at least one other contact hole (e.g., the fifth contact hole (CH5) in FIG. 9). The first alignment electrode (ALE1) and / or the first contact electrode (CNE1) of each subpixel (SPX) may be electrically connected to the pixel circuit (PXC) of the corresponding subpixel (SPX) through at least one contact hole (e.g., the first contact hole (CH1) in FIG. 8 and FIG. 9). The second alignment electrodes (ALE2) and / or the third contact electrode (CNE3) of each subpixel (SPX) may be electrically connected to the second power line (PL2) through at least one other contact hole (e.g., the second contact hole (CH2) in FIGS. 8 and 9).

[0172] The contact electrodes (CNE) may include a conductive material. In one embodiment, the contact electrodes (CNE) may include a transparent conductive material so that light generated from the light-emitting elements (LD) can pass through. For example, the contact electrodes (CNE) may include at least one conductive material selected from ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), and In2O3 (Indium Oxide), or other transparent conductive materials.

[0173] The first contact electrode (CNE1), the second contact electrode (CNE2), and / or the third contact electrode (CNE3) may be formed on the same or different layers. For example, the relative positions and / or formation order of the first contact electrode (CNE1), the second contact electrode (CNE2), and the third contact electrode (CNE3) may vary depending on the embodiment.

[0174] In one embodiment, a first contact electrode (CNE1) and a third contact electrode (CNE3) may first be formed on a second insulating layer (INS2). The first contact electrode (CNE1) and the third contact electrode (CNE3) may be formed simultaneously or sequentially. Subsequently, a third insulating layer (INS3) may be formed to cover the first contact electrode (CNE1) and the third contact electrode (CNE3), and a second contact electrode (CNE2) may be formed in each light-emitting region (EA) where the third insulating layer (INS3) is formed.

[0175] In another embodiment, a second contact electrode (CNE2) may first be formed on a second insulating layer (INS2). Subsequently, a third insulating layer (INS3) may be formed in each light-emitting region (EA) to cover at least the second contact electrode (CNE2), and a first contact electrode (CNE1) and a third contact electrode (CNE3) may be formed in each light-emitting region (EA) where the third insulating layer (INS3) is formed. The first contact electrode (CNE1) and the third contact electrode (CNE3) may be formed simultaneously or sequentially.

[0176] In one embodiment, the third insulating layer (INS3) may be formed over the entire display area (DA) and may include openings formed in the area corresponding to the second contact electrodes (CNE2) of the subpixels (SPX) (or the first and third contact electrodes (CNE1, CNE3)) of the subpixels (SPX). In another embodiment, the third insulating layer (INS3) may include separate insulating patterns formed individually for each corresponding light-emitting area (EA) to cover the first and third contact electrodes (CNE1, CNE3) (or the second contact electrode (CNE2)) formed in each light-emitting area (EA).

[0177] The third insulating layer (INS3) may be a single layer or multiple layers and may include an inorganic insulating material and / or an organic insulating material. For example, the third insulating layer (INS3) may be silicon nitride (SiNx ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (Al x O y It may include a photoresist material, or other insulating material. The first insulating layer (INS1), the second insulating layer (INS2) and / or the third insulating layer (INS3) may include the same insulating material or different insulating materials.

[0178] By using the third insulating layer (INS3), when contact electrodes (CNE) (for example, first and second contact electrodes (CNE1, CNE2), or second and third contact electrodes (CNE2, CNE3)) disposed on the first end (EP1) and second end (EP2) of each light-emitting element (LD) are disposed on different layers, the contact electrodes (CNE) can be stably separated and short-circuit defects can be prevented or reduced.

[0179] In some embodiments, the first contact electrode (CNE1), the second contact electrode (CNE2), and the third contact electrode (CNE3) may be placed on the same layer of the display layer (DPL) and may be formed simultaneously or sequentially. In this case, the display area (DA) may not include the third insulating layer (INS3). If the contact electrodes (CNE) are formed simultaneously on the same layer, the pixel process can be simplified and manufacturing efficiency can be increased.

[0180] In one embodiment, the display device (DD) may further include a light conversion layer (CCL) provided on top of the light-emitting elements (LD) and a second bank (BNK2). The light conversion layer (CCL) may be placed in each light-emitting region (EA) where the light-emitting elements (LD) are placed. The second bank (BNK2) may be placed in a non-light-emitting region (NEA) to overlap with the first bank (BNK1).

[0181] The second bank (BNK2) can define (or partition) each light-emitting region (EA) where the light-converting layer (CCL) is to be formed. In one embodiment, the second bank (BNK2) may be integrated with the first bank (BNK1).

[0182] The second bank (BNK2) may include a black matrix material, other light-blocking materials and / or reflective materials. The second bank (BNK2) may include the same or different materials as the first bank (BNK1).

[0183] The light conversion layer (CCL) may include light conversion particles (LCP) corresponding to each subpixel (SPX). The light conversion particles (LCP) may include wavelength conversion particles (or color conversion particles) that convert the wavelength and / or color of light emitted from light-emitting elements (LD) placed in the corresponding light-emitting region (EA), and / or light scattering particles that scatter light emitted from light-emitting elements (LD) to increase light emission efficiency. For example, each light conversion layer (CCL) may be provided on the light-emitting part (EMU) of each subpixel (SPX), each including wavelength conversion particles comprising at least one type of quantum dot (e.g., red, green, and / or blue quantum dots) and / or light scattering particles (SCT).

[0184] For example, when a subpixel (SPX) is set as a red (or green) subpixel and blue light-emitting elements (LDs) are provided in the light-emitting part (EMU) of the subpixel (SPX), a light conversion layer (CCL) including red (or green) quantum dots for converting blue light into red (or green) light may be disposed on the light-emitting part (EMU) of the subpixel (SPX). In one embodiment, the light conversion layer (CCL) may further include light-scattering particles. When a subpixel (SPX) is set as a blue subpixel and blue light-emitting elements (LDs) are provided in the light-emitting part (EMU) of the subpixel (SPX), a light conversion layer (CCL) including light-scattering particles may be provided on the light-emitting part (EMU) of the subpixel (SPX), or a light conversion layer (CCL) may not be provided.

[0185] A fourth insulating layer (INS4) may be formed on one side of a base layer (BSL) including light-emitting parts (EMU) and / or light-converting layers (CCL) of subpixels (SPX).

[0186] The fourth insulating layer (INS4) may be a single layer or multiple layers and may include an organic insulating material and / or an inorganic insulating material. The fourth insulating layer (INS4) may protect the light-emitting units (EMU) and / or light-converting layers (CCL). In one embodiment, the fourth insulating layer (INS4) may include an organic film containing an organic insulating material and may substantially flatten the surface of the display layer (DPL).

[0187] A color filter layer (CFL) can be placed on the fourth insulating layer (INS4).

[0188] The color filter layer (CFL) may include color filters (CF) corresponding to the colors of the subpixels (SPX). For example, the color filter layer (CFL) may include a first color filter (CF1) placed in the light-emitting region (EA) of the first subpixel (SPX1), a second color filter (CF2) placed in the light-emitting region (EA) of the second subpixel (SPX2), and a third color filter (CF3) placed in the light-emitting region (EA) of the third subpixel (SPX3). Each color filter (CF) may be provided on the light-emitting region (EMU) so as to overlap with the light-emitting region (EMU) of the corresponding subpixel (SPX).

[0189] In one embodiment, the first, second, and third color filters (CF1, CF2, CF3) may overlap each other in the non-emissive region (NEA), thereby blocking the transmission of light through the non-emissive region (NEA). In another embodiment, the first, second, and third color filters (CF1, CF2, CF3) may be formed separately from each other in the emissive regions (EA) of the subpixels (SPX), and a separate light-blocking pattern, etc., may be disposed between the first, second, and third color filters (CF1, CF2, CF3).

[0190] An encapsulation layer (ENC) may be disposed on the color filter layer (CFL). The encapsulation layer (ENC) may include a fifth insulating layer (INS5). The fifth insulating layer (INS5) may be a single layer or multiple layers and may include an organic insulating material and / or an inorganic insulating material. In one embodiment, the fifth insulating layer (INS5) may be formed over the entire surface of at least the display area (DA) to cover the circuit layer (PCL), the display layer (DPL), and / or the color filter layer (CFL), and may flatten the surface of the display panel (DPN). In another embodiment, the display panel (DPN) may be manufactured without including the encapsulation layer (ENC), and a separately manufactured protective film, etc., may be attached to the display panel (DPN).

[0191] FIG. 8 is a plan view showing a circuit layer (PCL) of a display area (DA) according to an embodiment of the present invention. For example, FIG. 8 is to show an example of the structure of a circuit layer (PCL) centered on the area where the pixel circuits (PXC) of the first pixel (PXL1) and the second pixel (PXL2) of FIG. 6 and the wiring around them are arranged.

[0192] In the embodiments, the pixels (PXL) placed in the display area (DA), including the first pixel (PXL1) and the second pixel (PXL2), may have substantially similar or identical structures. Accordingly, FIG. 8 describes the structure of the pixel circuits (PXC) provided to each pixel (PXL), focusing on the circuit elements constituting the first, second, and third pixel circuits (PXC1, PXC2, PXC3) of the first pixel (PXL1).

[0193] Referring to FIGS. 3 through 8, the circuit layer (PCL) may include pixel circuits (PXC) of subpixels (SPX) disposed in each pixel region (PXA). For example, the circuit layer (PCL) may include a first pixel circuit (PXC1), a second pixel circuit (PXC2), and a third pixel circuit (PXC3) disposed in a first circuit region (SPXA1), a second circuit region (SPXA2), and a third circuit region (SPXA3) of the corresponding pixel region (PXA), respectively.

[0194] The circuit layer (PCL) may further include wirings electrically connected to pixels (PXL). For example, the circuit layer (PCL) may further include scan lines (SL), data lines (DL), sensing lines (SENL), a first power line (PL1) (for example, a first power line (PL1) in a mesh form including first horizontal power lines (HPL1) and first vertical power lines (VPL1)), and a second power line (PL2) (for example, a second power line (PL2) in a mesh form including second horizontal power lines (HPL2) and second vertical power lines (VPL2)). In one embodiment, the circuit layer (PCL) may further include connecting wirings (CL) electrically connected to scan lines (SL). As the arrangement structure, extension direction, and / or position in cross-section of the scan lines (SL), data lines (DL), sensing lines (SENL), first power line (PL1), second power line (PL2), and connecting lines (CL) have been described in the embodiments of FIGS. 6 and 7, a redundant description will be omitted.

[0195] The circuit layer (PCL) may further include contact holes (CH) for electrically connecting circuit elements, electrodes, conduction patterns and / or wirings disposed in the circuit layer (PCL). In FIG. 8, only one contact hole (CH) (for example, a contact hole (CH) for electrically connecting the n-th scan line (Sn) and the gate electrodes (GE) of the second and third transistors (M2, M3)) is designated to represent the contact holes (CH) for connecting specific elements within the circuit layer (PCL).

[0196] In one embodiment, at least one wiring may be formed as multilayer wiring in at least a portion. For example, the connecting wirings (CL), including the n-th connecting wiring (CLn) and the n+1-th connecting wiring (CLn+1), may be formed as multilayer wiring including a main wiring (MLI) placed on the same layer as the lower metal layers (BML), a first sub-wiring (SLI1) placed on the same layer as the gate electrodes (GE), and a second sub-wiring (SLI2) placed on the same layer as the source and drain electrodes (SE, DE). Accordingly, delays in the power supply voltage (e.g., a first and / or first power supply voltage (VDD and / or VSS)) or signals (e.g., scan signals) supplied to the multilayer wirings can be prevented or reduced, and the pixels (PXL) can be driven stably.

[0197] The circuit layer (PCL) may further include first contact holes (CH1), second contact holes (CH2), and third contact holes (CH3) formed between it and the display layer (DPL).

[0198] Each first contact hole (CH1) can electrically connect each pixel circuit (PXC) and the corresponding light-emitting unit (EMU). For example, the first contact hole (CH1) corresponding to each first sub-pixel (SPX1) can be formed between the first pixel circuit (PXC1) and the first alignment electrode (ALE1) of the first light-emitting unit (EMU1) to electrically connect the first pixel circuit (PXC1) and the first light-emitting unit (EMU1). The first contact hole (CH1) corresponding to each second sub-pixel (SPX2) can be formed between the second pixel circuit (PXC2) and the first alignment electrode (ALE1) of the second light-emitting unit (EMU2) to electrically connect the second pixel circuit (PXC2) and the second light-emitting unit (EMU2). A first contact hole (CH1) corresponding to each third sub-pixel (SPX3) is formed between the third pixel circuit (PXC3) and the first alignment electrode (ALE1) of the third light-emitting unit (EMU3), so as to electrically connect the third pixel circuit (PXC3) and the third light-emitting unit (EMU3).

[0199] The second contact holes (CH2) can electrically connect the second power line (PL2) and the second alignment electrodes (ALE2) of the light-emitting units (EMU). For example, the second contact holes (CH2) may be formed between the second horizontal power lines (HPL2) that are repeatedly arranged every two or more horizontal lines and the second alignment electrodes (ALE2) of the light-emitting units (EMU) located around the second horizontal power lines (HPL2) (for example, overlapping with the second horizontal power lines (HPL2)). Accordingly, in the manufacturing process of the pixels (PXL) (for example, the alignment process of the light-emitting elements (LD)), a second alignment signal can be supplied to the second alignment electrodes (ALE2) through the second power line (PL2).

[0200] The third contact holes (CH3) can electrically connect the first power line (PL1) and the floating patterns of the display layer (DPL) (e.g., the floating patterns (FPT) of FIG. 9). For example, the third contact holes (CH3) can be formed between the first horizontal power lines (HPL1) which are repeatedly arranged every two or more horizontal lines, and the floating patterns (FPT) that overlap with the first horizontal power lines (HPL1). In the embodiments, the floating patterns (FPT) can be formed integrally with each of the first alignment electrodes (ALE1) and the third alignment electrodes (ALE3) in the pixel process (e.g., a process for forming pixels (PXL) on the base layer (BSL)) to form a first alignment wiring together with the first alignment electrodes (ALE1) and the third alignment electrodes (ALE3). Accordingly, during the alignment process of the light-emitting elements (LD), a first alignment signal can be supplied to the first alignment wiring through the first power line (PL1). After the alignment process of the light-emitting elements (LD) is completed, the first alignment wiring can be cut around the third contact holes (CH3) to separate the floating patterns (FPT) from the first alignment electrodes (ALE1). Accordingly, the subpixels (SPX) can be driven individually. In some embodiments, the floating patterns (FPT) can also be separated from the third alignment electrodes (ALE3).

[0201] Each of the first contact holes (CH1), the second contact holes (CH2), and the third contact holes (CH3) may consist of a single contact hole (or contact part) or via hole formed at the corresponding location, or may include two or more contact holes and / or via holes formed densely at the corresponding location and connecting identical elements.

[0202] Each pixel circuit (PXC) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a capacitor (Cst) disposed in each circuit area (SPXA). For example, the first pixel circuit (PXC1) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a capacitor (Cst) disposed in the first circuit area (SPXA1) of the corresponding pixel area (PXA). The second pixel circuit (PXC2) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a capacitor (Cst) disposed in the second circuit area (SPXA2) of the corresponding pixel area (PXA). The third pixel circuit (PXC3) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a capacitor (Cst) disposed in the third circuit area (SPXA3) of the corresponding pixel area (PXA).

[0203] Each first transistor (M1) may include a first semiconductor pattern (SCP1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1). In one embodiment, each first transistor (M1) may further include a lower metal layer (BML).

[0204] The lower metal layer (BML) may overlap with the first semiconductor pattern (SCP1), the first gate electrode (GE1), and the first source electrode (SE1). In one embodiment, the lower metal layer (BML) may be electrically connected to the first source electrode (SE1) through at least one contact hole (CH).

[0205] The first semiconductor pattern (SCP1) overlaps with the first gate electrode (GE1) and the lower metal layer (BML) and can be connected to the first source electrode (SE1) and the first drain electrode (DE1). For example, both ends of the first semiconductor pattern (SCP1) can be electrically connected to the first source electrode (SE1) and the first drain electrode (DE1) through respective contact holes (CH).

[0206] The first gate electrode (GE1) can be connected to the lower electrode (LE) and the second source electrode (SE2) of the capacitor (Cst). For example, the first gate electrode (GE1) can be formed integrally with the lower electrode (LE) of the capacitor (Cst) and can be electrically connected to the second source electrode (SE2) through at least one contact hole (CH).

[0207] The first source electrode (SE1) may be connected to the upper electrode (UE) and the third source electrode (SE3) of the capacitor (Cst). For example, the first source electrode (SE1) may be formed integrally with the upper electrode (UE) and the third source electrode (SE3) of the capacitor (Cst). The first source electrode (SE1) may be connected to the light-emitting part (EMU) of the corresponding subpixel (SPX). For example, the first source electrode (SE1) may be electrically connected to the first alignment electrode (ALE1) and / or the first contact electrode (CNE1) formed in the light-emitting part (EMU) of the corresponding subpixel (SPX) through the first contact hole (CH1). For example, the first source electrode (SE1) of the first pixel circuit (PXC1), the upper electrode (UE) of the capacitor (Cst), and the third source electrode (SE3) can be electrically connected to the first alignment electrode (ALE1) of the first light-emitting unit (EMU1) through a first contact hole (CH1) formed between the first pixel circuit (PXC1) and the first light-emitting unit (EMU1), and can be electrically connected to the first contact electrode (CNE1) of the first light-emitting unit (EMU1) through the first alignment electrode (ALE1).

[0208] The first drain electrode (DE1) can be connected to the first power line (PL1). For example, the first drain electrode (DE1) can be electrically connected to the first vertical power line (VPL1) through at least one contact hole (CH).

[0209] Each second transistor (M2) may include a second semiconductor pattern (SCP2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2).

[0210] The second semiconductor pattern (SCP2) overlaps with the second gate electrode (GE2) and can be connected to the second source electrode (SE2) and the second drain electrode (DE2). For example, both ends of the second semiconductor pattern (SCP2) can be electrically connected to the second source electrode (SE2) and the second drain electrode (DE2) through respective contact holes (CH).

[0211] The second gate electrode (GE2) can be connected to a scan line (SL). For example, the second gate electrode (GE2) can be electrically connected to a scan line (SL) of the corresponding horizontal line (e.g., the nth scan line (SLn)) through at least one contact hole (CH).

[0212] The second source electrode (SE2) can be connected to the lower electrode (LE) and the first gate electrode (GE1) of the capacitor (Cst). For example, the second source electrode (SE2) can be electrically connected to the lower electrode (LE) and the first gate electrode (GE1) of the capacitor (Cst) through at least one contact hole (CH).

[0213] The second drain electrode (DE2) can be connected to the sub-data line of the corresponding sub-pixel (SPX). For example, the second drain electrode (DE2) of the first pixel circuit (PXC1) can be electrically connected to the first sub-data line (D1) through at least one contact hole (CH). The second drain electrode (DE2) of the second pixel circuit (PXC2) can be electrically connected to the second sub-data line (D2) through at least one contact hole (CH). The second drain electrode (DE2) of the third pixel circuit (PXC3) can be electrically connected to the third sub-data line (D3) through at least one contact hole (CH).

[0214] Each third transistor (M3) may include a third semiconductor pattern (SCP3), a third gate electrode (GE3), a third source electrode (SE3), and a third drain electrode (DE3).

[0215] The third semiconductor pattern (SCP3) overlaps with the third gate electrode (GE3) and can be connected to the third source electrode (SE3) and the third drain electrode (DE3). For example, both ends of the third semiconductor pattern (SCP3) can be electrically connected to the third source electrode (SE3) and the third drain electrode (DE3) through respective contact holes (CH).

[0216] The third gate electrode (GE3) may be connected to each scan line (SL) or to a separate control line (SSL) separated from the scan line (SL). In one embodiment, the third gate electrode (GE3) is formed integrally with the second gate electrode (GE2) and may be electrically connected to each scan line (SL) through at least one contact hole (CH).

[0217] The third source electrode (SE3) can be connected to the upper electrode (UE) and the first source electrode (SE1) of the capacitor (Cst). For example, the third source electrode (SE3) can be formed integrally with the upper electrode (UE) and the first source electrode (SE1) of the capacitor (Cst).

[0218] The third drain electrode (DE3) can be connected to the sensing line (SENL). For example, the third drain electrode (DE3) can be electrically connected to the corresponding sensing line (SENL) through at least one contact hole (CH).

[0219] The capacitor (Cst) may include a lower electrode (LE) and an upper electrode (UE).

[0220] The lower electrode (LE) of the capacitor (Cst) can be connected to the first gate electrode (GE1) and the second source electrode (SE2). For example, the lower electrode (LE) of the capacitor (Cst) can be formed integrally with the first gate electrode (GE1) and can be electrically connected to the second source electrode (SE2) through at least one contact hole (CH).

[0221] The upper electrode (UE) of the capacitor (Cst) can be connected to the first source electrode (SE1) and the third source electrode (SE3). For example, the upper electrode (UE) of the capacitor (Cst) can be formed integrally with the first source electrode (SE1) and the third source electrode (SE3).

[0222] In one embodiment, the lower metal layers (BML) provided in the display area (DA) and at least some of the wirings (or parts of said wirings) extending in a second direction (DR2) may be disposed in the same layer of the circuit layer (PCL) (e.g., a first conductive layer within the circuit layer (PCL)). The semiconductor patterns (SCP) provided in the display area (DA) may be disposed in the same layer of the circuit layer (PCL) (e.g., a semiconductor layer within the circuit layer (PCL)). The gate electrodes (GE), the lower electrodes (LE) of the capacitors (Cst), and / or at least one sub-wiring (e.g., first sub-wirings (SLI1) of the connection wirings (CL)) provided in the display area (DA) may be disposed in the same layer of the circuit layer (PCL) (e.g., a second conductive layer within the circuit layer (PCL) (e.g., a gate layer)). Source electrodes (SE), drain electrodes (DE), upper electrodes (UE) of capacitors (Cst) provided in the display area (DA), at least some wirings extending in the first direction (DR1), and / or at least one sub-wiring (e.g., second sub-wirings (SLI2) of the connecting wirings (CL)) may be disposed in the same layer of the circuit layer (PCL) (e.g., a third conductive layer (e.g., a source-drain layer)) within the circuit layer (PCL).

[0223] In the embodiments of FIGS. 6 to 8, the area occupied by each pixel circuit (PXC) can be reduced or minimized by efficiently arranging the circuit elements and wiring of the circuit layer (PCL). Accordingly, the above-described embodiment can be usefully applied to high-resolution display devices (DD), such as high-resolution display devices (DD), where the area of ​​the pixel region (PXA) is narrow.

[0224] Additionally, in the second direction (DR2), wiring extending in the first direction (DR1) can be arranged on both sides of the light-emitting parts (EMU) so as to be immediately adjacent to the light-emitting parts (EMU) of the subpixels (SPX). For example, in the second direction (DR2), the nth scan line (SLn) and the first horizontal power line (HPL1) can be arranged on both sides of the light-emitting parts (EMU) of the first pixel (PXL) so as to be immediately adjacent to the light-emitting parts (EMU) provided to the first pixel (PXL1). Similarly, in the second direction (DR2), the n+1st scan line (SLn+1) and the second horizontal power line (HPL2) can be arranged on each side of the light-emitting parts (EMU) of the second pixel (PXL2) so as to be immediately adjacent to the light-emitting parts (EMU) provided to the second pixel (PXL2). Accordingly, in the display layer (DPL) formed on the circuit layer (PCL), the height of the bank (for example, the first bank (BNK1) of FIG. 9) can be increased or maximized.

[0225] Accordingly, the volume of the light-emitting regions (EA) can be increased, and in the process of supplying light-emitting elements (LD) to the light-emitting regions (EA), the light-emitting element ink containing the light-emitting elements (LD) can be prevented or reduced from flooding into the non-light-emitting regions (NEA) adjacent to both ends of the light-emitting regions (LD) (for example, the non-light-emitting region (NEA) adjacent to the light-emitting regions (LD) in the second direction (DR2) and where the ends of the first alignment electrodes (ALE1) are located). Accordingly, in a subsequent process, the first alignment wiring can be reliably separated into each first alignment electrode (ALE1) (and / or third alignment electrodes (ALE3)). According to the above-described embodiment, the occurrence of short-circuit defects in the display region (DA) (for example, short-circuit defects that may occur due to the first alignment electrodes (ALE1) not being reliably separated) can be prevented or reduced.

[0226] FIG. 9 is a plan view showing a display layer (DPL) of a display area (DA) according to an embodiment of the present invention. For example, FIG. 9 shows an embodiment of the structure of a display layer (DPL) centered on the area where the light-emitting parts (EMU) of the first pixel (PXL1) and the second pixel (PXL2) of FIG. 6, and the bank pattern (BNP) and the first bank (BNK1) around them are arranged. In FIG. 9, some wirings arranged in the circuit layer (PCL) (for example, the nth scan line (SLn), the n+1th scan line (SLn+1), the first horizontal power line (HPL1), and the second horizontal power line (HPL2) arranged inside and / or around the first pixel (PXL1) and the second pixel (PXL2)) are shown as dotted lines so that the location of the light-emitting parts (EMU) according to the present embodiment can be shown more clearly.

[0227] FIGS. 10 and 11 are plan views showing a display layer (DPL) of a display area (DA) according to embodiments of the present invention. For example, FIGS. 10 and 11 show different embodiments related to bank patterns (BNP) centered on an area where four pixels (PXL) adjacent to each other in a first direction (DR1) and a second direction (DR2) (e.g., a first pixel (PXL1), a second pixel (PXL2), a third pixel (PXL3) and a fourth pixel (PXL4)) are arranged.

[0228] FIG. 12 is a cross-sectional view showing a display area (DA) according to an embodiment of the present invention. For example, FIG. 12 schematically shows a cross-section of a display area (DA) corresponding to lines II to II' of FIG. 9.

[0229] First, referring to FIGS. 3 to 9, the subpixels (SPX) of each pixel (PXL) may include light-emitting regions (EA) arranged in a first direction (DR1), and light-emitting parts (EMU) provided in the light-emitting regions (EA).

[0230] In one embodiment, the light-emitting units (EMU) (or light-emitting regions (EA) corresponding to the light-emitting units (EMU)) may be located between a first wiring and a second wiring, each of which extends in a first direction (DR1) and is spaced apart from each other in a second direction (DR2). The first wiring and the second wiring may be immediately adjacent to the light-emitting units (EMU) in the second direction (DR2).

[0231] For example, the first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the first pixel (PXL1) (or the first, second, and third light-emitting regions (EA1, EA2, EA3) corresponding to the first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the first pixel (PXL1)) may be positioned between the nth scan line (SLn) for supplying a scan signal to the first pixel (PXL1) and the first horizontal power line (HPL1), and may be arranged along the first direction (DR1) between the nth scan line (SLn) and the first horizontal power line (HPL1). The first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the second pixel (PXL2) (or the first, second, and third light-emitting regions (EA1, EA2, EA3) corresponding to the first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the second pixel (PXL2)) may be positioned between the n+1 scan line (SLn+1) and the second horizontal power line (HPL2) for supplying a scan signal to the second pixel (PXL2), and may be arranged along the first direction (DR1) between the n+1 scan line (SLn+1) and the second horizontal power line (HPL2).

[0232] Each light-emitting unit (EMU) may include at least one pair of alignment electrodes (ALE), at least one light-emitting element (LD), and at least one pair of contact electrodes (CNE). For example, each light-emitting unit (EMU) may include a first alignment electrode (ALE1), a second alignment electrode (ALE2), a third alignment electrode (ALE3), first light-emitting elements (LD1), second light-emitting elements (LD2), a first contact electrode (CNE1), a second contact electrode (CNE2), and a third contact electrode (CNE3), which are disposed in each light-emitting region (EA).

[0233] In each light-emitting region (EA), the first alignment electrode (ALE1), the second alignment electrode (ALE2), and the third alignment electrode (ALE3) may be spaced apart from each other along the first direction (DR1) and each may extend in the second direction (DR2). First light-emitting elements (LD1) may be disposed between the first alignment electrode (ALE1) and the second alignment electrode (ALE2), and second light-emitting elements (LD2) may be disposed between the second alignment electrode (ALE2) and the third alignment electrode (ALE3). Here, the statement that light-emitting elements (LD) are disposed between each alignment electrode (ALE) may mean that, when viewed in a plane, at least a portion of the light-emitting elements (LD) is located in the region between each alignment electrode (ALE) and / or around it. The light-emitting elements (LD) may or may not overlap with the alignment electrodes (ALE) located around them.

[0234] In one embodiment, light-emitting elements (LDs) are prepared in a dispersed form within a solution and can be supplied to each light-emitting region (EA) via an inkjet method or a slit coating method, etc. For example, a light-emitting element ink containing light-emitting elements (LDs) can be supplied to each light-emitting region (EA) defined by a first bank (BNK1). When the light-emitting elements (LDs) are supplied to each light-emitting region (EA) and alignment signals are applied to the alignment electrodes (ALE) (or alignment wires) of the subpixels (SPX), the light-emitting elements (LDs) can be aligned between the alignment electrodes (ALE). For example, the first light-emitting elements (LD1) can be aligned to the first light-emitting element array region (AR1) such that the first ends (EP1) are adjacent to the first alignment electrode (ALE1) and the second ends (EP2) are adjacent to the second alignment electrode (ALE2). The second light-emitting elements (LD2) can be aligned in the second light-emitting element array region (AR2) such that the first ends (EP1) are adjacent to the third alignment electrode (ALE3) and the second ends (EP2) are adjacent to the second alignment electrode (ALE2). After the light-emitting elements (LD) are aligned, the solvent of the light-emitting element ink can be removed through a drying process or the like.

[0235] In one embodiment, the first alignment electrodes (ALE1), the third alignment electrodes (ALE3), and the floating patterns (FPT) provided in the display area (DA) can be formed to be connected to each other first in the pixel process to form a first alignment wiring. Accordingly, in the alignment process of the light-emitting elements (LD), a first alignment signal can be supplied to the first alignment wiring through the first power line (PL1). After the alignment process of the light-emitting elements (LD) is completed, the first alignment wiring can be cut around the third contact holes (CH3) to separate the floating patterns (FPT) from the first alignment electrodes (ALE1) (or the first alignment electrodes (ALE1) and the third alignment electrodes (ALE3)).

[0236] In one embodiment, some alignment electrodes (ALE) of adjacent light-emitting units (EMU) in a first direction (DR1) may first be formed to be connected to each other to form a single alignment wiring, and may be separated into individual alignment electrodes (ALE) after the alignment of the light-emitting elements (LD) is completed. For example, a first alignment electrode (ALE1) provided to a first light-emitting unit (EMU1) of each pixel (PXL) may be formed to be connected to a third alignment electrode (ALE3) provided to a third light-emitting unit (EMU3) of another pixel (PXL) adjacent in the first direction (DR1) to form a single first alignment wiring, and then may be separated from each other in a subsequent process. A first alignment electrode (ALE1) provided to a second light-emitting unit (EMU2) of each pixel (PXL) may be formed to be connected to a third alignment electrode (ALE3) provided to the first light-emitting unit (EMU1) of the corresponding pixel (PXL) to form a single first alignment wiring, and then may be separated from each other in a subsequent process. A first alignment electrode (ALE1) provided to the third light-emitting part (EMU3) of each pixel (PXL) is formed to be connected to a third alignment electrode (ALE3) provided to the second light-emitting part (EMU2) of the corresponding pixel (PXL) to form a single first alignment wiring, after which they can be separated from each other in a subsequent process.

[0237] In one embodiment, at least some of the alignment electrodes (ALE) adjacent to each other in the second direction (DR2) may first be formed to be connected to each other to form a single alignment wire, and may be separated into individual alignment electrodes (ALE) after the alignment of the light-emitting elements (LD) is completed. For example, the first alignment electrodes (ALE1) may first be formed continuously along the second direction (DR2) in the display area (DA) to form a first alignment wire, and may be separated into individual first alignment electrodes (ALE1) by being cut between adjacent light-emitting areas (EA) in the second direction (DR2) after the alignment of the light-emitting elements (LD) is completed. For example, after the alignment of the light-emitting elements (LD) is completed, the first alignment wire may be separated into the first alignment electrodes (ALE1) of the subpixels (SPX) by etching the first alignment wire in the non-light-emitting area (NEA) adjacent to each light-emitting area (EA) in the second direction (DR2). In this case, each first alignment electrode (ALE1) may include an end located in a part of a non-emissive region (NEA) adjacent to the emissive region (EA) of the corresponding subpixel (SPX) in the second direction (DR2).

[0238] In one embodiment, the third alignment electrodes (ALE3) may first be formed continuously along the second direction (DR2) in the display area (DA), and after the alignment of the light-emitting elements (LD) is completed, they may be separated into individual third alignment electrodes (ALE3) by being cut between adjacent light-emitting regions (EA) in the second direction (DR2). In this case, each third alignment electrode (ALE3) may include an end located in a part of the non-light-emitting region (NEA) adjacent to the light-emitting region (EA) of the corresponding subpixel (SPX) in the second direction (DR2).

[0239] Each first alignment electrode (ALE1) of each subpixel (SPX) can be electrically connected to the pixel circuit (PXC) of the corresponding subpixel (SPX) through each first contact hole (CH1) and can be electrically connected to the first contact electrode (CNE1) of the corresponding light-emitting unit (EMU) through each fourth contact hole (CH4). Additionally, each first alignment electrode (ALE1) of each subpixel (SPX) can be electrically connected to the light-emitting elements (LD) of the corresponding light-emitting unit (EMU) through the first contact electrode (CNE1). For example, each first alignment electrode (ALE1) can be electrically connected to the first ends (EP1) of the first light-emitting elements (LD1) located in each light-emitting region (EA) through each first contact electrode (CNE1).

[0240] In one embodiment, the second alignment electrodes (ALE2) of at least two light-emitting units (EMU) adjacent to each other in the second direction (DR2) may be connected to each other. For example, the second alignment electrode (ALE2) provided to the first light-emitting unit (EMU1) of the first pixel (PXL1) and the second alignment electrode (ALE2) provided to the first light-emitting unit (EMU1) of the second pixel (PXL2) may be formed integrally and may constitute a single integrated second alignment electrode (ALE2). In some embodiments, the second alignment electrodes (ALE2) arranged along the second direction (DR2) in the display area (DA) may be formed integrally to each other, but the embodiments are not limited thereto. In the alignment step of the light-emitting elements (LD), the second alignment electrodes (ALE2) may be connected to each other to form a second alignment wiring. After the alignment of the light-emitting elements (LD) is completed, the second alignment electrode (ALE2) extending along the second direction (DR2) in the display area (DA) may be separated from each other by being broken into at least two pixel rows, or may be formed integrally without being broken.

[0241] The second alignment electrodes (ALE2) can be electrically connected to the second power line (PL2) (e.g., the second horizontal power line (HPL2)) through the second contact holes (CH2). The second alignment electrodes (ALE2) can receive a second alignment signal through the second power line (PL2) during the alignment process of the light-emitting elements (LD). The first alignment signal and the second alignment signal may have different waveforms, potentials, and / or phases. Accordingly, an electric field is formed between the first alignment wiring and the second alignment electrodes (ALE2) (or the second alignment wiring formed by the second alignment electrodes (ALE2)), thereby enabling the light-emitting elements (LD) to be aligned between the first alignment wiring and the second alignment electrodes (ALE2). For example, first light-emitting elements (LD1) may be aligned in a first light-emitting element array region (AR1) between a first alignment electrode (ALE1) and a second alignment electrode (ALE2) of the light-emitting units (EMU), and second light-emitting elements (LD2) may be aligned in a second light-emitting element array region (AR2) between a second alignment electrode (ALE2) and a third alignment electrode (ALE3) of the light-emitting units (EMU). Each light-emitting element array region (AR) may be surrounded by a bank pattern (BNP).

[0242] When the display device (DD) is actually driven, a first power supply voltage (VDD) can be applied to the first alignment electrodes (ALE1) through the first power line (PL1) and the pixel circuit (PXC), and a second power supply voltage (VSS) can be applied to the second alignment electrodes (ALE2) through the second power line (PL2). Accordingly, a driving current can flow to each subpixel (SPX).

[0243] A first contact electrode (CNE1) may be disposed on the first ends (EP1) of the first light-emitting elements (LD1) and the first alignment electrode (ALE1). In one embodiment, the first contact electrode (CNE1) may be in contact with and / or electrically connected to the first ends (EP1) of the first light-emitting elements (LD1) and may be electrically connected to the first alignment electrode (ALE1) through a fourth contact hole (CH4). In one embodiment, the fourth contact hole (CH4) may be formed in the first insulating layer (INS1) of FIG. 7, etc., and may be formed in a non-light-emitting region (NEA) outside the light-emitting region (EA). In one embodiment, the fourth contact holes (CH4) of the subpixels (SPX) may be disposed outside the light-emitting region (EA) and may be formed in an area that does not overlap with the first bank (BNK1). In this case, the fourth contact holes (CH4) can be easily formed on a relatively flat area by avoiding the area where a step difference occurs due to the first bank (BNK1). The location of the fourth contact holes (CH4) may be changed according to the embodiments.

[0244] The second contact electrode (CNE2) may be disposed on the second ends (EP2) of the first light-emitting elements (LD1), a part of the second alignment electrode (ALE2), the first ends (EP1) of the second light-emitting elements (LD2), and the third alignment electrode (ALE3). For example, the second contact electrode (CNE2) may be an electrode having left and right pattern portions, such as a "U" shape. The left pattern portion of the second contact electrode (CNE2) may be disposed on the second ends (EP2) of the first light-emitting elements (LD1) and a part of the second alignment electrode (ALE2), and the right pattern portion of the second contact electrode (CNE2) may be disposed on the first ends (EP1) of the second light-emitting elements (LD2) and the third alignment electrode (ALE3). In one embodiment, the second contact electrode (CNE2) may be in contact with and / or electrically connected to the second ends (EP2) of the first light-emitting elements (LD1) and the first ends (EP1) of the second light-emitting elements (LD2). By the second contact electrode (CNE2), the first light-emitting elements (LD1) and the second light-emitting elements (LD2) may be connected in series with each other.

[0245] The third contact electrode (CNE3) may be disposed on the second ends (EP2) of the second light-emitting elements (LD2) and on another part of the second alignment electrode (ALE2). In one embodiment, the third contact electrode (CNE3) may be in contact with and / or electrically connected to the second ends (EP2) of the second light-emitting elements (LD2) and may be electrically connected to the second alignment electrode (ALE2) through the fifth contact hole (CH5). In one embodiment, the fifth contact hole (CH5) may be formed in the first insulating layer (INS1) of FIG. 7, etc., and may be formed in a non-light-emitting region (NEA) outside the light-emitting region (EA). In one embodiment, the fifth contact holes (CH5) of the subpixels (SPX) may be disposed outside the light-emitting region (EA) and may be formed in an area that does not overlap with the first bank (BNK1). In this case, the fifth contact holes (CH5) can be easily formed on a relatively flat area by avoiding the area where a step difference occurs due to the first bank (BNK1). The location of the fifth contact holes (CH5) may be changed according to the embodiments.

[0246] The shape, size, number, location, and / or mutual arrangement structure of the alignment electrodes (ALE) and contact electrodes (CNE) may be changed according to the embodiments.

[0247] Bank patterns (BNP) may be disposed on the lower portion of the alignment electrodes (ALE). In one embodiment, the bank patterns (BNP) may be formed as individual patterns formed separately from each other corresponding to each pixel (PXL), as illustrated in FIG. 10. For example, pixels (PXL) arranged in a first direction (DR1) including each subpixel (SPX) (e.g., a first pixel (PXL1) and a third pixel (PXL3), or a second pixel (PXL2) and a fourth pixel (PXL4)) may each include separate bank patterns (BNP). In another embodiment, as illustrated in FIG. 11, bank patterns (BNP) corresponding to at least two adjacent pixels (PXL) in the first direction (DR1) (e.g., provided to said at least two pixels (PXL)) may be formed integrally to form substantially one bank pattern (BNP). For example, a single integrated bank pattern (BNP) can be placed on each horizontal line of the display area (DA).

[0248] Each bank pattern (BNP) may include openings (OPN) corresponding to each light-emitting element array region (AR) provided in the light-emitting regions (EA) of the corresponding pixel (PXL). For example, each bank pattern (BNP) may include first openings (OPN1) corresponding to first light-emitting element array regions (AR1) provided in the first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the corresponding pixel (PXL), and second openings (OPN2) corresponding to second light-emitting element array regions (AR2) provided in the first, second, and third light-emitting parts (EMU1, EMU2, EMU3) of the corresponding pixel (PXL). In one embodiment, the bank patterns (BNP) may further include third openings (OPN3) formed between the light-emitting regions (EA) of the corresponding pixel (PXL).

[0249] In the embodiments, the light-emitting regions (EA) of each pixel (PXL) (for example, the first light-emitting region (EA1) of the first light-emitting unit (EMU1), the second light-emitting region (EA2) of the second light-emitting unit (EMU2), and the third light-emitting region (EA3) of the third light-emitting unit (EMU3)) may be located in the area between two wires (hereinafter referred to as "first wire" and "second wire") that are each extended in the first direction (DR1) and spaced apart from each other in the second direction (DR2). In one embodiment, the first, second, and third light-emitting regions (EA1, EA2, EA3) of each pixel (PXL) may be arranged in the first direction (DR1) in the area between the first wire and the second wire.

[0250] For example, the first, second, and third light-emitting regions (EA1, EA2, EA3) of the first pixel (PXL1) may be located between the n-th scan line (SLn) and the first horizontal power line (HPL1) in the second direction (DR2), and may be arranged in the first direction (DR1) between the n-th scan line (SLn) and the first horizontal power line (HPL1). The first, second, and third light-emitting regions (EA1, EA2, EA3) of the second pixel (PXL2) may be located between the n+1-th scan line (SLn+1) and the second horizontal power line (HPL2) in the second direction (DR2), and may be arranged in the first direction (DR1) between the n+1-th scan line (SLn+1) and the second horizontal power line (HPL2).

[0251] The bank pattern (BNP) of each pixel (PXL) can overlap with the first wiring and the second wiring. For example, the bank pattern (BNP) corresponding to the first pixel (PXL1) (for example, the bank pattern (BNP) formed in the first pixel (PXL1)) can overlap with the nth scan line (SLn) and the first horizontal power line (HPL1), and the bank pattern (BNP) corresponding to the second pixel (PXL2) (for example, the bank pattern (BNP) formed in the second pixel (PXL2)) can overlap with the n+1th scan line (SLn+1) and the second horizontal power line (HPL2).

[0252] In one embodiment, bank patterns (BNP) of subpixels (SPX) provided to each pixel (PXL) may be connected to each other in a first direction (DR1) and thus formed substantially into a single bank pattern (BNP). Each bank pattern (BNP) may include a first pattern portion (BNP_1) and a second pattern portion (BNP_2) adjacent to the first edge regions and the second edge regions of the light-emitting regions (EA) provided to the corresponding pixel (PXL). The first edge regions and the second edge regions of the light-emitting regions (EA) may be located at both ends of the light-emitting regions (EA) in a second direction (DR2). The first pattern portion (BNP_1) and the second pattern portion (BNP_2) of the bank pattern (BNP) may overlap with the first wiring and the second wiring of the corresponding pixel (PXL) and / or the corresponding horizontal line. For example, a first pattern portion (BNP_1) of the bank pattern (BNP) may overlap with a first wiring (e.g., a scan line (SLn) electrically connected to the pixel (PXL)) adjacent to the first edge regions of the light-emitting regions (EA) provided to the pixel (PXL), and a second pattern portion (BNP_2) of the bank pattern (BNP) may overlap with a second wiring (e.g., a first horizontal power line (HPL1) or a second horizontal power line (HPL2) located between the second and third pixel circuits (PXC2, PXC3) of the horizontal line) adjacent to the second edge regions of the light-emitting regions (EA) provided to the pixel (PXL). Additionally, each bank pattern (BNP) may further include third pattern parts (BNP_3) that extend in a direction different from the first pattern part (BNP_1) and the second pattern part (BNP_2) and connect the first pattern part (BNP_1) and the second pattern part (BNP_2).

[0253] For example, the bank pattern (BNP) of the first pixel (PXL1) overlaps with the n-th scan line (SLn) and is formed continuously along the first direction (DR1) in the periphery of the light-emitting regions (EA) of the first pixel (PXL1) (for example, a portion immediately adjacent to the first edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of the first pixel (PXL1), and overlaps with the first horizontal power line (HPL1) (for example, a first horizontal power line (HPL1) located between the second and third pixel circuits (PXC2, PXC3) of the first pixel (PXL)) and is formed in the periphery of the light-emitting regions (EA) of the first pixel (PXL1) (for example, a portion immediately adjacent to the second edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of the first pixel (PXL1)). It may include a second pattern portion (BNP_2) formed continuously along a direction (DR1). Additionally, the bank pattern (BNP) of the first pixel (PXL1) may include third pattern portions (BNP_3) disposed on both sides of each of the light-emitting element array regions (AR) of the first pixel (PXL1) in the first direction (DR1). The third pattern portions (BNP_3) may extend into the second direction (DR2).

[0254] Similarly, the bank pattern (BNP) of the second pixel (PXL2) overlaps with the n+1 scan line (SLn+1) and is formed continuously along the first direction (DR1) in the periphery of the light-emitting regions (EA) of the second pixel (PXL2) (for example, in the part immediately adjacent to the first edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of the second pixel (PXL2), and overlaps with the second horizontal power line (HPL2) (for example, the second horizontal power line (HPL2) located between the second and third pixel circuits (PXC2, PXC3) of the second pixel (PXL2)) and is formed in the periphery of the light-emitting regions (EA) of the second pixel (PXL2) (for example, in the part immediately adjacent to the second edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of the second pixel (PXL2)). It may include a second pattern portion (BNP_2) formed continuously along a direction (DR1). Additionally, the bank pattern (BNP) of the second pixel (PXL2) may include third pattern portions (BNP_3) disposed on both sides of each of the light-emitting element array regions (AR) of the second pixel (PXL2) in the first direction (DR1). The third pattern portions (BNP_3) may extend into the second direction (DR2).

[0255] A first bank (BNK1) may be placed in a display area (DA) in which bank patterns (BNP) and alignment electrodes (ALE), etc. are arranged. The first bank (BNK1) may include openings (OPN) corresponding to light-emitting regions (EA) of subpixels (SPX) and may surround said light-emitting regions (EA).

[0256] The first bank (BNK1) may be placed in a part of the non-emissive region (NEA). For example, the first bank (BNK1) may be opened between two adjacent pixel rows. For example, the first bank (BNK1) may be opened in at least a part of the regions where the first alignment wiring is cut off (for example, the surrounding region of the floating patterns (FPT) and the region between adjacent pixel rows) to separate the first alignment wiring into each of the first alignment electrodes (ALE1).

[0257] The first bank (BNK1) may overlap with the first wiring, the second wiring, and the bank pattern (BNP) in the area where the first wiring and the second wiring are arranged adjacent to the light-emitting regions (EA) of the corresponding horizontal line (e.g., each pixel row) in the second direction (DR2). In one embodiment, the first bank (BNK1) may be formed continuously along the first direction (DR1) in the portion overlapping with the first wiring, the second wiring, and the bank pattern (BNP). For example, the first wiring (e.g., the scan line (SL) of the corresponding horizontal line), the bank pattern (BNP) (e.g., the first pattern portion (BNP_1) of the bank pattern (BNP)), and the first bank (BNK1) may completely overlap each other in the non-light-emitting region (NEA) immediately adjacent to the first edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of each pixel (PXL). Similarly, the second wiring (e.g., the first horizontal power line (HPL1) or the second horizontal power line (HPL2) placed on the corresponding horizontal line), the bank pattern (BNP) (e.g., the second pattern portion of the bank pattern (BNP) (BNP_2)), and the first bank (BNK1) may completely overlap each other in the non-emissive region (NEA) immediately adjacent to the second edge regions of the first, second, and third light-emitting regions (EA1, EA2, EA3) of each pixel (PXL). In one embodiment, the first wiring and the second wiring may be provided on a conductive layer (e.g., the third conductive layer) placed relatively close to the display layer (DPL) among the conductive layers provided to the circuit layer (PCL) (e.g., closest to the display layer (DPL)).

[0258] In this way, the height of the first bank (BNK1) can be increased or maximized by overlapping the first or second wiring, the bank pattern (BNP), and the first bank (BNK1) in the non-emissive region (NEA) adjacent to both ends of the light-emitting regions (EA) in at least the second direction (DR2). For example, in the non-emissive region (NEA) immediately adjacent to the second edge regions (bottom edge regions) of the light-emitting regions (EA), the first horizontal power line (HPL1), the bank pattern (BNP), and the first bank (BNK1) can be continuously overlapped along the first direction (DR1), as shown in FIG. 12.

[0259] The first bank (BNK1) may be formed relatively higher than the portion that does not overlap with the first horizontal power line (HPL1) and / or the bank pattern (BNP) in the portion that overlaps with the first horizontal power line (HPL1) and / or the bank pattern (BNP). Accordingly, in the step of supplying a light-emitting element ink containing light-emitting elements (LD) to each light-emitting region (EA) defined by the first bank (BNK1), the capacity of the light-emitting element ink that each light-emitting region (EA) can accommodate can be increased, and the overflow of the light-emitting element ink into the non-light-emitting region (NEA) can be prevented or reduced.

[0260] As described above, a display device (DD) according to embodiments of the present invention comprises: a first wiring extending in a first direction (DR1) (e.g., a scan line (SL) of each horizontal line), a second wiring spaced apart from the first wiring in a second direction (DR2) (e.g., a first horizontal power line (HPL1) or a second horizontal power line (HPL2)), light-emitting regions (EA) located between the first wiring and the second wiring (e.g., first, second, and third light-emitting regions (EA1, EA2, EA3)), and subpixels (SPX) (e.g., first, second, and third subpixels (SPX1, SPX2, SPX3)) including light-emitting elements (LD) disposed in the light-emitting regions (EA), a bank pattern (BNP) including openings (OPN) corresponding to each light-emitting element array region (AR) in which the light-emitting elements (LD) are arranged overlapping with the first wiring and the second wiring, and the light-emitting It may include a first bank (BNK1) that surrounds regions (EA) and overlaps with the first wiring, the second wiring, and the bank pattern (BNP). According to embodiments of the present invention, the height of the first bank (BNK1) can be increased or maximized in the non-emissive region (NA) immediately adjacent to both ends of the light-emitting regions (EA) of the subpixels (SPX) in the second direction (DR2). Accordingly, the volume of the light-emitting regions (EA) can be increased, and in the process of supplying light-emitting ink to the light-emitting regions (EA), the overflow of light-emitting ink into the non-emissive region (NEA) surrounding the light-emitting regions (EA) (for example, the non-emissive region (NEA) adjacent to both ends of the light-emitting regions (EA) in the second direction (DR2)) can be prevented or reduced. Accordingly, the first alignment wiring can be reliably separated into each first alignment electrode (ALE1) in a subsequent process. In addition, short circuit defects that may occur due to the failure of the first alignment electrodes (ALE1) to separate can be prevented or reduced.

[0261] Although the present invention has been specifically described according to the aforementioned embodiments, it should be noted that the embodiments are intended to illustrate the invention and not to limit the scope of the invention. Those skilled in the art will understand that various modifications are possible within the scope of the technical concept of the present invention.

[0262] The scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be determined by the claims. Furthermore, all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0263] ALE1: First alignment electrode ALE2: Second alignment electrode ALE3: Third alignment electrode AR: Light-emitting element array region BNK1: First Bank BNK2: Second Bank BNP: Bank Pattern BNP_1: 1st pattern part BNP_2: Part 2 of the pattern BNP_3: Third pattern part BSL: Base layer CNE1: First contact electrode CNE2: Second contact electrode CNE3: Third contact electrode DA: Display area DD: Display device DL: Data line DPL: Display layer DPN: Display Panel EA: Luminous area EA1: First light-emitting zone EA2: Second light-emitting zone EA3: Third Luminous Zone EMU: Light-emitting unit EP1: Part 1 EP2: Part 2 HPL1: 1st horizontal power line HPL2: 2nd horizontal power line LD: Light-emitting element NEA: Non-luminescent region OPN: Opening PCL: Circuit layer PL1: First power line PL2: Second power line PXA: Pixel area PXC: Pixel Circuit PXL: Pixels SENL: Sensing line SL: Scan line SPX: Subpixel SPX1: 1st subpixel SPX2: Second subpixel SPX3: 3rd subpixel

Claims

Claim 1 A display device comprising: a first wiring extending in a first direction; a second wiring spaced apart from the first wiring in a second direction; subpixels including light-emitting regions located between the first wiring and the second wiring and light-emitting elements disposed in the light-emitting regions; a bank pattern including openings corresponding to light-emitting element array regions where the light-emitting elements are arranged and which overlap with the first wiring and the second wiring; and a bank surrounding the light-emitting regions and overlapping with the first wiring, the second wiring and the bank pattern, wherein the first wiring is a scan line to which a scan signal is applied and the second wiring is a power line to which a first power supply voltage or a second power supply voltage is applied. Claim 2 A display device according to claim 1, wherein the second wiring extends in the first direction, and the bank pattern comprises: a first pattern portion that overlaps with the first wiring and is continuously formed along the first direction around the light-emitting regions; a second pattern portion that overlaps with the second wiring and is continuously formed along the first direction around the light-emitting regions; and third pattern portions that are disposed on both sides of each of the light-emitting element array regions in the first direction and extend in the second direction. Claim 3 A display device according to claim 2, wherein the bank is continuously formed along the first direction in the portion overlapping with the first pattern portion and the second pattern portion of the bank pattern. Claim 4 delete Claim 5 A display device according to claim 1, wherein each of the subpixels comprises a first alignment electrode located around the first ends of the light-emitting elements and extending in the second direction, and the first alignment electrode comprises an end located in a part of a non-light-emitting region adjacent to the light-emitting region of the corresponding subpixel in the second direction. Claim 6 In claim 5, the first alignment electrode is electrically connected to the first ends of the light-emitting elements, a display device. Claim 7 A display device according to claim 6, wherein each of the subpixels further comprises a pixel circuit electrically connected to the first alignment electrode. Claim 8 A display device according to claim 5, wherein each of the subpixels further comprises a second alignment electrode located around the second ends of the light-emitting elements and extended in the second direction. Claim 9 A display device according to claim 8, further comprising a power line electrically connected to the second alignment electrode. Claim 10 A display device according to claim 1, wherein the subpixels each comprise a first subpixel, a second subpixel, and a third subpixel, each comprising a first light-emitting region, a second light-emitting region, and a third light-emitting region, and wherein the first light-emitting region, the second light-emitting region, and the third light-emitting region are arranged in the first direction between the first wiring and the second wiring. Claim 11 A display device according to claim 10, wherein the first wiring, the bank pattern, and the bank completely overlap each other in a non-luminous region immediately adjacent to the first edge regions of the first light-emitting region, the second light-emitting region, and the third light-emitting region, and the second wiring, the bank pattern, and the bank completely overlap each other in a non-luminous region immediately adjacent to the second edge regions of the first light-emitting region, the second light-emitting region, and the third light-emitting region. Claim 12 A display device according to claim 10, wherein the first subpixel further comprises a first pixel circuit electrically connected to light-emitting elements disposed in the first light-emitting region among the light-emitting elements, the second subpixel further comprises a second pixel circuit electrically connected to light-emitting elements disposed in the second light-emitting region among the light-emitting elements, and the third subpixel further comprises a third pixel circuit electrically connected to light-emitting elements disposed in the third light-emitting region among the light-emitting elements. Claim 13 In claim 12, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged in the second direction, in a display device. Claim 14 In claim 13, the second wiring is a display device disposed between the second pixel circuit and the third pixel circuit. Claim 15 In claim 13, the first pixel circuit and the third pixel circuit are arranged between the first wiring and the second wiring, forming a display device. Claim 16 A display device according to claim 1, wherein each of the subpixels comprises: a light-emitting part including at least one light-emitting element disposed in a corresponding light-emitting region among the light-emitting elements, and electrodes electrically connected to the at least one light-emitting element; and a pixel circuit including circuit elements electrically connected to the light-emitting part. Claim 17 A display device according to claim 16, comprising: a circuit layer including pixel circuits of the subpixels, the first wiring and the second wiring; and a display layer overlapping with the circuit layer and including light-emitting portions of the subpixels. Claim 18 A display device according to claim 17, wherein the circuit layer comprises conductive layers sequentially arranged along a third direction intersecting the first direction and the second direction, and the conductive layer among the conductive layers closest to the display layer comprises the first wiring and the second wiring. Claim 19 A display device according to claim 1, comprising at least two pixels arranged in the first direction, each including a subpixel among the subpixels, wherein the bank pattern comprises individual patterns formed separately from each other corresponding to each of the at least two pixels, or an integrated pattern formed integrally of patterns corresponding to each of the at least two pixels. Claim 20 A first wiring and a second wiring extending in a first direction and spaced apart from each other in a second direction; a first subpixel including a first light-emitting region located between the first wiring and the second wiring and light-emitting elements disposed in the first light-emitting region; a second subpixel including a second light-emitting region located between the first wiring and the second wiring adjacent to the first light-emitting region in the first direction and light-emitting elements disposed in the second light-emitting region; a third subpixel including a third light-emitting region located between the first wiring and the second wiring adjacent to the second light-emitting region in the first direction and light-emitting elements disposed in the third light-emitting region; and a bank pattern including openings that overlap with the first wiring and the second wiring and correspond to respective light-emitting element array regions located in the first light-emitting region, the second light-emitting region and the third light-emitting region. A display device comprising a bank surrounding the light-emitting regions and overlapping the first wiring, the second wiring, and the bank pattern, wherein the bank pattern and the bank overlap the first wiring and the second wiring in a portion immediately adjacent to both ends of the first light-emitting region, the second light-emitting region, and the third light-emitting region in the second direction, and each is formed continuously along the first direction, wherein the first wiring is a scan line to which a scan signal is applied, and the second wiring is a power line to which a first power supply voltage or a second power supply voltage is applied.

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