Display device and method of fabricating the same

Abstract

A display device and a method for manufacturing the same are provided. A display device comprises a first pixel electrode and a second pixel electrode spaced apart from each other and disposed on a substrate; an inorganic insulating layer disposed on the substrate, with a portion disposed on the first pixel electrode and the second pixel electrode; a bank structure comprising a first opening disposed on the inorganic insulating layer and overlapping with the first pixel electrode, and a second opening overlapping with the second pixel electrode; a first light-emitting layer disposed on the first pixel electrode; a second light-emitting layer disposed on the second pixel electrode; a first common electrode disposed on the first light-emitting layer; and a second common electrode disposed on the second light-emitting layer. The bank structure comprises a first bank layer disposed directly on the inorganic insulating layer and comprising MoTaOx; a second bank layer disposed on the first bank layer and comprising MoTaOx; and a third bank layer disposed between the first bank layer and the second bank layer and comprising copper (Cu). The second bank layer comprises the third at the sidewalls of the first opening and the second opening It includes a tip protruding from the bank layer, and the first bank layer and the second bank layer have different Ta content in MoTaOx.

Description

Technology Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. Display devices may be flat panel display devices, such as Liquid Crystal Display Devices, Field Emission Display Devices, and Organic Light Emitting Display Devices. Among these flat panel display devices, light-emitting display devices include light-emitting elements in which each pixel of the display panel can emit light independently, thereby enabling the display of images without a backlight unit that provides light to the display panel. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device including a metal layer with low reflectivity of external light and a method for manufacturing the same.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to an embodiment for solving the above problem comprises a first pixel electrode and a second pixel electrode spaced apart from each other and disposed on a substrate; an inorganic insulating layer disposed on the substrate, with a portion disposed on the first pixel electrode and the second pixel electrode; a bank structure comprising a first opening disposed on the inorganic insulating layer and overlapping with the first pixel electrode, and a second opening overlapping with the second pixel electrode; a first light-emitting layer disposed on the first pixel electrode; a second light-emitting layer disposed on the second pixel electrode; a first common electrode disposed on the first light-emitting layer; and a second common electrode disposed on the second light-emitting layer. The bank structure comprises a first bank layer disposed directly on the inorganic insulating layer and comprising MoTaOx, a second bank layer disposed on the first bank layer and comprising MoTaOx, and a third bank layer disposed between the first bank layer and the second bank layer and comprising copper (Cu). The second bank layer comprises the first opening and the second opening The sidewall includes a tip protruding from the third bank layer, and the first bank layer and the second bank layer have different Ta content in MoTaOx.

[0006] The first bank layer may have a Ta content of 2 at% or less in MoTaOx, and the second bank layer may have a Ta content of 6 at% to 12 at% in MoTaOx.

[0007] The first bank layer has a thickness of 200 Å or less, and the second bank layer may have a thickness in the range of 400 Å to 600 Å.

[0008] The thickness of the third bank layer may be greater than that of the first bank layer and the second bank layer.

[0009] The first bank layer may not protrude more than the third bank layer from the side walls of the first opening and the second opening.

[0010] The first common electrode and the second common electrode can each come into direct contact with the side of the third bank layer.

[0011] The first light-emitting layer and the second light-emitting layer each come into direct contact with the side of the third bank layer, and the area where the first light-emitting layer comes into contact with the side of the third bank layer may be smaller than the area where the first common electrode comes into contact with the side of the third bank layer.

[0012] The above inorganic insulating layer does not come into contact with the upper surfaces of the first pixel electrode and the second pixel electrode, respectively, and a portion of the first light-emitting layer may be disposed between the first pixel electrode and the inorganic insulating layer, and a portion of the second light-emitting layer may be disposed between the second pixel electrode and the inorganic insulating layer.

[0013] It may further include a residual pattern disposed between the first pixel electrode and the second pixel electrode and the inorganic insulating layer.

[0014] The above inorganic insulating layer is arranged to be in direct contact with a portion of the upper surface of the first pixel electrode and the second pixel electrode, and a portion of the first light-emitting layer and the second light-emitting layer may each be directly arranged on the inorganic insulating layer.

[0015] It may further include a first organic pattern disposed on the second bank layer surrounding the first opening and comprising the same material as the first light-emitting layer, a first electrode pattern disposed on the first organic pattern and comprising the same material as the first common electrode, a second organic pattern disposed on the second bank layer surrounding the second opening and comprising the same material as the second light-emitting layer, and a second electrode pattern disposed on the second organic pattern and comprising the same material as the second common electrode.

[0016] The invention further includes a first inorganic layer disposed on the side wall of the first opening and disposed on the first common electrode and the first electrode pattern, and a second inorganic layer disposed on the side wall of the second opening and disposed on the second common electrode and the second electrode pattern, wherein the first inorganic layer and the second inorganic layer are disposed spaced apart from each other, and a portion of the second bank layer may not overlap with the first inorganic layer and the second inorganic layer.

[0017] The above bank structure further includes a thin film encapsulation layer disposed thereon, and the thin film encapsulation layer may include a first encapsulation layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer.

[0018] It may further include a light-blocking layer disposed on the third encapsulation layer and comprising a plurality of opening holes that overlap with the first opening and the second opening, and a first color filter disposed on the light-blocking layer that overlaps with the first opening and a second color filter that overlaps with the second opening.

[0019] A method for manufacturing a display device according to an embodiment for solving the above problem comprises the steps of: forming a plurality of pixel electrodes spaced apart from each other on a substrate, a sacrificial layer disposed on the pixel electrodes, an inorganic insulating layer disposed on the sacrificial layer, a first bank material layer and a second bank material layer disposed on the inorganic insulating layer, and a third bank material layer disposed between the first bank material layer and the second bank material layer; forming a first hole that overlaps with the pixel electrodes and penetrates the first bank material layer, the second bank material layer, and the third bank material layer to expose the sacrificial layer disposed on the pixel electrodes; wet-etching the sidewalls of the sacrificial layer and the first hole to remove the sacrificial layer and forming a tip in which the second bank material layer protrudes beyond the sidewalls of the third bank material layer; forming a light-emitting layer and a common electrode on the pixel electrodes within a first opening formed by wet-etching the first hole, and forming an inorganic layer on the common electrode and the second bank material layer; and the second bank material layer The method includes the step of removing a portion of the inorganic layer disposed on top, wherein the first bank material layer and the second bank material layer each contain MoTaOx but have different Ta contents, and the third bank material layer contains copper (Cu).

[0020] The first bank material layer has a Ta content of 2 at% or less in MoTaOx, and the second bank material layer may have a Ta content of 6 at% to 12 at% in MoTaOx.

[0021] The first bank material layer has a thickness of 200 Å or less, and the second bank material layer may have a thickness in the range of 400 Å to 600 Å.

[0022] In the step of wet etching the sidewall of the first hole, a portion of the first bank material layer may be etched so that it does not protrude from the sidewall of the third bank material layer.

[0023] The common electrode and the light-emitting layer each contact the sidewall of the third bank material layer, and the area where the common electrode contacts the third bank material layer may be larger than the area where the light-emitting layer contacts the third bank material layer.

[0024] In the step of forming the light-emitting layer and the common electrode, an organic pattern including the same material as the light-emitting layer and an electrode pattern including the same material as the common electrode are formed on the second bank material layer, and the inorganic layer may be disposed on the electrode pattern.

[0025] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0026] A display device according to one embodiment may include a metal layer having a low reflectivity of external light, wherein the bank structure is disposed on the top layer. The display device can reduce the reflection of external light that may occur in the bank structure, including an opening where light-emitting elements are disposed, and can provide excellent visibility to the user of the display device.

[0027] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0028] FIG. 1 is a schematic perspective view of an electronic device according to one embodiment. FIG. 2 is a perspective view showing a display device included in an electronic device according to one embodiment. Figure 3 is a cross-sectional view of the display device of Figure 2 viewed from the side. FIG. 4 is a plan view showing a display layer of a display device according to one embodiment. FIG. 5 is a plan view showing the arrangement of light-emitting regions and color filters in a display area of ​​a display device according to one embodiment. FIG. 6 is a cross-sectional view showing a part of a display device according to one embodiment. Figure 7 is a cross-sectional view showing the first light-emitting region of Figure 6. Figure 8 is an enlarged view of area A of Figure 7. FIGS. 9 to 16 are cross-sectional views showing the display area portion in sequence during the manufacturing process of a display device according to one embodiment. FIG. 17 is a cross-sectional view showing a light-emitting region of a display device according to another embodiment. Specific details for implementing the invention

[0029] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0030] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0031] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0032] Hereinafter, embodiments will be described with reference to the attached drawings.

[0033] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0034] Referring to FIG. 1, the electronic device (1) displays a video or a still image. The electronic device (1) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, e-book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the electronic device (1).

[0035] The electronic device (1) may include a display device ('10' in FIG. 2) that provides a display screen. Examples of display devices include an inorganic light-emitting diode display device, an organic light-emitting diode display device, a quantum dot light-emitting display device, a plasma display device, a field emission display device, etc. Below, an example of a display device is given in which an organic light-emitting diode display device is applied, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display devices.

[0036] The shape of the electronic device (1) can be varied in many ways. For example, the electronic device (1) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a square with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area (DA) of the electronic device (1) may also be similar to the overall shape of the electronic device (1). In FIG. 1, an electronic device (1) with a rectangular shape having a long length in the second direction (DR2) is exemplified.

[0037] The electronic device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) is an area where a screen can be displayed, and the non-display area (NDA) is an area where a screen is not displayed. The display area (DA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DA) may generally occupy the center of the electronic device (1).

[0038] The display area (DA) may include a first display area (DA1), a second display area (DA2), and a third display area (DA3). The second display area (DA2) and the third display area (DA3) are areas where components for adding various functions to the electronic device (1) are placed, and the second display area (DA2) and the third display area (DA3) may correspond to component areas.

[0039] FIG. 2 is a perspective view showing a display device included in an electronic device according to one embodiment.

[0040] Referring to FIG. 2, an electronic device (1) according to one embodiment may include a display device (10). The display device (10) may provide a screen displayed on the electronic device (1). The display device (10) may have a planar shape similar to that of the electronic device (1). For example, the display device (10) may have a shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have curvature, but is not limited thereto and may be formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses.

[0041] The display device (10) may include a display panel (100), a display driving unit (200), a circuit board (300), and a touch driving unit (400).

[0042] The display panel (100) may include a main area (MA) and a sub-area (SBA).

[0043] The main area (MA) may include a display area (DA) containing pixels that display an image, and a non-display area (NDA) disposed around the display area (DA). The display area (DA) may include a first display area (DA1), a second display area (DA2), and a third display area (DA3). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel defining film defining a light-emitting area or an aperture area, and a self-light-emitting element.

[0044] For example, the self-luminous device may include at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (QLED) including a quantum dot light-emitting layer, an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (Micro LED), but is not limited thereto.

[0045] The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a gate driver (not shown) that supplies gate signals to gate lines, and fan-out lines (not shown) connecting the display driver (200) and the display area (DA).

[0046] The sub-region (SBA) may be an area extending from one side of the main area (MA). The sub-region (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region (SBA) is bent, the sub-region (SBA) may overlap with the main area (MA) in the thickness direction (third direction (DR3)). The sub-region (SBA) may include a pad portion connected to a display driving unit (200) and a circuit board (300). In another embodiment, the sub-region (SBA) may be omitted, and the display driving unit (200) and the pad portion may be placed in a non-display area (NDA).

[0047] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines. The display driver (200) can supply power voltage to power lines and supply gate control signals to the gate driver. The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a Chip on Glass (COG) method, a Chip on Plastic (COP) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in a sub-region (SBA) and can be overlapped in the thickness direction with the main region (MA) by bending the sub-region (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0048] The circuit board (300) can be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). The lead lines of the circuit board (300) can be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0049] The touch driving unit (400) may be mounted on the circuit board (300). The touch driving unit (400) may be connected to the touch sensing unit of the display panel (100). The touch driving unit (400) may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driving unit (400) may calculate whether an input has occurred and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driving unit (400) may be formed as an integrated circuit (IC).

[0050] Figure 3 is a cross-sectional view of the display device of Figure 2 viewed from the side.

[0051] Referring to FIG. 3, the display panel (100) may include a display layer (DU), a touch sensing layer (TSU), and a color filter layer (CFL). The display layer (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light-emitting element layer (EML), and a thin film encapsulation layer (TFEL).

[0052] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In other embodiments, the substrate (SUB) may include a glass material or a metal material.

[0053] A thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may include a plurality of thin-film transistors that constitute a pixel circuit of pixels. The thin-film transistor layer (TFTL) may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver (200) and the data lines, and lead lines connecting the display driver (200) and the pad portion. Each of the thin-film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area (NDA) of the display panel (100), the gate driver may include thin-film transistors.

[0054] The thin-film transistor layer (TFTL) can be placed in a display area (DA), a non-display area (NDA), and a sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines of each pixel of the thin-film transistor layer (TFTL) can be placed in the display area (DA). The gate control lines and fan-out lines of the thin-film transistor layer (TFTL) can be placed in the non-display area (NDA). The lead lines of the thin-film transistor layer (TFTL) can be placed in the sub-area (SBA).

[0055] A light-emitting element layer (EML) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include a plurality of light-emitting elements that emit light, including a first electrode, a second electrode, and a light-emitting layer, and a pixel defining film that defines pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be disposed in a display area (DA).

[0056] In one embodiment, the light-emitting layer may be an organic light-emitting layer comprising an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the first electrode receives a voltage through a thin-film transistor of a thin-film transistor layer (TFTL) and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and may combine with each other in the organic light-emitting layer to emit light.

[0057] In another embodiment, the light-emitting element may include a quantum dot light-emitting diode comprising a quantum dot light-emitting layer, an inorganic light-emitting diode comprising an inorganic semiconductor, or a micro light-emitting diode.

[0058] A display device (10) according to one embodiment may include a plurality of color filters (CF1, CF2, CF3 of FIG. 5 and 6) disposed on light-emitting elements of a light-emitting element layer (EML). Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filters may absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Thus, the color filters can prevent color distortion caused by external light reflection. Since the color filters are disposed on the light-emitting elements, the display device (10) may not require a separate substrate for the color filters. Therefore, the thickness of the display device (10) may be relatively small.

[0059] The thin film encapsulation layer (TFEL) can cover the top and sides of the light-emitting element layer (EML) and protect the light-emitting element layer (EML). The thin film encapsulation layer (TFEL) may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer (EML).

[0060] A touch sensing layer (TSU) may be disposed on an encapsulation layer (TFEL). The touch sensing layer (TSU) may include a plurality of touch electrodes for detecting a user's touch in a capacitive manner, and touch lines connecting the plurality of touch electrodes to a touch driving unit (400). For example, the touch sensing layer (TSU) may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0061] In another embodiment, the touch sensing layer (TSU) may be disposed on a separate substrate disposed on the display layer (DU). In this case, the substrate supporting the touch sensing layer (TSU) may be a base member that encapsulates the display layer (DU).

[0062] A plurality of touch electrodes of the touch sensing layer (TSU) may be placed in a touch sensor area that overlaps with the display area (DA). Touch lines of the touch sensing layer (TSU) may be placed in a touch peripheral area that overlaps with the non-display area (NDA).

[0063] In some embodiments, the display device (10) may further include an optical device (500). The optical device (500) may be placed in a second display area (DA2) or a third display area (DA3). The optical device (500) may emit or receive light in the infrared, ultraviolet, and visible light bands. For example, the optical device (500) may be an optical sensor that detects light incident on the display device (10), such as a proximity sensor, an illuminance sensor, and a camera sensor or an image sensor.

[0064] A color filter layer (CFL) can be disposed on a thin film encapsulation layer (TFEL). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters can selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer (CFL) can reduce reflected light caused by external light by absorbing a portion of the light entering from outside the display device (10). Therefore, the color filter layer (CFL) can prevent color distortion caused by external light reflection.

[0065] Since the color filter layer (CFL) is placed directly on the thin film encapsulation layer (TFEL), the display device (10) may not require a separate substrate for the color filter layer (CFL). Therefore, the thickness of the display device (10) may be relatively small.

[0066] FIG. 4 is a plan view showing a display layer of a display device according to one embodiment.

[0067] Referring to FIG. 4, the display layer (DU) may include a display area (DA) and a non-display area (NDA).

[0068] A display area (DA) may be positioned in the center of a display panel (100). A plurality of pixels (PX), a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of power lines (VL) may be positioned in the display area (DA). Each of the plurality of pixels (PX) may be defined as a minimum unit that emits light.

[0069] A plurality of gate lines (GL) can supply gate signals received from a gate driver (210) to a plurality of pixels (PX). The plurality of gate lines (GL) can be extended in a first direction (DR1) and can be spaced apart from each other in a second direction (DR2) that intersects the first direction (DR1).

[0070] A plurality of data lines (DL) can supply data voltage received from a display driving unit (200) to a plurality of pixels (PX). The plurality of data lines (DL) can be extended in a second direction (DR2) and can be spaced apart from each other in a first direction (DR1).

[0071] A plurality of power lines (VL) can supply power voltage received from a display driving unit (200) to a plurality of pixels (PX). Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. A plurality of power lines (VL) may extend in a second direction (DR2) and may be spaced apart from each other in a first direction (DR1).

[0072] A non-display area (NDA) may surround a display area (DA). A gate driver (210), fan-out lines (FOL), and gate control lines (GCL) may be placed in the non-display area (NDA). The gate driver (210) may generate a plurality of gate signals based on a gate control signal and may sequentially supply the plurality of gate signals to a plurality of gate lines (GL) according to a set order.

[0073] Fan-out lines (FOL) can extend from the display driver (200) to the display area (DA). The fan-out lines (FOL) can supply data voltage received from the display driver (200) to a plurality of data lines (DL).

[0074] The gate control line (GCL) can be extended from the display driver (200) to the gate driver (210). The gate control line (GCL) can supply a gate control signal received from the display driver (200) to the gate driver (210).

[0075] The sub-area (SBA) may include a display driving unit (200), a pad area (PA), and first and second touch pad areas (TPA1, TPA2).

[0076] The display driver (200) can output signals and voltages to drive the display panel (100) to the fan-out lines (FOL). The display driver (200) can supply data voltage to the data line (DL) through the fan-out lines (FOL). The data voltage can be supplied to a plurality of pixels (PX) and can control the brightness of the plurality of pixels (PX). The display driver (200) can supply a gate control signal to the gate driver (210) through the gate control line (GCL).

[0077] The pad area (PA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be placed at the edge of the sub-area (SBA). The pad area (PA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be electrically connected to the circuit board (300) using a material such as an anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste).

[0078] The pad area (PA) may include a plurality of display pad sections (DP). The plurality of display pad sections (DP) may be connected to a graphics system through a circuit board (300). The plurality of display pad sections (DP) may be connected to the circuit board (300) to receive digital video data and supply digital video data to a display driving unit (200).

[0079] FIG. 5 is a plan view showing the arrangement of light-emitting regions and color filters in a display area of ​​a display device according to one embodiment.

[0080] Referring to FIG. 5, the display device (10) may include a plurality of light-emitting regions (EA1, EA2, EA3) disposed in a display area (DA). The display area (DA) shown in FIG. 5 is a first display area (DA1), and a plurality of light-emitting regions (EA1, EA2, EA3) may be disposed in the first display area (DA1). However, a plurality of light-emitting regions (EA1, EA2, EA3) may also be disposed in a second display area (DA2) and a third display area (DA3) among the display areas (DA).

[0081] The light-emitting regions (EA1, EA2, EA3) may include a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3) that emit light of different colors. The first to third light-emitting regions (EA1, EA2, EA3) may each emit red, green, or blue light, and the color of the light emitted from each light-emitting region (EA1, EA2, EA3) may vary depending on the type of light-emitting element ('ED1', 'ED2', 'ED3' in FIG. 6) disposed on the light-emitting element layer (EML) described later. In an exemplary embodiment, the first light-emitting region (EA1) may emit a first red light, the second light-emitting region (EA2) may emit a second green light, and the third light-emitting region (EA3) may emit a third blue light. However, it is not limited thereto.

[0082] Multiple light-emitting regions (EA1, EA2, EA3) are Pentile TM Type, for example, diamond pentile TMThey can be arranged in a specific type. For example, the first light-emitting region (EA1) and the third light-emitting region (EA3) may be spaced apart from each other in a first direction (DR1), and they may be arranged alternately in the first direction (DR1) and the second direction (DR2). In the arrangement of the light-emitting regions (EA1, EA2, EA3), the first light-emitting region (EA1) and the third light-emitting region (EA3) may be arranged alternately in the first direction (DR1) in the first row (R1) and the third row (R3). The first light-emitting region (EA1) and the third light-emitting region (EA3) may be arranged alternately in the second direction (DR2) in the first column (C1) and the third column (C3).

[0083] A second light-emitting region (EA2) may be spaced apart from an adjacent second light-emitting region (EA2) in a first direction (DR1) and a second direction (DR2), and may be spaced apart from an adjacent first light-emitting region (EA1) and a third light-emitting region (EA3) in a fourth direction (DR4) or a fifth direction (DR5). A plurality of second light-emitting regions (EA2) may be repeatedly arranged along the first direction (DR1) and the second direction (DR2), and the second light-emitting region (EA2) and the first light-emitting region (EA1), or the second light-emitting region (EA2) and the third light-emitting region (EA3) may be alternately arranged along the fourth direction (DR4) or the fifth direction (DR5). In the arrangement of light-emitting regions (EA1, EA2, EA3), the second light-emitting region (EA2) may be repeatedly arranged in the first direction (DR1) in the second row (R2) and the fourth row (R4), and the second light-emitting region (EA2) may be repeatedly arranged in the second direction (DR2) in the second column (C2) and the fourth column (C4).

[0084] The first to third light-emitting regions (EA1, EA2, EA3) can each be defined by a plurality of openings (OPE1, OPE2, OPE3) formed in the bank structure ('BNS' in FIG. 6) of the light-emitting element layer (EML) described later. For example, the first light-emitting region (EA1) can be defined by the first opening (OPE1) of the pixel defining film, the second light-emitting region (EA2) can be defined by the second opening (OPE2) of the pixel defining film, and the third light-emitting region (EA3) can be defined by the third opening (OPE3) of the pixel defining film.

[0085] The area of ​​the light-emitting regions (EA1, EA2, EA3) may vary depending on the size of the openings (OPE1, OPE2, OPE3) of the bank structure. Depending on the area of ​​the light-emitting regions (EA1, EA2, EA3), the intensity of light emitted from the corresponding light-emitting regions (EA1, EA2, EA3) may vary, and the color tone of the screen displayed on the display device (10) or electronic device (1) can be controlled by adjusting the area of ​​the light-emitting regions (EA1, EA2, EA3). In an exemplary embodiment, the area or size of the first to third light-emitting regions (EA1, EA2, EA3) may be the same as each other. In the embodiment of FIG. 6, the area or diameter of the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may be the same as each other.

[0086] However, it is not limited thereto. The area of ​​the light-emitting region (EA1, EA2, EA3) can be freely adjusted according to the color tone of the screen required in the display device (10) and the electronic device (1). In addition, the area of ​​the light-emitting region (EA1, EA2, EA3) is related to light efficiency, the lifespan of the light-emitting element (ED), etc., and may have a trade-off relationship with reflection by external light. The area of ​​the light-emitting region (EA1, EA2, EA3) can be adjusted by taking the above matters into consideration. For example, in the display device (10), the area of ​​the third light-emitting region (EA3) may be larger than the area of ​​the first light-emitting region (EA1) and the second light-emitting region (EA2), and the area of ​​the first light-emitting region (EA1) may be larger than the area of ​​the second light-emitting region (EA2).

[0087] A display device (10) having an arrangement of light-emitting regions (EA1, EA2, EA3) as in FIG. 5 may have one first light-emitting region (EA1), two second light-emitting regions (EA2), and one third light-emitting region (EA3) arranged adjacent to each other to form a pixel group. A pixel group may include light-emitting regions (EA1, EA2, EA3) that emit light of different colors to express a white gradation. However, it is not limited thereto, and the combination of light-emitting regions (EA1, EA2, EA3) constituting a pixel group may be varied in many ways depending on the arrangement of the light-emitting regions (EA1, EA2, EA3) and the color of the light emitted by them.

[0088] The display device (10) may include a plurality of color filters (CF1, CF2, CF3) disposed on a light-emitting region (EA1, EA2, EA3). Each of the plurality of color filters (CF1, CF2, CF3) may be disposed corresponding to the light-emitting region (EA1, EA2, EA3). For example, the color filters (CF1, CF2, CF3) may be disposed in a plurality of opening holes (OPT1, OPT2, OPT3) of a light-shielding layer (BM) disposed corresponding to the light-emitting region (EA1, EA2, EA3) or the opening (OPE1, OPE2, OPE3). The opening holes (OPT1, OPT2, OPT3) of the light-shielding layer may be formed to overlap with the opening (OPE1, OPE2, OPE3) and may form a light-emitting region from which light emitted from the light-emitting region (EA1, EA2, EA3) is emitted. Each of the color filters (CF1, CF2, CF3) may have an area larger than the opening (OPE1, OPE2, OPE3), and each of the color filters (CF1, CF2, CF3) may completely cover the light-emitting area formed by the opening holes (OPT1, OPT2, OPT3) of the light-blocking layer (BM).

[0089] Color filters (CF1, CF2, CF3) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) positioned to correspond to different light emission regions (EA1, EA2, EA3), respectively. The color filters (CF1, CF2, CF3) may include a colorant, such as a dye or pigment, that absorbs light of a wavelength other than that of a specific wavelength, and may be positioned to correspond to the color of the light emitted from the light emission regions (EA1, EA2, EA3). For example, the first color filter (CF1) may be a red color filter that is positioned to overlap with the first light emission region (EA1) and transmits only the first red light. The second color filter (CF2) is positioned to overlap with the second light-emitting region (EA2) and is a green color filter that transmits only the second green light, and the third color filter (CF3) is positioned to overlap with the third light-emitting region (EA3) and is a blue color filter that transmits only the third blue light.

[0090] Similar to the arrangement of the light-emitting regions (EA1, EA2, EA3), the color filters (CF1, CF2, CF3) are Pentile TM Type, for example, diamond pentile TM They can be arranged in a specific type. For example, the first color filter (CF1) and the third color filter (CF3) can be arranged alternately in the first direction (DR1) and the second direction (DR2). In the arrangement of the color filters (CF1, CF2, CF3), the first color filter (CF1) and the third color filter (CF3) can be arranged alternately in the first direction (DR1) in the first row (R1) and the third row (R3). The first color filter (CF1) and the third color filter (CF3) can be arranged alternately in the second direction (DR2) in the first column (C1) and the third column (C3).

[0091] A second color filter (CF2) may be arranged in a first direction (DR1) and a second direction (DR2) with an adjacent second color filter (CF2), and may be arranged in a fourth direction (DR4) or a fifth direction (DR5) with an adjacent first color filter (CF1) and a third color filter (CF3). Multiple second color filters (CF2) may be arranged repeatedly along the first direction (DR1) and the second direction (DR2), and the second color filter (CF2) and the first color filter (CF1), or the second color filter (CF2) and the third color filter (CF3) may be arranged alternately along the fourth direction (DR4) or the fifth direction (DR5). In the arrangement of color filters (CF1, CF2, CF3), the second color filter (CF2) may be repeatedly arranged in the first direction (DR1) in the second row (R2) and the fourth row (R4), and the second color filter (CF2) may be repeatedly arranged in the second direction (DR2) in the second column (C2) and the fourth column (C4).

[0092] FIG. 6 is a cross-sectional view showing a part of a display device according to one embodiment. FIG. 7 is a cross-sectional view showing a first light-emitting region of FIG. 6. FIG. 6 is a cross-sectional view of a part of a display device (10), showing a cross-section of a substrate (SUB), a thin-film transistor layer (TFTL), a light-emitting element layer (EML), a thin-film encapsulation layer (TFEL), a touch sensing layer (TSU), and a color filter layer (CFL) of a display layer (DU). FIG. 7 shows a part of a first light-emitting element (ED1) and a bank structure (BNS) around it, disposed in the first light-emitting region (EA1) in FIG. 6.

[0093] Referring to FIG. 6 and FIG. 7 in addition to FIG. 5, the display panel (100) of the display device (10) may include a display layer (DU). The display layer (DU) may include a substrate (SUB), a thin-film transistor layer (TFTL), a light-emitting element layer (EML), and a thin-film encapsulation layer (TFEL). The display panel (100) may include a light-blocking layer (BM) and color filters (CF1, CF2, CF3) as an anti-reflection layer (RPL) disposed on the thin-film encapsulation layer (TFEL). The light-blocking layer (BM) is disposed on the thin-film encapsulation layer (TFEL), and the color filters (CF1, CF2, CF3) of the color filter layer (CFL) may be disposed on the light-blocking layer (BM). The color filter layer (CFL) and the light-blocking layer (BM) may serve as anti-reflection members in the display device (10).

[0094] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate (SUB) may include a glass material or a metal material.

[0095] The thin film transistor layer (TFTL) may include a first buffer layer (BF1), a lower metal layer (BML), a second buffer layer (BF2), a thin film transistor (TFT), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a capacitor electrode (CPE), a second interlayer insulating layer (ILD2), a first connecting electrode (CNE1), a first protective layer (PAS1), a second connecting electrode (CNE2), and a second protective layer (PAS2).

[0096] The first buffer layer (BF1) may be disposed on a substrate (SUB). The first buffer layer (BF1) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer (BF1) may include a plurality of inorganic films stacked alternately.

[0097] The lower metal layer (BML) may be disposed on the first buffer layer (BF1). For example, the lower metal layer (BML) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0098] The second buffer layer (BF2) may cover the first buffer layer (BF1) and the lower metal layer (BML). The second buffer layer (BF2) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the second buffer layer (BF2) may include a plurality of inorganic films stacked alternately.

[0099] A thin-film transistor (TFT) can be placed on a second buffer layer (BF2) and can form a pixel circuit for each of a plurality of pixels. For example, the thin-film transistor (TFT) may be a driving transistor or a switching transistor of a pixel circuit. The thin-film transistor (TFT) may include a semiconductor layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0100] A semiconductor layer (ACT) may be disposed on a second buffer layer (BF2). The semiconductor layer (ACT) may overlap with the lower metal layer (BML) and the gate electrode (GE) in the thickness direction and may be insulated from the gate electrode (GE) by a gate insulating layer (GI). A portion of the semiconductor layer (ACT) may form a source electrode (SE) and a drain electrode (DE) by making the material of the semiconductor layer (ACT) conductive.

[0101] The gate electrode (GE) can be placed on the gate insulating layer (GI). The gate electrode (GE) can be overlapped with the semiconductor layer (ACT) with the gate insulating layer (GI) in between.

[0102] A gate insulating layer (GI) may be disposed on a semiconductor layer (ACT). For example, the gate insulating layer (GI) may cover the semiconductor layer (ACT) and the second buffer layer (BF2), and may insulate the semiconductor layer (ACT) from the gate electrode (GE). The gate insulating layer (GI) may include a contact hole through which a first connecting electrode (CNE1) passes.

[0103] The first interlayer insulating layer (ILD1) may cover the gate electrode (GE) and the gate insulating layer (GI). The first interlayer insulating layer (ILD1) may include a contact hole through which the first connecting electrode (CNE1) passes. The contact hole of the first interlayer insulating layer (ILD1) may be connected to the contact hole of the gate insulating layer (GI) and the contact hole of the second interlayer insulating layer (ILD2).

[0104] A capacitor electrode (CPE) can be disposed on the first interlayer insulating layer (ILD1). The capacitor electrode (CPE) can overlap with the gate electrode (GE) in the thickness direction. The capacitor electrode (CPE) and the gate electrode (GE) can form a capacitance.

[0105] The second interlayer insulating layer (ILD2) may cover the capacitor electrode (CPE) and the first interlayer insulating layer (ILD1). The second interlayer insulating layer (ILD2) may include a contact hole through which the first connecting electrode (CNE1) passes. The contact hole of the second interlayer insulating layer (ILD2) may be connected to the contact hole of the first interlayer insulating layer (ILD1) and the contact hole of the gate insulating layer (GI).

[0106] The first connecting electrode (CNE1) may be disposed on the second interlayer insulating layer (ILD2). The first connecting electrode (CNE1) may electrically connect the drain electrode (DE) of the thin-film transistor (TFT) and the second connecting electrode (CNE2). The first connecting electrode (CNE1) may be inserted into a contact hole formed in the second interlayer insulating layer (ILD2), the first interlayer insulating layer (ILD1), and the gate insulating layer (GI) to make contact with the drain electrode (DE) of the thin-film transistor (TFT).

[0107] The first protective layer (PAS1) can cover the first connecting electrode (CNE1) and the second interlayer insulating layer (ILD2). The first protective layer (PAS1) can protect the thin-film transistor (TFT). The first protective layer (PAS1) may include a contact hole through which the second connecting electrode (CNE2) passes.

[0108] The second connecting electrode (CNE2) can be disposed on the first protective layer (PAS1). The second connecting electrode (CNE2) can electrically connect the first connecting electrode (CNE1) and the pixel electrodes (AE1, AE2, AE3) of the light-emitting element (ED). The second connecting electrode (CNE2) can be inserted into a contact hole formed in the first protective layer (PAS1) and contact the first connecting electrode (CNE1).

[0109] The second protective layer (PAS2) can cover the second connecting electrode (CNE2) and the first protective layer (PAS1). The second protective layer (PAS2) may include a contact hole through which the pixel electrodes (AE1, AE2, AE3) of the light-emitting element (ED) pass.

[0110] The light-emitting element layer (EML) may be disposed on the thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include a light-emitting element (ED) and a plurality of bank structures (BNS). The light-emitting element (ED) may include pixel electrodes (AE1, AE2, AE3), light-emitting layers (EL1, EL2, EL3), and common electrodes (CE1, CE2, CE3).

[0111] A display device (10) may include a plurality of light-emitting regions (EA1, EA2, EA3) disposed in a display area (DA). The light-emitting regions (EA1, EA2, EA3) may include a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3) that emit light of different colors. The first to third light-emitting regions (EA1, EA2, EA3) may each emit red, green, or blue light, and the color of the light emitted from each light-emitting region (EA1, EA2, EA3) may vary depending on the type of light-emitting element (ED) disposed in the light-emitting element layer (EML). In an exemplary embodiment, the first light-emitting region (EA1) may emit a first red light, the second light-emitting region (EA2) may emit a second green light, and the third light-emitting region (EA3) may emit a third blue light. However, it is not limited thereto.

[0112] The first to third light-emitting regions (EA1, EA2, EA3) can each be defined by a plurality of openings (OPE1, OPE2, OPE3) formed in the bank structure (BNS) of the light-emitting element layer (EML). For example, the first light-emitting region (EA1) can be defined by the first opening (OPE1) of the bank structure (BNS), the second light-emitting region (EA2) can be defined by the second opening (OPE2) of the bank structure (BNS), and the third light-emitting region (EA3) can be defined by the third opening (OPE3) of the bank structure (BNS).

[0113] In an exemplary embodiment, the area or size of the first to third light-emitting regions (EA1, EA2, EA3) may be the same. For example, the display device (10) may have the same diameter for the openings (OPE1, OPE2, OPE3) of the bank structures (BNS), and the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may have the same area. However, it is not limited thereto. The display device (10) may have different areas or sizes for the first to third light-emitting regions (EA1, EA2, EA3). For example, the area of ​​the second light-emitting region (EA2) may be larger than the area of ​​the first light-emitting region (EA1) and the third light-emitting region (EA3), and the area of ​​the third light-emitting region (EA3) may be larger than the area of ​​the first light-emitting region (EA1). The intensity of light emitted from the corresponding light-emitting areas (EA1, EA2, EA3) may vary depending on the area of ​​the light-emitting areas (EA1, EA2, EA3), and the color tone of the screen displayed on the display device (10) or electronic device (1) can be controlled by adjusting the area of ​​the light-emitting areas (EA1, EA2, EA3). In the embodiment of FIG. 5, the areas of each light-emitting area (EA1, EA2, EA3) are exemplified as being equal to each other, but are not limited thereto. The area of ​​the light-emitting areas (EA1, EA2, EA3) can be freely adjusted according to the color tone of the screen required by the display device (10) and electronic device (1). In addition, the area of ​​the light-emitting areas (EA1, EA2, EA3) is related to light efficiency, the lifespan of the light-emitting element (ED), etc., and may have a trade-off relationship with reflection by external light. The area of ​​the light-emitting areas (EA1, EA2, EA3) can be adjusted by taking the above matters into consideration.

[0114] A display device (10) may have a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3) arranged adjacent to each other to form a pixel group. A pixel group may include light-emitting regions (EA1, EA2, EA3) that emit light of different colors and may express a white gradation. However, it is not limited thereto, and the combination of light-emitting regions (EA1, EA2, EA3) constituting a pixel group may be varied in many ways depending on the arrangement of the light-emitting regions (EA1, EA2, EA3) and the color of the light emitted by them.

[0115] The display device (10) may include a plurality of light-emitting elements (ED1, ED2, ED3) disposed in different light-emitting regions (EA1, EA2, EA3). The light-emitting elements (ED1, ED2, ED3) may include a first light-emitting element (ED1) disposed in a first light-emitting region (EA1), a second light-emitting element (ED2) disposed in a second light-emitting region (EA2), and a third light-emitting element (ED3) disposed in a third light-emitting region (EA3). Each of the light-emitting elements (ED1, ED2, ED3) includes a pixel electrode (AE1, AE2, AE3), a light-emitting layer (EL1, EL2, EL3), and a common electrode (CE1, CE2, CE3), and the light-emitting elements (ED1, ED2, ED3) placed in different light-emitting regions (EA1, EA2, EA3) can emit light of different colors depending on the material of the light-emitting layer (EL1, EL2, EL3). For example, the first light-emitting element (ED1) placed in the first light-emitting region (EA1) can emit red light of the first color, the second light-emitting element (ED2) placed in the second light-emitting region (EA2) can emit green light of the second color, and the third light-emitting element (ED3) placed in the third light-emitting region (EA3) can emit blue light of the third color. The first to third light-emitting regions (EA1, EA2, EA3) constituting a single pixel may include light-emitting elements (ED1, ED2, ED3) that emit light of different colors, thereby expressing a white gradation.

[0116] Pixel electrodes (AE1, AE2, AE3) may be disposed on the second protective layer (PAS2). Pixel electrodes (AE1, AE2, AE3) may be disposed to overlap with any one of the openings (OPE1, OPE2, OPE3) of the bank structure (BNS). Pixel electrodes (AE1, AE2, AE3) may be electrically connected to the drain electrode (DE) of the thin-film transistor (TFT) through the first and second connecting electrodes (CNE1, CNE2).

[0117] Pixel electrodes (AE1, AE2, AE3) may each be disposed in a plurality of light-emitting regions (EA1, EA2, EA3). The pixel electrodes (AE1, AE2, AE3) may include a first pixel electrode (AE1) disposed in a first light-emitting region (EA1), a second pixel electrode (AE2) disposed in a second light-emitting region (EA2), and a third pixel electrode (AE3) disposed in a third light-emitting region (EA3). The first pixel electrode (AE1), the second pixel electrode (AE2), and the third pixel electrode (AE3) may each be disposed spaced apart from each other on a second protective layer (PAS2). Each of the pixel electrodes (AE1, AE2, AE3) may be disposed in different light-emitting regions (EA1, EA2, EA3) to form a light-emitting element (ED1, ED2, ED3) that emits light of different colors.

[0118] In an exemplary embodiment, the pixel electrodes (AE1, AE2, AE3) may have a stacked film structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof are stacked. The high work function layer may be positioned above the reflective material layer and positioned close to the light-emitting layer (EL1, EL2, EL3). For example, the pixel electrodes (AE1, AE2, AE3) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but are not limited thereto.

[0119] An inorganic insulating layer (ISL) may be disposed on a second protective layer (PAS2) and pixel electrodes (AE1, AE2, AE3). The inorganic insulating layer (ISL) may be disposed entirely on the second protective layer (PAS2), but may expose a portion of the upper surface of the pixel electrodes (AE1, AE2, AE3) while overlapping with the pixel electrodes (AE1, AE2, AE3). For example, the inorganic insulating layer (ISL) may expose the pixel electrodes (AE1, AE2, AE3) in a portion that overlaps with the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), and the light-emitting layer (EL1, EL2, EL3) disposed on the pixel electrodes (AE1, AE2, AE3) may be disposed directly on the pixel electrodes (AE1, AE2, AE3). The inorganic insulating layer (ISL) may include an inorganic insulating material. For example, the inorganic insulating layer (ISL) may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0120] According to one embodiment, an inorganic insulating layer (ISL) may be disposed on the pixel electrodes (AE1, AE2, AE3) but spaced apart from the upper surface of the pixel electrodes (AE1, AE2, AE3). The inorganic insulating layer (ISL) may partially overlap with the pixel electrodes (AE1, AE2, AE3) without direct contact, and a portion of the light-emitting layer (EL1, EL2, EL3) of the light-emitting element (ED1, ED2, ED3) may be disposed between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3). In the manufacturing process of the display device (10), a sacrificial layer ('SFL' in FIG. 9) may be disposed on the pixel electrodes (AE1, AE2, AE3) before forming the inorganic insulating layer (ISL). The inorganic insulating layer (ISL) is positioned to cover a portion of the sacrificial layer, and can be spaced apart from the upper surface of the pixel electrodes (AE1, AE2, AE3) as the sacrificial layer is removed. Subsequently, during the deposition process of the light-emitting layer (EL1, EL2, EL3), as the materials forming the light-emitting layer (EL1, EL2, EL3) fill the space between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3), a portion of the inorganic insulating layer (ISL) can be placed on the light-emitting layer (EL1, EL2, EL3). However, the inorganic insulating layer (ISL) may be in direct contact with the side of the pixel electrodes (AE1, AE2, AE3).

[0121] A display device (10) may include a plurality of bank structures (BNS) that are disposed on a thin film transistor layer (TFTL) or a substrate (SUB) and include a plurality of openings (OPE1, OPE2, OPE3). The bank structures (BNS) may have a structure in which bank layers (BN1, BN2, BN3) containing different materials are sequentially stacked, and may include a plurality of openings (OPE1, OPE2, OPE3) that form light-emitting regions (EA1, EA2, EA3). Light-emitting elements (ED1, ED2, ED3) of the display device (10) may be disposed to overlap with the openings (OPE1, OPE2, OPE3) of the bank structures (BNS).

[0122] The bank structure (BNS) may include a first bank layer (BN1) and a second bank layer (BN2) disposed on an inorganic insulating layer (ISL), and a third bank layer (BN3) disposed on the first bank layer (BN1) and the second bank layer (BN2). The bank structure (BNS) may have a structure in which the first bank layer (BN1), the third bank layer (BN3), and the second bank layer (BN2) are sequentially stacked. The first bank layer (BN1) may be the lowest layer of the bank structure (BNS), the second bank layer (BN2) may be the uppermost layer of the bank structure (BNS), and the third bank layer (BN3) may be an intermediate layer of the bank structure (BNS).

[0123] Figure 8 is an enlarged view of area A of Figure 7.

[0124] Referring to FIG. 8 in addition to FIG. 7, according to one embodiment, the first bank layer (BN1) and the second bank layer (BN2) may comprise substantially the same material, and the third bank layer (BN3) may comprise a material different from the first bank layer (BN1) and the second bank layer (BN2). The bank structure (BNS) may have the first to third bank layers (BN1, BN2, BN3) each comprising a metal material, but each comprising a different metal material, so that they each perform different roles. In an exemplary embodiment, the third bank layer (BN3) may comprise a metal material with high electrical conductivity, and the first bank layer (BN1) and the second bank layer (BN2) may comprise a metal material with low reflectivity.

[0125] For example, the first bank layer (BN1) and the second bank layer (BN2) may contain MoTaOx, and the third bank layer (BN3) may contain copper (Cu). The bank structure (BNS) may have a MoTaOx / Cu / MoTaOx structure sequentially stacked from the inorganic insulating layer (ISL), and a tip (TIP) may be formed in the MoTaOx layer of the second bank layer (BN2). The first bank layer (BN1) is the bottom layer of the bank structure (BNS) and may serve as a base layer on which the third bank layer (BN3) is placed, by being directly disposed on the inorganic insulating layer (ISL). The third bank layer (BN3) may contain copper (Cu), which has high electrical conductivity, and may be electrically connected to the common electrodes (CE1, CE2, CE3) of the light-emitting elements (ED1, ED2, ED3). The second bank layer (BN2) is the uppermost layer of the bank structure (BNS) and may include a material with a high light absorption rate to reduce reflection caused by external light. The first bank layer (BN1) and the second bank layer (BN2) may include Mo to have a higher light absorption rate or lower reflectance than Ti, and may include TaOx to have low solubility. The bank structure (BNS) of the display device (10) may include a plurality of openings (OPE1, OPE2, OPE3) to form a space where light-emitting elements (ED1, ED2, ED3) are arranged, and at the same time, may include a material with low reflectance that is electrically connected to the light-emitting elements (ED1, ED2, ED3) to improve the visibility of the display device (10).

[0126] According to one embodiment, the bank structure (BNS) may include a tip (TIP) in which the second bank layer (BN2) protrudes inward from the side of the third bank layer (BN3) into the opening (OPE1, OPE2, OPE3). On the other hand, the first bank layer (BN1) may not protrude much from the inner side of the third bank layer (BN3). In the bank structure (BNS), the sides of the third bank layer (BN3) may have a shape that is recessed inward from the side of the second bank layer (BN2), while forming a surface that is nearly parallel to the side of the first bank layer (BN1). In the bank structure (BNS), the third bank layer (BN3) may have a thicker thickness than the first bank layer (BN1) and the second bank layer (BN2), and the first bank layer (BN1) and the second bank layer (BN2) may have a relatively thin thickness. The first bank layer (BN1) and the second bank layer (BN2) contain substantially the same material, but due to a difference in the content of the components, a tip (TIP) may be formed only in the second bank layer (BN2). As the second bank layer (BN2) has a shape that protrudes toward the openings (OPE1, OPE2, OPE3) more than the third bank layer (BN3), an undercut may be formed on the inner side wall of the openings (OPE1, OPE2, OPE3) of the bank structure (BNS) below the tip (TIP) of the second bank layer (BN2).

[0127] The sidewall shape of the bank structure (BNS) may be a structure formed due to a difference in etching speed during an etching process, wherein the first bank layer (BN1), the second bank layer (BN2), and the third bank layer (BN3) include different materials. According to one embodiment, the second bank layer (BN2) may include a material with a slower etching speed than the third bank layer (BN3), and during the process of forming the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), the third bank layer (BN3) may be further etched so that an undercut is formed on the lower part of the tip (TIP) of the second bank layer (BN2).

[0128] As described above, the third bank layer (BN3) may contain copper (Cu), and the first bank layer (BN1) and the second bank layer (BN2) may each contain MoTaOx. In the manufacturing process of the display device (10), when forming the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), the third bank layer (BN3) may be etched more than the second bank layer (BN2) to form the tip (TIP) of the second bank layer (BN2). The first bank layer (BN1) contains MoTaOx in the same way as the second bank layer (BN2), but the Ta content of the first bank layer (BN1) and the second bank layer (BN2) may be different from each other. In an exemplary embodiment, the second bank layer (BN2) may have a Ta content of 6 at% or more in MoTaOx, and the first bank layer (BN1) may have a Ta content of 2 at% or less in MoTaOx. Due to the difference in Ta content between the first bank layer (BN1) and the second bank layer (BN2), the etching rate for the same etching solution may differ. In the MoTaOx layer, as the Ta content increases, the length of the tip (TIP) formed during the etching process may differ. Since the second bank layer (BN2) has a high Ta content, a tip (TIP) protruding from the side of the third bank layer (BN3) is formed, whereas since the first bank layer (BN1) has a low Ta content, no tip may be formed. In an exemplary embodiment, the first bank layer (BN1) may have a Ta content in the range of 0.5 at% to 2 at%, and the second bank layer (BN2) may have a Ta content in the range of 6 at% to 12 at%. In an exemplary embodiment, the second bank layer (BN2) may have a Ta content in the range described above, and the width (T) of the tip (TIP) protruding from the side wall of the third bank layer (BN3) may be 0.2 μm or more. In an embodiment where the Ta content of the second bank layer (BN2) is 6 at%, the width (T) of the tip (TIP) is 0.2 μm, and the width (T) may increase as the Ta content increases.

[0129] Additionally, the first bank layer (BN1) and the second bank layer (BN2) can serve different roles as the lowest and uppermost layers of the bank structure (BNS), respectively. For example, the first bank layer (BN1) can be placed directly on the inorganic insulating layer (ISL) to maintain the adhesion of the third bank layer (BN3) containing copper (Cu). The second bank layer (BN2) can be placed on the third bank layer (BN3) to absorb external light and reduce the reflection of external light. Accordingly, the first bank layer (BN1) and the second bank layer (BN2) have different Ta contents, and in addition, their thicknesses may also differ.

[0130] In one embodiment, the thickness (TH1) of the first bank layer (BN1) may be smaller than the thickness (TH2) of the second bank layer (BN2). For example, the thickness (TH1) of the first bank layer (BN1) may be in the range of 100 Å to 200 Å, and the thickness (TH2) of the second bank layer (BN2) may be in the range of 400 Å to 600 Å. The first bank layer (BN1) may have a thin thickness so that no residue remains in the etching process due to the low Ta content. However, it may have a minimum thickness so that at least the copper (Cu) of the third bank layer (BN3) is placed in a well-bonded state. The second bank layer (BN2) may have a thickness of at least 400 Å or more to have a sufficiently low reflectance to external light. However, since the reflectivity of the second bank layer (BN2) decreases if its thickness is 600 Å or more, its thickness may be smaller than 600 Å. The third bank layer (BN3) may have a thicker thickness than the first bank layer (BN1) and the second bank layer (BN2). As described below, since the third bank layer (BN3) is electrically connected by contacting the common electrode (CE1, CE2, CE3) of the light-emitting elements (ED1, ED2, ED3), it may have low resistance and high electrical conductivity. For example, the thickness of the third bank layer (BN3) may be in the range of 4000 Å to 10000 Å, or around 6000 Å.

[0131] The bank structure (BNS) includes openings (OPE1, OPE2, OPE3) that form light-emitting regions (EA1, EA2, EA3), and a light-blocking layer (BM) may be disposed thereon. The top layer of the bank structure (BNS) may include a material with low reflectivity to reduce external light reflection. Additionally, the bank structure (BNS) may have a third bank layer (BN3) that is electrically connected to the common electrodes (CE1, CE2, CE3) of different light-emitting elements (ED1, ED2, ED3). The light-emitting elements (ED1, ED2, ED3) placed in different light-emitting regions (EA1, EA2, EA3) may not have their common electrodes (CE1, CE2, CE3) directly connected, but may be electrically connected through the third bank layer (BN3) of the bank structure (BNS).

[0132] In the manufacturing process of a display device (10), a mask process is required to form a pixel definition film that forms light-emitting regions (EA1, EA2, EA3) using an organic material, or to form light-emitting layers (EL1, EL2, EL3) of light-emitting elements (ED1, ED2, ED3) for each light-emitting region (EA1, EA2, EA3). To perform the mask process, the display device (10) may require a structure for mounting the mask, or an unnecessarily large non-display area (NDA) area may be required to control the dispersion resulting from the mask process. If this mask process is minimized, unnecessary components in the display device (10), such as a structure for mounting the mask, can be omitted, and the non-display area (NDA) area for dispersion control can be minimized.

[0133] A display device (10) according to one embodiment includes a bank structure (BNS) that forms light-emitting regions (EA1, EA2, EA3), and can be formed by deposition and etching processes rather than a mask process. Additionally, since the bank structure (BNS) includes first to third bank layers (BN1, BN2, BN3) that include different metal materials, and the inner sidewalls of the openings (OPE1, OPE2, OPE3) have a structure including a tip (TIP), it is possible to form different layers individually in different light-emitting regions (EA1, EA2, EA3) even by a deposition process. For example, even if the light-emitting layers (EL1, EL2, EL3) of the light-emitting elements (ED1, ED2, ED3) and the common electrodes (CE1, CE2, CE3) are formed by a deposition process without using a mask, the materials deposited by the tip (TIP) of the second bank layer (BN2) formed on the inner side wall of the openings (OPE1, OPE2, OPE3) may be disconnected and not connected between the openings (OPE1, OPE2, OPE3). After forming a material for forming a specific layer on the front surface of the display device (10), it is possible to form different layers individually in different light-emitting regions (EA1, EA2, EA3) through a process of etching and removing the layer formed in the unwanted region. The display device (10) can form different light-emitting elements (ED1, ED2, ED3) for each light-emitting region (EA1, EA2, EA3) through deposition and etching processes without using a mask process, and unnecessary components in the display device (10) can be omitted and the area of ​​the non-display region (NDA) can be minimized.

[0134] The light-emitting layers (EL1, EL2, EL3) can be placed on the pixel electrodes (AE1, AE2, AE3). The light-emitting layers (EL1, EL2, EL3) may be organic light-emitting layers made of organic material and may be formed on the pixel electrodes (AE1, AE2, AE3) through a deposition process. When a thin-film transistor (TFT) applies a predetermined voltage to the pixel electrode (AE1, AE2, AE3) of the light-emitting element (ED1, ED2, ED3) and the common electrode (CE1, CE2, CE3) of the light-emitting element (ED1, ED2, ED3) receives a common voltage or a cathode voltage, holes and electrons can move to the light-emitting layer (EL1, EL2, EL3) through the hole transport layer and the electron transport layer, respectively, and holes and electrons can combine with each other in the light-emitting layer (EL1, EL2, EL3) to emit light.

[0135] The light-emitting layers (EL1, EL2, EL3) may include a first light-emitting layer (EL1), a second light-emitting layer (EL2), and a third light-emitting layer (EL3) disposed in different light-emitting regions (EA1, EA2, EA3). The first light-emitting layer (EL1) may be disposed on a first pixel electrode (AE1) in the first light-emitting region (EA1), the second light-emitting layer (EL2) may be disposed on a second pixel electrode (AE2) in the second light-emitting region (EA2), and the third light-emitting layer (EL3) may be disposed on a third pixel electrode (AE3) in the third light-emitting region (EA3). The first to third light-emitting layers (EL1, EL2, EL3) may each be a light-emitting layer of a first to third light-emitting element (ED1, ED2, ED3). The first light-emitting layer (EL1) may be a light-emitting layer that emits red light of the first color, the second light-emitting layer (EL2) may be a light-emitting layer that emits green light of the second color, and the third light-emitting layer (EL3) may be a light-emitting layer that emits blue light of the third color.

[0136] According to one embodiment, a portion of the light-emitting layer (EL1, EL2, EL3) of the light-emitting element (ED1, ED2, ED3) may be disposed between the pixel electrode (AE1, AE2, AE3) and the inorganic insulating layer (ISL). The inorganic insulating layer (ISL) may be disposed on the pixel electrode (AE1, AE2, AE3) but may be spaced apart from the upper surface of the pixel electrode (AE1, AE2, AE3). The deposition process of the light-emitting layer (EL1, EL2, EL3) may be performed such that the material of the light-emitting layer is deposited in an inclined direction rather than in a direction perpendicular to the upper surface of the substrate (SUB). Accordingly, the light-emitting layers (EL1, EL2, EL3) can be positioned to fill the upper surface of the pixel electrodes (AE1, AE2, AE3) exposed to the openings (OPE1, OPE2, OPE3) of the bank structure (BNS), and the space between the pixel electrodes (AE1, AE2, AE3) and the inorganic insulating layer (ISL).

[0137] In the manufacturing process of the display device (10), a sacrificial layer ('SFL' in FIG. 8) is disposed between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3), and then a light-emitting layer (EL1, EL2, EL3) can be disposed in the area where the sacrificial layer (SFL) is partially removed. Accordingly, the bottom surface of the inorganic insulating layer (ISL) can be spaced apart from the pixel electrodes (AE1, AE2, AE3). However, the sacrificial layer (SFL) may remain as a partial residual pattern (RP) in the area between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3). The area between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3) may be filled with the partial residual pattern (RP) and the light-emitting layer (EL1, EL2, EL3).

[0138] Common electrodes (CE1, CE2, CE3) can be placed on the light-emitting layer (EL1, EL2, EL3). The common electrodes (CE1, CE2, CE3) may include a transparent conductive material so that light generated in the light-emitting layer (EL1, EL2, EL3) can be emitted. The common electrodes (CE1, CE2, CE3) can receive a common voltage or a low potential voltage. When the pixel electrodes (AE1, AE2, AE3) receive a voltage corresponding to the data voltage and the common electrodes (CE1, CE2, CE3) receive a low potential voltage, a potential difference is formed between the pixel electrodes (AE1, AE2, AE3) and the common electrodes (CE1, CE2, CE3), thereby allowing the light-emitting layer (EL1, ED2, ED3) to emit light.

[0139] In an exemplary embodiment, the common electrode (CE1, CE2, CE3) may comprise a layer of a material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The common electrode (CE1, CE2, CE3) may further comprise a transparent metal oxide layer disposed on the layer of the material with a low work function.

[0140] The common electrodes (CE1, CE2, CE3) may include a first common electrode (CE1), a second common electrode (CE2), and a third common electrode (CE3) disposed in different light-emitting regions (EA1, EA2, EA3). The first common electrode (CE1) may be disposed on a first light-emitting layer (EL1) in a first light-emitting region (EA1), the second common electrode (CE2) may be disposed on a second light-emitting layer (EL2) in a second light-emitting region (EA2), and the third common electrode (CE3) may be disposed on a third light-emitting layer (EL3) in a third light-emitting region (EA3).

[0141] According to one embodiment, a portion of the common electrode (CE1, CE2, CE3) of the light-emitting elements (ED1, ED2, ED3) may be disposed on the side of the third bank layer (BN3) of the bank structure (BNS). Similar to the light-emitting layers (EL1, EL2, EL3), the common electrode (CE1, CE2, CE3) may also be formed through a deposition process. The deposition process of the common electrode (CE1, CE2, CE3) may be performed such that the electrode material is deposited in an inclined direction rather than in a direction perpendicular to the upper surface of the substrate (SUB). Accordingly, the common electrode (CE1, CE2, CE3) may be disposed on the side of the third bank layer (BN3) below the tip (TIP) of the second bank layer (BN2) of the bank structure (BNS). The common electrode (CE1, CE2, CE3) may be in direct contact with the side of the third bank layer (BN3). The common electrodes (CE1, CE2, CE3) of different light-emitting elements (ED1, ED2, ED3) can each come into direct contact with the third bank layer (BN3) of the bank structure (BNS), and each of the common electrodes (CE1, CE2, CE3) can be electrically connected to one another. Unlike pixel electrodes (AE1, AE2, AE3), the common electrodes (CE1, CE2, CE3) can be implemented in the form of electrodes that are electrically common to the entire pixel without being separated by multiple pixels.

[0142] According to one embodiment, the contact area between the common electrodes (CE1, CE2, CE3) and the side of the third bank layer (BN3) may be larger than the contact area between the side of the light-emitting layer (EL1, EL2, EL3) and the side of the third bank layer (BN3). The common electrodes (CE1, CE2, CE3) and the light-emitting layer (EL1, EL2, EL3) are each deposited such that the material is deposited in a tilted direction rather than in a direction perpendicular to the upper surface of the substrate (SUB), and the area disposed on the side of the third bank layer (BN3) may vary depending on the tilted angle. In an exemplary embodiment, the deposition process of the common electrodes (CE1, CE2, CE3) may be performed in a more tilted direction than the deposition process of the light-emitting layer (EL1, EL2, EL3). Common electrodes (CE1, CE2, CE3) on the side walls of the openings (OPE1, OPE2, OPE3) may be positioned over a larger area than the light-emitting layers (EL1, EL2, EL3) or at a higher position from the side walls of the openings (OPE1, OPE2, OPE3). Since the common electrodes (CE1, CE2, CE3) of different light-emitting elements (ED1, ED2, ED3) are electrically connected through the third bank layer (BN3), it may be advantageous to have contact with the third bank layer (BN3) over a larger area.

[0143] A capping layer (CPL) may be disposed on common electrodes (CE1, CE2, CE3). The capping layer (CPL) may include an inorganic insulating material and cover patterns disposed on the light-emitting elements (ED1, ED2, ED3) and the bank structure (BNS). The capping layer (CPL) may prevent the light-emitting elements (ED1, ED2, ED3) from being damaged by the outside air and may prevent the patterns disposed on the bank structure (BNS) from peeling off during the manufacturing process of the display device (10). In an exemplary embodiment, the capping layer (CPL) may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0144] In the manufacturing process of the display device (10), the light-emitting layers (EL1, EL2, EL3) of each light-emitting element (ED1, ED2, ED3), the common electrode (CE1, CE2, CE3), and the capping layer (CPL) can be formed through a deposition process. Since the bank structure (BNS) includes a tip (TIP) formed in the second bank layer (BN2), even if the deposition process is performed across the entire front of the display area (DA) of the display panel (100) without using a mask, a layer of material can be formed between different openings (OPE1, OPE2, OPE3) of the bank structure (BNS). The first to third inorganic layers (TL1, TL2, TL3) formed after the common electrode (CE1, CE2, CE3) may be arranged to cover the periphery of the light-emitting region (EA1, EA2, EA3) on the bank structure (BNS), and patterns containing the same material as the light-emitting layer (EL1, EL2, EL3), the common electrode (CE1, CE2, CE3), and the capping layer (CPL) may remain on the bank structure (BNS).

[0145] According to one embodiment, the display device (10) may include first to third organic patterns (ELP1, ELP2, ELP3), first to third electrode patterns (CEP1, CEP2, CEP3), and a capping pattern (CLP) disposed on a bank structure (BNS).

[0146] A plurality of organic patterns (ELP1, ELP2, ELP3) may each be disposed on the second bank layer (BN2). The organic patterns (ELP1, ELP2, ELP3) may each include a first organic pattern (ELP1), a second organic pattern (ELP2), and a third organic pattern (ELP3) comprising the same material as the light-emitting layers (EL1, EL2, EL3) of the light-emitting elements (ED1, ED2, ED3).

[0147] The first organic pattern (ELP1) may include the same material as the first light-emitting layer (EL1) of the first light-emitting element (ED1). The second organic pattern (ELP2) may include the same material as the second light-emitting layer (EL2) of the second light-emitting element (ED2), and the third organic pattern (ELP3) may include the same material as the third light-emitting layer (EL3) of the third light-emitting element (ED3). Each of the organic patterns (ELP1, ELP2, ELP3) may be formed in the same process as the light-emitting layers (EL1, EL2, EL3) that include the same material. Each of the organic patterns (ELP1, ELP2, ELP3) may be disposed adjacent to the light-emitting regions (EA1, EA2, EA3) where each light-emitting layer (EL1, EL2, EL3) is disposed. For example, a first organic pattern (ELP1) may be placed on a second bank layer (BN2) surrounding the first opening (OPE1) in the vicinity of the first light-emitting region (EA1) or the first opening (OPE1). A second organic pattern (ELP2) may be placed on a second bank layer (BN2) surrounding the second opening (OPE2) in the vicinity of the second light-emitting region (EA2) or the second opening (OPE2), and a third organic pattern (ELP3) may be placed on a second bank layer (BN2) surrounding the third opening (OPE3) in the vicinity of the third light-emitting region (EA3) or the third opening (OPE3).

[0148] These organic patterns (ELP1, ELP2, ELP3) may be traces formed by being disconnected from the light-emitting layers (EL1, EL2, EL3) as the bank structure (BNS) includes a tip (TIP). Within the openings (OPE1, OPE2, OPE3), the light-emitting layers (EL1, EL2, EL3) are formed, and the organic patterns (ELP1, ELP2, ELP3) and the light-emitting layers (EL1, EL2, EL3) may be disconnected from each other by the tip (TIP) of the bank structure (BNS). As the light-emitting layers (EL1, EL2, EL3) are formed by a deposition process without using a mask, the materials of the light-emitting layers (EL1, EL2, EL3) can be formed entirely on the bank structure (BNS), and the organic pattern (ELP1, ELP2, ELP3) may be formed by patterning around each light-emitting region (EA1, EA2, EA3) or opening (OPE1, OPE2, OPE3).

[0149] A plurality of electrode patterns (CEP1, CEP2, CEP3) may each be disposed on a plurality of organic patterns (ELP1, ELP2, ELP3). The electrode patterns (CEP1, CPE2, CEP3) may each include a first electrode pattern (CEP1), a second electrode pattern (CEP2), and a third electrode pattern (CEP3) comprising the same material as the common electrode (CE1, CE2, CE3) of the light-emitting elements (ED1, ED2, ED3).

[0150] For example, the first electrode pattern (CEP1), the second electrode pattern (CEP2), and the third electrode pattern (CEP3) may be placed directly on the first organic pattern (ELP1), the second organic pattern (ELP2), and the third organic pattern (ELP3), respectively. The arrangement relationship between the electrode patterns (CEP1, CPE2, CEP3) and the organic patterns (ELP1, ELP2, ELP3) may be the same as the arrangement relationship between the light-emitting layers (EL1, EL2, EL3) of the light-emitting elements (ED1, ED2, ED3) and the common electrode (CE1, CE2, CE3). These electrode patterns (CEP1, CPE2, CEP3) may be traces formed where the deposited material is not connected to the common electrode (CE1, CE2, CE3) and is broken, as the bank structure (BNS) includes a tip (TIP). The display device (10) can form common electrodes (CE1, CE2, CE3) individually in different regions even in a deposition process that does not use a mask by means of the tip (TIP) of the bank structure (BNS).

[0151] A capping pattern (CLP) can be placed on electrode patterns (CEP1, CEP2, CPE3). The capping pattern (CLP) may include the same material as the capping layer (CPL) placed on the common electrode (CE1, CE2, CE3). Each of the capping patterns (CLP) may be placed directly on the first electrode pattern (CEP1), the second electrode pattern (CEP2), and the third electrode pattern (CEP3). The arrangement relationship between the capping pattern (CLP) and the electrode patterns (CEP1, CEP2, CEP3) may be the same as the arrangement relationship between the common electrode (CE1, CE2, CE3) and the capping layer (CPL) of the light-emitting elements (ED1, ED2, ED3). This capping pattern (CLP) may be a trace formed where the deposited material is disconnected from the capping layer (CPL) as the bank structure (BNS) includes a tip (TIP).

[0152] A plurality of organic patterns (ELP1, ELP2, ELP3), electrode patterns (CEP1, CPE2, CEP3), and capping pattern (CLP) are disposed on a bank structure (BNS) and may be disposed to surround the periphery of light-emitting regions (EA1, EA2, EA3) or openings (OPE1, OPE2, OPE3). The stacked structure of the plurality of organic patterns (ELP1, ELP2, ELP3), electrode patterns (CEP1, CPE2, CEP3), and capping pattern (CLP) disposed around the light-emitting regions (EA1, EA2, EA3) may be partially etched during the manufacturing process of the display device (10) so that the pattern shape may be changed. Accordingly, a portion of the upper surface of the second bank layer (BN2) of the bank structure (BNS) may not be covered by a plurality of organic patterns (ELP1, ELP2, ELP3), electrode patterns (CEP1, CPE2, CEP3), and capping pattern (CLP), and a trench portion (TP) may be formed by said patterns in this portion.

[0153] A thin film encapsulation layer (TFEL) is disposed on light-emitting elements (ED1, ED2, ED3) and a bank structure (BNS) and can cover a plurality of light-emitting elements (ED1, ED2, ED3) and a bank structure (BNS). The thin film encapsulation layer (TFEL) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). The thin film encapsulation layer (TFEL) may include at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust.

[0154] In an exemplary embodiment, the thin film encapsulation layer (TFEL) may include a first encapsulation layer (TFE1), a second encapsulation layer (TFE2), and a third encapsulation layer (TFE3) stacked sequentially. The first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) are inorganic encapsulation layers, and the second encapsulation layer (TFE2) disposed between them may be an organic encapsulation layer.

[0155] The first encapsulation layer (TFE1) and the third encapsulation layer (TFE3) may each include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0156] The second encapsulation layer (TFE2) may include a polymer-based material. Polymer-based materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. For example, the second encapsulation layer (TFE2) may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer (TFE2) may be formed by curing a monomer or by applying a polymer.

[0157] The first encapsulation layer (TFE1) may be disposed on light-emitting elements (ED1, ED2, ED3), a plurality of patterns, and a bank structure (BNS). The first encapsulation layer (TFE1) may include a first inorganic layer (TL1), a second inorganic layer (TL2), and a third inorganic layer (TL3) disposed corresponding to different light-emitting regions (EA1, EA2, EA3), respectively.

[0158] The first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) each comprise an inorganic insulating material and can cover the light-emitting elements (ED1, ED2, ED3). The first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) can prevent the light-emitting elements (ED1, ED2, ED3) from being damaged by the outside air and can prevent patterns placed on the bank structure (BNS) from peeling off during the manufacturing process of the display device (10). In an exemplary embodiment, the first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) may comprise aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0159] The first to third inorganic layers (TL1, TL2, TL3) are formed on the bank structure (BNS) and may be arranged to cover light-emitting elements (ED1, ED2, ED3) in each light-emitting region (EA1, EA2, EA3) or in the openings (OPE1, OPE2, OPE3) of the bank structure (BNS). The first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) may be placed directly on the capping layer (CPL) within each opening (OPE1, OPE2, OPE3) of the bank structure (BNS). Since the first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) may be formed via chemical vapor deposition, they may be formed with a uniform thickness along the step of the layer being deposited. For example, the first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) can form a thin film even under the undercut by the tip (TIP) of the bank structure (BNS).

[0160] In the display device (10), the first to third inorganic layers (TL1, TL2, TL3) may be seen as being placed on the same layer, but they may be formed in different processes during the manufacturing process of the display device (10). For example, the first to third light-emitting elements (ED1, ED2, ED3) may be formed in different processes, rather than each light-emitting layer (EL1, EL2, EL3) being formed simultaneously. Similarly, the first to third inorganic layers (TL1, TL2, TL3) may also be formed in different processes. In an exemplary embodiment, the first inorganic layer (TL1) may be formed after the formation of the first common electrode (CE1), the second inorganic layer (TL2) may be formed after the formation of the second common electrode (CE2), and the third inorganic layer (TL3) may be formed after the formation of the third common electrode (CE3). That is, the first inorganic layer (TL1) is formed before the second light-emitting element (ED2) and the third light-emitting element (ED3), and the second inorganic layer (TL2) can be formed before the third light-emitting element (ED3).

[0161] The first to third inorganic layers (TL1, TL2, TL3) may be partially disposed on the bank structure (BNS) around the periphery of the light-emitting region (EA1, EA2, EA3). The shape of these inorganic layers (TL1, TL2, TL3) may be formed such that the inorganic layers (TL1, TL2, TL3) completely cover the bank structure (BNS) and then partially patterned.

[0162] A first inorganic layer (TL1) may be disposed on a first light-emitting element (ED1). The first inorganic layer (TL1) may be disposed to cover the first light-emitting element (ED1) and the first opening (OPE1) along the inner sidewalls. Additionally, the first inorganic layer (TL1) may be disposed on a bank structure (BNS) to cover a first organic pattern (ELP1), a first electrode pattern (CEP1), and a capping pattern (CLP) disposed around the first opening (OPE1).

[0163] The second inorganic layer (TL2) may be disposed on the second light-emitting element (ED2). The second inorganic layer (TL2) may be disposed to cover the second light-emitting element (ED2) and the second opening (OPE2) along the inner sidewalls. Additionally, the second inorganic layer (TL2) may be disposed on the bank structure (BNS) to cover the second organic pattern (ELP2), the second electrode pattern (CEP2), and the capping pattern (CLP) disposed around the second opening (OPE2).

[0164] A third inorganic layer (TL3) may be disposed on a third light-emitting element (ED3). The third inorganic layer (TL3) may be disposed to cover the third light-emitting element (ED3) and the third opening (OPE3) along the inner sidewalls. Additionally, the third inorganic layer (TL3) may be disposed on a bank structure (BNS) to cover a third organic pattern (ELP3), a third electrode pattern (CEP3), and a capping pattern (CLP) disposed around the third opening (OPE3).

[0165] In an exemplary embodiment, the first inorganic layer (TL1), the second inorganic layer (TL2), and the third inorganic layer (TL3) may be spaced apart from each other on the bank structure (BNS). Accordingly, the second bank layer (BN2) of the bank structure (BNS) may have a portion that does not overlap with the inorganic layers (TL1, TL2, TL3) exposed and may come into direct contact with the second encapsulation layer (TFE2) of the thin film encapsulation layer (TFEL).

[0166] A touch sensing layer (TSU) may be disposed on a thin film encapsulation layer (TFEL). The touch sensing layer (TSU) may include a first touch insulating layer (SIL1), a second touch insulating layer (SIL2), a touch electrode (TEL), and a third touch insulating layer (SIL3).

[0167] The first touch insulating layer (SIL1) may be disposed on the thin film encapsulation layer (TFEL). The first touch insulating layer (SIL1) may have insulating and optical functions. The first touch insulating layer (SIL1) may include at least one inorganic film. Optionally, the first touch insulating layer (SIL1) may be omitted.

[0168] The second touch insulating layer (SIL2) may cover the first touch insulating layer (SIL1). Although not shown in the drawing, another layer of touch electrodes may be disposed on the first touch insulating layer (SIL1), and the second touch insulating layer (SIL2) may cover these touch electrodes (TEL). The second touch insulating layer (SIL2) may have insulating and optical functions. For example, the second touch insulating layer (SIL2) may be an inorganic film comprising at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0169] Some of the touch electrodes (TEL) may be disposed on the second touch insulating layer (SIL2). Each touch electrode (TEL) may not overlap with the first to third light-emitting regions (EA1, EA2, EA3). Each touch electrode (TEL) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0170] The third touch insulating layer (SIL3) may cover the touch electrode (TEL) and the second touch insulating layer (SIL2). The third touch insulating layer (SIL3) may have insulating and optical functions. The third touch insulating layer (SIL3) may be made of the material exemplified in the second touch insulating layer (SIL2).

[0171] An anti-reflective layer (RPL) may be disposed on a touch sensing layer (TSU). The anti-reflective layer (RPL) may include a light-blocking layer (BM) and a color filter layer (CFL).

[0172] A light-blocking layer (BM) may be disposed on a touch sensing layer (TSU). The light-blocking layer (BM) may include a plurality of opening holes (OPT1, OPT2, OPT3) disposed to overlap with light-emitting regions (EA1, EA2, EA3). For example, a first opening hole (OPT1) may be disposed to overlap with a first light-emitting region (EA1). A second opening hole (OPT2) may be disposed to overlap with a second light-emitting region (EA2), and a third opening hole (OPT3) may be disposed to overlap with a third light-emitting region (EA3). The area or size of each opening hole (OPT1, OPT2, OPT3) may be larger than the area or size of the light-emitting regions (EA1, EA2, EA3) defined by the bank structure (BNS). As the opening holes (OPT1, OPT2, OPT3) of the light-blocking layer (BM) are formed larger than the light-emitting regions (EA1, EA2, EA3), the light emitted from the light-emitting regions (EA1, EA2, EA3) can be seen by the user not only from the front but also from the side of the display device (10).

[0173] The light-blocking layer (BM) may include a light-absorbing material. For example, the light-blocking layer (BM) may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but is not limited thereto. The light-blocking layer (BM) can improve the color reproduction rate of the display device (10) by preventing visible light from interfering and mixing between the first to third light-emitting regions (EA1, EA2, EA3).

[0174] A plurality of color filters (CF1, CF2, CF3) may each be placed in light-emitting regions (EA1, EA2, EA3). The color filters (CF1, CF2, CF3) may be placed on a light-blocking layer (BM) comprising a plurality of opening holes (OPT1, OPT2, OPT3) that are placed corresponding to the light-emitting regions (EA1, EA2, EA3). The holes in the light-blocking layer may be formed to overlap with the openings of the light-emitting regions (EA1, EA2, EA3) or bank structures (BNS), and may form a light-emitting region from which light emitted from the light-emitting regions (EA1, EA2, EA3) is emitted. Each of the color filters (CF1, CF2, CF3) may have an area larger than the holes in the light-blocking layer (BM), and each of the color filters (CF1, CF2, CF3) may completely cover the light-emitting region formed by the holes.

[0175] Color filters (CF1, CF2, CF3) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) positioned to correspond to different light emission regions (EA1, EA2, EA3), respectively. The color filters (CF1, CF2, CF3) may include a colorant, such as a dye or pigment, that absorbs light of a wavelength other than that of a specific wavelength, and may be positioned to correspond to the color of the light emitted from the light emission regions (EA1, EA2, EA3). For example, the first color filter (CF1) may be a red color filter that is positioned to overlap with the first light emission region (EA1) and transmits only the first red light. The second color filter (CF2) is positioned to overlap with the second light-emitting region (EA2) and is a green color filter that transmits only the second green light, and the third color filter (CF3) is positioned to overlap with the third light-emitting region (EA3) and is a blue color filter that transmits only the third blue light.

[0176] Multiple color filters (CF1, CF2, CF3) may be spaced apart from each other on the light-blocking layer (BM) with adjacent other color filters (CF1, CF2, CF3). Each color filter (CF1, CF2, CF3) may have an area larger than the opening holes (OPT1, OPT2, OPT3) of the light-blocking layer (BM) and may have an area sufficient to be spaced apart from other color filters (CF1, CF2, CF3) on the light-blocking layer (BM). However, they are not limited thereto. Multiple color filters (CF1, CF2, CF3) may be arranged to partially overlap with adjacent other color filters (CF1, CF2, CF3). Different color filters (CF1, CF2, CF3) may overlap each other on the light-blocking layer (BM) in an area that does not overlap with the light-emitting region (EA1, EA2, EA3). The display device (10) can reduce the intensity of reflected light from external light by overlapping color filters (CF1, CF2, CF3). Furthermore, the color tone of reflected light from external light can be controlled by adjusting the arrangement, shape, and area of ​​the color filters (CF1, CF2, CF3) in a planar view.

[0177] Color filters (CF1, CF2, CF3) of the color filter layer (CFL) can be placed on the light-blocking layer (BM). Different color filters (CF1, CF2, CF3) can each be placed corresponding to different light-emitting regions (EA1, EA2, EA3) or openings (OPE1, OPE2, OPE3) and opening holes (OPT1, OPT2, OPT3) of the light-blocking layer (BM). For example, the first color filter (CF1) can be placed corresponding to the first light-emitting region (EA1), the second color filter (CF2) can be placed corresponding to the second light-emitting region (EA2), and the third color filter (CF3) can be placed corresponding to the third light-emitting region (EA3). A first color filter (CF1) may be placed in a first opening hole (OPT1) of a light-blocking layer (BM), a second color filter (CF2) may be placed in a second opening hole (OPT2) of a light-blocking layer (BM), and a third color filter (CF3) may be placed in a third opening hole (OPT3) of a light-blocking layer (BM). Each of the color filters (CF1, CF2, CF3) may be placed to have a larger area in a planar view than the opening holes (OPT1, OPT2, OPT3) of the light-blocking layer (BM), and some may be placed directly on the light-blocking layer (BM).

[0178] An overcoat layer (OC) is placed on color filters (CF1, CF2, CF3) to flatten the top of the color filters (CF1, CF2, CF3). The overcoat layer (OC) may be a colorless transparent layer that does not have a color in the visible light band. For example, the overcoat layer (OC) may include a colorless transparent organic material such as an acrylic resin.

[0179] Hereinafter, the manufacturing process of a display device (10) according to one embodiment will be described with reference to other drawings.

[0180] FIGS. 9 to 16 are cross-sectional views showing the display area portion in sequence during the manufacturing process of a display device according to one embodiment.

[0181] FIGS. 9 to 16 schematically illustrate the formation process of bank structures (BNS) and light-emitting elements (ED) as light-emitting element layers (EML) of a display device (10). Hereinafter, regarding the manufacturing process of the display device (10), the description of the formation process of each layer will be omitted, and the formation order of each layer will be described.

[0182] Referring to FIG. 9, a plurality of pixel electrodes (AE1, AE2, AE3), a sacrificial layer (SFL), an inorganic insulating layer (ISL), and a plurality of bank material layers (BNL1, BNL2, BNL3) are formed on a thin film transistor layer (TFTL).

[0183] Although not shown in the drawing, the thin-film transistor layer (TFTL) can be placed on the substrate (SUB), and the structure of the thin-film transistor (TFTL) is the same as described above with reference to FIG. 6. A detailed description of these is omitted.

[0184] A plurality of pixel electrodes (AE1, AE2, AE3) may be spaced apart from each other on a thin-film transistor layer (TFTL). The pixel electrodes (AE1, AE2, AE3) may include a first pixel electrode (AE1), a second pixel electrode (AE2), and a third pixel electrode (AE3) of different light-emitting elements (ED1, ED2, ED3). The first to third pixel electrodes (AE1, AE2, AE3) may be spaced apart from each other on a thin-film transistor layer (TFTL).

[0185] A sacrificial layer (SFL) may be disposed on the pixel electrodes (AE1, AE2, AE3). The sacrificial layer (SFL) may be disposed on the pixel electrodes (AE1, AE2, AE3), and then a portion of it may be removed in a subsequent process to form a space where the light-emitting layer (EL1, EL2, EL3) is disposed. The sacrificial layer (SFL) may prevent the upper surface of the pixel electrodes (AE1, AE2, AE3) and the inorganic insulating layer (ISL) from coming into contact with each other, and the sacrificial layer (SFL) may be removed to form a space between the pixel electrodes (AE1, AE2, AE3) and the inorganic insulating layer (ISL). In an exemplary embodiment, the sacrificial layer (SFL) may include an oxide semiconductor. For example, the sacrificial layer (SFL) may comprise at least one of indium-gallium-zinc oxide (IGZO), zinc-tin oxide (ZTO), indium-tin oxide (IZO), etc.

[0186] An inorganic insulating layer (ISL) and bank material layers (BNL1, BNL2, BNL3) may be disposed on the sacrificial layer (SFL). The inorganic insulating layer (ISL) is disposed to completely cover the sacrificial layer (SFL) and the thin-film transistor layer (TFTL), and a plurality of bank material layers (BNL1, BNL2, BNL3) may be disposed to completely cover the inorganic insulating layer (ISL). The bank material layers (BNL1, BNL2, BNL3) may include a first bank material layer (BNL1), a second bank material layer (BNL2), and a third bank material layer (BNL3) disposed between them. The first bank material layer (BNL1) may be disposed directly on the inorganic insulating layer (ISL), and the third bank material layer (BNL3) and the second bank material layer (BNL2) may be disposed sequentially on the first bank material layer (BNL1). The bank material layers (BNL1, BNL2, BNL3) can be partially etched in a subsequent process to form the bank layers (BN1, BN2, BN3) of the bank structure (BNS) illustrated in FIGS. 6 and 7, respectively. The first bank material layer (BNL1) and the second bank material layer (BNL2) may contain the same material, and the third bank material layer (BNL3) may contain a different metal material. Since the description of each of the bank material layers (BNL1, BNL2, BNL3) is substantially the same as the description of the bank layers (BN1, BN2, BN3) described above, a detailed description will be omitted.

[0187] Next, referring to FIG. 10, a first etching process (1) is performed to form a photoresist (PR) on bank material layers (BNL1, BNL2, BNL3) and to etch a portion of the bank material layers (BNL1, BNL2, BNL3) using the photoresist (PR) as a mask. st Perform etching and form the first hole (HOL1).

[0188] The photoresist (PR) can be spaced apart from each other on the bank material layers (BNL1, BNL2, BNL3). The photoresists (PR) can be arranged so as not to overlap with the first pixel electrode (AE1) on the second bank material layer (BNL2), and to expose the portion of the bank material layers (BNL1, BNL2, BNL3) that overlaps with the first pixel electrode (AE1).

[0189] In an exemplary embodiment, the first etching process (1 st The etching process can be performed by dry etching. The first etching process (1 st As the etching is performed as a dry etching process, bank material layers (BNL1, BNL2, BNL3) containing different materials can be etched anisotropically. In this process, the bank material layers (BNL1, BNL2, BNL3) and a portion of the inorganic insulating layer (ISL) can be etched together, and the underlying sacrificial layer (SFL) can be partially exposed. A first hole (HOL1) can be formed in an area overlapping with pixel electrodes (AE1, AE2, AE3), and the first hole (HOL1) can form openings (OPE1, OPE2, OPE3) of the bank structure (BNS).

[0190] Next, referring to FIG. 10, a second etching process (2) for removing a sacrificial layer (SFL) disposed on a first pixel electrode (AE1). nd etching) is performed. In an exemplary embodiment, the sacrificial layer (SFL) includes an oxide semiconductor layer, and a second etching process (2 ndThe etching process can be performed as a wet etching process. In this process, the inner sidewall of the first hole (HOL1) can be etched isotropically as the sacrificial layer (SFL) is removed. Among the plurality of bank material layers (BNL1, BNL2, BNL3), the third bank material layer (BNL3) may have a faster etching rate than the other bank material layers, and the second bank material layer (BNL2) may have a tip (TIP) formed that protrudes further than the side of the third bank material layer (BNL3). An undercut may be formed on the side of the third bank material layer (BNL3) below the tip (TIP) of the second bank material layer (BNL2). The first bank material layer (BNL1) may have a faster etching rate than the second bank material layer (BNL2), and may not protrude compared to the side of the third bank material layer (BNL3) and may not form a tip. The second etching process (2 nd By etching, the first hole (HOL1) can form a first opening (OPE1) or a first light-emitting region (EA1).

[0191] The sacrificial layer (SFL) may be removed in the portion exposed by the first hole (HOL1) and in the portion between the inorganic insulating layer (ISL) and the first pixel electrode (AE1). However, the sacrificial layer (SFL) may not be completely removed and may remain as a partial residual pattern (RP) between the inorganic insulating layer (ISL) and the first pixel electrode (AE1). As a portion after the sacrificial layer (SFL) is removed, a space may be formed between the first pixel electrode (AE1) and the inorganic insulating layer (ISL) disposed thereon. In a subsequent process, the first light-emitting layer (EL1) disposed on the first pixel electrode (AE1) may be formed to fill the space.

[0192] Next, referring to FIG. 12, a first light-emitting layer (EL1), a first common electrode (CE1), and a capping layer (CPL) are deposited on a first pixel electrode (AE1) to form a first light-emitting element (ED1). The first light-emitting layer (EL1) and the first common electrode (CE1) are formed within a first aperture (OPE1), and the materials forming the first light-emitting layer (EL1) and the first common electrode (CE1) in the deposition process may also be deposited on second bank material layers (BNL2) to form multiple patterns. For example, some of the materials may be deposited on the second bank material layers (BNL2) to form a first organic pattern (ELP1) and a first electrode pattern (CEP1). A portion of the capping layer (CPL) may be disposed within the first opening (OPE1) to cover the first light-emitting element (ED1), and another portion may be disposed on the second bank material layer (BNL2) to cover the first organic pattern (ELP1) and the first electrode pattern (CEP1). The description of the structure of the first light-emitting layer (EL1) and the first common electrode (CE1), and the first organic pattern (ELP1) and the first electrode pattern (CEP1) is the same as described above.

[0193] Meanwhile, the first light-emitting layer (EL1) and the first common electrode (CE1) can be formed through a deposition process. The deposition of material in the first opening (OPE1) may not be smooth due to the tip (TIP) of the second bank material layer (BNL2). However, since the materials of the first light-emitting layer (EL1) and the first common electrode (CE1) are deposited in an inclined direction rather than a direction perpendicular to the upper surface of the substrate, deposition can also be performed in the area of ​​the third bank material layer (BNL3) that is obscured by the tip (TIP).

[0194] For example, the deposition process for forming the first light-emitting layer (EL1) may be performed such that the materials are deposited in a direction not perpendicular to the upper surface of the first pixel electrode (AE1), for example, in a direction tilted at a first angle. In an exemplary embodiment, the deposition of the material in the process for forming the light-emitting layers (EL1, EL2, EL3) may be performed at an angle of 45° to 50° from the upper surface of the pixel electrodes (AE1, AE2, AE3). The first light-emitting layer (EL1) may be formed to fill the space between the first pixel electrode (AE1) and the inorganic insulating layer (ISL), and may also be formed in the area covered by the tip (TIP) of the second bank material layer (BNL2). For example, the first light-emitting layer (EL1) may be partially disposed on the side of the third bank material layer (BNL3) in the area covered by the tip (TIP).

[0195] The deposition process for forming the first common electrode (CE1) may be performed such that the materials are deposited in a direction not perpendicular to the upper surface of the first pixel electrode (AE1), for example, in a direction tilted at a second angle. In an exemplary embodiment, in the process for forming the common electrodes (CE1, CE2, CE3), the deposition of the material may be performed at an angle of 30° or less from the upper surface of the pixel electrodes (AE1, AE2, AE3). The first common electrode (CE1) may be placed on the first light-emitting layer (EL1) and may also be formed in an area obscured by the tip (TIP) of the second bank material layer (BNL2). For example, the first common electrode (CE1) may be partially placed on the side of the third bank material layer (BNL3) in an area obscured by the tip (TIP).

[0196] The deposition process for forming the common electrodes (CE1, CE2, CE3) may be performed at an angle that is relatively closer to a horizontal direction than the deposition process for forming the light-emitting layers (EL1, EL2, EL3). Accordingly, the common electrodes (CE1, CE2, CE3) may have a larger contact area with the side of the third bank material layer (BNL3) or the third bank layer (BN3) than with the light-emitting layers (EL1, EL2, EL3). Alternatively, the common electrodes (CE1, CE2, CE3) may be deposited to a higher position on the side of the third bank material layer (BNL3) or the third bank layer (BN3) than with the light-emitting layers (EL1, EL2, EL3). Different common electrodes (CE1, CE2, CE3) may be electrically connected to each other by contacting the highly conductive third bank material layer (BNL3) or the third bank layer (BN3).

[0197] Next, referring to FIG. 13, a first inorganic layer (TL1) is formed covering the first light-emitting element (ED1) and the capping layer (CPL). Unlike the light-emitting layers (EL1, EL2, EL3) and the common electrode (CE1, CE2, CE3), the first inorganic layer (TL1) can be formed by a chemical vapor deposition (CVD) process, and the first inorganic layer (TL1) can form a uniform film regardless of the step height of the deposited portion. The first inorganic layer (TL1) can be formed to completely cover the outer surface of the first light-emitting element (ED1), the bank material layers (BNL1, BNL2, BNL3), and the capping layer (CPL). In particular, the first inorganic layer (TL1) can also be deposited on the underside of the tip (TIP) of the second bank material layer (BNL2).

[0198] Next, referring to FIG. 14, a photoresist (PR) is formed on a first inorganic layer (TL1), and a third etching process (3) is performed to remove a first organic pattern (ELP1), a first electrode pattern (CEP1), a capping layer (CPL), and a portion of the first inorganic layer (TL1) disposed on bank material layers (BNL1, BNL2, BNL3). rd Performs etching.

[0199] In this process, a photoresist (PR) may be positioned to overlap with a first opening (OPE1) or a first light-emitting element (ED1). A first organic pattern (ELP1), a first electrode pattern (CEP1), a capping pattern (CLP), and a first inorganic layer (TL1) disposed on bank material layers (BNL1, BNL2, BNL3) may all be removed except around the first opening (OPE1) or the first light-emitting element (ED1). In this process, a region of the second bank material layer (BNL2) excluding the area around the first opening (OPE1) or the first light-emitting element (ED1) may be exposed. In an exemplary embodiment, a third etching process (3) for removing the first inorganic layer (TL1) disposed on bank material layers (BNL1, BNL2, BNL3). rd Etching can be performed by a dry etching process using a fluorine (F)-based etchant.

[0200] Through the above process, a first light-emitting element (ED1), a first organic pattern (ELP1), a first electrode pattern (CEP1), and a first inorganic layer (TL1) covering the capping layer (CPL) can be formed.

[0201] Referring to FIGS. 15 and 16, a second light-emitting element (ED2), a third light-emitting element (ED3), a second inorganic layer (TL2), and a third inorganic layer (TL3) can be formed by repeating processes similar to those described above.

[0202] Next, although not shown in the drawing, a second encapsulation layer (TFE2) and a third encapsulation layer (TFE3) are formed on the first encapsulation layer (TFE1) and the bank structure (BNS) to form a thin film encapsulation layer (TFEL), and a touch sensing layer (TSU), a light-blocking layer (BM), a color filter layer (CFL), and an overcoat layer (OC) are formed to manufacture a display device (10).

[0203] Hereinafter, various embodiments of the display device (10) will be described with reference to other drawings.

[0204] FIG. 17 is a cross-sectional view showing a light-emitting region of a display device according to another embodiment.

[0205] Referring to FIG. 17, a display device (10) according to one embodiment may omit the sacrificial layer. In the manufacturing process of the display device (10), the sacrificial layer (SFL) may not be placed on the pixel electrodes (AE1, AE2, AE3) of the light-emitting elements (ED1, ED2, ED3), and an inorganic insulating layer (ISL) may be placed directly. Accordingly, the inorganic insulating layer (ISL) may be placed to cover the edge portions of the pixel electrodes (AE1, AE2, AE3). The inorganic insulating layer (ISL) may come into direct contact with a portion of the upper surface of the pixel electrodes (AE1, AE2, AE3). Additionally, the space between the inorganic insulating layer (ISL) and the pixel electrodes (AE1, AE2, AE3) may disappear, and the residual pattern (RP) caused by the sacrificial layer (SFL) may not remain. In a display device (10) according to one embodiment, as the sacrificial layer is omitted, the inorganic insulating layer (ISL) is placed directly on the pixel electrodes (AE1, AE2, E3), and the material of the light-emitting layer (EL1, EL2, EL3) can be prevented from being cut by the tip formed on the inorganic insulating layer (ISL).

[0206] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0207] 1: Electronic devices 10: Display device 100: Display panel EML: Light-emitting diode layer ED: Light-emitting element BM: Shading layer CF1, CF2, CF3: Color filters BNS: Bank structure BN1, BN2, BN3: Bank layer

Claims

Claim 1 A first pixel electrode and a second pixel electrode spaced apart from each other and disposed on a substrate; an inorganic insulating layer disposed on the substrate, with a portion disposed on the first pixel electrode and the second pixel electrode; a bank structure disposed on the inorganic insulating layer and including a first opening overlapping with the first pixel electrode and a second opening overlapping with the second pixel electrode; a first light-emitting layer disposed on the first pixel electrode and a second light-emitting layer disposed on the second pixel electrode; A display device comprising a first common electrode disposed on the first light-emitting layer and a second common electrode disposed on the second light-emitting layer, wherein the bank structure comprises a first bank layer disposed directly on the inorganic insulating layer and comprising MoTaOx, a second bank layer disposed on the first bank layer and comprising MoTaOx, and a third bank layer disposed between the first bank layer and the second bank layer and comprising copper (Cu), wherein the second bank layer comprises a tip protruding from the side wall of the first opening and the second opening than the third bank layer, and the first bank layer and the second bank layer have different Ta contents in MoTaOx. Claim 2 A display device according to claim 1, wherein the first bank layer has a Ta content of 2 at% or less in MoTaOx, and the second bank layer has a Ta content of 6 at% to 12 at% in MoTaOx. Claim 3 A display device according to claim 2, wherein the first bank layer has a thickness of 200 Å or less, and the second bank layer has a thickness in the range of 400 Å to 600 Å. Claim 4 In claim 2, the third bank layer is a display device having a thickness greater than that of the first bank layer and the second bank layer. Claim 5 In claim 1, the first bank layer is a display device that does not protrude more than the third bank layer from the side walls of the first opening and the second opening. Claim 6 In claim 1, the first common electrode and the second common electrode are each in direct contact with the side of the third bank layer. Claim 7 A display device according to claim 6, wherein the first light-emitting layer and the second light-emitting layer each directly contact the side of the third bank layer, and the area of ​​the first light-emitting layer contacting the side of the third bank layer is smaller than the area of ​​the first common electrode contacting the side of the third bank layer. Claim 8 A display device according to claim 1, wherein the inorganic insulating layer does not contact the upper surfaces of the first pixel electrode and the second pixel electrode, respectively, and a portion of the first light-emitting layer is disposed between the first pixel electrode and the inorganic insulating layer, and a portion of the second light-emitting layer is disposed between the second pixel electrode and the inorganic insulating layer. Claim 9 A display device according to claim 8, further comprising a residual pattern disposed between the first pixel electrode and the second pixel electrode and the inorganic insulating layer. Claim 10 A display device according to claim 1, wherein the inorganic insulating layer is disposed to be in direct contact with a portion of the upper surface of the first pixel electrode and the second pixel electrode, and a portion of the first light-emitting layer and the second light-emitting layer are each disposed directly on the inorganic insulating layer. Claim 11 A display device according to claim 1, further comprising: a first organic pattern disposed on the second bank layer surrounding the first opening and comprising the same material as the first light-emitting layer; a first electrode pattern disposed on the first organic pattern and comprising the same material as the first common electrode; a second organic pattern disposed on the second bank layer surrounding the second opening and comprising the same material as the second light-emitting layer; and a second electrode pattern disposed on the second organic pattern and comprising the same material as the second common electrode. Claim 12 A display device according to claim 11, further comprising: a first inorganic layer disposed on the side wall of the first opening and disposed on the first common electrode and the first electrode pattern; and a second inorganic layer disposed on the side wall of the second opening and disposed on the second common electrode and the second electrode pattern, wherein the first inorganic layer and the second inorganic layer are disposed spaced apart from each other, and a portion of the second bank layer does not overlap with the first inorganic layer and the second inorganic layer. Claim 13 A display device according to claim 1, further comprising a thin film encapsulation layer disposed on the bank structure, wherein the thin film encapsulation layer comprises a first encapsulation layer; a second encapsulation layer disposed on the first encapsulation layer; and a third encapsulation layer disposed on the second encapsulation layer. Claim 14 A display device according to claim 13, further comprising: a light-blocking layer disposed on the third encapsulation layer and including a plurality of opening holes that overlap with the first opening and the second opening; and a first color filter disposed on the light-blocking layer that overlaps with the first opening and a second color filter that overlaps with the second opening. Claim 15 A step of forming a plurality of pixel electrodes spaced apart from each other on a substrate, a sacrificial layer disposed on the pixel electrodes, an inorganic insulating layer disposed on the sacrificial layer, a first bank material layer and a second bank material layer disposed on the inorganic insulating layer, and a third bank material layer disposed between the first bank material layer and the second bank material layer; a step of forming a first hole that overlaps with the pixel electrodes and penetrates the first bank material layer, the second bank material layer, and the third bank material layer to expose the sacrificial layer disposed on the pixel electrodes; a step of wet-etching the sidewalls of the sacrificial layer and the first hole to remove the sacrificial layer and forming a tip in which the second bank material layer protrudes beyond the sidewalls of the third bank material layer; a step of forming a light-emitting layer and a common electrode on the pixel electrodes within a first opening formed by wet-etching the first hole, and forming an inorganic layer on the common electrode and the second bank material layer; A method for manufacturing a display device comprising the step of removing a portion of the inorganic layer disposed on the second bank material layer, wherein the first bank material layer and the second bank material layer each comprise MoTaOx but have different Ta contents, and the third bank material layer comprises copper (Cu). Claim 16 A method for manufacturing a display device according to claim 15, wherein the first bank material layer has a Ta content of 2 at% or less in MoTaOx, and the second bank material layer has a Ta content of 6 at% to 12 at% in MoTaOx. Claim 17 A method for manufacturing a display device according to claim 16, wherein the first bank material layer has a thickness of 200 Å or less, and the second bank material layer has a thickness in the range of 400 Å to 600 Å. Claim 18 A method for manufacturing a display device according to claim 15, wherein, in the step of wet-etching the sidewall of the first hole, a portion of the first bank material layer is etched so as not to protrude from the sidewall of the third bank material layer. Claim 19 A method for manufacturing a display device according to claim 15, wherein the common electrode and the light-emitting layer each contact the sidewall of the third bank material layer, and the area where the common electrode contacts the third bank material layer is larger than the area where the light-emitting layer contacts the third bank material layer. Claim 20 A method for manufacturing a display device according to claim 15, wherein, in the step of forming the light-emitting layer and the common electrode, an organic pattern including the same material as the light-emitting layer and an electrode pattern including the same material as the common electrode are formed on the second bank material layer, and the inorganic layer is disposed on the electrode pattern.

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