Superconducting quantum qubit device and manufacturing method thereof

Abstract

The present invention comprises the steps of: forming a superconducting qubit layer by implementing a superconducting qubit and superconducting wiring on a first substrate; forming an interconnect layer including DC and RF routing circuits by alternately and repeatedly implementing a superconducting wiring and an insulating film on a second substrate; forming a mask pattern layer on a silicon substrate and forming a via pattern on the silicon substrate using the mask pattern layer as an etching mask, then removing the mask pattern layer and forming an oxide film on the silicon substrate and the via pattern; bonding the silicon substrate upside down onto the interconnect layer, polishing the back surface of the silicon substrate to expose the via pattern to form via holes in the silicon substrate, and removing the oxide film and the insulating film on the interconnect layer exposed in the via holes; and depositing a superconducting metal layer on the total surface of the silicon substrate and the via holes so that the superconducting metal layer contacts the DC and RF routing circuits, wherein the superconducting metal layer formed on the back surface of the silicon substrate The technical gist of the invention is a method for manufacturing a superconducting quantum qubit device and a superconducting quantum qubit device manufactured thereby, comprising the steps of: forming an interposer layer by patterning to form a resonator and a connection line; and upside down the superconducting qubit layer and bonding it to the interposer layer using an indium bumper.

Description

Technology Field

[0001] The present invention relates to a quantum qubit device and a method for manufacturing the same, and in particular to a superconducting quantum qubit structure, and to a three-dimensional superconducting quantum qubit device and a method for manufacturing the same for realizing a quantum computer with a commercialization level of integration. Background Technology

[0002] In order for a quantum computer to achieve quantum supremacy—that is, to reach a practical level where it can perform calculations impossible for classical von Neumann computers—at least hundreds to thousands of qubits must be integrated. In fact, some companies have presented roadmaps to achieve 1,121 qubits by 2023 and are planning for a one-million-qubit Quantum Process Unit (QPU) in the long term.

[0003] In the case of the most technologically advanced superconducting qubits currently available, integration densities of over 100 have been reported. In the case of superconducting qubits, the size, or footprint, of the qubit is hundreds of micros x hundreds of micros, which is incomparably larger than that of conventional semiconductor devices.

[0004] In addition, microwaves at the 3–10 GHz level are used to control qubits and perform computational operations through quantum logic gates or to read out the results. The components required for this, such as co-planar waveguides (CPWs) and resonators, are several millimeters in length or larger. For example, since the wavelength of a typical 5 GHz frequency reaches about 60 mm in free space, even if the resonator is designed with λ / 2 or λ / 4, a size of several millimeters or larger cannot be avoided.

[0005] Furthermore, signals entering or exiting the qubits are transmitted to the qubits via a resonator through bond pads configured at the chip's perimeter; however, since the resonator is very large compared to the qubits, increasing the number of qubits also entails the problem of difficulty in connecting the data bus to the qubits located inside the chip.

[0006] In particular, as the number of qubits increases, many interconnections between qubits are required not only to control the qubits but also to utilize entanglement, and the structural degrees of freedom that enable this decrease rapidly. Of course, for superior quantum computer performance, the connections between qubits must be as numerous as possible.

[0007] Furthermore, since the signals transmitted to the qubits are microwaves, as the data bus becomes denser and more complex, not only does crosstalk occur between signals, but it also negatively affects the qubit's coherence time.

[0008] In addition, the dielectric substrate contains electromagnetic waves of the fundamental mode having the frequency of the following equation. If the x and y values, that is, the size of the chip, become too large, a problem arises in which the frequency of the fundamental mode overlaps with the frequency band (3~8GHz) that controls the qubit, and this effectively becomes a factor that limits the size of the chip.

[0009]

[0010] c: Speed ​​of light in free space

[0011] ε r Dielectric constant

[0012] x, y: chip size

[0013] Due to the aforementioned problems, it is not possible to implement a QPU of hundreds to thousands of qubits or more using a planar architecture where all components are placed on the same plane, and therefore, there is a growing demand for a 3D architecture to overcome this.

[0014] One method proposed to implement this is a structure utilizing superconducting Through Silicon Via (TSV). This structure implements a qubit layer, a TSV interposer and resonator layer, and a wiring layer on each substrate, with each layer connected using an indium bumper. Electrical signals between the layers are transmitted through the TSV interposer.

[0015] FIG. 1 shows a three-dimensional superconducting quantum qubit and circuit element using an interposer layer (30) fabricated with conventional TSV technology. First, a superconducting qubit layer (10) equipped with a superconducting qubit and superconducting wiring (connecting circuit) (12), and an interconnect layer (20) equipped with one or more layers of superconducting wiring and insulating film for DC and RF routing circuits (22) are connected to each other through the superconducting TSV interposer layer (30) and integrated in three dimensions. The superconducting TSV interposer layer (30) may be equipped with a connection line (circuit) (32), such as a resonator for applying a microwave signal to the qubit to control the qubit, that is, to perform quantum logic operations, and wiring for readout.

[0016] Here, the connection between the qubit and the resonator utilizes capacitive coupling, so direct contact is not required, and the mechanical and electrical connection between the qubit plane and the resonator plane is bonded using an indium bumper, a superconducting metal. The superconducting TSV interposer layer (30) and the interconnect layer (20) are also mechanically and electrically connected by bonding using an indium bumper (40). In other words, two indium bumper (40) bondings are required.

[0017] Meanwhile, in the field of Si CMOS technology, TSV technology is a technology developed for three-dimensional integration and is typically fabricated in the following steps.

[0018] - Via formation: Reactive Ion Etching or Laser Drilling

[0019] - Dielectric Deposition: Forming a SiO2 or Si3N4 liner that acts as a diffusion barrier between Cu and Si via thermal evaporation or PECVD.

[0020] - Adhesion & Seed Layer Deposition: Ti / Cu deposition by PVD

[0021] - Cu Electroplating: Stress relief through heat treatment after filling vias with Cu

[0022] - Remove overburden Cu with CMP

[0023] - TSV Reveal: Via exposure by grinding / polishing or wet etching

[0024] However, for the following reasons, TSV technology typically used in CMOS is difficult to apply as is.

[0025] - Dielectric liners such as SiO2 and Si3N4 (Dielectric liners cause dielectric loss in microwaves, thereby reducing coherence time)

[0026] Superconducting metals must be used instead of Cu. While electroplating is difficult when using Al, the PVD process for producing high-quality superconducting Al is too slow to fill vias and causes stress. Additionally, since it is used at cryogenic temperatures, the difference in thermal expansion coefficients between the metal and Si is also important.

[0027] - Residues from the CMP process contaminate the insulating Si substrate or act as dopants, reducing the coherence time of qubits.

[0029] Therefore, in order to apply TSV technology to a superconducting quantum QPU structure, it is necessary to develop new TSV technology that is compatible with the QPU.

[0030] In addition, there is a need to develop an interposer process that does not degrade the characteristics of the qubits, and two indium bumpers are used to mechanically and electrically connect the three layers, but as the TSV line density increases, alignment between them becomes difficult and the process becomes complex. Prior art literature

[0031] US20180013052A1“Qubit and Coupler Circuit Structures and Coupling Techniques” The problem to be solved

[0032] The present invention aims to solve the above problems by first bonding an interposer with a via pattern to a DC and RF routing interconnect layer using wafer bonding, then forming an interposer layer, and connecting it through indium bumper bonding, thereby providing a superconducting quantum qubit device with a three-dimensional structure. means of solving the problem

[0033] To achieve the above objective, the present invention comprises the steps of: forming a superconducting qubit layer by implementing a superconducting qubit and superconducting wiring on a first substrate; forming an interconnect layer including DC and RF routing circuits by alternately and repeatedly implementing a superconducting wiring and an insulating film on a second substrate; forming a mask pattern layer on a silicon substrate and forming a via pattern on the silicon substrate using the mask pattern layer as an etching mask, then removing the mask pattern layer and forming an oxide film on the silicon substrate and the via pattern; bonding the silicon substrate upside down onto the interconnect layer, polishing the back surface of the silicon substrate to expose the via pattern to form via holes in the silicon substrate, and removing the oxide film and the insulating film on the interconnect layer exposed in the via holes; depositing a superconducting metal layer on the total surface of the silicon substrate and the via holes so that the superconducting metal layer contacts the DC and RF routing circuits, and the superconducting formed on the back surface of the silicon substrate The technical gist of the invention is a method for manufacturing a superconducting quantum qubit device, comprising the steps of: patterning a metal layer to form resonators and connection lines to form an interposer layer; and flipping the superconducting qubit layer upside down and bonding it to the interposer layer using an indium bumper.

[0034] In addition, the present invention provides another technical feature of a superconducting quantum qubit device comprising: a first substrate; a superconducting qubit layer including a superconducting qubit and superconducting wiring formed on the first substrate; a second substrate; an interconnect layer including DC and RF routing circuits formed by alternately and repeatedly forming superconducting wiring and an insulating film on the second substrate; a silicon interposer layer including a resonator and a connection line formed by patterning the superconducting metal layer, wherein a silicon substrate having a via pattern is inverted and bonded to the interconnect layer, and the via pattern is exposed to form a via hole, and a superconducting metal layer is deposited on the front surface of the via hole and the silicon substrate, so as to be in contact with the superconducting metal layer and the DC and RF routing circuits, and wherein the superconducting qubit layer and the silicon interposer layer are bonded to the silicon interposer layer using an indium bumper.

[0035] In addition, it is preferable that the interconnect layer and the interposer layer be bonded as oxide film to oxide film.

[0036] In addition, it is preferable that the first substrate and the second substrate are formed from any one of high-resistance Si, sapphire, and alumina (Al2O3).

[0037] In addition, the superconducting metal is preferably at least one of Al, TiN, Nb, Ta, and V.

[0038] In addition, the insulating film included in the interconnect layer is an oxide film or a nitride film, and it is preferable that the top insulating film be formed of a silicon oxide film.

[0039] In addition, the depth of the via pattern is preferably 1 to 300 μm, or 50 to 200 μm.

[0040] In addition, the above qubit is preferably one of a Charge Qubit, a Flux Qubit, or a Phase Qubit that includes at least one Josephson element.

[0041] In addition, the resonator formed in the interposer layer preferably has a length of 1 / 4, 1 / 2, or an integer multiple thereof of the wavelength corresponding to the microwave frequency used.

[0042] In addition, it is preferable that the superconducting qubit and the resonator are capacitively coupled without the superconducting metal being in direct contact.

[0043] In addition, it is preferable that the superconducting qubit layer and the interposer layer are electrically and mechanically connected by one or more indium bumpers.

[0044] In addition, the oxide film formed on the silicon substrate is preferably formed by depositing an oxide film on the silicon substrate or by performing heat treatment in an oxygen atmosphere. Effects of the invention

[0046] The present invention provides a superconducting quantum qubit device of a three-dimensional structure by first bonding an interposer with a via pattern to a DC and RF routing interconnect layer using wafer bonding, exposing via holes, forming an interposer layer with resonators and connection lines formed by the deposition and patterning of a superconducting metal layer, and connecting the interposer layer through indium bumper bonding.

[0047] In a conventional TSV interposer fabrication process, via holes that completely penetrate the substrate are fabricated and filled with metal, and then the substrate on the opposite side of the via holes is partially removed using a CMP process to allow the via holes to penetrate the substrate. At this time, the process is carried out by temporarily bonding the substrate to another substrate for handling.

[0048] On the other hand, the technology proposed in the present invention involves fabricating via holes that do not completely penetrate the substrate, bonding them to DC and RF routing interconnect layers using wafer bonding, and then etching the residual insulating film and depositing a superconducting metal layer. This eliminates the need for a handling substrate, excludes the use of indium bumpers, and allows for a simple process and precise alignment by directly electrically connecting to the superconducting metal formed on the DC and RF routing interconnect layers. Brief explanation of the drawing

[0049] Fig. 1 - A figure showing a three-dimensional superconducting quantum qubit and circuit element using an interposer fabricated with conventional TSV technology. FIG. 2 - Schematic cross-sectional view of a superconducting qubit layer according to an embodiment of the present invention. FIG. 3 - Schematic cross-sectional view of a DC and RF routing interconnect layer according to an embodiment of the present invention. FIG. 4 - Schematic diagram of a process for forming via patterns and oxide films on a silicon substrate to utilize wafer bonding technology according to an embodiment of the present invention. FIG. 5 - Schematic diagram of a process for forming a silicon interposer layer by bonding a silicon substrate fabricated using wafer bonding technology according to an embodiment of the present invention to an interconnect layer, and then forming a superconducting resonator and a connection line. FIG. 6 - Schematic diagram of a three-dimensional superconducting quantum qubit device implemented by bonding a silicon interposer layer and a superconducting qubit layer by an indium bumper according to an embodiment of the present invention. Specific details for implementing the invention

[0050] The present invention provides a superconducting quantum qubit device of a three-dimensional structure by first bonding an interposer with a via pattern to a DC and RF routing interconnect layer using wafer bonding, exposing via holes, forming an interposer layer with resonators and connection lines formed by the deposition and patterning of a superconducting metal layer, and connecting the interposer layer through indium bumper bonding.

[0051] In a conventional TSV interposer fabrication process, via holes that completely penetrate the substrate are fabricated and filled with metal, and then the substrate on the opposite side of the via holes is partially removed using a CMP process to allow the via holes to penetrate the substrate. At this time, the process is carried out by temporarily bonding the substrate to another substrate for handling.

[0052] On the other hand, the technology proposed in the present invention involves fabricating via holes that do not completely penetrate the substrate, bonding them to DC and RF routing interconnect layers using wafer bonding, and then etching the residual insulating film and depositing a superconducting metal layer. This eliminates the need for a handling substrate, excludes the use of indium bumpers, and allows for a simple process and precise alignment by directly electrically connecting to the superconducting metal formed on the DC and RF routing interconnect layers.

[0054] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings.

[0055] FIG. 2 is a schematic cross-sectional view of a superconducting qubit layer according to an embodiment of the present invention, FIG. 3 is a schematic cross-sectional view of a DC and RF routing interconnect layer according to an embodiment of the present invention, FIG. 4 is a schematic diagram of a process for forming via patterns and oxide films on a silicon substrate to utilize wafer bonding technology according to an embodiment of the present invention, FIG. 5 is a schematic diagram of a process for forming a silicon interposer layer by bonding a silicon substrate fabricated using wafer bonding technology according to an embodiment of the present invention to an interconnect layer, and then forming a superconducting resonator and connection lines, FIG. 6 is a schematic diagram of a superconducting quantum qubit device with a three-dimensional structure in which a silicon interposer layer and a superconducting qubit layer are bonded by an indium bumper according to an embodiment of the present invention.

[0056] A method for manufacturing a superconducting quantum qubit device according to an embodiment of the present invention comprises the steps of: forming a superconducting qubit layer (100) by implementing a superconducting qubit and a superconducting wiring (140) on a first substrate (120); alternately and repeatedly implementing a superconducting wiring (240) and an insulating film (260) on a second substrate (220) to form an interconnect layer (200) including DC and RF routing circuits; forming a mask pattern layer (340) on a silicon substrate (300), and using the mask pattern layer (340) as an etching mask to form a via pattern (360) on the silicon substrate (300), then removing the mask pattern layer (340) and forming an oxide film (380) on the silicon substrate (300) and the via pattern (360); and bonding the silicon substrate (300) upside down onto the interconnect layer (200), and the silicon The method is characterized by comprising the steps of: polishing the back surface of a substrate (300) to expose the via pattern (360) to form a via hole (420) in the silicon substrate (300); removing the insulating film (260) on the interconnect layer (200) exposed to the oxide film and the via hole (420); depositing a superconducting metal layer (440) on the total surface of the silicon substrate (300) and the via hole (420) so that the superconducting metal layer (440) contacts the DC and RF routing circuits; patterning the superconducting metal layer (440) formed on the back surface of the silicon substrate (300) to form a resonator and a connection line (460) to form an interposer layer (400); and flipping the superconducting qubit layer (100) upside down and bonding it to the interposer layer (400) using an indium bumper (500). does.

[0057] First, as shown in FIG. 2, a superconducting qubit layer (100) is formed by implementing a superconducting qubit and superconducting wiring (140) on a first substrate (120).

[0058] That is, a superconducting metal layer (440) for forming a superconducting qubit and the necessary superconducting wiring (140) is deposited on a first substrate (120), and a superconducting qubit layer (100) is formed by patterning the same.

[0059] In one embodiment of the present invention, the superconducting qubit may include one or more Josephson elements and a capacitance, inductor, or superconducting loop, but is not limited thereto.

[0060] In addition, the superconducting qubit may be any one of a Charge Qubit, Flux Qubit, or Phase Qubit, which includes at least one Josephson element.

[0061] The superconducting wiring required above may vary depending on the type of superconducting qubit, i.e., the mode of operation, but since this is irrelevant to the concept of the present invention, a detailed description is not provided.

[0063] Then, as shown in FIG. 3, superconducting wiring (240) and insulating film (260) are alternately and repeatedly implemented on the second substrate (220) to form an interconnect layer (200) including DC and RF routing circuits.

[0064] A superconducting metal layer is formed on the second substrate (220) and superconducting wiring (240) is formed by patterning the same, and an insulating film (260) is deposited on the upper portion and flattened using a CMP process or the like, and then the process of forming superconducting wiring (240) by the deposition and patterning process of the superconducting metal layer and depositing the insulating film (260) is repeated as many times as necessary to complete an interconnect layer (200) including a multilayer DC and RF routing circuit.

[0065] The superconducting wiring (240) uses a superconducting metal, and a metal with a superconducting critical temperature higher than the operating temperature of a superconducting qubit (tens of mK) can be used. Specifically, various metals such as Al, TiN, Nb, Ta, and V can be used. However, when using Al, the thermal budget for subsequent processes must be considered to be limited to about 400°C, and considering this, a metal with a melting point higher than Al is preferably preferred.

[0066] In addition, the insulating film (260) can use various oxide-based or nitride-based materials, but an oxide film (SiO2) can be used considering that oxide-to-oxide bonding (SiO2-SiO2) is easy when bonding with the subsequent interconnect layer (200).

[0067] The first substrate (120) and the second substrate (220) used when fabricating the superconducting qubit layer (100) and the DC and RF routing interconnect layer (200) may be of the same or different type of substrate, and are not particularly limited when composed of a material with low dielectric loss, but can typically be formed from any one of high resistance Si, sapphire, and alumina (Al2O3).

[0069] Then, as shown in FIG. 4, a mask pattern layer (340) is formed on a silicon substrate (300), and a via pattern (360) is formed on the silicon substrate (300) using the mask pattern layer (340) as an etching mask, and then the mask pattern layer (340) is removed and an oxide film (380) is formed on the silicon substrate (300) and the via pattern (360).

[0070] A mask layer (320) is formed on a silicon substrate (300), and a mask pattern layer (340) is formed by patterning the mask layer (340). After forming a via pattern (360) on the silicon substrate (300) using the mask pattern layer (340) as an etching mask, the mask layer (320) is removed, and an oxide film (380) is formed on the silicon substrate (300) and the via pattern (360).

[0071] First, a mask layer (320) is formed on a high-resistance silicon substrate (300), and a mask pattern layer (340) is formed by patterning the mask layer (340). Using the mask pattern layer (340) as an etching mask, the silicon substrate (300) is etched to a required depth using a dry etching process. The depth of the via pattern (360) can be set from 1 to 300 μm, but typically a range of 50 to 200 μm is preferred.

[0072] In addition, this process describes a conventional technique, and when using a different process, it may proceed with a different process. For example, the via pattern (360) to be etched can be formed by laser drilling.

[0073] Then, the mask pattern layer (340) is removed, and an oxide film (380) is formed on the silicon substrate (300) and via pattern (360). At this time, the method of forming the oxide film (380) is not limited, but considering the convenience of the process and the quality of the oxide film, a method of Si oxidation by heat treatment is preferred.

[0074] At this time, the method for forming the oxide film may involve performing heat treatment in an oxygen atmosphere to form a natural silicon oxide film, but is not limited thereto; however, considering the convenience of the process and the quality of the oxide film, an oxidation method by heat treatment is preferable.

[0076] Then, as shown in FIG. 5, the silicon substrate (300) is upside down and bonded onto the interconnect layer (200). At this time, the bonding is performed using a conventional wafer bonding technique in which the surfaces of the two layers are cleaned, brought into contact, and then heat-treated to bond. Bonding is particularly easy when the surfaces of the two layers are oxides. Therefore, it is preferable to form an oxide film on the silicon substrate (300) and to form an insulating film (260) formed on the interconnect layer (200), particularly the top insulating film, as an oxide film, and in one embodiment of the present invention, a silicon oxide film (SiO2) is formed.

[0077] Then, the back surface (top surface in the drawing) of the silicon substrate (300) is polished to expose the via pattern (360) to form a via hole (420) on the silicon substrate (300), and the insulating film (260) on the interconnect layer (200) exposed to the oxide film and the via hole (420) is removed.

[0078] That is, after bonding, the back surface of the silicon substrate (300) is partially removed through a CMP process to expose the via pattern (360) and form a via hole (420). Then, the oxide film is removed, and at this time, not only the oxide film on the wall of the via hole (420) but also the oxide film (insulating film (260)) covering the superconducting wiring (240) to be electrically connected to the via hole (420) in the DC and RF routing interconnect layer (200) is removed.

[0079] Then, a superconducting metal layer (440) is deposited on the front surface of the silicon substrate (300) and via hole (420) so that the superconducting metal layer (440) and the DC and RF routing circuits come into contact, and the superconducting metal layer (440) formed on the back surface of the silicon substrate (300) is patterned to form a resonator and a connection line (460) to form an interposer layer (400).

[0080] The types of superconducting metals used at this time include Al, TiN, Nb, Ta, and V, but are not limited to these. However, considering the step coverage of the deposition process, TiN would be preferable.

[0081] Meanwhile, when fabricating superconducting qubits in three dimensions, the reason for using an interposer instead of directly connecting, for example, DC and RF routing interconnect layers to the superconducting qubit layer is that direct connection would severely degrade the characteristics of the superconducting qubit.

[0082] In other words, as described above, the process of fabricating interconnect layers is similar to the BEOL process used in conventional CMOS technology, in which a multilayer wiring is completed by repeating the process of forming metal wiring, depositing an insulating film (typically an oxide) to provide insulation, and then forming metal wiring again on top of it. However, if this surface is directly connected to a superconducting qubit layer and an indium bumper and brought close together, dielectric loss occurs, which severely damages the characteristics of the qubit; therefore, an interposer is used to block this.

[0084] Then, by flipping the superconducting qubit layer (100) upside down and bonding it with the interposer layer (400) using an indium bumper (500), a superconducting quantum qubit device is completed as shown in FIG. 6.

[0085] The superconducting qubit layer (100) is electrically and mechanically connected to the interposer layer (400) by one or more indium bumpers (500).

[0086] At this time, because an indium bumper (500) is used, the superconducting qubit (140) and the resonator have a gap of about a few micrometers, and the connection between the two components is made by capacitively coupled without the superconducting metal coming into direct contact.

[0087] In addition, the resonator formed in the interposer layer (400) preferably has a length of 1 / 4, 1 / 2, or an integer multiple thereof of the wavelength corresponding to the microwave frequency used. The present invention can provide a compact superconducting quantum qubit device even if the resonator is designed to be λ / 4, λ / 2, or an integer multiple.

[0089] Meanwhile, a superconducting quantum qubit device fabricated according to an embodiment of the present invention comprises: a first substrate (120); a superconducting qubit layer (100) including a superconducting qubit and superconducting wiring (140) formed on the first substrate (120); a second substrate (220); and an interconnect layer (200) including DC and RF routing circuits formed by alternately and repeatedly forming superconducting wiring (240) and an insulating film (260) on the second substrate (220); and a silicon substrate (300) having a via pattern (360) formed thereon, which is then inverted and bonded to the interconnect layer (200), and the via pattern (360) is exposed to form a via hole (420); and a superconducting metal layer (440) is deposited on the front surface of the via hole (420) and the silicon substrate (300), and the superconducting metal layer (440) and the DC and RF routing circuits are formed. The invention includes a silicon interposer layer (400) that is in contact with the circuit and includes a resonator and a connection line (460) formed by patterning the superconducting metal layer (440), and the superconducting qubit layer (100) and the silicon interposer layer (400) are bonded to the silicon interposer layer (400) using an indium bumper (500).

[0090] Accordingly, the superconducting quantum qubit device according to an embodiment of the present invention forms a superconducting qubit and superconducting wiring (140) for controlling the same on a superconducting qubit layer (100) to perform operations such as a quantum logic gate, and readout is performed through a resonator (460) provided on the upper part of an interposer layer (400), and the DC signal and microwave signal controlling it are transmitted through a DC and RF routing interconnect layer (200). In addition, a resonator bus for entanglement between qubits can be provided on an interposer layer (400) in which a via hole (420) is formed by exposing a via pattern (360) by wafer bonding.

[0091] In addition, the reason for using an interposer instead of directly connecting, for example, the DC and RF routing interconnect layer (200) to the superconducting qubit layer (100) when fabricating a superconducting qubit in three dimensions according to the present invention is that the characteristics of the superconducting qubit are severely degraded when directly connected. The process of fabricating the interconnect layer (200) involves alternately and repeatedly implementing superconducting wiring (240) and an insulating film (260) on a second substrate (220) to complete multilayer wiring. However, if this surface is connected and brought close to the superconducting qubit layer (100) through an indium bumper (500) as is, dielectric loss occurs, causing severe damage to the characteristics of the qubit; therefore, an interposer is used to block this.

[0092] In order to overcome the problem of dielectric loss as described above, unlike the prior art, the conventional TSV interposer fabrication process involves fabricating via holes that completely penetrate the substrate and filling them with metal, and then partially removing the substrate opposite the via holes through a CMP process so that the via holes penetrate the substrate. At this time, the process is carried out by temporarily bonding the substrate to another substrate to handle the substrate.

[0093] According to an embodiment of the present invention, instead of a process penetrating tens to hundreds of micrometers, a process penetrating silicon with a thickness of several to tens of micrometers is used. This allows all problems cited as issues in the existing TSV process, such as the problem caused by the difference in the coefficient of thermal expansion between the superconducting metal penetrating the via and the substrate, and the problem of reduced coherence time of the qubit due to CMP residue, to be overcome, so there is no need to develop a complex process to bypass the problems of the existing TSV process.

[0094] In addition, according to an embodiment of the present invention, after oxide-to-oxide bonding is performed between a silicon substrate having a via pattern and a DC and RF routing interconnect layer, a superconducting metal layer is deposited by exposing via holes, and a resonator and a necessary superconducting connection line are provided on the interposer layer, and alignment is performed with the circuit of the interconnect layer, thereby solving the alignment error problem using an indium bumper as in the prior art.

[0095] In other words, the present invention provides a method for implementing three-dimensional integration of qubits, which is unavoidable for implementing a quantum computer with commercial-level integration density, while minimizing the reduction of qubit coherence time and providing ease of process compared to the method using a conventional TSV interposer.

[0096] In addition, the indium bumper process, which is used twice in existing technology, is reduced to once, and the complex wiring connection between the interposer layer and the interconnect is replaced by a conventional patterning process instead of the indium bumper process, which has the advantage of enabling precise connection. Explanation of the symbols

[0097] 10: Superconducting qubit layer 12: Superconducting qubit or / and superconducting wiring 20: Interconnect Layer 22: DC and RF Routing Circuits 30 : Interposer layer fabricated using TSV technology 32: Resonator or / and connecting line 40: Indium bumper 100: Superconducting qubit layer 120: First substrate 140: Superconducting qubit or / and superconducting wiring 200: Interconnect layer 220: Second substrate 240: Superconducting wiring (DC and RF routing circuits) 260 : Insulating film 300 : Silicon substrate 320 : Mask layer 340 : Mask pattern layer 360: Via pattern 380: Oxide film 400 : Interposer Layer 420 : Via Hole 440: Superconducting metal layer 460: Resonator or / and connecting line 500 : Indium Bumper

Claims

Claim 1 A step of forming a superconducting qubit layer by implementing superconducting qubits and superconducting wiring on a first substrate; a step of forming an interconnect layer including DC and RF routing circuits by alternately and repeatedly implementing superconducting wiring and an insulating film on a second substrate; a step of forming a mask pattern layer on a silicon substrate, forming a via pattern on the silicon substrate using the mask pattern layer as an etching mask, removing the mask pattern layer, and forming an oxide film on the silicon substrate and the via pattern; a step of bonding the silicon substrate upside down onto the interconnect layer, polishing the back side of the silicon substrate to expose the via pattern to form via holes in the silicon substrate, and removing the oxide film and the insulating film on the interconnect layer exposed in the via holes; a step of depositing a superconducting metal layer on the total surface of the silicon substrate and the via holes so that the superconducting metal layer contacts the DC and RF routing circuits, and patterning the superconducting metal layer formed on the back side of the silicon substrate to form a resonator and A method for manufacturing a superconducting quantum qubit device comprising: a step of forming an interposer layer by forming a connection line; and a step of upside down the superconducting qubit layer and bonding it to the interposer layer using an indium bumper. Claim 2 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the interconnect layer and the interposer layer are bonded as oxide film to oxide film. Claim 3 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the first substrate and the second substrate are formed from any one of high-resistance Si, sapphire, and alumina (Al2O3). Claim 4 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the superconducting metal is at least one of Al, TiN, Nb, Ta, and V. Claim 5 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the insulating film included in the interconnect layer is an oxide film or a nitride film, and the top insulating film is formed of a silicon oxide film. Claim 6 A method for manufacturing a superconducting quantum qubit device according to claim 1, characterized in that the depth of the via pattern is 1 to 300 μm or 50 to 200 μm. Claim 7 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the superconducting qubit is one of a Charge Qubit, a Flux Qubit, or a Phase Qubit comprising at least one Josephson element. Claim 8 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the resonator formed in the interposer layer has a length of any one of 1 / 4, 1 / 2, and an integer multiple thereof of the wavelength corresponding to the microwave frequency used. Claim 9 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the superconducting qubit and the resonator are capacitively coupled without direct contact of the superconducting metal. Claim 10 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the superconducting qubit layer and the interposer layer are electrically and mechanically connected by one or more indium bumpers. Claim 11 A method for manufacturing a superconducting quantum qubit device according to claim 1, wherein the oxide film formed on the silicon substrate is formed by depositing an oxide film on the silicon substrate or by performing heat treatment in an oxygen atmosphere. Claim 12 A superconducting quantum qubit device comprising: a first substrate and a superconducting qubit layer including a superconducting qubit and superconducting wiring formed on the first substrate; a second substrate and an interconnect layer including DC and RF routing circuits formed by alternately and repeatedly forming superconducting wiring and an insulating film on the second substrate; a silicon interposer layer including a resonator and a connection line formed by patterning the superconducting metal layer, wherein a silicon substrate having a via pattern is inverted and bonded to the interconnect layer, the via pattern is exposed to form a via hole, and a superconducting metal layer is deposited on the via hole and the front surface of the silicon substrate, so as to be in contact with the DC and RF routing circuits and the superconducting metal layer; wherein the superconducting qubit layer and the silicon interposer layer are bonded to the silicon interposer layer using an indium bumper. Claim 13 A superconducting quantum qubit device according to claim 12, wherein the interconnect layer and the silicon interposer layer are bonded as oxide-to-oxide film. Claim 14 A superconducting quantum qubit device according to claim 12, wherein the first substrate and the second substrate are formed from any one of high-resistance Si, sapphire, and alumina (Al2O3). Claim 15 A superconducting quantum qubit device according to claim 12, characterized in that the superconducting metal is at least one of Al, TiN, Nb, Ta, and V. Claim 16 A superconducting quantum qubit device according to claim 12, wherein the insulating film included in the interconnect layer is an oxide film or a nitride film, and the top insulating film is formed of a silicon oxide film. Claim 17 A superconducting quantum qubit device according to claim 12, characterized in that the depth of the via pattern is 1 to 300 μm or 50 to 200 μm. Claim 18 A superconducting quantum qubit device according to claim 12, wherein the superconducting qubit is one of a Charge Qubit, a Flux Qubit, or a Phase Qubit comprising at least one Josephson element. Claim 19 A superconducting quantum qubit device according to claim 12, wherein the resonator formed on the silicon interposer layer has a length of any one of 1 / 4, 1 / 2, and an integer multiple thereof of the wavelength corresponding to the microwave frequency used. Claim 20 In claim 12, the superconducting quantum qubit device is characterized in that the superconducting qubit and the resonator are capacitively coupled without direct contact of the superconducting metal. Claim 21 A superconducting quantum qubit device according to claim 12, wherein the superconducting qubit layer and the silicon interposer layer are electrically and mechanically connected by one or more indium bumpers. Claim 22 In claim 12, the oxide film formed on the silicon substrate is characterized by being formed by depositing an oxide film on the silicon substrate or by performing heat treatment in an oxygen atmosphere.

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