Methods and apparatus for forming semiconductor devices including tungsten layers using a tungsten growth inhibitor

Abstract

A method for depositing metal includes the steps of providing a structure to a process chamber, and providing a metal fluoride gas and a growth inhibitor gas into the process chamber to deposit metal on the structure. The metal may include word lines or other conductors of a three-dimensional memory device.

Description

Technology Field

[0001] The present disclosure generally relates to the field of semiconductor device manufacturing, and in particular to methods for manufacturing semiconductor devices such as three-dimensional memory devices comprising tungsten layers deposited using a tungsten growth inhibitor. Background Technology

[0002] Three-dimensional memory devices include various conductive layers, such as word lines containing tungsten. Tungsten can be deposited using fluorine-containing precursor gases, such as tungsten hexafluoride. However, residual fluorine can cause voids in adjacent insulating layers of memory devices during the degassing process following tungsten deposition. These voids degrade the reliability of memory devices.

[0003] According to one aspect of the present disclosure, a method for depositing metal comprises the steps of providing a structure to a process chamber, and providing a metal fluoride gas and a growth inhibitor gas into the process chamber to deposit metal on the structure.

[0004] According to another aspect of the present disclosure, a method for depositing metal comprises the steps of providing a structure to a process chamber, and providing a metal fluoride gas and two growth inhibitor gases into the process chamber to deposit metal on the structure.

[0005] According to another aspect of the present disclosure, a tungsten deposition apparatus comprises at least one tungsten deposition chamber configured to deposit a tungsten layer on at least one substrate by receiving at least one substrate and flowing tungsten hexafluoride gas, a surface treatment chamber connected to at least one tungsten deposition chamber—the surface treatment chamber configured to receive at least one substrate and expose the substrate to a tungsten growth inhibitor gas—and at least one load lock configured to transport at least one substrate between the surface treatment chamber and at least one tungsten deposition chamber.

[0006] According to another aspect of the present disclosure, a method for depositing an electrically conductive layer comprises the steps of providing a structure having a cavity inside, placing the structure in a process chamber, depositing a first portion of an electrically conductive layer on at least one surface of the cavity, exposing the first portion of the electrically conductive layer to a tungsten growth inhibitor gas, and depositing a second tungsten portion of the electrically conductive layer on the first portion of the electrically conductive layer by decomposition of tungsten hexafluoride.

[0007] According to another aspect of the present disclosure, a semiconductor structure comprises an active semiconductor device and a tungsten layer located within a cavity in the semiconductor structure. The tungsten layer has at least one of chlorine or nitrogen atoms of different concentrations in a first portion located closer to the cavity sidewalls compared to a second portion located further from the cavity sidewalls, and the tungsten layer has fluorine atoms of different concentrations in a first portion located closer to the cavity sidewalls compared to a second portion located further from the cavity sidewalls. The amount of fluorine atoms increases in the opposite direction to the amount of at least one of chlorine or nitrogen atoms through the thickness of the tungsten layer. Brief explanation of the drawing

[0008] FIG. 1 is a schematic vertical cross-sectional view of an exemplary structure after the formation of a semiconductor material layer and at least one peripheral device, sacrificial via filling structures embedded in a dielectric material layer, according to one embodiment of the present disclosure. FIG. 2 is a schematic vertical cross-sectional view of an exemplary structure after the formation of alternating stacks of insulating layers and sacrificial material layers according to one embodiment of the present disclosure. FIG. 3 is a schematic vertical cross-sectional view of an exemplary structure after the formation of stepped terraces and a retro-stepped dielectric material portion according to one embodiment of the present disclosure. FIG. 4a is a schematic vertical cross-sectional view of an exemplary structure after the formation of memory openings and support openings according to one embodiment of the present disclosure. FIG. 4b is a plan view of the exemplary structure of FIG. 4a. The vertical plane A ― A' is the plane of the cross-section of FIG. 4a. FIGS. 5a through 5h are sequential schematic vertical cross-sectional views of a memory opening in an exemplary structure during the formation of a memory stack structure, an optional dielectric core, and a drain region therein, according to one embodiment of the present disclosure. FIG. 6 is a schematic vertical cross-sectional view of an exemplary structure after the formation of memory stack structures and support column structures according to one embodiment of the present disclosure. FIG. 7a is a schematic vertical cross-sectional view of an exemplary structure after the formation of rear trenches according to one embodiment of the present disclosure. FIG. 7b is a partial perspective plan of the exemplary structure of FIG. 7a. The vertical plane A–A’ is the plane of the schematic vertical section of FIG. 7a. FIG. 7c is a vertical cross-sectional view of an exemplary section of a structure along the vertical plane C ― C' of FIG. 7b. FIG. 8 is a schematic vertical cross-sectional view of an exemplary structure after the formation of rear recesses according to one embodiment of the present disclosure. FIGS. 9a through 9d are sequential vertical cross-sectional views of sections of an exemplary structure during the formation of electrically conductive layers according to one embodiment of the present disclosure. FIG. 10a is a schematic vertical cross-sectional view of an exemplary structure after removing a deposited conductive material from inside a rear trench, according to one embodiment of the present disclosure. FIG. 10b is a partial perspective plan of the exemplary structure of FIG. 10a. The vertical plane A–A’ is the plane of the schematic vertical section of FIG. 10a. FIG. 10c is a vertical cross-sectional view of an exemplary section of a structure along the vertical plane C ― C' of FIG. 10b. FIG. 11 is a schematic vertical cross-sectional view of an exemplary structure after the formation of an insulating spacer and a rear contact structure according to one embodiment of the present disclosure. FIG. 12a is a schematic vertical cross-sectional view of an exemplary structure after the formation of additional contact via cavities according to one embodiment of the present disclosure. FIG. 12b is a schematic vertical cross-sectional view of a portion of the peripheral area of ​​the exemplary structure of FIG. 12a. FIG. 13a is a schematic vertical cross-sectional view of an exemplary structure after the formation of additional contact via structures according to one embodiment of the present disclosure. FIG. 13b is a plan view of the exemplary structure of FIG. 13a. The vertical plane A ― A' is the plane of the schematic vertical section of FIG. 13a. FIG. 13c is a vertical cross-sectional view of an exemplary section of a structure along the vertical plane C ― C' of FIG. 13b. FIG. 13d is a schematic vertical cross-sectional view of a portion of the peripheral area of ​​the exemplary structure of FIG. 13a. FIGS. 14a to 14e are sequential schematic diagrams illustrating a mechanism for inhibiting the deposition rate of a metal through the adsorption of growth-inhibiting atoms according to one embodiment of the present disclosure. FIGS. 15a to 15g are sequential vertical cross-sectional views of a rear recess during the formation of an electrically conductive layer according to one embodiment of the present disclosure. FIGS. 16a through 16f are sequential vertical cross-sectional views of a rear trench during the formation of a rear contact via structure according to one embodiment of the present disclosure. FIG. 17 is a vertical cross-sectional view of a portion of the peripheral area of ​​an exemplary structure after the formation of a device contact via cavity according to one embodiment of the present disclosure. FIGS. 18a through 18f are sequential vertical cross-sectional views of a device contact via cavity during the formation of a contact via structure according to one embodiment of the present disclosure. FIGS. 19a through 19d are flow rate versus time plots of exemplary gas flow sequences that can be employed in deposition processes according to one embodiment of the present disclosure. FIG. 20 is a flowchart of a first exemplary sequence of processing steps according to one embodiment of the present disclosure. FIG. 21 is a flowchart of a second exemplary sequence of processing steps according to one embodiment of the present disclosure. FIG. 22a is a flowchart of a third exemplary sequence of processing steps according to one embodiment of the present disclosure. FIGS. 22b and FIGS. 22c illustrate, respectively, top and vertical cross-sectional views of the surface of a nucleation portion of a metal layer during a third exemplary sequence of processing steps according to one embodiment of the present disclosure. FIGS. 23a and FIGS. 23b illustrate respective top and vertical cross-sectional views of the surface of a barrier liner during a fourth exemplary sequence of processing steps according to one embodiment of the present disclosure. FIG. 24 is a schematic diagram of a first exemplary apparatus for implementing a deposition process according to one embodiment of the present disclosure. FIG. 25 is a schematic diagram of a second exemplary apparatus for implementing a deposition process according to one embodiment of the present disclosure. FIG. 26 is a schematic diagram of a third exemplary apparatus for implementing a deposition process according to one embodiment of the present disclosure. FIG. 27 is a schematic diagram of a fourth exemplary apparatus for implementing a deposition process according to one embodiment of the present disclosure. Specific details for implementing the invention

[0009] As discussed above, the embodiments of the present disclosure relate to tungsten layers deposited using a tungsten growth inhibitor, and various aspects thereof are described below. The embodiments of the present disclosure may be employed to form various structures including multi-level memory structures, and non-limiting examples thereof include semiconductor devices such as three-dimensional memory array devices including a plurality of NAND memory strings.

[0010] Drawings are not drawn to scale. Unless the absence of overlap of elements is explicitly stated or clearly otherwise indicated, multiple instances of an element may overlap when a single instance of an element is drawn. Ordinal numbers such as "first," "second," and "third" are employed merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0011] Identical reference numerals denote identical or similar elements. Unless otherwise indicated, elements having identical reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. If two or more elements do not come into direct contact with each other or between each other, these two elements are "disengaged" from each other or between each other.

[0012] As used herein, a first element located "on" a second element may be located on an outer surface of the surface of the second element or on an inner surface of the second element. As used herein, if physical contact exists between the surface of the first element and the surface of the second element, the first element is located "directly" on the second element. As used herein, if a conductive path consisting of at least one conductive material exists between the first element and the second element, the first element is "electrically connected" to the second element. As used herein, a "prototype" structure or "in-process" structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified.

[0013] As used herein, “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, may contain one or more layers within it, or may have one or more layers on, over, and / or beneath it.

[0014] Generally, a semiconductor die or semiconductor package may contain a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). The same simultaneous operations may occur on each plane, but there are some limitations. Each plane contains multiple blocks, which are the smallest units capable of being erased in a single erase operation. Each block contains multiple pages, which are the smallest units capable of being programmed—that is, the smallest units capable of performing read operations.

[0015] Referring to FIG. 1, an exemplary structure according to one embodiment of the present disclosure is illustrated, which may be employed to manufacture a device structure including, for example, vertical NAND memory devices. The exemplary structure includes a substrate (9, 10) which may be a semiconductor substrate. The substrate may include a substrate semiconductor layer (9) and an optional semiconductor material layer (10). The substrate semiconductor layer (9) may be a semiconductor wafer or a semiconductor material layer and may include at least one elemental semiconductor material (e.g., a single-crystal silicon wafer or layer), at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate may have a main surface (7) which may be, for example, the top surface of the substrate semiconductor layer (9). The main surface (7) may be a semiconductor surface. In one embodiment, the main surface (7) may be a single-crystal semiconductor surface, such as a single-crystal semiconductor surface.

[0016] As used herein, "semiconductor material" is 1.0 × 10 -6 S / cm to 1.0 × 10 5 It refers to a material having electrical conductivity in the range of S / cm. As used herein, "semiconductor material" refers to 1.0 × 10⁻⁶ when no electrical dopant is present internally. -6 S / cm to 1.0 × 10 5 It refers to a material having electrical conductivity in the range of S / cm, and 1.0 S / cm to 1.0 × 10⁻⁶ when suitable doped with an electrical dopant. 5Doped materials having electrical conductivity in the range of S / cm can be produced. As used herein, "electric dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to 1.0 × 10⁻⁶ 5 It refers to a material having electrical conductivity greater than S / cm. As used herein, "insulating material" or "dielectric material" refers to 1.0 × 10⁻⁶ -6 It refers to a material having electrical conductivity of less than S / cm. As used herein, "highly doped semiconductor material" refers to a material that becomes a conductive material when formed as a crystalline material or when converted into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., 1.0 × 10⁻⁶. 5 It refers to a semiconductor material doped with an electric dopant at a sufficiently high atomic concentration to have electrical conductivity exceeding S / cm. The "doped semiconductor material" may be a highly doped semiconductor material, or 1.0 × 10⁻⁶ -6 S / cm to 1.0 × 10 5 It may be a semiconductor material comprising an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration that provides electrical conductivity in the S / cm range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconductive or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconductive or conductive depending on the atomic concentration of the electrical dopant within it. As used herein, "metallic material" refers to a conductive material containing at least one metallic element within it. All measurements of electrical conductivity are performed under standard conditions.

[0017] At least one semiconductor device (700) may be formed on a portion of the substrate semiconductor layer (9). The at least one semiconductor device may include, for example, field-effect transistors. For example, at least one shallow trench isolation structure (720) may be formed by etching portions of the substrate semiconductor layer (9) and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed on the substrate semiconductor layer (9) and subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric (750), a gate electrode (752, 754), and a gate cap dielectric (758). The gate electrode (752, 754) may include a stack of a first gate electrode portion (752) and a second gate electrode portion (754). At least one gate spacer (756) may be formed around at least one gate structure (750, 752, 754, 758) by depositing a dielectric liner and anisotropically etching. Active regions (730) may be formed on upper portions of the substrate semiconductor layer (9), for example, by employing at least one gate structure (750, 752, 754, 758) as masking structures to introduce an electric dopant. Additional masks may be employed as needed. The active regions (730) may include source regions and drain regions of field-effect transistors. A first dielectric liner (761) and a second dielectric liner (762) may be optionally formed. Each of the first and second dielectric liners (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer.As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxide having more than two or fewer than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an exemplary example, the first dielectric liner (761) may be a silicon oxide layer, and the second dielectric liner (762) may be a silicon nitride layer.

[0018] A dielectric material, such as silicon oxide, may be deposited on at least one semiconductor device and subsequently planarized to form a dielectric material layer, which is referred to herein as a planarized dielectric layer (770). Contact via cavities may be formed through the planarized dielectric layer (770) and may be filled within a sacrificial filler material, such as amorphous silicon, germanium, carbon, or organosilicate glass, to form sacrificial via filler structures (771). An etch-stopping dielectric layer (772), such as a silicon nitride layer or a dielectric metal oxide layer, may be optionally formed on the planarized dielectric layer (770).

[0019] An optional semiconductor material layer (10) may be formed on the top surface of the substrate semiconductor layer (9) before or after the formation of at least one semiconductor device (700), for example, by the deposition of a single-crystal semiconductor material, where present, by optional epitaxy. The deposited semiconductor material may be the same as or different from the semiconductor material of the substrate semiconductor layer (9). The deposited semiconductor material may be any material that can be employed in the substrate semiconductor layer (9) as described above. The single-crystal semiconductor material of the semiconductor material layer (10) may be epitaxially aligned with the single-crystal structure of the substrate semiconductor layer (9). The portions of the deposited semiconductor material located on the top surface of the planarizing dielectric layer (770) may be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer (10) may have a top surface coplanar with the top surface of the planarizing dielectric layer (770).

[0020] A region (i.e., a region) of at least one semiconductor device (700) is referred to herein as a peripheral device region (200). A region where a memory array is subsequently formed is referred to herein as a memory array region (100). A contact region (300) for subsequently forming stepped terraces of electrically conductive layers may be provided between the memory array region (100) and the peripheral device region (200).

[0021] In one alternative embodiment, a peripheral device area (200) comprising at least one semiconductor device (700) (e.g., a transistor for a peripheral / driver circuit) may be located below the memory array area (100) in a CMOS under array configuration. In another alternative embodiment, the peripheral device area (200) may be located on a separate substrate, which is subsequently bonded to the memory array area (100).

[0022] Referring to FIG. 2, a stack of alternating first material layers (which may be insulating layers (32)) and second material layers (which may be sacrificial material layers (42)) is formed on the top surface of a substrate (9, 10). The alternating stack is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) may include insulating layers (32) composed of a first material, and sacrificial material layers (42) composed of a second material different from the material of the insulating layers (32). The first material of the insulating layers (32) may be at least one insulating material. Thus, each insulating layer (32) may be an insulating material layer. Insulating materials that may be employed in the insulating layers (32) include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides and their silicates, dielectric metal oxynitrides and their silicates, commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), and organic insulating materials. In one embodiment, the first material of the insulating layers (32) may be silicon oxide.

[0023] The second material of the sacrificial material layers (42) is a sacrificial material that can be selectively removed with respect to the first material of the insulating layers (32). As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, the removal of the first material is "selective" with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material with respect to the second material. The sacrificial material layers (42) may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers (42) may subsequently be replaced, for example, with electrically conductive electrodes that can function as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (e.g., amorphous silicon), and a polycrystalline semiconductor material (e.g., polysilicon). In one embodiment, the sacrificial material layers (42) may be spacer material layers comprising silicon nitride, or a semiconductor material comprising at least one of silicon and germanium.

[0024] The thicknesses of the insulating layers (32) and the sacrificial material layers (42) may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be employed for each insulating layer (32) and each sacrificial material layer (42). The number of repetitions of pairs of insulating layers (32) and sacrificial material layers (42) may be in the range of 2 to 1,024, and typically 8 to 256, but a larger number of repetitions may also be employed. The sacrificial material layers (42) are replaced with electrically conductive layers that function as select gate electrodes and word lines / control gate electrodes. The top and bottom gate electrodes in the stack may function as select gate electrodes. In one embodiment, each sacrificial material layer (42) in the alternating stack (32, 42) may have a uniform thickness that is substantially invariant within each sacrificial material layer (42).

[0025] The present disclosure is described by employing an embodiment in which the spacer material layers are sacrificial material layers (42) that are subsequently replaced by electrically conductive layers, but embodiments in which the sacrificial material layers are formed as electrically conductive layers are clearly considered herein. In such cases, steps for replacing the spacer material layers with electrically conductive layers may be omitted.

[0026] Optionally, an insulating cap layer (70) may be formed on the alternating stacks (32, 42). The insulating cap layer (70) comprises a dielectric material different from the material of the sacrificial material layers (42). In one embodiment, the insulating cap layer (70) may comprise a dielectric material that can be employed in the insulating layers (32) as described above. The insulating cap layer (70) may have a greater thickness than each of the insulating layers (32). The insulating cap layer (70) may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer (70) may be a silicon oxide layer.

[0027] Referring to FIG. 3, stepped surfaces are formed in the peripheral area of ​​the alternating stack (32, 42), which is referred to herein as a terrace area. The terrace area is formed in a contact area (300) located between a peripheral device area (200) containing at least one semiconductor device for a peripheral circuit portion and a memory array area (100). The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise as a function of the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that increases the depth of the cavity in the vertical direction by one or more levels, and a second type of etching process that laterally expands the area to be etched in the vertical direction in a subsequent etching process of the first type. As used in this specification, a “level” of a structure comprising an alternating plurality is defined as the relative position of a pair of first material layers and second material layers within the structure.

[0028] Each sacrificial material layer (42), other than the top sacrificial material layer (42) in the alternating stack (32, 42), extends laterally further than any upper sacrificial material layer (42) in the alternating stack (32, 42) in the terrace area. The terrace area includes stepped surfaces of the alternating stack (32, 42) that extend continuously from the bottom layer in the alternating stack (32, 42) to the top layer in the alternating stack (32, 42).

[0029] The reverse step dielectric material portion (65) (i.e., the insulating filler material portion) may be formed in the stepped cavity by the deposition of a dielectric material within it. For example, a dielectric material such as silicon oxide may be deposited within the stepped cavity. Excess portions of the deposited dielectric material may be removed from the top surface of the insulating cap layer (70), for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the reverse step dielectric material portion (65). As used herein, a “reverse step” element refers to an element having a horizontal cross-sectional area that increases monotonically as a function of the vertical distance from the stepped surfaces and the top surface of the substrate on which the element exists. When silicon oxide is used in the reverse step dielectric material portion (65), the silicon oxide of the reverse step dielectric material portion (65) may be doped with a dopant such as B, P and / or F, or may not be doped.

[0030] Optionally, drain select level isolation structures (72) may be formed through a subset of the insulating cap layer (70) and the sacrificial material layers (42) located at the drain select levels. The drain select level isolation structures (72) may be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. The excess portion of the dielectric material may be removed from the top surface of the insulating cap layer (70).

[0031] Referring to FIGS. 4a and 4b, a lithography material stack (not shown) comprising at least a photoresist layer may be formed on an insulating cap layer (70) and an inverse step dielectric material portion (65), and may be lithographically patterned to form openings within. The openings include a first set of openings formed on a memory array area (100) and a second set of openings formed on a contact area (300). The pattern within the lithography material stack may be transferred through the insulating cap layer (70) or the inverse step dielectric material portion (65) and through the alternating stack (32, 42) by at least one anisotropic etching employing the patterned lithography material stack as an etching mask. The portions of the alternating stack (32, 42) placed below the openings within the patterned lithography material stack are etched to form memory openings (49) and support openings (19). As used herein, “memory opening” refers to a structure in which memory elements, such as a memory stack structure, are subsequently formed. As used herein, “support opening” refers to a structure in which a support structure (e.g., a support pillar structure) that mechanically supports other elements is subsequently formed. Memory openings (49) are formed through the entire insulating cap layer (70) and alternating stacks (32, 42) within the memory array area (100). Support openings (19) are formed through the reverse stepped dielectric material portion (65) within the contact area (300) and the portion of the alternating stacks (32, 42) that lies beneath the stepped surfaces.

[0032] Memory openings (49) extend through the entire alternating stack (32, 42). Support openings (19) extend through a subset of layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process employed to etch through the materials of the alternating stack (32, 42) may be alternate to optimize the etching of the first and second materials within the alternating stack (32, 42). The anisotropic etching may be, for example, a series of reactive ion etchings. The sidewalls of the memory openings (49) and support openings (19) may be substantially vertical or tapered. The patterned lithographic material stack may be subsequently removed, for example, by ashing. The memory openings (49) and support openings (19) may extend from the top surface of the alternating stack (32, 42) to a horizontal plane including at least the top surface of the semiconductor material layer (10).

[0033] FIGS. 5a through 5h illustrate structural changes in a memory opening (49), which is one of the memory openings (49) in the exemplary structure of FIGS. 4a and 4b. The same structural change occurs simultaneously in each of the other memory openings (49) and in each support opening (19).

[0034] Referring to FIG. 5a, a memory opening (49) within the exemplary device structure of FIG. 4a and FIG. 4b is illustrated. The memory opening (49) extends through the insulating cap layer (70), the alternating stack (32, 42), and optionally into the upper portion of the semiconductor material layer (10). In this processing step, each supporting opening (19) may extend through a subset of layers within the reverse step dielectric material portion (65) and the alternating stack (32, 42), and optionally through the upper portion of the semiconductor material layer (10). The recess depth of the lower surface of each memory opening relative to the upper surface of the semiconductor material layer (10) may be in the range of 0 nm to 30 nm, but larger recess depths may also be employed. Optionally, the sacrificial material layers (42) may be partially laterally recessed to form lateral recesses (not illustrated), for example by isotropic etching.

[0035] Referring to FIG. 5b, an optional pedestal channel portion (e.g., an epitaxial pedestal) (11) may be formed, for example, by optional epitaxy at the bottom portion of each memory opening (49) and each support opening (19). Each pedestal channel portion (11) comprises a single-crystal semiconductor material that is epitaxially aligned with the single-crystal semiconductor material of the semiconductor material layer (10). In one embodiment, the pedestal channel portion (11) may be doped with an electrical dopant of the same conductive type as the semiconductor material layer (10). A memory cavity (49') exists within the uncharged portion of the memory opening (49) above the pedestal channel portion (11). In one embodiment, the pedestal channel portion (11) may comprise single-crystal silicon. In one embodiment, the pedestal channel portion (11) may have a first type of doping that is the same as the type of conductivity of the semiconductor material layer (10) that the pedestal channel portion contacts.

[0036] Referring to FIG. 5c, a stack of layers including an optional blocking dielectric layer (52), a memory material layer (54), a dielectric material liner (56), and an optional sacrificial cover material layer (601) can be sequentially deposited within memory openings (49) by their respective conformal deposition processes.

[0037] Referring to FIG. 5d, an optional sacrificial cover material layer (601), a dielectric material liner (56), a memory material layer (54), and a blocking dielectric layer (52) placed on an insulating cap layer (70) are sequentially anisotropically etched by employing at least one anisotropic etching process. Each remaining portion of the sacrificial cover material layer (601) may have a tubular configuration. The memory material layer (54) may include a charge trapping material, a floating gate material, a ferroelectric material, a resistive memory material capable of providing at least two different resistance levels (e.g., a phase change material), or other memory material capable of storing information by a state change. In one embodiment, each memory material layer (54) may include a vertical stack of charge storage regions that store electric charge during programming. In one embodiment, the memory material layer (54) may be a memory material layer in which each portion adjacent to the sacrificial material layers (42) constitutes a charge storage region. The surface of the pedestal channel portion (11) (or the surface of the semiconductor material layer (10) if the pedestal channel portions (11) are not employed) may be physically exposed through a sacrificial cover material layer (601), a dielectric material liner (56), a memory material layer (54), and a blocking dielectric layer (52) under the opening. A set of the blocking dielectric layer (52), the memory material layer (54), and the dielectric material liner (56) within the memory opening (49) constitutes a memory film (50), which includes a plurality of charge storage zones (including a portion of the memory material layer (54)) that are insulated from surrounding materials by the blocking dielectric layer (52) and the dielectric material liner (56). In one embodiment, the sacrificial cover material layer (601), the dielectric material liner (56), the memory material layer (54), and the blocking dielectric layer (52) may have sidewalls that match in the vertical direction. The sacrificial cover material layer (601) can be selectively and subsequently removed from the material of the dielectric material liner (56).If the sacrificial cover material layer (601) comprises a semiconductor material, a wet etching process employing high-temperature trimethyl-2 hydroxyethyl ammonium hydroxide ("high-temperature TMY") or tetramethyl ammonium hydroxide (TMAH) may be performed to remove the sacrificial cover material layer (601). Alternatively, the sacrificial cover material layer (601) may be retained within the final device if it comprises a semiconductor material.

[0038] Referring to FIG. 5e, the semiconductor channel layer (60L) may be deposited directly on the semiconductor surface of the pedestal channel portion (11), or directly on the semiconductor material layer (10) and on the dielectric material liner (56) when the pedestal channel portion (11) is omitted. The semiconductor channel layer (60L) comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer (60L) comprises amorphous silicon or polysilicon. The semiconductor channel layer (60L) may have a first type of doping that is the same as the type of conductivity of the semiconductor material layer (10) and the pedestal channel portions (11). The semiconductor channel layer (60L) may be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer (60L) may be in the range of 2 nm to 10 nm, but smaller and larger thicknesses may also be employed. The semiconductor channel layer (60L) may partially fill the memory cavity (49') within each memory opening, or may completely fill the cavity within each memory opening.

[0039] Referring to FIG. 5f, if the memory cavity (49') within each memory opening is not completely filled by the semiconductor channel layer (60L), a dielectric core layer (62L) may be deposited within the memory cavity (49') to fill any remaining portion of the memory cavity (49') within each memory opening. The dielectric core layer (62L) comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer (62L) may be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating.

[0040] Referring to FIG. 5g, the horizontal portion of the dielectric core layer (62L) can be removed by a recess etching process, for example, such that each remaining portion of the dielectric core layer (62L) is located within its respective memory opening (49) and has its respective top surface below a horizontal plane including the top surface of the insulating cap layer (70). Each remaining portion of the dielectric core layer (62L) constitutes the dielectric core (62).

[0041] Referring to FIG. 5h, a doped semiconductor material having a second type of conductivity doping can be deposited inside each recessed area on the dielectric core (62). The deposited semiconductor material may have a second type of conductivity doping opposite to the first type of conductivity. For example, if the first type of conductivity is p-type, the second type of conductivity is n-type, and vice versa. The dopant concentration in the deposited semiconductor material is 5.0 × 10⁻⁶ 18 / cm 3 Up to 2.0 × 10 21 / cm 3 It may be within the range, but lower and higher dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0042] Excess portions of the deposited semiconductor material having a horizontal portion of the second conductive type doping and the semiconductor channel layer (60L) can be removed from the horizontal plane including the top surface of the insulating cap layer (70) by, for example, chemical mechanical planarization (CMP) or a recess etching process. Each remaining portion of the doped semiconductor material having the second conductive type doping constitutes a drain region (63). Each remaining portion of the semiconductor channel layer (60L) (having the first conductive type doping) constitutes a vertical semiconductor channel (60). The vertical semiconductor channel (60) is formed directly on the dielectric material liner (56).

[0043] Each combination of the memory film (50) and the vertical semiconductor channel (60) within the memory opening (49) constitutes a memory stack structure (55). The memory stack structure (55) is a combination of a plurality of memory elements, implemented as parts of a semiconductor channel, a dielectric material liner, and a memory material layer (54), and an optional blocking dielectric layer (52). The entire set of material parts filling the memory opening (49) is referred to herein as a memory opening filling structure (58). The entire set of material parts filling the support opening (19) constitutes a support pillar structure.

[0044] Generally, a memory opening filling structure (58) can be formed within each memory opening (49). The memory opening filling structure (58) includes an optional blocking dielectric layer (52), a memory material layer (54), an optional dielectric material liner (56), and a vertical semiconductor channel (60). The dielectric material liner (56) can laterally surround the vertical semiconductor channel (60). The memory material layer (54) can laterally surround the dielectric material liner (56). When the sacrificial material layers (42) are subsequently replaced with electrically conductive layers, a vertical NAND string can be formed through each memory opening.

[0045] Referring to FIG. 6, an exemplary structure is illustrated after the formation of memory opening filling structures (58) and support pillar structures (20) within each memory opening (49) and support opening (19). An instance of the memory opening filling structure (58) may be formed within each memory opening (49) of the structure of FIG. 4a and FIG. 4b. An instance of the support pillar structure (20) may be formed within each support opening (19) of the structure of FIG. 4a and FIG. 4b.

[0046] Each memory stack structure (55) comprises a vertical semiconductor channel (60) and a memory film (50). The memory film (50) may comprise a dielectric material liner (56) that laterally surrounds the vertical semiconductor channel (60), and a vertical stack of charge storage regions (including a portion of the memory material layer (54)) that laterally surround the dielectric material liner (56) and an optional blocking dielectric layer (52). The methods of the embodiments of the present disclosure may be applied to alternative memory stack structures comprising different layer stacks or structures for the memory film (50) and / or the vertical semiconductor channel (60).

[0047] Referring to FIGS. 7a through 7c, a contact level dielectric layer (73) may be formed on an alternating stack (32, 42) of insulating layers (32) and sacrificial material layers (42), and on memory opening filling structures (58) and support pillar structures (20). The contact level dielectric layer (73) comprises a dielectric material different from the dielectric material of the sacrificial material layers (42). For example, the contact level dielectric layer (73) may comprise silicon oxide. The contact level dielectric layer (73) may have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses may also be employed.

[0048] A photoresist layer (not shown) may be applied over a contact level dielectric layer (73) and lithographically patterned to form openings in regions between clusters of memory opening filling structures (58). The pattern within the photoresist layer may be transferred through the contact level dielectric layer (73), alternating stacks (32, 42), and / or reverse step dielectric material portions (65) by employing anisotropic etching to form rear trenches (79), which extend vertically from the top surface of the contact level dielectric layer (73) to at least the top surface of the substrate (9, 10) and extend laterally through the memory array region (100) and the contact region (300).

[0049] In one embodiment, the rear trenches (79) may extend laterally along a first horizontal direction (e.g., word line direction) (hd1) and may be laterally spaced from one another along a second horizontal direction (e.g., bit line direction) (hd2) perpendicular to the first horizontal direction (hd1). Memory stack structures (55) may be arranged in rows extending along the first horizontal direction (hd1). Drain select level isolation structures (72) may extend laterally along the first horizontal direction (hd1). Each rear trench (79) may have a uniform width that is invariant along the length direction (i.e., along the first horizontal direction (hd1)). Multiple rows of memory stack structures (55) may be located between adjacent pairs of back trenches (79) and drain selection level isolation structures (72), or between adjacent pairs of drain selection level isolation structures (72). In one embodiment, the back trenches (79) may include a source contact opening where a source contact via structure may subsequently be formed. The photoresist layer may be removed, for example, by ashing.

[0050] A source region (61) can be formed in a surface portion of the semiconductor material layer (10) below each rear trench (79) by injecting an electric dopant into physically exposed surface portions of the semiconductor material layer (10). An upper portion of the semiconductor material layer (10) extending between the source region (61) and a plurality of pedestal channel portions (11) forms a horizontal semiconductor channel (59) for a plurality of field-effect transistors. The horizontal semiconductor channel (59) is connected to a plurality of vertical semiconductor channels (60) through each pedestal channel portion (11). The horizontal semiconductor channel (59) is in contact with the source region (61) and the plurality of pedestal channel portions (11).

[0051] Referring to FIGS. 8 and 9a, an etching agent that selectively etches the second material of the sacrificial material layers (42) with respect to the first material of the insulating layers (32) may be introduced into the back trenches (79), for example, by employing an etching process. FIG. 9a illustrates a section of the exemplary structure of FIG. 8. Back recesses (43) are formed within the volume from which the sacrificial material layers (42) have been removed. The removal of the second material of the sacrificial material layers (42) may be selective for the first material of the insulating layers (32), the material of the reverse step dielectric material portion (65), the semiconductor material of the semiconductor material layer (10), and the material of the outermost layer of the memory films (50). In one embodiment, the sacrificial material layers (42) may comprise silicon nitride, and the materials of the insulating layers (32) and the reverse step dielectric material portion (65) may be selected from silicon oxide and dielectric metal oxide.

[0052] Each rear recess (43) may be a laterally extending cavity having lateral dimensions larger than the vertical size of the cavity. Each of the plurality of rear recesses (43) may extend substantially parallel to the top surface of the substrate (9, 10). The rear recess (43) may be vertically bounded by the top surface of the insulating layer (32) placed underneath and the bottom surface of the insulating layer (32) placed above. In one embodiment, each rear recess (43) may have a uniform height over the entire area.

[0053] Optional pedestal channel portions (11) and physically exposed surface portions of the semiconductor material layer (10) can be converted into dielectric material portions by thermal conversion and / or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and / or plasma conversion may be employed to convert the surface portion of each pedestal channel portion (11) into a tubular dielectric spacer (116) and to convert each physically exposed surface portion of the semiconductor material layer (10) into a planar dielectric portion (616).

[0054] Referring to FIG. 9b, a rear blocking dielectric layer (44) may be optionally formed. The rear blocking dielectric layer (44), if present, comprises a dielectric material that functions as a control gate dielectric for control gates subsequently formed within the rear recesses (43). The rear blocking dielectric layer (44) is optional when the blocking dielectric layer (52) is present within each memory opening. When the blocking dielectric layer (52) is omitted, the rear blocking dielectric layer (44) is present.

[0055] Referring to FIG. 9c, a metallic barrier liner (46A) may be deposited within the rear recesses (43). The metallic barrier liner (46A) comprises an electrically conductive metallic material that can function as a diffusion barrier layer and / or an adhesion-promoting layer for a metallic filler material to be subsequently deposited. The metallic barrier liner (46A) may comprise a pure metal such as Mo or Ru, a conductive metallic nitride, oxynitride, or carbonate material such as TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, or a stack thereof, or a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof.

[0056] Referring to FIG. 9d and FIG. 10, a metal filler material is deposited within a plurality of rear recesses (43), on the sidewalls of at least one rear trench (79), and on the top surface of the contact level dielectric layer (73) to form a metal filler material layer (46B). In one embodiment, the metal filler material layer (46B) may essentially consist of at least one elemental metal, such as tungsten. According to one aspect of the disclosure, the rear recesses (43) may include high aspect ratio voids, wherein the ratio of the maximum lateral dimension of each rear recess (43) to the height of each rear recess (43) is greater than 3 and / or greater than 5 and / or greater than 10. According to one embodiment of the present disclosure, a metal filler material layer (e.g., a tungsten layer) (46B) can be deposited by employing a conformal metal deposition process, which is described in more detail below, and by employing a metal fluoride gas such as tungsten hexafluoride gas.

[0057] A plurality of electrically conductive layers (46) may be formed within a plurality of rear recesses (43), and a continuous metallic material layer (46L) may be formed on the sidewalls of each rear trench (79) and on the contact level dielectric layer (73). Each electrically conductive layer (46) comprises a portion of a metallic barrier liner (46A) and a portion of a metal filler material layer (46B) located between pairs of dielectric material layers that are vertically adjacent, such as pairs of insulating layers (32). The continuous metallic material layer (46L) comprises a continuous portion of the metallic barrier liner (46A) and a continuous portion of the metal filler material layer (46B) located within the rear trenches (79) or on the contact level dielectric layer (73).

[0058] Each sacrificial material layer (42) can be replaced with an electrically conductive layer (46). A rear cavity (79') exists within the portion of each rear trench (79) that is not filled with the rear blocking dielectric layer (44) and the continuous metallic material layer (46L). Tubular dielectric spacers (116) laterally surround the pedestal channel portion (11). The bottom electrically conductive layer (46) laterally surrounds each tubular dielectric spacer (116) during the formation of the electrically conductive layers (46).

[0059] Referring to FIGS. 10a through 10c, the deposited metallic material of the continuous electrically conductive material layer (46L) is etched back from the sidewalls of each rear trench (79) and from above the contact level dielectric layer (73) by, for example, isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material within the rear recesses (43) constitutes an electrically conductive layer (46). Each electrically conductive layer (46) may be a conductive line structure. Thus, the sacrificial material layers (42) are replaced by the electrically conductive layers (46).

[0060] At least one uppermost and at least one lowermost electrically conductive layer (46) can function as a select gate electrode (e.g., drain and source select gate electrodes, respectively). A plurality (or all) of residual electrically conductive layers (46) can function as a combination of a plurality of control gate electrodes located at the same level and a word line that electrically interconnects, i.e., electrically shorts, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer (46) are control gate electrodes for vertical memory devices including memory stack structures (55). In other words, each electrically conductive layer (46) can be a word line that functions as a common control gate electrode for a plurality of vertical memory devices.

[0061] In one embodiment, the removal of the continuous electrically conductive material layer (46L) may be optional for the material of the rear blocking dielectric layer (44). In this case, the horizontal portion of the rear blocking dielectric layer (44) may be located at the bottom of each rear trench (79). In another embodiment, the removal of the continuous electrically conductive material layer (46L) may not be optional for the material of the rear blocking dielectric layer (44), or the rear blocking dielectric layer (44) may not be employed. The planar dielectric portions (616) may be removed during the removal of the continuous electrically conductive material layer (46L). A rear cavity (79') is located within each rear trench (79).

[0062] Referring to FIG. 11, an insulating material layer may be formed within the back trenches (79) and on the contact level dielectric layer (73) by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer comprises an insulating material such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicate glass, or a combination thereof.

[0063] In one embodiment, the insulating material layer may comprise silicon oxide. The insulating material layer may be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer may be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses may also be employed. Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer (73) and at the bottom of each rear trench (79). Each remaining portion of the insulating material layer forms an insulating spacer (74). A rear cavity (79') exists within a volume enclosed by each insulating spacer (74). The top surface of the semiconductor material layer (10) may be physically exposed at the bottom of each rear trench (79).

[0064] A rear contact via structure (76) may be formed within each rear cavity (79'). Each contact via structure (76) may fill its respective cavity (79'). The contact via structures (76) may be formed by depositing at least one conductive material within the remaining unfilled volume of the rear trench (79) (i.e., the rear cavity (79')). For example, the at least one conductive material may comprise a metal barrier liner (76A) and a metal filler material portion (76B). The metal barrier liner (76A) may comprise a pure metal such as Mo or Ru, a conductive metallic nitride, oxynitride, or carbonate material such as TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, or a stack thereof, or a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. The thickness of the metal barrier liner (76A) may be in the range of 3 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0065] According to one embodiment of the present disclosure, the rear trenches (79) may include high aspect ratio voids, wherein the ratio of the height of each rear trench (79) to the width of each rear trench (79) is greater than 3 and / or greater than 5 and / or greater than 10. According to one embodiment of the present specification, a metal filler material portion (e.g., a tungsten portion) (76B) may be deposited by employing a metal fluoride gas, such as tungsten hexafluoride gas, by employing the conformal metal deposition process of the present disclosure to be described in subsequent sections.

[0066] At least one conductive material can be planarized by employing a contact-level dielectric layer (73) placed on the alternating stack (32, 46) as a stop layer. If a chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer (73) can be employed as a CMP stop layer. Each remaining continuous portion of the at least one conductive material within the rear trenches (79) forms a rear contact via structure (76). The rear contact via structure (76) extends through the alternating stack (32, 46) and contacts the top surface of the source region (61).

[0067] Alternatively, the insulating material layer described above may be formed within the rear trenches (79) to completely fill the entire volume of the rear trench (79) and may essentially consist of at least one dielectric material. In this alternative embodiment, the source zone (61) and the rear trench via structure (76) may be omitted, and a horizontal source line (e.g., a direct strap contact) may contact the side of the lower portion of the semiconductor channel (60).

[0068] Referring to FIGS. 12a and 12b, a photoresist layer (not shown) may be applied over a contact-level dielectric layer (73) and lithographically patterned to form openings therethrough. The pattern of openings within the photoresist layer includes patterns of contact via structures to be formed continuously through the contact-level dielectric layer (73) and the reverse-step dielectric material portion (65). An anisotropic etching process may be performed to transfer the pattern of openings within the photoresist layer through the contact-level dielectric layer (73), through the reverse-step dielectric material portion (65), through a rear-blocking dielectric layer (44) in contact with the stepped bottom surfaces of the reverse-step dielectric material portion (65), and, if present, through an etching stop dielectric layer (772). Drain regions (63), electrically conductive layers (46), and sacrificial via filling structures (771) may function as etching stop structures. A contact via cavity (87) can be formed over each drain region (63) of the memory opening charge structures (58), so that the top surface of the drain region (63) is physically exposed below each drain contact via cavity (87). A contact via cavity (85) can be formed over the electrically conductive layers (46), so that the top surface of the electrically conductive layers (46) is physically exposed below each word line contact via cavity (85). An upper device contact via cavity (83U) can be formed over each sacrificial via charge structure (771) within the peripheral region, so that the top surface of the sacrificial via charge structure (771) is physically exposed below each upper device contact via cavity.

[0069] A selective isotropic etching process may be performed to remove the material of selective sacrificial via fill structures (771) from the materials of the reverse step dielectric material portion (65), the planarized dielectric layer (770), the drain regions (63), and the electrically conductive layers (46). For example, if the sacrificial via fill structure (771) comprises amorphous silicon or a silicon-germanium alloy, a wet etching process employing tetramethylammonium hydroxide (TMAH) or hot trimethyl-2 hydroxyethylammonium hydroxide ("hot TMY") may be performed to remove the sacrificial via fill structures (771) through the upper device contact via cavity (83U). If the sacrificial via fill structures (771) comprise a carbon-based material, ashing may be used to remove the sacrificial via structures (771). The device contact via cavity (83L) may be formed within each volume from which the sacrificial via filling structure (771) is removed. Each contiguous combination of the upper device contact via cavity (83U) and the lower device contact via cavity (83L) constitutes the device contact via cavity (83), which may be a two-layer contact via cavity having a stepped vertical cross-sectional profile. In one embodiment, the device contact via cavity (83) may include an upper tapered profile around the upper device contact via cavity (83U), a lower tapered profile around the lower device contact via cavity (83L), and an annular connecting surface connecting the upper periphery of the lower device contact via cavity and the lower periphery of the upper device contact via cavity.

[0070] Referring to FIGS. 13a through 13d, at least one conductive material may be deposited within drain contact via cavities (87), word line contact via cavities (85), and device contact via cavities (83). For example, the at least one conductive material may include a metallic barrier liner material and a conductive filler material. The metallic barrier liner material may include a conductive metallic liner, such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or a stack thereof. The metallic barrier liner material may be conformally deposited, and the thickness of the metallic barrier liner material may be in the range of 3 nm to 30 nm, but smaller and larger thicknesses may also be employed. According to one embodiment of the present disclosure, device contact via cavities (83), word line contact via cavities (85), and optionally drain contact via cavities (87) may include high aspect ratio cavities in which the ratio of height to width is greater than 3 and / or greater than 5 and / or greater than 10. According to one embodiment of the present disclosure, a conductive filler material such as tungsten may be deposited by employing a conformal metal deposition process as described in more detail below, employing a metal fluoride gas such as tungsten hexafluoride.

[0071] At least one conductive material can be planarized by employing a contact level dielectric layer (73) placed on an alternating stack (32, 46) as a stop layer. When a chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer (73) can be employed as a CMP stop layer. Each remaining portion of the at least one conductive material filling the device contact via cavity (83) forms a device contact via structure (96). Each remaining portion of the at least one conductive material filling the drain contact via cavity forms a drain contact via structure (88). Each remaining portion of the at least one conductive material filling the word line contact via cavity forms a word line contact via structure (86).

[0072] Each device contact via structure (96) may include a metal barrier liner (96A) and a metal filler material portion (96B). Each drain contact via structure (88) may include a metal barrier liner (88A) and a metal filler material portion (88B). Each word line contact via structure (86) may include a metal barrier liner and a metal filler material portion. In one embodiment, the metal barrier liners (96A, 88A) of the various contact via structures (88, 86, 96) may have the same material composition and the same thickness and may be deposited in the same metal liner deposition process. In one embodiment, the metal filler material portions (88B, 96B) of the various contact via structures may have the same material composition and may be deposited in the same deposition process, such as the conformal metal deposition process of the present disclosure employing a metal fluoride gas, which will be described in subsequent sections.

[0073] According to an embodiment of the present disclosure, a structure comprising a cavity is provided. The cavity may be a horizontally extending cavity such as the rear recess (43) described above, or a vertically extending cavity such as the rear cavity remaining after forming an insulating spacer (74) in the rear trench (79) described above, a device contact via cavity (83) described above, a word line contact via cavity (85) described above, or a drain contact via cavity (87) described above. Generally, any via cavity that may be formed during a semiconductor manufacturing process may be employed to implement the tungsten deposition process of the embodiments of the present disclosure. In some embodiments, the via cavity may have a high aspect ratio in which the longitudinal or depth dimension along the direction perpendicular to the opening of the via cavity connected to the periphery is greater than the width dimension of the opening by a factor of at least 3, at least 5 and / or at least 10, e.g., a factor of 3 to 100. Although the tungsten deposition of the embodiments of the present disclosure may be provided in a cavity of any size or aspect ratio, the gain of the embodiments of the present specification may be increased when the tungsten is deposited in a cavity having a high aspect ratio such as greater than 3 and / or greater than 5 and / or greater than 10, e.g., an aspect ratio having a factor of 3 to 100.

[0074] A structure including a cavity may be placed within a process chamber, and the process chamber may be a vacuum chamber configured for a chemical vapor deposition process or atomic layer deposition. A tungsten growth inhibitor gas may be supplied into a deposition chamber during tungsten growth from a tungsten fluoride source gas, such as a tungsten hexafluoride source gas, to inhibit (i.e., reduce or inhibit) the tungsten growth rate at least in the inner part of the tungsten layer. The growth inhibitor gas may be supplied into the deposition chamber together with and / or alternately with tungsten hexafluoride, as described in more detail below. The tungsten growth inhibitor gas reduces the tungsten growth rate at least in the inner part of the tungsten layer and allows residual fluorine atoms from tungsten hexafluoride to be degassed from the cavity before the cavity is completely filled by the tungsten layer. It is believed that this can reduce the fluorine-induced voids in the layers surrounding the cavity when fluorine trapped in the cavity by the tungsten layer diffuses into adjacent layers. Therefore, the growth inhibitor gas reduces the tungsten deposition rate of the simultaneous or subsequent tungsten deposition process and preferably does not contain or substantially does not contain fluorine atoms. Generally, the growth inhibitor gas may also be referred to as an inhibitor gas.

[0075] Without being bound by any specific theory, a possible mechanism for inhibiting the deposition rate of tungsten through the adsorption of growth inhibitor atoms from a growth inhibitor gas according to one embodiment of the present disclosure is illustrated in FIGS. 14a to 14e. The growth inhibitor atoms may include nitrogen and / or halogen atoms other than fluorine, such as chlorine.

[0076] Referring to FIG. 14a, a metal fluoride gas and a metal growth inhibitor gas may be simultaneously flowed into a process chamber comprising a metal surface, which may be the surface of a cavity on a substrate, during a first metal deposition step. In the illustrated example, the metal surface may be a tungsten surface, the metal fluoride gas may be tungsten hexafluoride, and the growth inhibitor gas may be dichlorosilane (DCS, SiH2Cl2). Generally, the metal fluoride gas may be any metal fluoride gas composed of elemental metals and fluorine atoms. Exemplary metal fluoride gases include, but are not limited to, WF6, MoF6, RuF6, RhF6, ReF6, OsF6, IrF6, and PtF6. Atoms and radicals from the metal fluoride gas and the growth inhibitor gas may be adsorbed onto the metal surface. For example, chlorine atoms from the growth inhibitor gas, fluorine atoms from the metal fluoride gas, and WF 6-x Metal fluoride compounds such as [list of compounds] can be adsorbed onto metal surfaces. Generally, metal fluoride compounds can be adsorbed at sites on the metal surface where metal atoms, SiH radicals, or hydrogen atoms are present. Metal fluoride compounds and fluorine atoms are not adsorbed at sites where chlorine atoms are adsorbed. Since the total number of sites for atomic adsorption per unit area is finite, the higher the proportion of sites adsorbing chlorine atoms, the lower the proportion of sites adsorbing fluorine or metal fluoride compounds. It should be noted that the adsorption of chlorine and fluorine atoms is reversible, and there is a dynamic equilibrium between the proportion of sites adsorbing chlorine atoms and the proportion of sites adsorbing fluorine atoms.

[0077] In some embodiments, a nitrogen atom may be used as a growth inhibitor atom instead of or in addition to a chlorine atom to provide a similar effect. Generally, the molecule of the growth inhibitor gas contains at least one chlorine atom and / or at least one nitrogen atom internally. In one embodiment, the growth inhibitor gas contains at least one chlorine atom. In one embodiment, the growth inhibitor gas contains a silicon-containing chloride gas selected from SiH3Cl, SiH2Cl2, SiHCl3, or SiCl4. In one embodiment, the growth inhibitor gas contains a boron-containing chloride gas selected from BH2Cl, BHCl2, or BCl3. In one embodiment, the growth inhibitor gas contains at least one nitrogen atom, such as N2 or NH3. Generally, the growth rate of a metal (e.g., tungsten) and / or the adsorption of fluorine on the metal surface is reduced due to the presence of adsorbed growth inhibitor atoms, such as chlorine and / or nitrogen atoms (which would not have been present if the growth inhibitor gas had not flowed into the process chamber during the metal deposition step).

[0078] Referring to Fig. 14b, the chemical reactions occurring on a metal surface upon the adsorption of a metal fluoride compound are illustrated. Generally, the adsorption of a metal fluoride compound on a metal surface leads to the loss of fluorine atoms through, for example, bonding with silicon hydride radicals (e.g., SiH), hydrogen atoms, or silicon atoms, and the subsequent formation of volatile fluorine-containing compounds (e.g., SiF4, SiH2F2, HF, etc.). Consequently, the molecules of the metal fluoride compound tend to lose fluorine atoms until most of the fluorine atoms dissociate from the metal atoms of the metal fluoride compound, and the metal atoms are incorporated into the metal material layer. For example, WF x is SiH y and reacts with hydrogen atoms, SiF zVolatile gas byproducts, such as (e.g., SiF4), HF, and unreacted WF6 molecules, are removed as a flow stream in the chemical vapor deposition process or during the purge step in the atomic layer deposition process. The purge step may include an inert gas (e.g., argon) purge step, where the inert gas is introduced into the process chamber to purge volatile fluorine-containing gas byproducts out of the process chamber.

[0079] Referring to FIG. 14c, a selective reduction step (e.g., a hydrogen immersion step) in which a hydrogen-containing gas, such as pure hydrogen gas, flows into a process chamber can be performed continuously. The hydrogen gas is applied to the WF-adsorbed on the metal surface. x Reacts with compounds, fluorine atoms, and chlorine atoms, and WF on metal surfaces x Removal of compounds, fluorine atoms, and chlorine atoms. Generally, the H2-Cl reaction rate is lower than that of the H2-F reaction, and while a significant proportion of fluorine atoms can be removed from the metal surface by hydrogen gas, a significant proportion of chlorine atoms may remain on the metal surface after the reduction process. The proportion of chlorine atoms remaining on the metal surface depends on the process conditions of the reduction step. According to one embodiment of the present disclosure, the process conditions of the reduction step may be selected such that a significant proportion of chlorine atoms adsorbed during the flow of the growth inhibitor gas (e.g., more than 50%), or at least 30% and / or 15%, remain on the metal surface at the end of the reduction step, as illustrated in FIG. 14d.

[0080] Referring to FIG. 14e, a second metal deposition step is performed, wherein a metal fluoride (e.g., tungsten hexafluoride) gas and a growth inhibitor gas (e.g., DCS) can be simultaneously flowed into the process chamber. The growth rate of the metal on the metal surface is reduced due to the presence of existing adsorbed chlorine atoms in addition to newly adsorbed chlorine atoms adsorbed on the growth surface during the second metal deposition step. Therefore, even if the flow rates of the respective gases in the first and second metal deposition steps are the same, the growth rate of the metal during the second metal deposition step may be lower than the growth rate of the metal during the first metal deposition step.

[0081] Accordingly, by using a growth inhibitor gas, a more uniform metal (e.g., tungsten) filler can be obtained in large surface area cavities such as back recesses (43), back trenches (79) and / or device contact cavities (83). The growth inhibitor gas controls the decomposition of metal fluoride to help a more conformal cover of metal (e.g., tungsten) in the cavities.

[0082] As discussed above, the processes of the embodiments of the present disclosure may be performed to deposit metal into the aforementioned rear recess (43), into the rear cavity remaining after the formation of the insulating spacer (74) in the aforementioned rear trench (79), into the aforementioned device contact via cavity (83), into the aforementioned word line contact via cavity (85), into the aforementioned drain contact via cavity (87), or into any via cavity that may be formed during the semiconductor manufacturing process.

[0083] FIGS. 15a through 15g are sequential vertical cross-sectional views of a rear recess (43) during the formation of an electrically conductive layer (46) according to one embodiment of the present disclosure. FIGS. 16a through 16g are sequential vertical cross-sectional views of a rear trench (79) during the formation of a rear contact via structure (76) according to one embodiment of the present disclosure. FIG. 17 is a vertical cross-sectional view of a portion of the peripheral area of ​​an exemplary structure after the formation of device contact via cavities (83) in the processing steps of FIGS. 12a and 12b. FIGS. 18a through 18f are sequential vertical cross-sectional views of a device contact via cavity (83) during the formation of a contact via structure (96) according to one embodiment of the present disclosure.

[0084] Examples of the present disclosure for depositing a metal using a metal fluoride gas (e.g., tungsten hexafluoride) and a growth inhibitor gas (e.g., a nitrogen and / or non-fluorinated halogen-containing gas) are now described with reference to FIGS. 15a to 15g, FIGS. 16a to 16f, and FIGS. 18a to 18f.

[0085] Referring to FIGS. 15a, 16a, and 18a, a structure including a cavity inside is provided and disposed within a process chamber. In one embodiment, the structure may include an exemplary structure shown in FIGS. 8 and 9a, a portion thereof of which is shown in FIG. 15a. In one embodiment, the structure may include an exemplary structure shown in FIGS. 10a through 10c, a portion thereof of which is shown in FIG. 16a. In one embodiment, the structure may include an exemplary structure shown in FIGS. 12a and 12b, a portion thereof of which is shown in FIG. 18a.

[0086] Referring to FIGS. 15b and FIGS. 16b, a dielectric material may be selectively deposited on the surface of the cavity. For example, the aforementioned back-blocking dielectric layer (44) may be selectively conformally deposited on the physically exposed surfaces of the insulating layers (32) and memory stack structures (55) as shown in FIG. 15b.

[0087] The dielectric material of the rear blocking dielectric layer (44) may be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and / or at least one lanthanide element. Alternatively or additionally, the rear blocking dielectric layer (44) may comprise a silicon oxide layer. The rear blocking dielectric layer (44) is formed on the sidewalls of the rear trenches (79), the horizontal surfaces and sidewalls of the insulating layers (32), and portions of the sidewall surfaces of the memory stack structures (55) that are physically exposed to the rear recesses (43). A rear cavity (79') exists within each portion of the rear trench (79) that is not filled with the rear blocking dielectric layer (44).

[0088] In another example, an insulating spacer (74) may be formed in the surrounding area of ​​each rear trench (79) by conformal deposition of an insulating material (e.g., undoped silicate glass or doped silicate glass) and by an anisotropic etching process that removes horizontally extended portions of the insulating material. The remaining vertically extended tubular portions of the insulating material within each rear trench (79) constitute the insulating spacer (74).

[0089] Generally, forming insulating liners, insulating layers, or insulating spacers on the surfaces of the cavity is optional. In other words, such insulating liners, insulating layers, or insulating spacers may or may not be formed on the surfaces of the cavity.

[0090] Referring to FIG. 15c, FIG. 16c, and FIG. 18b, optional metal barrier liners (46A, 76A, 96A) may be conformally deposited on physically exposed surfaces of their respective cavities, which may be physically exposed surfaces of the rear blocking dielectric layer (44), physically exposed surfaces of the insulating spacer (74), or physically exposed surfaces of the contact via structure (83), which may include physically exposed surfaces of the reverse step dielectric material portion (65) of the flattening dielectric layer (770).

[0091] A metallic barrier layer (46A, 76A, 96A) may be deposited on physically exposed surfaces of each cavity. The metallic barrier layer (46A, 76A, 96A) may comprise an electrically conductive metallic material capable of functioning as a diffusion barrier layer and / or an adhesion-promoting layer for a metal (e.g., tungsten) to be subsequently deposited. The metallic barrier layer (46A, 76A, 96A) may comprise a conductive metallic nitride material, such as TiN, TaN, WN, or a stack thereof, or a conductive metallic carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer (46A, 76A, 96A) may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer (46A, 76A, 96A) may be in the range of 2 nm to 50 nm, e.g., 5 nm to 20 nm, but smaller and larger thicknesses may also be employed. In one embodiment, the metallic barrier layer (46A, 76A, 96A) may essentially be made of a conductive metal nitride such as TiN.

[0092] Referring to FIGS. 15d through 15f, FIGS. 16d through 16f, and FIGS. 18c through 18e, at least one metal deposition process may be performed. According to one embodiment of the present disclosure, the aforementioned metal fluoride gas and growth inhibitor gas are flowed into a process chamber simultaneously or alternately in one or more of at least one metal deposition processes. Each gas molecule of the metal fluoride gas comprises an elemental metal atom and a fluorine atom. Generally, the species of the elemental metal may be any metal capable of forming gaseous fluoride molecules. For example, the elemental metal may be selected from W, Mo, Ru, Rh, Re, Os, Ir, or Pt. In one embodiment, the elemental metal may be an element that forms a metal hexafluoride. In one embodiment, the elemental metal may be W.

[0093] In one embodiment, each molecule of the growth inhibitor gas may contain a growth inhibitor element selected from N and / or Cl. In this case, the atoms of the growth inhibitor element inhibit the attachment of fluorine atoms to the growth surface as discussed above with reference to FIGS. 14a through 14e and reduce the growth rate of the elemental metal on the growth surface. In one embodiment, the molecule of the growth inhibitor gas contains at least one chlorine atom and / or at least one nitrogen atom internally. In one embodiment, the growth inhibitor gas contains at least one chlorine atom. In one embodiment, the growth inhibitor gas contains a silicon-containing chloride gas selected from SiH3Cl, SiH2Cl2, SiHCl3, or SiCl4. In one embodiment, the growth inhibitor gas contains a boron-containing chloride gas selected from BH2Cl, BHCl2, or BCl3. In one embodiment, the growth inhibitor gas contains at least one nitrogen atom, such as N2 or NH3.

[0094] In each metal deposition process in which a metal fluoride gas and a growth inhibitor gas flow into a process chamber simultaneously or alternately, the metal fluoride gas is decomposed and atoms of the elemental metal contained in the metal fluoride gas are deposited on at least one surface of the cavity to form a metal layer (e.g., a tungsten layer). According to one aspect of the present disclosure, atoms of the growth inhibitor element (which may include chlorine or nitrogen atoms) are adsorbed onto the growth surface to inhibit the attachment of fluorine atoms from the metal fluoride gas, inhibit the attachment of the metal fluoride compound to atoms of the elemental metal on the growth surface, and reduce the growth rate of the elemental metal on the growth surface.

[0095] In one embodiment, the metal fluoride gas and the growth inhibitor gas may flow simultaneously into the process chamber for a certain period of time during the deposition process. In some embodiments, the initiation of the growth inhibitor gas flow into the process chamber occurs later than the initiation of the metal fluoride gas flow into the process chamber. In some other embodiments, the initiation of the growth inhibitor gas flow into the process chamber occurs simultaneously with the initiation of the metal fluoride gas flow into the process chamber. In one embodiment, the volume or flow rate of the growth inhibitor gas may comprise 10% or less, e.g., 5% or less, e.g., 1 to 5%, e.g., 2 to 4% of the respective volume or flow rate of the metal fluoride gas. In other words, the ratio of the volume or flow rate of the growth inhibitor gas to the respective volume or flow rate of the metal fluoride gas may be 0.1 or less to 1, e.g., 0.01 to 1 to 0.05 to 1.

[0096] Generally, a residual amount of a growth-inhibiting element may be incorporated into the deposited metal layer. In this case, the deposited metal layer comprises an elemental metal (e.g., tungsten) with an atomic concentration in the range of 97.0% to 99.99%, for example, 99.0% to 99.9%, and atoms of a growth-inhibiting element (e.g., Cl or N) with an atomic concentration in the range of 0.01% to 3.0%, for example, 0.1% to 1.0%.

[0097] In an exemplary example, the deposition process may include a nucleation process in which a nucleation layer (361) of elemental metal is nucleated on at least one surface of the cavity, a bulk-partial deposition process in which a bulk-filled portion (362) of the metal layer is deposited on the nucleation layer (361), and an optional terminal deposition process in which a capping portion (363) of the metal layer is formed. In the example illustrated in FIGS. 15d through 15f, the deposited metal layer may include a nucleation layer (46B1) of the metal filling material layer (46B), a bulk-filled portion (46B2) of the metal filling material layer (46B), and a capping portion (46B3) of the metal filling material layer (46B). In the examples illustrated in FIGS. 16d to 16f, the deposited metal layer may include a nucleation layer (76B1) of the metal filler material portion (76B), a bulk filler portion (76B2) of the metal filler material portion (76B), and a capping portion (76B3) of the metal filler material portion (76B). In the examples illustrated in FIGS. 18c to 18e, the deposited metal layer may include a nucleation layer (96B1) of the metal filler material portion (96B), a bulk filler portion (96B2) of the metal filler material portion (96B), and a capping portion (96B3) of the metal filler material portion (96B).

[0098] In one embodiment illustrated in FIGS. 15a through 15g, a metal layer (46B) is deposited on a structure comprising a memory device including a stack of insulating layers (32) spaced perpendicularly apart from each other by cavities (43), and memory opening filling structures (58) that extend vertically through each insulating layer within the stack of insulating layers, each comprising a memory film (50) and a vertical semiconductor channel (60). The metal layer (46B) is deposited into the cavities (43) to form word lines (46).

[0099] In other embodiments illustrated in FIGS. 16a through 16f, a metal layer (76B) is deposited on a structure comprising a memory device including memory opening filling structures (58) each comprising a memory film (50) and a vertical semiconductor channel (60), and two stacks of insulating layers (32) and electrically conductive layers (46) spaced laterally by a line trench (79). The metal layer (76) is deposited into the line trench (79).

[0100] In other embodiments illustrated in FIGS. 18a through 18f, a metal layer (96B) is deposited on a structure comprising at least one dielectric material portion (770) comprising a transistor (700) and a cavity (83) located on the transistor (700). The metal layer (96B) is deposited into the cavity (83).

[0101] In one embodiment, the deposition method comprises a chemical vapor deposition process, and the step of providing a metal fluoride gas and a growth inhibitor gas into a process chamber includes the step of simultaneously providing tungsten hexafluoride gas and a tungsten growth inhibitor gas into the process chamber to deposit a tungsten layer.

[0102] In another embodiment, the metal deposition process comprises an atomic layer deposition process in which a plurality of iterations of a unit process cycle are repeated. In one embodiment, the unit process cycle comprises at least a metal deposition step in which a metal fluoride gas is flowed into a process chamber and a reduction step in which hydrogen is flowed into a process chamber. Where the metal deposition process comprises a nucleation process, a bulk-partial deposition process, and a terminal deposition process, one, a plurality, or each of the nucleation process, the bulk-partial deposition process, and the terminal deposition process may comprise a respective atomic layer deposition process in which a plurality of iterations of their respective unit process cycles are repeated. In one embodiment, each unit process cycle comprises a reactant immersion step in which a metal fluoride gas is flowed into a process chamber and a reduction step in which hydrogen is flowed into a process chamber.

[0103] The conditions for the nucleation process, the bulk-partial deposition process, and the terminal deposition process may differ among the three processes. For example, in the nucleation process, a nucleation layer (361) of elemental metal is nucleated on at least one surface of the cavity as illustrated in FIG. 15d, FIG. 16d, and FIG. 18c. In one embodiment, the nucleation process comprises first iterations among a number of iterations of a unit process cycle. In the bulk-partial deposition process, a bulk filling portion (362) of the metal layer is deposited on the nucleation layer (361) of elemental metal. The bulk-partial deposition process may comprise second iterations among a number of iterations of a unit process cycle.

[0104] In one embodiment, the growth inhibitor gas is used during the nucleation process but not during the bulk filling process. In another embodiment, a higher proportion (e.g., a higher relative volume or flow rate) of the growth inhibitor gas is used during the nucleation process compared to during the bulk filling process. In these embodiments, the bulk-partial deposition process differs from the nucleation process in that there are more atoms of the growth inhibitor element incorporated into the nucleation layer (361) compared to the bulk filling portion (362). Thus, there is a gradient in the concentration of atoms of the growth inhibitor element (e.g., nitrogen and / or chlorine atoms) between the nucleation layer (361) and the bulk filling portion (362) of the metal (e.g., tungsten) layer. For example, the outer nucleation portion (361) of the metal (e.g., tungsten) layer (46, 76, 96, 86, 88) located closer to the walls of the cavity (43, 79, 83, 85, 87) containing the metal layer has a higher concentration of growth-inhibiting elements compared to the inner bulk filling portion (362) of the metal (e.g., tungsten) layer (46, 76, 96, 86, 88) located further from the walls of the cavity (43, 79, 83, 85, 87) than the outer nucleation portion (361). The concentration difference may include at least a 10% difference, e.g., a difference of 20% to 100%.

[0105] In this embodiment, the semiconductor structure comprises an active semiconductor device (e.g., a transistor (700) and / or a memory device including memory aperture filling structures), and a tungsten layer (46B, 76B, 96B) located in a cavity (43, 79, 83) within the semiconductor structure. The tungsten layer has at least one of chlorine or nitrogen atoms of different concentrations in a first portion (361) located closer to the cavity sidewalls compared to a second portion (362) located further from the cavity sidewalls. The tungsten layer also has fluorine atoms of different concentrations in a first portion (361) located closer to the cavity sidewalls compared to a second portion (362) located further from the cavity sidewalls. The amount of fluorine atoms increases in the opposite direction to the amount of at least one of chlorine or nitrogen atoms through the thickness of the tungsten layer.

[0106] In one embodiment, the concentration of at least one of a chlorine or nitrogen atom in the first portion located closer to the cavity sidewalls is greater than in the second portion located further away from the cavity sidewalls, and the concentration of a fluorine atom in the first portion located closer to the cavity sidewalls is lower than in the second portion located further away from the cavity sidewalls. In another embodiment, the concentration of at least one of a chlorine or nitrogen atom in the first portion located closer to the cavity sidewalls is lower than in the second portion located further away from the cavity sidewalls, and the concentration of a fluorine atom in the first portion located closer to the cavity sidewalls is greater than in the second portion located further away from the cavity sidewalls.

[0107] In one embodiment, the concentration of at least one of a chlorine or nitrogen atom in the first portion (361) located closer to the cavity sidewalls differs by at least 10 atomic percent compared to the second portion (362) located further away from the cavity sidewalls. The concentration of a fluorine atom in the first portion (361) located closer to the cavity sidewalls differs by at least 10 atomic percent compared to the second portion (362) located further away from the cavity sidewalls. In one embodiment, the atomic concentration of a chlorine atom in the tungsten layer is in the range of 0.01% to 3.0% and / or the atomic concentration of a nitrogen atom in the tungsten layer is in the range of 0.01% to 3.0%.

[0108] As described above, the controlled tungsten deposition process allows HF to be effectively purged during tungsten deposition. Thus, the fluorine concentration profile within the metal layer (e.g., tungsten layer) can change in the opposite direction to the growth-inhibiting element. In these embodiments, the bulk-partial deposition process differs from the nucleation process in that fewer fluorine atoms are incorporated into the nucleation layer (361) compared to the bulk-filled portion (362). Therefore, there is a gradient in the concentration of fluorine atoms between the nucleation layer (361) and the bulk-filled portion (362) of the metal (e.g., tungsten) layer. For example, the outer nucleation portion (361) of the metal (e.g., tungsten) layer (46, 76, 96, 86, 88) located closer to the walls of the cavity (43, 79, 83, 85, 87) containing the metal layer has a lower concentration of fluorine compared to the inner bulk filling portion (362) of the metal (e.g., tungsten) layer (46, 76, 96, 86, 88) located further from the walls of the cavity (43, 79, 83, 85, 87) than the outer nucleation portion (361). The difference in fluorine concentration may include at least a 10% difference, e.g., a difference of 20% to 100%.

[0109] In the deposition process, more growth-inhibiting elements are incorporated per unit area per surface monolayer of elemental metal during the nucleation process compared to during the bulk filling process. In other words, fewer atoms of growth-inhibiting elements can be adsorbed per unit area on the growth surface during the bulk-partial deposition process compared to during the nucleation process. The bulk-filled portion (362) of the metal layer can be deposited on the nucleation layer (361) during the bulk-partial deposition process as shown in FIGS. 15e, FIGS. 16e and FIGS. 18d.

[0110] In one embodiment, the metal deposition process further includes an optional terminal deposition process in which additional monolayers of the metal layer are deposited on the bulk-filled portion (362) of the metal layer. In one embodiment, the terminal deposition process may include third iterations among a plurality of iterations of a unit process cycle. In one embodiment, the terminal deposition process may differ from the bulk-partial deposition process in that the total number of incorporated atoms of the growth-inhibiting element per surface monolayer of the elemental metal per unit area is different. In other words, more or fewer atoms of the growth-inhibiting element may be adsorbed per unit area on the growth surface during the terminal deposition process compared to during the bulk-partial deposition process. The capping portion (363) of the metal layer may be deposited on the bulk-filled portion (362) during the terminal deposition process as illustrated in FIGS. 15f, FIGS. 16f, and FIGS. 18e.

[0111] Alternatively, the metal deposition process may comprise chemical vapor deposition in which a metal fluoride gas is flowed into the process chamber throughout the deposition stage, a growth inhibitor gas is flowed into the process chamber at least during the nucleation deposition stage, and then provided at a suspended or reduced flow rate during the bulk-partial deposition process and / or the capping deposition process to obtain a gradient distribution of nucleation inhibitor elements of the aforementioned metal layer. In another embodiment, the growth inhibitor gas may be flowed into the process chamber for the entire duration of the metal layer deposition. Alternatively, the growth inhibitor gas may be flowed into the process chamber intermittently with periodic or non-periodic stops in the flow of the growth inhibitor gas.

[0112] In one embodiment, the metal deposition process may include a nucleation process in which a nucleation layer (361) of elemental metal is nucleated on at least one surface of the cavity, and a bulk-partial deposition process in which a bulk-filled portion (362) of the metal layer is deposited on the nucleation layer of the elemental metal. In one embodiment, the ratio of the flow rate of metal fluoride gas to the flow rate of growth inhibitor gas in the bulk-partial deposition process is different from that in the nucleation process. In one embodiment, the metal deposition process may further include an optional terminal deposition process in which a capping portion (363) is deposited on the bulk-filled portion (362) of the metal layer. In one embodiment, the ratio of the flow rate of metal fluoride gas to the flow rate of growth inhibitor gas in the terminal deposition process is different from that in the bulk-partial deposition process.

[0113] The embodiments are described as having a higher chlorine and / or nitrogen concentration and a lower fluorine concentration in the outer nucleation portion (361) compared to the inner bulk filling portion (362) of the metal (e.g., tungsten) layer. In an alternative embodiment, a growth inhibitor gas may be used during the bulk filling process but may not be used during the nucleation process. In this alternative embodiment described below with respect to FIG. 21, a lower chlorine and / or nitrogen concentration and a higher fluorine concentration may be presented in the outer nucleation portion (361) compared to the inner bulk filling portion (362) of the metal (e.g., tungsten) layer.

[0114] Due to the difference in the fluorine and growth-inhibiting element concentration profiles between the internal bulk filling portion (362) of the metal (e.g., tungsten) layer (46, 76, 96, 86, 88) and the external nucleation portion (361) of the metal layer, the stress and / or grain size of the internal bulk filling portion (362) may differ from the stress and / or grain size of the external nucleation portion (361).

[0115] Referring to FIG. 15g, FIG. 18f, FIG. 11 and FIG. 13a through FIG. 13d, excess portions of the metal layer deposited outside the cavity can be removed as needed. For example, an etch back process employing an anisotropic etching process or an isotropic etching process may be employed to remove vertically extended portions of the metal layer outside horizontally extended cavities such as rear recesses (43). Alternatively, an etch back process or a chemical mechanical polishing (CMP) process may be employed to remove horizontally extended portions of the metal layer over vertically extended cavities such as rear trenches (79), drain contact via cavities (87), word line contact via cavities (85), and / or device contact via cavities (83).

[0116] Referring again to FIGS. 15a through 15g, the metal layer (46B) can be deposited into horizontally extended cavities (i.e., rear recesses (43)) located between insulating layers (32) that are spaced perpendicularly apart from each other by cavities. In this case, at least one surface of the cavity on which the metal layer is deposited and / or thereon may include the horizontal planes of adjacent pairs of insulating layers (32) and cylindrical surface segments of memory opening filling structures (58) (e.g., cylindrical surface segments of the outer wall of the rear blocking dielectric layer (52)). Suppression of the tungsten growth rate allows more time for tungsten deposition in the memory opening filling structures (58) located distal from the rear trench (79). As a result, a more uniform tungsten filling is achieved along the length of the rear recess (43), and defects (e.g., voids) caused by fluorine degassing are reduced.

[0117] Referring again to FIGS. 16a through 16f, the metal layer (76B) may be deposited into vertically extending cavities (i.e., rear trenches (79)) located between two stacks of the insulating layer (32) and the electrically conductive layer (46). In this case, at least one surface of the cavity on which the metal layer (76) is deposited and / or thereon comprises the sidewalls of the two stacks of the insulating layer (32) and the electrically conductive layer (46) that are physically exposed to the rear trench (79).

[0118] Referring again to FIGS. 17 and FIGS. 18a through 18f, the metal layer (96B) may be deposited into vertically extended cavities (83) located in at least one dielectric material portion (e.g., inversely stepped dielectric material portion (65)) located on the semiconductor device (700). In this case, at least one surface of the cavity on which the metal layer (83) is deposited and / or thereon comprises the top surface of the element of the semiconductor device (700) (e.g., active region, i.e., source / drain region or gate electrode) and the sidewall surface of the via cavity (83) of the at least one dielectric material portion (65).

[0119] In an embodiment where the metal deposition process includes an atomic layer deposition process, the unit process cycle may have various types of gas flow sequences. FIGS. 19a through 19d are exemplary gas flow sequences that may be employed in ALD processes according to one embodiment of the present disclosure. The ALD process includes a plurality of unit process cycles, each unit process cycle including a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step.

[0120] In one embodiment illustrated in FIG. 19a, a metal fluoride gas (e.g., WF6) and a growth inhibitor gas (e.g., inhibitor) are simultaneously flowed into a process chamber for a certain period of time during the deposition step. In one embodiment, the initiation of the flow of the growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber. The flow of the growth inhibitor gas and the metal fluoride gas may be simultaneously terminated before the initiation of the reduction step.

[0121] In another embodiment illustrated in FIG. 19b, hydrogen gas (H2) and growth inhibitor gas (e.g., inhibitor) are simultaneously flowed into the process chamber for a certain period of time during the reduction step. In one embodiment, the initiation of the flow of growth inhibitor gas into the process chamber occurs later than the initiation of the flow of hydrogen gas into the process chamber. The flow of growth inhibitor gas and hydrogen gas may be terminated simultaneously before the initiation of the tungsten deposition step. Thus, in this embodiment, when tungsten hexafluoride gas is flowed into the process chamber, the growth inhibitor gas may not be flowed into the process chamber.

[0122] In another embodiment illustrated in FIG. 19c, the metal fluoride gas, hydrogen gas (H2), and growth inhibitor gas (e.g., inhibitor) are flowed individually into the process chamber in separate stages. The flow of the growth inhibitor gas into the process chamber occurs between each of the unit process cycles. A reduction stage may follow the tungsten deposition stage, and a growth inhibitor gas flow stage may follow. The flow rate of the growth inhibitor gas may be lower than the flow rate of the tungsten hexafluoride gas.

[0123] In another embodiment illustrated in FIG. 19d, the growth inhibitor gas is provided into the process chamber during some, but not all, of the cycles. For example, FIG. 19d illustrates an embodiment in which a first unit process cycle comprising a first tungsten deposition step and a first reduction step is repeated N1 times without flowing the growth inhibitor gas during or between these cycles. However, the growth inhibitor gas is flowed during a second unit process cycle comprising a second tungsten deposition step and a second reduction step, which is repeated N2 times. For example, the growth inhibitor gas is flowed simultaneously with the tungsten hexafluoride gas during the second unit process cycle. The number of times (N1) may be in the range of 2 to 100, and the number of times (N2) may be in the range of 2 to 100, but a higher number may be employed for each of N1 and N2.

[0124] In another embodiment illustrated in FIG. 20, two different growth inhibitor gases may be used during different stages of the process of forming a metal (e.g., tungsten) layer. A first growth inhibitor gas may be used to control the initial reaction rate of tungsten deposition within the nucleation portion (361) of the tungsten layer, while a different second growth inhibitor gas may be used to control the reaction rate of tungsten deposition within the bulk filling portion (362) of the tungsten layer. In one aspect of this embodiment, ALD may be used to controllably deposit a smooth tungsten layer and to avoid irregular initial tungsten growth during the nucleation stage.

[0125] In the first deposition process, a nucleation portion (361) of a metal (e.g., tungsten) layer is deposited within the cavity. The nucleation portion (361) may be deposited using K1 ALD cycles. The number (K1) may be in the range of 2 to 100, but a higher number may be employed. Each of the K1 ALD cycles may include a metal (e.g., tungsten) deposition step by flowing a dose of metal fluoride gas (e.g., tungsten hexafluoride) into the process chamber, followed by a metal fluoride purging step. This is followed by a reduction step in which a hydrogen-containing gas, such as silane and / or diborane, is flowed into the process chamber. The growth inhibitor gas may be omitted during the K1 ALD cycles.

[0126] A growth inhibition step follows K1 ALD cycles. During the inhibition step, a first type of growth inhibitor gas is supplied into the process chamber. For example, nitrogen containing a growth inhibitor gas, such as N2 and / or NH3, is flowed into the process chamber, followed by a nitrogen-containing growth inhibitor gas purge step.

[0127] Following the growth inhibition step, a second deposition process follows in which a bulk filling portion (362) is deposited on the nucleation portion (361) of the metal layer. The bulk filling portion (362) may be deposited using K2 ALD cycles. The number (K2) may be in the range of 2 to 100, but a higher number may be employed. Each of the K2 ALD cycles may include a metal (e.g., tungsten) deposition step and a subsequent purging step by flowing a dose of metal fluoride gas (e.g., tungsten hexafluoride) and a second type of growth-inhibitor gas into a process chamber using any of the sequences described above for FIGS. 19a to 19d. The second type of growth inhibitor gas may include the aforementioned silicon and chlorine-containing gas (e.g., DCS) and / or a chlorine-containing gas such as the aforementioned boron and chlorine-containing gas. This is followed by a reduction step including the step of flowing hydrogen gas into the process chamber, and then a hydrogen gas purging step.

[0128] In another embodiment illustrated in FIG. 21, the nucleation portion (361) of the metal (e.g., tungsten) layer is omitted. Instead, hydrogen gas is used during an initial immersion step to inhibit the decomposition of the metal fluoride (e.g., tungsten hexafluoride) precursor. During the metal fluoride (e.g., tungsten hexafluoride) immersion step, the metal fluoride gas is introduced into the process chamber simultaneously (e.g., in a CVD process) or sequentially (e.g., in an ALD process) with hydrogen gas (e.g., H2 gas) and hydrogen-containing gas (e.g., silane and / or diborane). In an ALD process, a first purge step follows the metal fluoride immersion step, followed by a hydrogen gas and hydrogen-containing gas immersion step, followed by a second purge step.

[0129] Following the immersion step, a deposition process follows in which a bulk filling portion (362) is deposited into the cavity (e.g., directly onto the barrier liner (46A, 76A, or 96A)). The bulk filling portion (362) may be deposited using K2 ALD cycles. The number (K2) may be in the range of 2 to 100, but a higher number may be employed. Each of the K2 ALD cycles may include a metal (e.g., tungsten) deposition step and a subsequent purging step by flowing a dose of metal fluoride gas (e.g., tungsten hexafluoride) and a growth-inhibiting gas into the process chamber using any of the sequences described above for FIG. 19a to 19d. The growth inhibitor gas may include a nitrogen-containing gas (e.g., nitrogen or ammonia) or a chlorine-containing gas such as the aforementioned silicon and chlorine-containing gas (e.g., DCS) and / or the aforementioned boron and chlorine-containing gas. This is followed by a reduction step comprising the step of flowing hydrogen gas into a process chamber, followed by a hydrogen gas purge step.

[0130] FIGS. 22a through 22c illustrate a third exemplary sequence of processing steps according to one embodiment of the present disclosure. The third exemplary sequence differs from the first exemplary sequence in that a growth inhibitor gas is provided only between the formation of the nucleation portion (361) (e.g., 46B1, 76B1, 96B1) and the bulk filling portion (362) (e.g., 46B, 76B, 96B) of the metal layer (e.g., 46B, 76B, 96B). Molecules of the growth inhibitor gas (e.g., growth inhibitor element), such as chlorine and / or nitrogen, are located on the surface of the nucleation portion (361). The growth inhibitor gas may include a nitrogen-containing gas (e.g., nitrogen or ammonia) or a chlorine-containing gas such as the aforementioned silicon and chlorine-containing gas (e.g., DCS) and / or the aforementioned boron and chlorine-containing gas. However, the growth inhibitor gas may be omitted during the deposition of the bulk filling portion (362) (e.g., 46B, 76B, 96B) of the metal layer.

[0131] According to another embodiment, a growth-inhibitor surface treatment is provided on the barrier liner prior to the deposition of the metal layer to reduce the deposition rate of the metal layer in a subsequent deposition process. FIGS. 23a and 23b illustrate a fourth exemplary sequence of processing steps according to this embodiment of the present disclosure. After the barrier liner (46A, 76A, 96A) is formed in the cavity, a growth inhibitor gas is provided to the process chamber. Molecules of the growth inhibitor gas (e.g., growth inhibitor element), such as chlorine and / or nitrogen, are located on the surface of the barrier liner. The growth inhibitor element reduces the deposition rate of the metal layer (46B, 76B, 96B) on each barrier liner (46A, 76A, 96A). The growth inhibitor gas may be omitted or provided during the subsequent deposition of the metal layer (46B, 76B, 96B).

[0132] In this embodiment, a method for depositing an electrically conductive layer (46, 76, 96) comprises the steps of providing a structure having a cavity (43, 79, 83) inside, placing the structure in a process chamber, depositing a first portion (46A, 76A, 96A or 361) of the electrically conductive layer on at least one surface of the cavity, exposing the first portion of the electrically conductive layer to a tungsten growth inhibitor gas, and depositing a second portion (46B, 76B, 96B or 362) of the electrically conductive layer on the first portion of the electrically conductive layer by decomposition of tungsten hexafluoride.

[0133] In one embodiment illustrated in FIGS. 22a to 22c, the first portion of the electrically conductive layer comprises a tungsten nucleation portion (361) of the tungsten layer (46B, 76B, 96B), and the second portion of the electrically conductive layer comprises a tungsten bulk filling portion (362) of the tungsten layer (46B, 76B, 96B).

[0134] In another embodiment illustrated in FIG. 23a and FIG. 23b, a first portion of the electrically conductive layer comprises an electrically conductive barrier liner (46A, 76A, 96A), and a second tungsten portion of the electrically conductive layer comprises a tungsten layer (46B, 76B, 96B). The barrier liner (46A, 76A, 96A) comprises Ru, Mo, TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, TiC, TaC, WC, or a stack thereof.

[0135] According to one aspect of the present disclosure, apparatuses are provided for carrying out various deposition processes, dipping processes, and purging processes of metal layers of embodiments of the present disclosure as described above. FIG. 24 is a schematic diagram of a first exemplary apparatus (240) for implementing a deposition process according to one embodiment of the present disclosure. FIG. 25 is a schematic diagram of a second exemplary apparatus (250) for implementing a deposition process according to one embodiment of the present disclosure. FIG. 26 is a schematic diagram of a third exemplary apparatus (260) for implementing a deposition process according to one embodiment of the present disclosure. FIG. 27 is a schematic diagram of a fourth exemplary apparatus (270) for implementing a deposition process according to one embodiment of the present disclosure.

[0136] Referring collectively to FIGS. 24 through 27, each of the metal deposition apparatus comprises at least one metal deposition chamber (410, 510), which may be referred to as a "process chamber" in one embodiment. Each of the at least one metal deposition chamber (410, 510) is configured to receive at least one substrate (412) loaded therein and to deposit a metal layer (e.g., a tungsten layer) on each substrate (412) by flowing a metal fluoride gas therein during their respective deposition processes. Generally, each metal deposition chamber (410, 510) may be configured to perform any step of the metal deposition steps described with reference to FIGS. 15a through 23b of the present disclosure. Each metal deposition chamber (410, 510) may include an ALD or CVD deposition chamber. In one embodiment, the growth inhibitor gas may be provided into a metal deposition chamber (410, 510) as described above with respect to FIG. 19a, FIG. 19b, FIG. 19d, FIG. 20, or FIG. 21.

[0137] In another embodiment, the growth inhibitor gas may be supplied into a surface treatment chamber (420) separate from the metal deposition chamber (410, 510). In this embodiment, the process chamber may comprise a volume of a combination of the metal deposition chamber(s) (410, 510), the surface treatment chamber (420), and any optional transfer chambers (430) to which the wafer (412) can be accessed without breaking the vacuum. For example, the surface treatment chamber (420) may be connected to at least one metal deposition chamber (410, 510) via one or more load locks (422) or conduits of a multi-chamber vacuum processing unit (240, 250, 260, 270). One or more first gas tanks (416) are fluidically connected to the deposition chambers (410) and contain tungsten hexafluoride. One or more second gas tanks (426) are fluidically connected to the surface treatment chamber (420) and contain a tungsten growth inhibitor gas selected from SiH3Cl, SiH2Cl2, SiHCl3, SiCl4, N2, NH3, BH2Cl, BHCl2, or BCl3. Separate metal deposition chamber(s) (410, 510) and the surface treatment chamber (420) may be used to perform the methods described above with respect to FIG. 19c, FIG. 20, FIG. 22a to FIG. 22c or FIG. 23a and FIG. 23b.

[0138] A surface treatment chamber (420) is configured to accommodate a substrate (412) loaded therein and to expose the substrate (412) to a growth inhibitor gas to perform any of the aforementioned inhibition (e.g., growth inhibition) steps using the growth inhibitor gas. The molecules of the growth inhibitor gas may contain growth inhibitor elements such as nitrogen and / or chlorine, and atoms of the growth inhibitor elements are adsorbed onto the surface of the substrate (412). The surface treatment chamber (420) may include a single-wafer deposition chamber configured to load only a single substrate, or a multi-wafer chamber configured to load multiple substrates and perform a surface treatment process on multiple substrates.

[0139] Additionally, each of the metal deposition devices includes a process controller (480) configured to transfer each substrate (412) processed in a surface treatment chamber (420) to and / or from each of at least one metal deposition chamber (410, 510). The substrates (412) may be transferred between the various chambers (240, 250, 260, 270) of the device using a robot arm and / or a conveyor, as is known in the art.

[0140] In one embodiment, at least one metal deposition chamber (410) comprises a plurality of single wafer deposition chambers (410) within the apparatus (240) illustrated in FIG. 24. In one embodiment, each of the plurality of single wafer deposition chambers (410) may be configured to accommodate their own single substrate (412) and to deposit their own metal layer on their respective single substrate (412). A transfer chamber (430) equipped with at least one substrate-transfer robot arm (not shown) may be provided to facilitate transfer of substrates (412) from the surface treatment chamber (420) to the plurality of single wafer deposition chambers (410), and vice versa.

[0141] In another embodiment, at least one metal deposition chamber (410) comprises at least one multi-wafer deposition chamber (410), wherein each of the plurality of substrates (412) is loaded into different sub-chambers (414) within each metal deposition chamber (410) of the devices (250 or 260) as illustrated in FIG. 25 and 26. A transfer chamber (430) equipped with at least one substrate-transfer robot arm (not shown) may be provided to facilitate transfer of substrates from the surface treatment chamber (420) to the plurality of deposition chambers (410) in the device (250) as illustrated in FIG. 25, and vice versa. Alternatively, the surface treatment chamber (420) may be connected to each of the deposition chambers (410) via various load locks or conduits (422) and may function as a transfer chamber of the device (260) as illustrated in FIG. 26.

[0142] In another embodiment, at least one metal deposition chamber includes a furnace chamber (510) (or multiple furnace chambers (510)) in which a plurality of substrates (412) are stacked in a cassette. As illustrated in FIG. 27, the substrates may be stacked vertically on top of each other such that the regions of the plurality of substrates (412) overlap in a planar view (e.g., a top view), and the plurality of substrates (412) are spaced vertically apart from each other in the device (270).

[0143] The use of a growth inhibitor gas during the pre-deposition dipping step and / or during the deposition step reduces the deposition rate of metals (e.g., tungsten) derived from metal fluoride (e.g., tungsten hexafluoride) precursor gases and increases the conformability of the deposition profile of the deposited metal layer. The improved conformability of the deposition profile reduces the volume of voids in high aspect ratio cavities and reduces the seam effect of the deposited metal layer or metal parts. Fluorine trapping within the voids is reduced or eliminated, and the reliability of the devices can be improved by reducing fluorine-induced voids.

[0144] While the foregoing refers to specific preferred embodiments, it will be understood that the present disclosure is not so limited. It will come to those skilled in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present disclosure. Compatibility is presumed between all embodiments that are not alternatives. The word “comprise” or “include” considers all embodiments in which the word “consist essentially of” or the word “consist essentially of” replaces the word “comprise” unless otherwise explicitly stated. Where an embodiment employing a specific structure and / or configuration is exemplified in the present disclosure, it is understood that the present disclosure may be implemented with any other functionally equivalent compatible structures and / or configurations, unless such substitution is expressly prohibited or otherwise known to those skilled in the art as impossible. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

Claim 1 A method for depositing a metal, comprising: providing a structure into a process chamber; and providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, wherein the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and the at least one growth inhibitor gas comprises a chlorine-containing gas that inhibits the growth of tungsten. Claim 2 A method according to claim 1, wherein at least one growth inhibitor gas comprises a silicon-containing chloride gas. Claim 3 In paragraph 2, the method wherein at least one growth inhibitor gas is selected from the group consisting of SiH3Cl, SiH2Cl2, SiHCl3 and SiCl4. Claim 4 In claim 1, the method wherein the at least one growth inhibitor gas comprises a boron-containing chloride gas. Claim 5 In paragraph 4, the at least one growth inhibitor gas is BH2Cl, BHCl 12 A method selected from the group consisting of and BCl3. Claim 6 A method for depositing a metal, comprising the steps of: providing a structure into a process chamber; and providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, and wherein the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein the at least one growth inhibitor gas is not flowed into the process chamber during a first set of unit process cycles, and the at least one growth inhibitor gas is flowed into the process chamber during a second set of unit process cycles. Claim 7 A method for depositing metal, comprising the step of providing a structure into a process chamber; The method comprises the step of providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, and the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and each molecule of the at least one growth inhibitor gas comprises a growth inhibitor element selected from at least one of N and Cl, and an atom of the growth inhibitor element binds to tungsten on the growth surface to inhibit the attachment of fluorine atoms to the tungsten, and the A method for reducing the growth rate of the tungsten on the growth surface. Claim 8 A method for depositing metal, comprising the step of providing a structure into a process chamber; The method comprises the step of depositing the metal on the structure by providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, and the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and the step of depositing the metal comprises providing at least one of a silane and a diborane into the process chamber together with or after providing the tungsten hexafluoride into the process chamber, thereby forming a tungsten nucleation portion A method comprising: a step of depositing; and a step of depositing the tungsten bulk filling portion on the tungsten nucleation portion by providing the tungsten hexafluoride into the process chamber without providing at least one of the silane and diborane into the process chamber together with or after depositing the tungsten bulk filling portion. Claim 9 In claim 8, the step of depositing the tungsten nucleation portion comprises the step of depositing the tungsten nucleation portion on an electrically conductive barrier liner. Claim 10 A method for depositing metal, comprising the step of providing a structure into a process chamber; The method comprises the step of providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, and the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and the structure comprises a memory device comprising a stack of insulating layers spaced perpendicularly apart from each other by cavities, and memory opening filling structures each comprising a memory film and a vertical semiconductor channel and extending perpendicularly through each of the insulating layers within the stack of insulating layers. A method comprising, wherein the metal is deposited into the cavities to form word lines. Claim 11 A method for depositing metal, comprising the step of providing a structure into a process chamber; The method comprises the step of depositing the metal on the structure by providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and the structure comprises a memory device comprising memory aperture filling structures each comprising a memory film and a vertical semiconductor channel, and two stacks of insulating layers and electrically conductive layers spaced laterally by a line trench, and the metal comprises the line Method of settling into the trench. Claim 12 A method for depositing a metal comprises the steps of: providing a structure into a process chamber; and providing a metal fluoride gas and at least one growth inhibitor gas into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, and the at least one growth inhibitor gas comprises at least one of a nitrogen-containing gas and a gas containing a halogen other than fluorine, the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein during the tungsten deposition step, the initiation of the flow of the at least one growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber, and wherein the structure comprises at least one dielectric material portion comprising a transistor and a cavity located above the transistor, and wherein the metal is deposited into the cavity. Claim 13 A method for depositing a metal comprises the steps of: providing a structure into a process chamber; and providing a metal fluoride gas and two different growth inhibitor gases into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, the first growth inhibitor gas comprises a nitrogen-containing gas, and the second growth inhibitor gas comprises a gas containing a halogen other than fluorine, wherein the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein, during the tungsten deposition step, the initiation of the flow of the second growth inhibitor gas into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber. Claim 14 A method for depositing a metal comprises the steps of: providing a structure into a process chamber; and providing a metal fluoride gas and two different growth inhibitor gases into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, the first growth inhibitor gas comprises a nitrogen-containing gas, and the second growth inhibitor gas comprises a gas containing a halogen other than fluorine, and the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein the flow of the first growth inhibitor gas into the process chamber occurs during the reduction step. Claim 15 In paragraph 14, the flow of the second growth inhibitor gas into the process chamber occurs between each unit process cycle. Claim 16 A method for depositing a metal, comprising the steps of: providing a structure into a process chamber; and providing a metal fluoride gas and two different growth inhibitor gases into the process chamber to deposit the metal on the structure, wherein the metal comprises tungsten, the metal fluoride gas comprises tungsten hexafluoride, the first growth inhibitor gas comprises a nitrogen-containing gas, and the second growth inhibitor gas comprises a gas containing a halogen other than fluorine, wherein the method comprises an atomic layer deposition process comprising a plurality of unit process cycles, each unit process cycle comprising a tungsten deposition step, a tungsten hexafluoride purge step, a reduction step, and a reduction gas purge step, wherein the second growth inhibitor gas is not flowed into the process chamber during a first set of the unit process cycles, and the second growth inhibitor gas is flowed into the process chamber during a second set of the unit process cycles. Claim 17 A method for depositing an electrically conductive layer, comprising the steps of: providing a structure including a cavity inside; placing the structure in a process chamber; depositing a first portion of the electrically conductive layer on at least one surface of the cavity, wherein the first portion comprises at least one metallic barrier material selected from Ru, Mo, TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, TiC, TaC, or WC; and exposing the first portion of the electrically conductive layer to a gaseous environment containing a combination of the tungsten growth inhibitor gas and the metal fluoride gas by simultaneously and continuously flowing the tungsten growth inhibitor gas and the metal fluoride gas into the process chamber such that the flow rate of the tungsten growth inhibitor gas introduced into the process chamber and the flow rate of the metal fluoride gas introduced into the process chamber are simultaneously positive, thereby directly depositing a first tungsten portion on the at least one metallic barrier material while incorporating chlorine atoms into the first tungsten portion. A method comprising: a tungsten growth inhibitor gas comprising at least one chlorine-containing gas selected from SiH3Cl, SiH2Cl2, SiHCl3, SiCl4, BH2Cl, BHCl2, or BCl3; and a step of depositing a second tungsten portion of the electrically conductive layer on the first tungsten portion of the electrically conductive layer by decomposition of tungsten hexafluoride, wherein the first tungsten portion contains a higher concentration of chlorine atoms and a lower concentration of fluorine atoms compared to the second tungsten portion. Claim 18 delete Claim 19 In paragraph 17, the growth inhibitor gas is selected from BH2Cl, BHCl2, or BCl3. Claim 20 delete Claim 21 A method according to claim 17, wherein the initiation of the growth inhibitor gas flow into the process chamber occurs during the flow of the metal fluoride gas into the process chamber and after the initiation of the flow of the metal fluoride gas into the process chamber. Claim 22 delete Claim 23 delete Claim 24 In claim 17, the structure comprises a memory device comprising a stack of insulating layers spaced perpendicularly apart from each other by cavities, and memory opening filling structures each comprising a memory film and a vertical semiconductor channel and extending perpendicularly through each of the insulating layers within the stack of insulating layers, wherein the electrically conductive layer is deposited into the cavities to form word lines. Claim 25 In claim 17, the structure comprises a memory device comprising memory aperture filling structures each comprising a memory film and a vertical semiconductor channel, and two stacks of insulating layers and electrically conductive layers spaced laterally by a line trench, wherein the electrically conductive layer is deposited into the line trench. Claim 26 In claim 17, the structure comprises at least one dielectric material portion including a transistor and a cavity located above the transistor, and the electrically conductive layer is deposited into the cavity. Claim 27 A method for depositing an electrically conductive layer, comprising: providing a structure including a cavity therein; placing the structure in a process chamber; depositing a first portion of the electrically conductive layer on at least one surface of the cavity, wherein the first portion comprises at least one metallic barrier material selected from Ru, Mo, TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, TiC, TaC, or WC; and performing an atomic layer deposition process to directly deposit a first tungsten portion of the electrically conductive layer on the metallic barrier material, wherein the atomic layer deposition process comprises a first gas flow step of flowing a metal fluoride gas into the process chamber; a first purge step of purging the metal fluoride gas from the process chamber; and a gas combination into the process chamber such that the flow rate of a tungsten growth inhibitor gas introduced into the process chamber and the flow rate of hydrogen gas introduced into the process chamber are simultaneously positive to incorporate chlorine atoms into the first tungsten portion. A method comprising: a step of performing an atomic layer deposition process comprising a second gas flow step of simultaneously flowing a tungsten growth inhibitor gas and a hydrogen gas, wherein the tungsten growth inhibitor gas comprises at least one chlorine-containing gas selected from SiH3Cl, SiH2Cl2, SiHCl3, SiCl4, BH2Cl, BHCl2, or BCl3; and a step of depositing a second tungsten portion of the electrically conductive layer on the first tungsten portion of the electrically conductive layer by decomposition of tungsten hexafluoride without the tungsten growth inhibitor gas, wherein the first tungsten portion contains a higher concentration of chlorine atoms and a lower concentration of fluorine atoms compared to the second tungsten portion. Claim 28 delete Claim 29 In claim 27, the method comprises a growth inhibitor gas comprising a boron and chlorine-containing gas including BH2Cl, BHCl2, or BCl3. Claim 30 delete Claim 31 delete Claim 32 A method for depositing an electrically conductive layer, comprising: providing a structure including a cavity therein; placing the structure within a process chamber; depositing a first portion of the electrically conductive layer on at least one surface of the cavity, wherein the first portion comprises at least one metallic barrier material selected from Ru, Mo, TiN, TaN, WN, MoN, TiON, TiSiN, WCN, MoCN, TiC, TaC, or WC; and performing an atomic layer deposition process to directly deposit a first tungsten portion of the electrically conductive layer on the metallic barrier material, wherein the atomic layer deposition process comprises: a first gas flow step for flowing a metal fluoride gas into the process chamber; a first purge step for purging the metal fluoride gas from the process chamber; a second gas flow step for flowing hydrogen gas into the process chamber, initiated after the completion of the first purge step; a second purge step for purging the hydrogen gas from the process chamber; and a tungsten growth inhibitor gas introduced into the process chamber A step of performing an atomic layer deposition process, wherein the tungsten growth inhibitor gas is flowed into the process chamber to mix chlorine atoms into the first tungsten portion by making the flow rate positive, and wherein the third gas flow step initiated after the completion of the second purge step is included, and the tungsten growth inhibitor gas comprises at least one chlorine-containing gas selected from SiH3Cl, SiH2Cl2, SiHCl3, SiCl4, BH2Cl, BHCl2, or BCl3;A method comprising the step of depositing a second tungsten portion of the electrically conductive layer on the first portion of the electrically conductive layer by decomposition of tungsten hexafluoride, wherein the first tungsten portion contains chlorine atoms at a higher concentration and fluorine atoms at a lower concentration than the second tungsten portion, and the concentration of chlorine atoms is higher near the at least one surface of the cavity than far from the at least one surface of the cavity.; Claim 33 delete Claim 34 In paragraph 32, the method comprises a growth inhibitor gas comprising a boron and chlorine-containing gas including BH2Cl, BHCl2, or BCl3. Claim 35 delete Claim 36 A method according to claim 32, wherein the first portion of the electrically conductive layer comprises a tungsten nucleation portion of the tungsten layer, and the second portion of the electrically conductive layer comprises a tungsten bulk filling portion of the tungsten layer. Claim 37 delete Claim 38 delete Claim 39 delete Claim 40 delete Claim 41 delete Claim 42 delete Claim 43 delete Claim 44 delete Claim 45 delete Claim 46 delete Claim 47 delete Claim 48 delete Claim 49 delete Claim 50 delete Claim 51 delete Claim 52 delete Claim 53 delete Claim 54 delete Claim 55 delete Claim 56 delete Claim 57 delete Claim 58 delete Claim 59 delete Claim 60 delete

Images