Motor diagnostic circuit

Abstract

A diagnostic circuit according to the present embodiment may include a plurality of FETs for motor control; a first resistor connected in parallel between the gate-source terminals of any one of the plurality of FETs; and a control unit that detects an abnormality by determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected among the plurality of FETs.

Description

Technology Field

[0001] The present invention relates to a motor diagnostic circuit, and more specifically, to a circuit that individually diagnoses FETs controlling a motor. Background Technology

[0002] Recently, to increase energy efficiency, three-phase BLDC motors (Brushless DC motors) controlled by inverters are used in automobiles and home appliances. This is a motor that generates torque by switching the current flowing through the stator windings through the switching of electronic circuits using power switching semiconductor devices such as transistors, MOSFETs, and IGBTs, instead of brushes and commutators, which are important components of DC motors.

[0003] Compared to single-phase motors, BLDC motors are easier to control in terms of torque, have higher efficiency, and are advantageous in terms of noise, so most high-capacity motors are driven in three phases. In a three-phase BLDC motor, the U-phase, V-phase, and W-phase coils are arranged facing the permanent magnets of the rotor so that they have an electrical phase difference of 120 degrees. When the stator coils of each phase are selectively energized through a switching element, the rotor rotates due to the magnetic force between the cores that are magnetized accordingly and the magnetic poles of the permanent magnets.

[0004] The circuit controlling a 3-phase BLDC motor includes a High-side FET and a Low-side FET connected to three coils and implemented as a pair of bridge circuits. When diagnosing faults and verifying the function of the motor control circuit, there is a problem in that each FET cannot be verified individually in a bridge circuit consisting of six FETs. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a circuit that individually diagnoses FETs controlling a motor.

[0006] The problems of the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] To solve the above technical problem, the diagnostic circuit according to the present embodiment includes a plurality of FETs for motor control; a first resistor connected in parallel between the gate-source terminals of any one of the plurality of FETs; and a control unit that detects an abnormality by determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected among the plurality of FETs.

[0008] The control unit applies a first voltage to the gate terminal of the FET, measures the time it takes for the gate-source voltage of the FET connected to the first resistor among the plurality of FETs to reach a preset second voltage, and determines that an abnormality has occurred if the measured time is shorter than the preset first time.

[0009] The second voltage above may be smaller than the first voltage applied to the gate terminal of the FET in the control unit.

[0010] The above control unit can diagnose a FET that has an abnormality when the first resistor is connected as a normal FET, and diagnose a FET that has no abnormality when the first resistor is connected as an abnormal FET.

[0011] The first resistor may have a resistance value less than or equal to half of the second resistor connected in series to the gate terminal of the FET.

[0012] The first resistor may be optionally connected in parallel with any one of the third resistors connected between the gate-source terminals of each of the plurality of FETs.

[0013] The plurality of FETs includes three upper FETs and three lower FETs, and the control unit can detect an abnormality by selectively connecting the first resistor in parallel between the gate-source terminals of each of the three upper FETs and the three lower FETs.

[0014] The control unit diagnoses the FET that has an abnormality when the first resistor is connected as a normal FET, and diagnoses the FET that has no abnormality when the first resistor is connected as an abnormal FET. The control unit may operate the lower brake when at least one of the upper FETs is diagnosed as the abnormal FET, and operate the upper brake when at least one of the lower FETs is diagnosed as the abnormal FET.

[0015] The above control unit can diagnose whether it is normal by sequentially connecting the first resistor between the gate-source terminals of the plurality of FETs through a switch.

[0016] The above control unit can detect an abnormality by comparing the operation of the FET to which the first resistor is connected among the plurality of FETs with the operation of the remaining FETs.

[0017] A diagnostic method according to the present embodiment includes the step of connecting a first resistor in parallel to the gate-source terminal of any one of a plurality of FETs controlling a motor; and the step of determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected in parallel.

[0018] The step of determining whether there is a voltage drop between the gate and source of the FET in which the first resistor is connected in parallel may include: a step of measuring the time it takes for the voltage between the gate and source of the FET in which the first resistor is connected in parallel to reach a preset first voltage; and a step of determining that an abnormality has occurred if the measured time is shorter than a preset first time.

[0019] The step of determining whether there is a gate-source voltage drop of the FET in which the first resistor is connected in parallel can be performed by sequentially connecting the first resistor in parallel between the gate-source terminals of each of the plurality of FETs, and comparing the operation of the FET in which the first resistor is connected in parallel with the operation of the remaining FETs. Effects of the invention

[0020] According to the present embodiment, in a bridge circuit using six FETs to control a motor, each FET can be individually diagnosed for failure and verified for function, and through this, the FET that has a problem can be individually repaired or replaced.

[0021] In addition, since the diagnostic circuit requires one resistor that is selectively connected to six FETs, the circuit implementation can be relatively simple and inexpensive.

[0022] The effects according to the present invention are not limited to those exemplified above, and various other effects are included in this specification. Brief explanation of the drawing

[0023] Figure 1 shows a block diagram of a diagnostic circuit according to the present embodiment. FIG. 2 is a block diagram of a diagnostic circuit according to the present embodiment. FIG. 3 illustrates a part of the diagnostic circuit according to the present embodiment. FIG. 4 is a diagram illustrating the process of detecting abnormalities occurring during FET diagnosis using a diagnostic circuit according to the present embodiment. FIGS. 5 to 7 are flowcharts of a method for diagnosing through a diagnostic circuit according to the present embodiment. Specific details for implementing the invention

[0024] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0025] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0026] In addition, terms used in this embodiment (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which this embodiment belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0027] Furthermore, the terms used in this embodiment are for the purpose of describing the embodiment and are not intended to limit the invention.

[0028] In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as "at least one of A and B and C (or more than one)," it may include one or more of all combinations that can be formed from A, B, and C.

[0029] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present embodiment. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0030] And, where it is stated that a component is 'connected', 'combined', or 'connected' to another component, this may include not only cases where the component is directly 'connected', 'combined', or 'connected' to the other component, but also cases where it is 'connected', 'combined', or 'connected' due to another component located between the component and the other component.

[0031] Furthermore, when described as being formed or placed "above" or "below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above" or "below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0033] Hereinafter, a diagnostic circuit according to the present embodiment will be described with reference to FIGS. 1 to 4. FIGS. 1 and 2 illustrate block diagrams of a diagnostic circuit according to the present embodiment. FIG. 3 illustrates a part of the diagnostic circuit according to the present embodiment. FIG. 4 is a diagram for explaining the process of detecting an abnormality occurring during FET diagnosis using the diagnostic circuit according to the present embodiment.

[0034] The diagnostic circuit (100) according to the present embodiment includes a plurality of FETs (120) for controlling the motor (110).

[0035] A plurality of FETs (120) include an upper side (HS, High Side) FET and a lower side (LS, Low Side) FET. The upper side FET and the lower side FET receive a gate control signal to drive the motor. The gate terminals of the upper side FET and the lower side FET can receive a voltage or control signal from an electronic control unit (ECU). Through this, the upper side FET and the lower side FET can output a driving voltage to the driving coil of the motor (110).

[0036] Each of the upper FET and the lower FET can be connected to a three-phase motor. It may include first to third upper FETs and first to third lower FETs, each connected to the driving coils of the U-phase, V-phase, and W-phase of the three-phase motor. The first upper FET and the first lower FET may be connected to the driving coil of the U-phase in the form of a bridge circuit connected to each other, the second upper FET and the second lower FET may be connected to the driving coil of the V-phase in the form of a bridge circuit connected to each other, and the third upper FET and the third lower FET may be connected to the driving coil of the W-phase in the form of a bridge circuit connected to each other. A pair of bridge circuits consisting of the first upper FET and the first lower FET can output a driving voltage to the driving coil of the U-phase. A pair of bridge circuits consisting of the second upper FET and the second lower FET can output a driving voltage to the driving coil of the V-phase. A pair of bridge circuits consisting of a third upper FET and a third lower FET can output a driving voltage to the driving coil of the W phase.

[0037] In conventional fault diagnosis and functional verification of the six upper and lower FETs included in the motor control circuit, a specific timing called Tvdq was commonly set in the internal memory of the gate driver IC, and fault diagnosis or functional verification of the FETs was performed by determining whether the time taken to reach a preset voltage when a normal voltage is applied to the gate terminal exceeded the specific timing of Tvdq. In other words, for fault diagnosis, Tvdq was artificially shortened to induce a fault, and the FET with the fault was judged to be operating normally. This diagnostic method has a problem in that it cannot induce a fault in each FET individually because the shortened Tvdq is applied commonly to all six FETs. However, the diagnostic circuit according to the present embodiment can diagnose each FET individually, allowing for the determination of which FET is abnormal and enabling individual repair or replacement. Below, a configuration for individually diagnosing each FET through the diagnostic circuit according to the present embodiment will be described.

[0038] The diagnostic circuit (100) according to the present embodiment may include a first resistor (131) connected in parallel between the gate-source terminals of any one of the plurality of FETs (120).

[0039] More specifically, the first resistor (131) may be selectively connected in parallel between the gate-source terminals of any one of the plurality of FETs (120). The first resistor (131) may be connected in parallel between the gate-source terminals of any one of the plurality of FETs (120) by the control of the switch (150) of the control unit (140). The first resistor (131) and the FET to be fault-diagnosed may be connected to each other by closing the switch (150), and the switch (150) connected to the remaining FET may be opened. When the fault diagnosis of the FET connected to the first resistor (131) is completed, the first resistor (131) may be sequentially connected to the remaining FET.

[0040] Referring to FIGS. 1 and 2, a first resistor (131) and a switch (150) are each disposed on each of the plurality of FETs (120), but this is merely illustrative and is not specifically limited thereto. For example, the diagnostic circuit (100) may include only one first resistor (131) and the FET and the first resistor (131) may be selectively connected by controlling the on / off of the switch (150) connected to each FET.

[0041] When the first resistor (131) is connected in parallel between the gate-source terminals of the FET, the resistance value (Rgs) of the gate-source resistor can be reduced by the first resistor (131). When the resistance value of the gate-source resistor is reduced, the voltage across the gate terminal can be lowered by the voltage divider rule.

[0042] The diagnostic circuit (100) according to the present embodiment may include a control unit (140).

[0043] More specifically, the control unit (140) can detect an abnormality by determining whether there is a gate-source voltage drop of the FET to which the first resistor (131) is connected among the plurality of FETs (120). The control unit (140) can apply a first voltage, which is a normal voltage, to the gate terminal of the FET. The control unit (140) can apply the same first voltage to the gate terminals of the plurality of FETs (120). The control unit (140) can determine whether there is a gate voltage drop of the FET to which the first resistor (131) is connected, and can diagnose the abnormality by comparing the gate voltage of the FET to which the first resistor (131) is connected with the gate voltage of the FET not to which the first resistor (131) is connected.

[0044] The control unit (140) can detect that a fault has occurred when the gate voltage drops due to the first resistor (131) being connected to the FET. Here, the fault is an error artificially created to diagnose the fault and verify the function of the FET. Accordingly, the control unit (140) can diagnose the FET that has a fault due to the gate voltage dropping when the first resistor (131) is connected as a normal FET, and diagnose the FET that does not experience a voltage drop when the first resistor (131) is connected as an abnormal FET.

[0045] The control unit (140) sequentially connects the first resistor (131) to each FET and can store a bit of 1 for the FET in which an abnormality is detected and a bit of 0 for the FET in which no abnormality is detected. For example, when the first resistor (131) is connected in parallel to the first upper FET to diagnose a fault in the first upper FET and a first voltage, which is a normal voltage, is applied to six FETs, the first upper FET can be diagnosed as a normal FET by storing the bit of the first upper FET as 1 and the bit of the remaining FETs as 0. On the other hand, when the bit of the first upper FET is stored as 0 and no abnormality is detected, the first upper FET can be diagnosed as an abnormal FET. That is, for diagnosis, an abnormality can be detected by comparing the operation of the FET to which the first resistor (131) is connected with the operation of the remaining FETs.

[0046] The control unit (140) can operate the lower brake if at least one of the upper FETs is diagnosed as an abnormal FET through diagnosis, and can operate the upper brake if at least one of the lower FETs is diagnosed as an abnormal FET. If at least one of the multiple FETs is diagnosed as an abnormal FET, the entire brake can be operated. If any one of the upper FETs is diagnosed as an abnormal FET, it means that motor control by the upper FET is not possible, so the lower brake can be operated to stop the operation of the motor. Similarly, if any one of the lower FETs is diagnosed as an abnormal FET, it means that motor control by the lower FET is not possible, so the upper brake can be operated to stop the operation of the motor.

[0047] In other words, in conventional motor control circuit diagnostic methods, it was not possible to determine which FET had a problem, so both brakes were always activated to stop the motor drive. However, through this embodiment, the problematic FET can be identified individually, allowing the motor drive to be stopped with less fuel or energy.

[0048] Hereinafter, the resistance value of the first resistor (131) for FET diagnosis is described with reference to FIG. 3. Each FET may include a second resistor (132) connected in series to the gate terminal and a third resistor (133) connected in parallel with the second resistor (132). The first resistor (131) may be connected in parallel with the third resistor (133) between the second resistor (132) and the third resistor (133). The first resistor (131) may be connected in parallel with the third resistor (133) between the third resistor (133) and the gate terminal. The resistance value of the first resistor (131) may be designed to have a resistance value less than or equal to half the resistance value of the second resistor (132). The first resistor (131) has a resistance value less than half that of the second resistor (132), thereby significantly reducing the resistance value of the gate-source terminal resistance (Rgs), and thereby making it easy to detect or identify the voltage drop across the gate terminal.

[0049] Hereinafter, a diagnostic method using a diagnostic circuit will be described in detail with reference to FIG. 4. FIG. 4(a) may correspond to a case where no abnormality is detected in a normal FET where the first resistor (131) is not connected, or where no abnormality is detected in an abnormal FET where the first resistor (131) is connected. FIG. 4(b) may correspond to a case where an abnormality is detected in a normal FET where the first resistor (131) is connected.

[0050] The control unit (140) applies a first voltage (V1), which is a normal voltage, to the gate terminal of the FET, measures the time (T2) when the gate-source voltage of the FET reaches a preset second voltage (V2), and detects that an abnormality has occurred if the measured time (T2) is smaller than the preset first time (T1). Here, the preset second voltage (V2) may be a value smaller than the first voltage (V1), which is a normal voltage. For example, the second voltage (V2) may have a voltage value of -1V compared to the first voltage (V1). The preset first time (T1) may be Tvdq, which is a time commonly set in the internal memory of the gate driver IC as described above, or any time stored in the control unit (140).

[0051] As shown in FIG. 4(a), a normal FET in which the first resistor (131) is not connected or an abnormal FET in which the first resistor (131) is connected may not have any faults detected (No fault). A first voltage (V1), which is a normal voltage, is applied to the FET, and the time (T2) for reaching a second voltage (V2) that is smaller than the first voltage (V1) can be measured. If the measured time (T2) is smaller than a preset time (T1), it can be detected that no fault has occurred. A plurality of FETs (120) can be determined to be normal through the fact that no fault is detected in the FET in which the first resistor (131) is not connected and that a fault is detected in the FET in which the first resistor (131) is connected. An abnormal FET can be diagnosed through the fact that no fault is detected in the FET in which the first resistor (131) is connected.

[0052] As shown in FIG. 4(b), a fault may be detected in a normal FET connected to the first resistor (131). In the FET connected to the first resistor (131), a voltage drop between the gate and source occurs due to a decrease in resistance between the gate and source terminals. Consequently, even if a normal voltage, the first voltage (V1), is applied to the FET, it may not reach the first voltage (V1) and the second voltage (V2), and the time to reach the second voltage (V2) may exceed a preset time (T1). In this case, the control unit (140) may detect that a fault has occurred, and accordingly, the FET connected to the first resistor (131) may be diagnosed as a normal FET.

[0054] FIGS. 5 to 7 are flowcharts of a method for diagnosing using a diagnostic circuit according to the present embodiment. Since the detailed description of each step in FIGS. 5 to 7 corresponds to the detailed description of the diagnostic circuit in FIGS. 1 to 4, the redundant description will be omitted.

[0055] The FET diagnosis method using a diagnosis circuit according to the present embodiment includes the steps of: connecting a parallel resistor to the gate-source terminal of one of a plurality of FETs (S10); determining whether there is a voltage drop between the gate and source of the FET connected to the resistor (S20); diagnosing whether each FET is normal through the voltage drop (S30); and if there is an undiagnosed FET among the plurality of FETs, returning to S10 to diagnose the FET, and if there is no undiagnosed FET, terminating the diagnosis (S40).

[0056] The step (S20) of determining whether there is a gate-source voltage drop of the FET connected to the resistor may specifically include a step (S21) of measuring the time it takes for the gate-source voltage of the FET connected to the resistor to reach a preset first voltage, and a step (S22) of determining whether the measured time is smaller than the preset first time. Additionally, it may include a step (S23) of comparing the operation of the FET connected to the resistor with the operation of the remaining FET not connected to the resistor.

[0057] In this way, since fault diagnosis and functional verification of each FET can be performed individually, it is not necessary to replace all six FET bridge circuits included in the motor control circuit, and individual repair or replacement of the problematic FET is possible. In addition, since motor driving can be controlled through FETs other than the problematic one among the upper or lower FETs, relatively less energy can be consumed.

[0059] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0060] 100: Diagnostic circuit 110: Motor 120: Multiple FETs 131: First resistor 132: Second resistor 133: Second resistor 140: Control unit 150: Switch

Claims

Claim 1 A diagnostic circuit comprising: a plurality of FETs for motor control; a first resistor connected in parallel between the gate-source terminals of any one of the plurality of FETs; and a control unit that detects an abnormality by determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected among the plurality of FETs, wherein the first resistor is selectively connected in parallel with any one of the third resistors connected between the gate-source terminals of each of the plurality of FETs. Claim 2 A diagnostic circuit according to claim 1, wherein the control unit applies a first voltage to the gate terminal of the FET, measures the time it takes for the gate-source voltage of the FET connected to the first resistor among the plurality of FETs to reach a preset second voltage, and determines that an abnormality has occurred if the measured time is shorter than the preset first time. Claim 3 In paragraph 2, the second voltage is a diagnostic circuit that is smaller than the first voltage applied to the gate terminal of the FET in the control unit. Claim 4 In claim 1, the control unit is a diagnostic circuit that diagnoses an FET with an abnormality as a normal FET when the first resistor is connected, and diagnoses an FET without an abnormality as an abnormal FET when the first resistor is connected. Claim 5 In paragraph 2, the first resistor is a diagnostic circuit having a resistance value less than or equal to half the resistance of the second resistor connected in series to the gate terminal of the FET. Claim 6 A diagnostic circuit comprising: a plurality of FETs for motor control; a first resistor connected in parallel between the gate-source terminals of any one of the plurality of FETs; and a control unit that detects an abnormality by determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected among the plurality of FETs, wherein the plurality of FETs includes three upper FETs and three lower FETs, and the control unit selectively connects the first resistor in parallel between the respective gate-source terminals of the three upper FETs and the three lower FETs to detect an abnormality. Claim 7 In claim 1, the plurality of FETs includes three upper FETs and three lower FETs, and the control unit is a diagnostic circuit that detects an abnormality by selectively connecting the first resistor in parallel between the gate-source terminals of each of the three upper FETs and the three lower FETs. Claim 8 In claim 7, the control unit diagnoses the FET that has an abnormality when the first resistor is connected as a normal FET, and diagnoses the FET that has no abnormality when the first resistor is connected as an abnormal FET, and the control unit activates the lower brake when at least one of the upper FETs is diagnosed as the abnormal FET, and activates the upper brake when at least one of the lower FETs is diagnosed as the abnormal FET. Claim 9 In claim 1, the control unit is a diagnostic circuit that diagnoses normality by sequentially connecting the first resistor between the gate-source terminals of the plurality of FETs through a switch. Claim 10 In claim 1, the control unit is a diagnostic circuit that detects an abnormality by comparing the operation of the FET to which the first resistor is connected among the plurality of FETs with the operation of the remaining FETs. Claim 11 A diagnostic method comprising: a step of connecting a first resistor in parallel to the gate-source terminal of any one of a plurality of FETs controlling a motor; and a step of determining whether there is a voltage drop between the gate and source of the FET to which the first resistor is connected in parallel, wherein the first resistor is selectively connected in parallel with any one of a third resistor connected between the gate-source terminals of each of the plurality of FETs. Claim 12 A diagnostic method according to claim 11, wherein the step of determining whether there is a gate-source voltage drop of the FET in which the first resistor is connected in parallel comprises: a step of measuring the time it takes for the gate-source voltage of the FET in which the first resistor is connected in parallel to reach a preset first voltage; and a step of determining that an abnormality has occurred if the measured time is shorter than a preset first time. Claim 13 In claim 11, the step of determining whether there is a gate-source voltage drop of the FET in which the first resistor is connected in parallel is a diagnostic method in which the first resistor is sequentially connected in parallel between the gate-source terminals of each of the plurality of FETs, and the operation of the FET in which the first resistor is connected in parallel is compared with the operation of the remaining FETs.

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