Fabricating method for power semiconductor device and power semiconductor device thereof

Abstract

One embodiment of the present disclosure relates to a method for manufacturing a power semiconductor device and a semiconductor device according thereto, wherein by forming an electric field concentration mitigation layer on the lower part of a gate oxide, the phenomenon of electric field concentration under the gate oxide when a reverse voltage is applied between the source and the drain can be mitigated, thereby improving the reliability of the power semiconductor device and maintaining low on-resistance and high breakdown voltage. For example, a method for manufacturing a power semiconductor device is disclosed, comprising the steps of: preparing a SiC substrate of a first conductivity type; forming at least one SiC epitaxial layer of the first conductivity type on the SiC substrate; forming at least one floating island-shaped electric field concentration relaxation layer inside the SiC epitaxial layer; forming a second conductivity type base region inside the SiC epitaxial layer; forming a first conductivity type region on top of the second conductivity type base region; forming a second conductivity type well region on the SiC epitaxial layer and forming a trench on the upper side of the electric field concentration relaxation layer; forming a gate region in the trench; forming an insulating layer covering the upper side of the gate region and a contact region exposing the first conductivity type region and the second conductivity type well region; forming a source electrode in the contact region and forming a drain electrode on the lower side of the SiC substrate.

Description

Technology Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide (SiC) power semiconductor device and a SiC power semiconductor device according to the same. Background Technology

[0002] Generally, power devices are semiconductor devices that convert or control power, and have progressed in terms of high voltage, high current, high speed, and high frequency. Recently, however, MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), and power integrated circuits (ICs) have become the center of power devices.

[0003] These high-power semiconductor devices (MOSFETs or IGBTs) must have high breakdown voltage and low on-resistance values ​​in DC characteristics, and fast switching speed (i.e., low switching loss value) in AC characteristics. The on-resistance value of high-power semiconductor devices is largely composed of channel resistance, JFET resistance, accumulation resistance, and epitaxial resistance (or drift resistance) components, and as the rated voltage increases, the epitaxial resistance component accounts for most of the total on-resistance value.

[0004] In addition, high-power semiconductor devices require higher breakdown voltage values ​​as the rated voltage increases; therefore, the thickness and resistivity of the epitaxial region must be increased to meet this requirement, which inevitably leads to an increase in the on-resistance of the epitaxial region. Consequently, there is a trade-off relationship between low on-resistance and high breakdown voltage values ​​in high-power semiconductor devices, and this must be taken into account when designing high-power semiconductor devices.

[0005] Meanwhile, SiC is being applied as a substrate for power devices due to its superior properties compared to Si, such as a lower intrinsic carrier concentration, high dielectric breakdown characteristics, high thermal conductivity, and a large electron flow rate.

[0006] Accordingly, research and development of power semiconductor devices using silicon carbide (SiC), which can replace existing silicon (Si) semiconductor devices, are actively underway. Silicon carbide (SiC) is a wide-gap semiconductor material with a higher bandgap than silicon. Silicon carbide has a much higher dielectric breakdown electric field than silicon and high thermal conductivity, providing superior stability compared to silicon-based devices even at high temperatures and voltages.

[0007] SiC Trench MOSFETs utilize a trench structure, which allows for easy control of high power by connecting multiple units in parallel. As such, they are utilized as power devices capable of conducting high power while maintaining high operating speeds. In this type of trench-structured SiC MOSFET, a channel is formed in the surrounding sidewalls; to achieve this, a gate insulating film is formed on the trench sidewalls, and a gate is formed in the trench. In other words, SiC MOSFETs using a trench structure utilize a trench gate to densely pack the channel, thereby reducing resistance and decreasing the gate area to increase switching speed, which can improve device performance and reduce costs.

[0008] However, SiC Trench MOSFETs suffer from a phenomenon where the electric field is concentrated beneath the gate insulating layer. This high electric field makes the gate oxide layer susceptible to degradation, resulting in a problem of poor reliability. Furthermore, while this was not an issue with conventional Si because the insulating layer's Ec was higher than Si's critical electric field (Ec), SiC, being a wide band gap material, has an Ec level equivalent to that of the insulating layer, which can lead to the breakdown of the gate insulating layer and potentially compromise device stability.

[0009] The information described above disclosed in the background technology of this invention is intended only to enhance understanding of the background of the present invention and may therefore include information that does not constitute prior art. The problem to be solved

[0010] The present disclosure provides a method for manufacturing a power semiconductor device and a power semiconductor device according thereto, which can improve the reliability of the semiconductor device by mitigating the phenomenon of electric field concentration under the gate oxide film when a reverse voltage is applied between the source and the drain, and can maintain low on-resistance and high breakdown voltage. means of solving the problem

[0011] A method for manufacturing a power semiconductor device according to an embodiment of the present disclosure may include the steps of: preparing a SiC substrate of a first conductivity type; forming at least one SiC epitaxial layer of the first conductivity type on the SiC substrate; forming at least one floating island-shaped electric field concentration mitigation layer inside the SiC epitaxial layer; forming a second conductivity type base region inside the SiC epitaxial layer; forming a first conductivity type region on top of the second conductivity type base region; forming a second conductivity type well region on the SiC epitaxial layer and forming a trench on the upper side of the electric field concentration mitigation layer; forming a gate region in the trench; forming an insulating layer covering the upper side of the gate region and a contact region exposing the first conductivity type region and the second conductivity type well region; forming a source electrode in the contact region and forming a drain electrode on the lower side of the SiC substrate.

[0012] The above trench can be formed by etching the first conductivity type region, the second conductivity type base region, and a part of the SiC epitaxial layer.

[0013] The electric field concentration relaxation layer can be formed to be located at a set depth from the upper surface of the second conductivity type base region within the SiC epitaxial layer.

[0014] The above trench can be formed on top of the at least one electric field concentration relaxation layer by etching a width wider than the total width of the at least one electric field concentration relaxation layer.

[0015] The gate region may include a gate insulating film formed on the inner wall of the trench and a gate electrode formed by depositing polysilicon on the inner side of the gate insulating film.

[0016] The second conductivity type well region can be formed from the upper part of the second conductivity type base region to the upper part of the SiC epitaxial layer.

[0017] A barrier metal formed on the upper portion of the first conductive region and the second conductive well region is formed in the contact region, and the source electrode may be formed to cover the upper portion of the barrier metal and the insulating layer.

[0018] When the above SiC epitaxial layer is formed as two layers, the SiC epitaxial layer may include a first SiC epitaxial layer of a first conductivity type formed on the SiC substrate and a second SiC epitaxial layer of a first conductivity type formed on the upper part of the first SiC epitaxial layer.

[0019] The electric field concentration relaxation layer can be formed on the upper side of the interior of the first SiC epitaxial layer.

[0020] The second conductive base region can be formed inside the second SiC epitaxial layer.

[0021] The thickness of the second SiC epitaxial layer can correspond to a set depth from the upper surface of the second conductive base region at the location of the electric field concentration relaxation layer formed inside the first SiC epitaxial layer.

[0022] Additionally, a power semiconductor device according to an embodiment of the present disclosure may include a first conductivity type SiC substrate, a first conductivity type SiC epitaxial layer formed as at least one layer on top of the SiC substrate, at least one floating island-shaped electric field concentration mitigation layer formed inside the SiC epitaxial layer, a second conductivity type base region formed inside the SiC epitaxial layer, a first conductivity type region formed on top of the second conductivity type base region, a second conductivity type well region formed from the upper surface of the first conductivity type region to the upper surface of the second conductivity type base region, a gate region formed inside the trench and on the upper side of the electric field concentration mitigation layer, an insulating layer covering the upper surface of the gate region, a source electrode formed on the surface of the first conductivity type region and the second conductivity type well region, and a drain electrode formed on the lower surface of the SiC substrate.

[0023] The above trench can be formed by etching the first conductivity type region, the second conductivity type base region, and a part of the SiC epitaxial layer.

[0024] The electric field concentration relaxation layer can be formed to be located at a set depth from the upper surface of the second conductivity type base region within the SiC epitaxial layer.

[0025] The above trench can be formed on top of the at least one electric field concentration relaxation layer by etching a width wider than the total width of the at least one electric field concentration relaxation layer.

[0026] The gate region may include a gate insulating film formed on the inner wall of the trench and a gate electrode formed by depositing polysilicon on the inner side of the gate insulating film.

[0027] A barrier metal is formed on the upper portion of the first conductivity type region and the second conductivity type well region, and the source electrode can be formed to cover the upper portion of the barrier metal and the insulating layer.

[0028] When the above SiC epitaxial layer is formed as two layers, the SiC epitaxial layer may include a first SiC epitaxial layer of a first conductivity type formed on the SiC substrate and a second SiC epitaxial layer of a first conductivity type formed on the upper part of the first SiC epitaxial layer.

[0029] The electric field concentration relaxation layer can be formed on the upper side of the interior of the first SiC epitaxial layer.

[0030] The second conductive base region can be formed inside the second SiC epitaxial layer.

[0031] The thickness of the second SiC epitaxial layer can correspond to a set depth from the upper surface of the second conductive base region at the location of the electric field concentration relaxation layer formed inside the first SiC epitaxial layer. Effects of the invention

[0032] A method for manufacturing a power semiconductor device according to one embodiment of the present disclosure and a semiconductor device according thereto can mitigate the phenomenon of electric field concentration under the gate oxide film when a reverse voltage is applied between the source and the drain by forming an electric field concentration mitigation layer on the lower part of the gate oxide film. Accordingly, the reliability of the power semiconductor device can be improved, and low on-resistance and high breakdown voltage can be maintained.

[0033] In addition, the method for manufacturing a power semiconductor device according to one embodiment of the present disclosure and the semiconductor device according thereto can prevent the destruction of the oxide film by forming a P+ layer under the gate oxide film and dispersing the electric field concentrated on the gate oxide film, thereby preventing the destruction of the oxide film by applying a high electric field to the gate oxide film, and thus can improve the reliability of the SiC MOSFET.

[0034] In addition, the method for manufacturing a power semiconductor device according to one embodiment of the present disclosure and the semiconductor device according thereto can improve breakdown voltage (BV) and device stability by forming a P layer at the lower edge of the gate oxide film in a conventional structure using a trench gate, thereby dispersing the electric field that may be concentrated at the edge of the gate oxide film to the P layer and preventing breakdown of the gate oxide film.

[0035] In addition, the method for manufacturing a power semiconductor device according to one embodiment of the present disclosure and the semiconductor device according thereto can obtain the effect of reducing conduction resistance by adding an N-layer to a JFET region with increased resistance. Brief explanation of the drawing

[0036] FIG. 1 is a flowchart illustrating a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure. FIGS. 2a to 2i are cross-sectional views sequentially illustrating a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure. FIG. 3 is a flowchart illustrating a method for manufacturing a power semiconductor device according to another embodiment of the present invention. FIGS. 4a to 4d are cross-sectional views sequentially illustrating a method for manufacturing a power semiconductor device according to another embodiment of the present invention. Specific details for implementing the invention

[0037] The embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art.

[0038] Additionally, in the drawings below, the thickness or size of each layer is exaggerated for convenience and clarity of explanation, and like reference numerals in the drawings refer to like elements. As used herein, the term "and / or" includes any one of the listed items and all combinations of one or more thereof. Furthermore, in this specification, the meaning of "connected" refers not only to cases where Member A and Member B are directly connected, but also to cases where Member C is interposed between Member A and Member B so that Member A and Member B are indirectly connected.

[0039] The terms used herein are for describing specific embodiments and are not intended to limit the invention. As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Additionally, as used herein, "comprise, include" and / or "comprising, including" specify the presence of the mentioned features, numbers, steps, actions, parts, elements, and / or groups thereof, and do not exclude the presence or addition of one or more other features, numbers, actions, parts, elements, and / or groups.

[0040] Although terms such as "first," "second," etc. are used in this specification to describe various components, parts, regions, layers, and / or parts, it is obvious that these components, parts, regions, layers, and / or parts should not be limited by these terms. These terms are used solely to distinguish one component, part, region, layer, or part from another region, layer, or part. Accordingly, the first component, part, region, layer, or part described below may refer to the second component, part, region, layer, or part without departing from the teachings of the present invention.

[0041] Spatial terms such as "beneath," "below," "lower," "above," and "upper" may be used to facilitate understanding of one element or feature depicted in the drawings and another element or feature. These spatial terms are intended to facilitate understanding of the invention according to various process or usage conditions of the invention and are not intended to limit the invention. For example, if an element or feature in the drawings is inverted, an element or feature described as "beneath" or "below" becomes "upper" or "on top." Therefore, "beneath" is a concept that encompasses "upper" or "below."

[0042] Hereinafter, a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure will be described.

[0043] FIG. 1 is a flowchart illustrating a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure, and FIG. 2a to 2i are cross-sectional views sequentially illustrating a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure.

[0044] Referring to FIG. 1, a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure may include a SiC substrate preparation step (S1), a SiC epitaxial layer formation step (S2), an electric field concentration relaxation layer formation step (S3), a second conductivity type base region formation step (S4), a first conductivity type region formation step (S5), a second conductivity type well region formation step (S6), a gate region formation step (S7), an insulating layer formation step (S8), and an electrode formation step (S9).

[0045] As illustrated in FIG. 2a, in the SiC substrate preparation step (S1), a SiC substrate (110) of a first conductivity type can be prepared. This SiC substrate (110) can be formed in a plate-like shape including an upper surface and a lower surface. The SiC substrate (110) may, for example, be an N+ type SiC substrate formed by injecting impurities such as nitrogen (N) and phosphorus (P), which are group 5 elements, into a silicon carbide (SiC) substrate at a high concentration. Additionally, for example, 4H or 6H-SiC may be used for the SiC substrate (110).

[0046] Next, in the epitaxial layer formation step (S2), an epitaxial layer (120) of a first conductivity type may be formed on the upper surface of the SiC substrate (110). For example, at a high temperature of 600 to 2000°C, a gas containing a hydrocarbon such as monomethylsilane or silane and propane, and a gas containing a pentavalent element such as nitrogen (N) and phosphorus (P) may be flowed together at a low concentration on the upper surface of the SiC substrate (110), thereby allowing an N-type epitaxial layer (120) to be deposited on the surface of the SiC substrate (110). The epitaxial layer (120) formed at this time may be used and designated as a single or multilayer semiconductor layer. That is, in one embodiment, at least one epitaxial layer (120) of a first conductivity type may be formed on the SiC substrate (110).

[0047] As shown in FIG. 2b, in the electric field concentration relaxation layer formation step (S3), at least one floating island-shaped electric field concentration relaxation layer (122) may be formed inside the SiC epitaxial layer (120).

[0048] First, an oxide film (Hard Mask, 121) can be deposited on the upper surface of the SiC epitaxial layer (120) in an area other than where the electric field concentration relaxation layer (122) is formed, and used as a Hard Mask. Then, a P+ type electric field concentration relaxation layer (122) can be formed by a process of directly ion-implanting aluminum (Al) impurities into the interior from the upper surface of the SiC epitaxial layer (120) where the oxide film (121) is not formed. That is, in one embodiment, the electric field concentration relaxation layer (122) can be formed to be located at a set depth from the upper surface of the second conductivity type base region (130) to be described later within the SiC epitaxial layer (120).

[0049] The oxide film (121) may be formed from any one selected from silicon oxide, nitrogen oxide, undoped polysilicon, PSG (Phospho-Silicate-Glass), BPSG (Boro-Phosphor-Silicate-Glass), or equivalents thereof, but is not limited thereto. At this time, the oxide film may be made of TEOS (Tetraethyl orthosilicate) and may have a thickness of 15,000 to 30,000 Å. After hard mask deposition, the region to be Floating P+ Ion Implanted may be oxide etched through a photo process. In one embodiment, the oxide etching method may use dry etching and may over-etch the oxide to be etched. Floating P+ can be formed by ion implanting aluminum (Al) impurities into the SiC epitaxial layer (120). At this time, the ion implantation energy must be high so that the thickness of the hard mask on the surface is sufficiently secured, and it must be prevented from penetrating the mask and implanting ions into unwanted areas with a high concentration of ion implant source. Once ion implantation is complete, the oxide used as the hard mask can be etched using wet etching. At this time, sufficient over-etching can be performed so that no residual oxide remains. The Floating P+ for field concentration relief, i.e., the field concentration relief layer (122), can be formed in the form of floating islands, and as shown in the drawing, it can be formed in three, but the number and shape are not limited.

[0050] This electric field concentration mitigation layer (122) is formed below the gate insulating film (151) described later, and can mitigate the phenomenon of electric field concentration below the gate insulating film (151) when a reverse voltage is applied between the source and the drain.

[0051] As illustrated in FIG. 2c, in the step (S4) of forming a second conductivity base region, a second conductivity base region (130) may be formed inside the SiC epitaxial layer (120). The second conductivity base region (130) may be formed to a certain depth from the upper surface of the SiC epitaxial layer (120) toward the interior. This second conductivity base region (130) may be located between the first conductivity region (140) described later and the SiC epitaxial layer (120). Additionally, the second conductivity base region (130) may be formed to cover the entire upper surface of the SiC epitaxial layer (120). This second conductivity base region (130) may be formed to have a P-type through a process of directly ion-implanting aluminum (Al) impurities into the SiC epitaxial layer (120).

[0052] In addition, when forming the second conductivity type base region (130), an oxide film (Hard Mask, not shown) can be deposited and used as a hard mask. At this time, the oxide film can be made of TEOS and can have a thickness of 15,000 to 30,000 Å. After the hard mask deposition, the oxide can be etched in the region to be P-body Ion Implanted through a photolithography process. The oxide etching method uses dry etching and can be over-etched compared to the thickness of the oxide to be etched. The second conductivity type region, i.e., the P-body, can be formed through a process of ion implanting aluminum (Al) impurities into the SiC epitaxial layer (120). At this time, the ion implantation energy is high so that the thickness of the hard mask on the surface must be sufficiently secured, and it must be prevented from a high concentration of ion implantation source penetrating the mask and implanting ions into unwanted areas. Once the ion implantation is completed, the oxide used as the hard mask can be etched using wet etching. At this time, sufficient over-etching can be performed so that no residual oxide remains.

[0053] As illustrated in FIG. 2d, in the first conductivity region formation step (S5), a first conductivity region (140) may be formed inside the SiC epitaxial layer (120). The first conductivity region (140) may be formed to a certain depth inward from the upper surface of the SiC epitaxial layer (120) and the second conductivity base region (130). The first conductivity region (140) may be formed on the upper surface of the second conductivity base region (130). This first conductivity region (140) may be formed to have an N+ type through a process of directly ion-implanting impurities such as nitrogen (N) and phosphorus (P) into the SiC epitaxial layer (120) and the second conductivity base region (130). Additionally, the first conductivity region (140) may be referred to as the source region in a MOSFET.

[0054] In addition, the first conductivity region (140) can be formed to cover the entire upper surface of the SiC epitaxial layer (120), that is, the upper surface of the second conductivity base region (130). For example, when forming the first conductivity region (140), an oxide film (Hard Mask, not shown) can be deposited and used as a hard mask. At this time, the oxide film can be made of TEOS and can have a thickness of 15,000 to 30,000 Å. The first conductivity region (140), N+, can be formed through a process of ion implanting phosphorus impurities into the SiC epitaxial layer (120) and the second conductivity base region (130). At this time, although the ion implantation energy is not higher than that for forming the second conductivity base region, sufficient hard mask thickness must be ensured on the surface, and a high concentration of ion implantation source must be prevented from penetrating the mask and implanting ions into unwanted areas. Once ion implantation is complete, the oxide used as a hard mask can be etched using wet etching. At this time, sufficient over-etching can be performed to ensure that no residual oxide remains.

[0055] In one embodiment, in the second conductivity type well region formation step (S6), a mask (not shown) is formed in an area other than the one where the second conductivity type well region (131) is to be formed on the upper part of the first conductivity type region (140), and the second conductivity type well region (131) can be formed through a process of directly ion-implanting aluminum (Al) impurities into the second conductivity type base region (130). The second conductivity type well region (131) may be of the P+ type and may be formed to penetrate a part of the SiC epitaxial layer (120) from the upper surface of the second conductivity type base region (130). Here, the second conductivity type well region (131) may also be formed as a pair.

[0056] This second challenge type well region (131), together with the electric field concentration mitigation layer (122), can mitigate the phenomenon of electric field concentration under the gate insulating film (151) when a reverse voltage is applied between the source and the drain.

[0057] Meanwhile, after forming a second conductive well region, the mask may be removed, and a capping layer (not shown) may be formed on top of the SiC epitaxial layer (120), and annealing at a high temperature may be further included. After such annealing process, the capping layer may be removed.

[0058] Additionally, as shown in FIGS. 2e and 2f, in the gate region formation step (S7), a trench (132) penetrating a portion of the first conductivity region (140), the second conductivity base region (130), and the SiC epitaxial layer (120) may be formed.

[0059] First, a mask (10) is formed in an area other than the one where the trench (132) is to be formed on the upper part of the first conductive region (140), and the trench (132) can be formed by etching a portion of the first conductive region (140), the second conductive base region (130), and the SiC epitaxial layer (120). The upper part of the SiC epitaxial layer (120) can be exposed to the outside by the trench (132).

[0060] Such trenches (132) may be formed on top of the electric field concentration relaxation layer (122). In one embodiment, trenches (132) may be formed on top of at least one electric field concentration relaxation layer (122) by etching a width wider than the total width of at least one electric field concentration relaxation layer (122).

[0061] Then, a gate insulating film (151) and a gate electrode (152) can be formed in the trench (132). First, a gate insulating film (151) of a certain thickness can be formed on the inner wall of the trench (132). The gate insulating film (151) can be formed from any one selected from silicon oxide, nitrogen oxide, PSG (Phospho-Silicate-Glass), BPSG (Boro-Phosphor-Silicate-Glass), or equivalents thereof, but is not limited thereto. Then, a gate electrode (152) can be formed by depositing polysilicon on the trench (132) where the gate insulating film (151) is formed.

[0062] For example, a trench etch region can be opened through a photolithography process after depositing an oxide film (hard mask). The opened region allows for etching the SiC in a vertical direction. Here, the width of the trench etch region must be wider than the trench region where the floating P+ is formed. Furthermore, etching can be performed to a depth that allows for a gate separated from the floating P+ region. Subsequently, a gate insulating film of a certain thickness can be formed on the inner wall of the trench etch region to form the gate region. The gate insulating film is formed using oxidation or CVD methods, and may be formed using either one selected from these, or a mixed oxide film may be used. However, the oxide film used in this disclosure is not limited to this. After forming the gate insulating film inside the trench etched region, a gate can be formed by depositing polysilicon.

[0063] As illustrated in FIG. 2g, in the insulating layer formation step (S8), an insulating layer (160) may be formed on top of the gate insulating film (151) and the gate electrode (152). Additionally, the insulating layer (160) may be formed to extend to cover a portion of the first conductive region (140). The insulating layer (160) may be formed from any one selected from silicon oxide, nitrogen oxide, PSG (Phospho-Silicate-Glass), BPSG (Boro-Phosphor-Silicate-Glass), or equivalents thereof, but is not limited thereto.

[0064] Additionally, in the insulating layer formation step (S8) of one embodiment, a contact area (160a) can be formed by exposing a portion of the second conductivity type well area (131), which is the P region, and the first conductivity type area (140), which is the N+ region, to the outside. The insulating layer can be formed from a silicon oxide film, a silicon nitride film (SiN), PSG (Phospho-Silicate-Glass), BPSG (Boro-Phosphor-Silicate-Glass), or any one selected from these. At this time, a material having a high dielectric constant must be selected as a material capable of withstanding the high electric field of the SiC power semiconductor, and a material that does not affect reliability during device operation must be selected.

[0065] Additionally, as illustrated in FIGS. 2h and 2i, in the electrode formation step (S9), a source electrode (170) may be formed in the contact region (160a) and a drain electrode (180) may be formed on the lower part of the SiC substrate (110). For example, a barrier metal (170a) of relatively thin thickness may be formed in the contact region (160a). The barrier metal (170a) may be formed on the upper part of the first conductivity region (140) and the second conductivity well region (131). Thus, an ohmic junction layer may be formed between the barrier metal (170a) and the first conductivity region (140) and the second conductivity well region (131). Additionally, a drain electrode (180) (or drain metal) may be formed on the lower part of the SiC substrate (110).

[0066] Then, by forming a source electrode (170) (or source metal) on the barrier metal (170a), a power semiconductor device according to one embodiment of the present invention can be completed. Here, the source electrode (170) may be formed to cover both the barrier metal (170a) and the insulating layer (160).

[0067] At this time, nickel (Ni) may be used as the metal, and silicide may be formed through instantaneous heat treatment at a high temperature, and an ohmic junction layer may be formed at the above location. Subsequently, by forming a source electrode (or source metal) on the ohmic metal using aluminum (Al) or an aluminum-copper (Al-Cu) alloy, a SiC power semiconductor device according to one embodiment can be completed.

[0068] In this way, a method for manufacturing a power semiconductor device according to one embodiment of the present disclosure forms a second conductivity type well region (131) penetrating a first conductivity type region (140) and a second conductivity type base region (130), and forms an electric field concentration mitigation layer (122) on the lower side of the gate oxide film, thereby mitigating the phenomenon of electric field concentration under the gate oxide film when a reverse voltage is applied between the source and the drain. Accordingly, the reliability of the power semiconductor device can be improved, and low on-resistance and high withstand voltage can be maintained.

[0069] FIG. 3 is a flowchart illustrating a method for manufacturing a power semiconductor device according to another embodiment of the present invention. FIG. 4a to 4d are cross-sectional views sequentially illustrating a method for manufacturing a power semiconductor device according to another embodiment of the present invention.

[0070] Referring to FIG. 3, a method for manufacturing a power semiconductor device according to another embodiment of the present disclosure may include a SiC substrate preparation step (S11), a first epitaxial layer formation step (S12), an electric field concentration relaxation layer formation step (S13), a second epitaxial layer formation step (S14), a second conductivity type base region formation step (S15), a first conductivity type region formation step (S16), a second conductivity type well region formation step (S17), a gate region formation step (S18), an insulating layer formation step (S19), and an electrode formation step (S20).

[0071] Here, most of the steps (S11, S15 to S20) of the method for manufacturing a power semiconductor device illustrated in FIG. 3 may be identical to most of the steps (S1, S4 to S9) of the method for manufacturing a power semiconductor device illustrated in FIG. 1. In addition, only the steps (S12 to S14) of forming an epitaxial layer and forming a field concentration relaxation layer in FIG. 3 may differ from the steps (S2 and S3) of forming a SiC epitaxial layer and forming a field concentration relaxation layer in FIG. 1. Therefore, the following description will focus on S11 to S15 based on these differences.

[0072] As illustrated in FIG. 4a, in the SiC substrate preparation step (S11), a SiC substrate (110) of a first conductivity type can be prepared. This SiC substrate (110) can be formed in a plate-like shape including an upper surface and a lower surface.

[0073] And in the first epitaxial layer formation step (S12), a first epitaxial layer (120a) of a first conductivity type may be formed on the upper surface of the SiC substrate (110).

[0074] Next, as illustrated in FIG. 4b, at least one field concentration relaxation layer (122) can be formed inside the first epitaxial layer (120a) in the field concentration relaxation layer formation step (S13). At this time, in the field concentration relaxation layer formation step, an oxide film (Hard Mask, 121) is deposited on the upper part of the SiC epitaxial layer (120) in an area other than where the field concentration relaxation layer (122) is to be formed, and a P+ type field concentration relaxation layer (122) can be formed by a process of directly ion implanting aluminum (Al) impurities into the interior from the upper surface of the SiC epitaxial layer (120) where the oxide film (121) is not formed. At this time, when the SiC epitaxial layer (120) is formed as a single layer, an ion implantation process can be performed such that, when viewed from the state in which the power semiconductor device is manufactured, the electric field concentration relaxation layer (122) is located at a set depth from the upper surface of the second conductivity type base region (130).

[0075] On the other hand, if the SiC epitaxial layer (120) is formed in at least two layers, an electric field concentration relaxation layer (122) may be formed on the upper side inside the first epitaxial layer (120a). And the thickness of the second epitaxial layer (120b) described later may vary in correspondence with a set depth from the upper surface of the second conductive base region (130) relative to the location of the electric field concentration relaxation layer (122) formed inside the first epitaxial layer (120a). For example, the thickness of the second epitaxial layer (120b) may be equal to or shorter than the set depth.

[0076] That is, the injection depth of the electric field concentration relaxation layer (122) may vary depending on the setting. Accordingly, in one embodiment, the electric field concentration relaxation layer (122) may be formed to be located at a set depth from the upper surface of the second conductivity type base region (130) inside the SiC epitaxial layer (120) when viewed in the state where the power semiconductor device is manufactured.

[0077] This electric field concentration mitigation layer (122) is formed below the gate insulating film (151) described later, and can mitigate the phenomenon of electric field concentration below the gate insulating film (151) when a reverse voltage is applied between the source and the drain.

[0078] As illustrated in FIG. 4c, in the second epitaxial layer formation step (S14), a second epitaxial layer (120b) of the first conductivity type may be formed on the upper surface of the first epitaxial layer (120a). For example, at a high temperature of 600 to 2000°C, a gas containing a hydrocarbon such as monomethylsilane or silane and propane, and a gas containing a pentavalent element such as nitrogen (N) and phosphorus (P) may be flowed together at a low concentration on the upper surface of the first epitaxial layer (120a), thereby allowing an N-type second epitaxial layer (120b) to be additionally deposited on the surface of the first epitaxial layer (120a). That is, in one embodiment, the formed SiC epitaxial layer (120) may be used and designated as a multilayer semiconductor layer.

[0079] Meanwhile, since the SiC epitaxial layer (120) is formed with a first epitaxial layer (120a) and a second epitaxial layer (120b) of the same first conductivity type, it can be viewed as a single epitaxial layer (120) after formation. In one embodiment, the total thickness of the first epitaxial layer (120a) and the second epitaxial layer (120b) may be the same as the thickness of the epitaxial layer (120) formed as a single layer. Here, thickness may refer to the thickness in the stacking direction.

[0080] And as illustrated in FIG. 4d, in the second conductivity base region formation step (S15), a second conductivity base region (130) may be formed inside the second epitaxial layer (120b). The second conductivity base region (130) may be formed to a certain depth from the upper surface of the second epitaxial layer (120b) toward the interior. This second conductivity base region (130) may be formed on the upper surface of the second epitaxial layer (120b) to cover the entire upper surface. This second conductivity base region (130) may be formed to have a P-type through a process of directly ion-implanting aluminum (Al) impurities into the second epitaxial layer (120b).

[0081] For subsequent steps (S16 to S20), refer to FIGS. 2d to 2i.

[0082] In the first conductivity region formation step (S16), a first conductivity region (140) can be formed inside the SiC epitaxial layer (120). The first conductivity region (140) can be formed on top of the second conductivity base region (130). This first conductivity region (140) can be formed to have an N+ type through a process of directly ion-implanting impurities such as nitrogen (N) and phosphorus (P) into the SiC epitaxial layer (120) and the second conductivity base region (130).

[0083] And in the second conductivity type well region formation step (S17), a second conductivity type well region (131) that penetrates a portion of the first conductivity type region (140) and the second conductivity type base region (130) may be formed. Here, the second conductivity type well region (131) may also be formed as a pair. This second conductivity type well region (131), together with the electric field concentration mitigation layer (122), can mitigate the phenomenon of electric field concentration under the gate insulating film (151) when a reverse voltage is applied between the source and the drain.

[0084] Additionally, in the gate region formation step (S18), a trench (132) penetrating a portion of the first conductivity region (140), the second conductivity base region (130), and the SiC epitaxial layer (120) may be formed. For example, a mask (10) may be formed in the area other than where the trench (132) is to be formed above the first conductivity region (140), and the trench (132) may be formed by etching a portion of the first conductivity region (140), the second conductivity base region (130), and the SiC epitaxial layer (120). A gate insulating film (151) and a gate electrode (152) may be formed in the trench (132). First, a gate insulating film (151) of a certain thickness may be formed on the inner wall of the trench (132). Then, a gate electrode (152) can be formed by depositing polysilicon in the trench (132) where the gate insulating film (151) is formed.

[0085] And in the insulating layer formation step (S19), an insulating layer (160) may be formed on top of the gate insulating film (151) and the gate electrode (152). Additionally, the insulating layer (160) may be formed to extend to cover a portion of the first conductive region (140). In the insulating layer formation step, a contact region (160a) may be formed by exposing a portion of the second conductive well region (131), which is the P region, and a portion of the first conductive region (140), which is the N+ region, to the outside.

[0086] Finally, in the electrode formation step (S20), a source electrode (170) may be formed in the contact region (160a) and a drain electrode (180) may be formed on the lower part of the SiC substrate (110). For example, a barrier metal (170a) of relatively thin thickness may be formed in the contact region (160a). Additionally, a drain electrode (180) (or drain metal) may be formed on the lower part of the SiC substrate (110). Then, by forming a source electrode (170) (or source metal) on the barrier metal (170a), a power semiconductor device according to one embodiment of the present invention may be completed. Here, the source electrode (170) may be formed to cover both the barrier metal (170a) and the insulating layer (160).

[0087] In this way, the method for manufacturing a power semiconductor device according to one embodiment of the present disclosure can more easily secure a sufficient thickness for trench gate etching up to the top of the electric field concentration relaxation layer (122) by additionally forming a second epitaxial layer (120b) after the formation of the electric field concentration relaxation layer (122), which is a Floating P+ region, is completed on the first epitaxial layer (120a).

[0088] The above description is merely one embodiment for implementing the present invention, and the present invention is not limited to the above-described embodiment. The technical spirit of the present invention extends to the scope in which various modifications can be made by anyone with ordinary knowledge in the field to which the invention belongs, without departing from the essence of the invention as claimed in the following patent claims. Explanation of the symbols

[0089] 110: SiC substrate 120: SiC epitaxial layer 120a, b: 1st and 2nd epitaxial layers 121, 123: Oxide film 122: Electric field concentration relaxation layer 130: Second conductivity type base region 131: Second Challenge Well Area 132: Trench 140: First conductivity type region 151: Gate insulating film 152: Gate electrode 160: Insulating layer 160a: Contact area 170: Source electrode 170a: Barrier metal 180: Drain electrode

Claims

Claim 1 A step of preparing a SiC substrate of a first conductivity type; a step of forming at least one first SiC epitaxial layer of a first conductivity type on the SiC substrate; a step of forming at least one second conductivity type floating island-shaped electric field concentration relaxation layer inside the first SiC epitaxial layer; a step of continuously forming a second SiC epitaxial layer of a first conductivity type on top of the first SiC epitaxial layer; a step of forming a second conductivity type base region inside the second SiC epitaxial layer; a step of forming a first conductivity type region on top of the second conductivity type base region; a step of forming a second conductivity type well region extending from the upper surface of the first conductivity type region to the upper surface of the second conductivity type base region, and forming a trench with a depth penetrating the second SiC epitaxial layer to reach the upper side of the electric field concentration relaxation layer; a step of forming a gate insulating film on the inner wall of the trench and forming a gate electrode on the inner side of the gate insulating film to construct a gate region; covering the upper surface of the gate region A method for manufacturing a power semiconductor device comprising the steps of: stacking an insulating layer and forming a contact region that exposes the first conductivity region and the second conductivity well region; and forming a source electrode in the contact region and forming a drain electrode on the lower part of the SiC substrate. Claim 2 A method for manufacturing a power semiconductor device according to claim 1, wherein the trench is formed by etching the first conductivity type region, the second conductivity type base region, and a part of the SiC epitaxial layer. Claim 3 A method for manufacturing a power semiconductor device according to claim 1, wherein the electric field concentration relaxation layer is formed to be located at a set depth from the upper surface of the second conductivity type base region within the SiC epitaxial layer. Claim 4 A method for manufacturing a power semiconductor device according to claim 1, wherein the trench is formed on top of the at least one electric field concentration relaxation layer by etching a width wider than the total width of the at least one electric field concentration relaxation layer. Claim 5 A method for manufacturing a power semiconductor device according to claim 1, wherein the gate region comprises a gate insulating film formed on the inner wall of the trench and a gate electrode formed by depositing polysilicon on the inner side of the gate insulating film. Claim 6 A method for manufacturing a power semiconductor device according to claim 5, wherein the second conductivity type well region is formed from the upper part of the second conductivity type base region to the upper part of the SiC epitaxial layer. Claim 7 A method for manufacturing a power semiconductor device according to claim 1, wherein a barrier metal formed on the upper portion of the first conductivity type region and the second conductivity type well region is formed in the contact region, and the source electrode is formed to cover the upper portion of the barrier metal and the insulating layer. Claim 8 delete Claim 9 A method for manufacturing a power semiconductor device according to claim 1, wherein the electric field concentration relaxation layer is formed on the upper side inside the first SiC epitaxial layer. Claim 10 A method for manufacturing a power semiconductor device according to claim 1, wherein the second conductivity type base region is formed inside the second SiC epitaxial layer. Claim 11 A method for manufacturing a power semiconductor device according to claim 1, wherein the thickness of the second SiC epitaxial layer corresponds to a set depth from the upper surface of the second conductive base region at the location of the electric field concentration relaxation layer formed inside the first SiC epitaxial layer. Claim 12 A SiC substrate of a first conductivity type; a SiC epitaxial layer comprising a first SiC epitaxial layer of a first conductivity type formed as at least one layer on top of the SiC substrate and a second SiC epitaxial layer of a first conductivity type formed on top of the first SiC epitaxial layer; at least one floating island-shaped electric field concentration mitigation layer formed inside the first SiC epitaxial layer; a second conductivity type base region formed inside the second SiC epitaxial layer; a first conductivity type region formed on top of the second conductivity type base region; a second conductivity type well region extending from the upper surface of the first conductivity type region to the upper surface of the second conductivity type base region; a trench formed penetrating the SiC epitaxial layer so as to be located on the upper side of the electric field concentration mitigation layer; a gate region formed inside the trench and on the upper side of the electric field concentration mitigation layer; an insulating layer covering the upper surface of the gate region; and a source electrode formed on the surface of the first conductivity type region and the second conductivity type well region. A power semiconductor device comprising a drain electrode formed on the lower part of the SiC substrate. Claim 13 In claim 12, the trench is a power semiconductor device formed by etching the first conductivity type region, the second conductivity type base region, and a portion of the SiC epitaxial layer. Claim 14 In claim 12, the electric field concentration relaxation layer is formed to be located at a set depth from the upper surface of the second conductivity type base region within the SiC epitaxial layer. Claim 15 In claim 12, the power semiconductor device formed on the electric field concentration relaxation layer by etching a wide width of the trench compared to the total width of the at least one electric field concentration relaxation layer. Claim 16 A power semiconductor device according to claim 12, wherein the gate region comprises a gate insulating film formed on the inner wall of the trench and a gate electrode formed by depositing polysilicon on the inner side of the gate insulating film. Claim 17 A power semiconductor device according to claim 12, wherein a barrier metal is formed on the upper portion of the first conductivity type region and the second conductivity type well region, and the source electrode is formed to cover the upper portion of the barrier metal and the insulating layer. Claim 18 delete Claim 19 In claim 12, the electric field concentration relaxation layer is a power semiconductor device formed on the upper side inside the first SiC epitaxial layer. Claim 20 In claim 12, the second conductivity type base region is a power semiconductor device formed inside the second SiC epitaxial layer. Claim 21 In claim 12, the thickness of the second SiC epitaxial layer corresponds to a set depth from the upper surface of the second conductive base region at the location of the electric field concentration relaxation layer formed inside the first SiC epitaxial layer, in a power semiconductor device.

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