Apparatus for accelerating stochastic computing neural network using single random bit-stream partitioning and variable reduction coefficients

Abstract

The present invention relates to a neural network accelerator device based on probabilistic operation using a single random number bitstream splitting and a variable reduction factor, comprising: a single random number generator that generates a pseudo-random number bitstream; a random number allocation wiring unit that splits the random number bitstream into a plurality of bit regions and selectively allocates some bits of the bit regions for each operation path; a plurality of probabilistic operation units that generate a probability pulse and perform a logical AND operation by comparing the allocated random number bits with an input signal, a weight signal, and a variable reduction factor, and selectively bypass the variable reduction factor according to external control to variably perform 2-input or 3-input probability multiplication; a counter unit that converts the output pulse of the probabilistic operation units into binary data; and a plurality of adders and subtractors that sum the binary data and form sigmoid activation function characteristics through a step-by-step bit expansion structure and a final stage saturation logic.

Description

Technology Field

[0001] The present invention relates to hardware acceleration technology for artificial intelligence computation, and more specifically, to a neural network accelerator device that simplifies multiplication operations using a stochastic bitstream, reduces correlation between computation units while sharing a single random number source, dynamically controls the computation structure through a variable decay factor, and implements a non-linear activation function using the saturation characteristics of a hierarchical addition and subtraction structure. Background Technology

[0003] Recently, deep learning-based neural networks have demonstrated high performance in various fields such as image recognition and natural language processing, but hardware accelerators required to implement them require large-scale Multiply-Accumulate (MAC) operations, which causes problems such as high power consumption and increased chip area.

[0004] As an alternative to address this, Stochastic Computing has been proposed, which has the advantage of significantly reducing circuit complexity by converting input data into a probabilistic bitstream and then approximating multiplication through simple logical operations (e.g., AND operation).

[0005] However, conventional probabilistic computation-based structures have the following limitations.

[0006] First, if an independent random number generator is required for each computational unit, there is a problem of increased overall system area and power consumption.

[0007] Second, when a single random number generator is shared, a problem arises where computational accuracy deteriorates due to increased correlation between computational units caused by identical random numbers.

[0008] Third, there is a problem in that the output value saturates prematurely during the process of summing the results of stochastic multiplication, distorting non-linear characteristics and requiring a separate activation function operator.

[0009] Fourth, in existing structures, it is difficult to flexibly incorporate additional control parameters other than input signals and weights, so there are limitations in dynamically adjusting the computational strength or the gradient of the activation function. Prior art literature

[0011] U.S. Patent Publication No. 2016-0125263A1 U.S. Patent Publication No. 2019-0362284A1 The problem to be solved

[0012] The present specification has been devised to solve the problems described above, and aims to provide a neural network accelerator device capable of effectively reducing correlation between computation units by sharing a single random number generator among all computation units while dividing and rearranging the random number bitstream into multiple bit regions and assigning them differently to each computation path.

[0013] In addition, another objective of the present invention is to provide a neural network accelerator device capable of flexibly switching between 2-input and 3-input probabilistic multiplications and dynamically controlling computational strength and activation characteristics by providing a probabilistic computation structure that can selectively apply or bypass a variable reduction factor in addition to input signals and weight signals.

[0014] In addition, another objective of the present invention is to provide a neural network accelerator device capable of implementing non-linear characteristics corresponding to a sigmoid activation function without a separate activation function operator by converting a probability pulse into binary data, then gradually expanding the bit width in a hierarchical addition / subtraction tree, and applying saturation logic in the final step.

[0015] In addition, another objective of the present invention is to provide a neural network accelerator that enables high-speed operation and excellent power efficiency while minimizing hardware resources through the above structure. means of solving the problem

[0017] According to one embodiment of the present specification for achieving the above purpose, a neural network accelerator device based on probabilistic operation according to the present specification comprises: a single random number generator that generates a pseudo-random number bit stream; a random number allocation wiring unit that divides the random number bit stream into a plurality of bit regions and selectively allocates some bits of the bit regions for each operation path; a plurality of probabilistic operation units that generate a probability pulse and perform a logical AND operation by comparing the allocated random number bits with an input signal, a weight signal, and a variable reduction factor, and selectively bypass the variable reduction factor according to external control to variably perform a 2-input or 3-input probability multiplication; a counter unit that converts the output pulse of the probabilistic operation units into binary data; and a plurality of adders and subtractors that sum the binary data and form sigmoid activation function characteristics through a step-by-step bit expansion structure and a final stage saturation logic.

[0018] Preferably, the random number allocation wiring unit divides the random number bitstream into a plurality of predefined bit intervals and selectively allocates some of the bit intervals to each operation path, thereby reducing the random number correlation between operation units.

[0019] Preferably, the random number allocation wiring unit is characterized by rearranging the order of bits selected from the bit interval using a cross-wiring or position shift method and supplying them to each operation path.

[0020] Preferably, the single random number generator is characterized by including a linear feedback shift register (LFSR) or an XOR-based random number generator using a previous state value.

[0021] Preferably, the probabilistic operation unit is configured such that the comparator output corresponding to the variable reduction coefficient is fixed to a logic 'High' value in bypass mode, and is characterized by performing a 2-input probability multiplication for the input signal and the weight signal.

[0022] Preferably, the variable reduction coefficient is applied in common to a plurality of the probabilistic operation units and operates as a Global Gain parameter that controls the magnitude of the total operation output.

[0023] Preferably, the probability pulse generation frequency is controlled according to the value of the variable reduction coefficient, and the slope of the sigmoid activation function is variably adjusted.

[0024] Preferably, the counter unit is characterized by accumulating and measuring probability pulses occurring during a predetermined clock cycle and converting them into binary data.

[0025] Preferably, the plurality of adders and subtractors are arranged in a hierarchical tree structure and are configured to have a bit width that is 1 bit longer than the bit width of the input data at each stage.

[0026] Preferably, the final stage of the adder / subtractor is characterized by the application of saturation logic that fixes the output value to a maximum value when an upper bit exceeding a predetermined bit width occurs.

[0027] Preferably, the saturation logic is characterized by implementing characteristics similar to a sigmoid activation function by combining with distribution characteristics generated by probabilistic operations to form a continuous non-linear output curve.

[0028] Preferably, a latch or flip-flop for pipeline processing is disposed between the probabilistic operation unit, the counter unit, and the adder / subtractor to minimize data path delay.

[0029] Preferably, instead of the plurality of adders / subtractors, it is characterized by including a single sequential adder / subtractor that calculates a cumulative sum by sequentially processing binary data output from the counter unit in time.

[0030] Preferably, the single sequential adder / subtractor includes an input selection logic that sequentially selects and supplies one of a plurality of input channels according to a channel selection signal provided from a control unit, and is configured to sequentially accumulate binary data for the plurality of input channels during the processing time of a bitstream generated by probabilistic operation. Effects of the invention

[0032] As explained above, according to the present specification, the following effects can be obtained.

[0033] First, since correlation between operation units can be effectively suppressed through the splitting and rearrangement of bitstreams while sharing a single random number generator, circuit area and power consumption can be significantly reduced compared to the case where multiple separate random number generators are used.

[0034] Second, 2-input and 3-input operations can be selectively performed through a 3-input probability multiplication structure using a variable reduction factor and a bypass function, thereby improving the flexibility and adaptability of the operation.

[0035] Third, the above variable decay factor acts as a global gain that adjusts the magnitude of the overall computation output, allowing for dynamic control of the gradient of the activation function, thereby improving learning and inference performance.

[0036] Fourth, by converting the probability pulse into binary data, gradually expanding the bit width in a hierarchical adder / subtractor, and applying saturation logic in the final stage, non-linear characteristics similar to a sigmoid can be efficiently implemented without a separate activation function operator.

[0037] Fifth, by applying a pipeline structure, data path delay is minimized and high-speed clock operation is enabled, which can improve the overall system throughput.

[0038] Sixth, due to the nature of probabilistic computation, even if some computational error exists, it can be absorbed during the neural network's learning process, enabling stable operation even at low precision and maximizing energy efficiency. Brief explanation of the drawing

[0040] FIG. 1 is a block diagram schematically showing the overall configuration of a probabilistic computation-based neural network accelerator device according to one embodiment of the present invention. FIG. 2 is a block diagram showing the detailed configuration of a probabilistic operation unit according to an embodiment of the present invention. FIG. 3 is a block diagram showing a post-operation structure including a counter unit and a plurality of adders / subtractors according to an embodiment of the present invention. FIG. 4 is a block diagram showing an accumulation operation structure using a single sequential adder / subtractor according to another embodiment of the present invention. FIG. 5 is a graph illustrating the output characteristics of a probabilistic computation-based neural network accelerator device according to an embodiment of the present invention, FIG. 6 is a graph showing how similar the output generated by a probabilistic computation-based neural network accelerator device according to one embodiment of the present invention is to an ideal sigmoid activation function, and FIGS. 7 to 9 are graphs showing changes in output characteristics according to various computation conditions or parameter settings in a probabilistic computation-based neural network accelerator device according to an embodiment of the present invention. Specific details for implementing the invention

[0041] It should be noted that technical terms used in this specification are used merely to describe specific embodiments and are not intended to limit the invention. Furthermore, unless specifically defined otherwise in this specification, technical terms used in this specification should be interpreted in the sense generally understood by those skilled in the art to which the invention pertains, and should not be interpreted in an overly broad or overly narrow sense. Additionally, if a technical term used in this specification is an incorrect technical term that fails to accurately express the spirit of the invention, it should be understood as being replaced by a technical term that can be correctly understood by those skilled in the art. Moreover, general terms used in this invention should be interpreted according to their prior definitions or the context, and should not be interpreted in an overly narrow sense.

[0042] Additionally, singular expressions used in this specification include plural expressions unless the context clearly indicates otherwise. In this application, terms such as "composed of" or "comprising" should not be interpreted as necessarily including all of the various components or steps described in the specification, and should be interpreted as meaning that some of the components or steps may not be included, or that additional components or steps may be included.

[0043] Furthermore, the suffixes "module" and "part" for components used in this specification are assigned or used interchangeably solely for the sake of ease of drafting the specification, and do not inherently possess distinct meanings or roles.

[0044] Additionally, terms including ordinal numbers, such as first, second, etc., used herein may be used to describe various components, but said components should not be limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0045] Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Identical or similar components are given the same reference number regardless of the drawing symbols, and redundant descriptions thereof will be omitted.

[0046] Furthermore, in describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such descriptions could obscure the essence of the invention. Additionally, it should be noted that the attached drawings are intended only to facilitate an understanding of the concept of the present invention and should not be interpreted as limiting the concept of the invention.

[0047] FIG. 1 is a block diagram schematically showing the overall configuration of a neural network accelerator device based on probabilistic computation according to one embodiment of the present invention, and FIG. 2 is a block diagram showing the detailed configuration of a probabilistic computation unit according to one embodiment of the present invention.

[0048] Referring to FIG. 1, a neural network accelerator device based on probabilistic operation according to the present invention may include a single random number generator (100), a random number allocation wiring unit (200), a plurality of probabilistic operation units (300), a counter unit (400), and a plurality of adders / subtractors (500).

[0049] A single random number generator (100) is a component that generates a pseudo-random number bitstream.

[0050] A single random number generator (100) can be implemented in a structure that generates random number bits of length 32 to 40 bits, for example, and can use a linear feedback shift register (LFSR) or an XOR feedback-based structure. In this way, by sharing the single random number generator (100) with a plurality of probabilistic operation units (300), circuit area and power consumption can be reduced.

[0051] The random number allocation wiring unit (200) divides the random number bitstream into multiple bit regions and allocates selected bits, for example, a partial bitstream in units of 8 bits, to each probabilistic operation unit (300). At this time, the random number allocation wiring unit (200) can reduce the correlation between random numbers input to each probabilistic operation unit (300) while sharing a single random number generator (100) by performing at least one of non-linear selection of bit indices, shifting of bit positions, and cross-connection of wiring. Accordingly, the accuracy of the probabilistic operation is improved.

[0052] Each probabilistic operation unit (300) is an input signal ( ), weighted signal( ) and variable reduction factor( Generates a probability pulse using ).

[0053] The probabilistic operation unit (300) includes a plurality of comparators (310, 320, 330) and a logical operation unit (340). Specifically, the first comparator (310) is an input signal ( A first probability signal is generated by comparing ) and a random number bit, and the second comparator (320) is a weight signal ( A second probability signal is generated by comparing ) and a random number bit, and the third comparator (330) is a variable reduction coefficient ( A third probability signal is generated by comparing the ) and a random number bit. The logic operation unit (340) performs a logical AND operation on the first to third probability signals to output a final probability pulse. Accordingly, the output probability follows a probability multiplication structure as shown in the following mathematical formula 1.

[0054]

[0055] Meanwhile, the third comparator (330) is commonly connected to a plurality of probabilistic operation units (300), and a variable reduction coefficient ( ) is applied commonly to all operation paths. Accordingly, the variable reduction factor ( ) acts as a global gain that controls the scale of the entire operation.

[0056] In addition, the probabilistic operation unit (300) has a variable reduction coefficient ( It is configured to selectively bypass ). Specifically, when the bypass is disabled, the output of the third comparator (330) is included in the AND operation and a 3-input probability multiplication is performed, and when the bypass is enabled, the output of the third comparator (330) is fixed to a logic 'High', substantially A 2-input probability multiplication of the form is performed.

[0057] In addition, each probabilistic operation unit (300) is an input signal ( ) and weighted signals( It may further include a sign bit operation unit for processing sign information of ). The sign bit operation unit is, for example, and The sign of the final output is determined by performing an XOR operation on the sign bit. This allows the sign information to be accurately reflected separately from the magnitude information represented by the probabilistic bitstream.

[0058] Variable reduction factor ( ) is applied commonly to multiple probabilistic operation units (300) and acts as a global gain that controls the frequency of occurrence of the total probability pulse. That is, a variable reduction coefficient ( As ) increases, the probability of output pulse generation increases, causing the output slope to increase, and the variable reduction coefficient ( If ) decreases, the probability of output pulse generation decreases, and a smooth output is formed.

[0059] FIG. 3 is a block diagram showing a post-operation structure including a counter unit and a plurality of adders / subtractors according to an embodiment of the present invention.

[0060] Referring to FIG. 3, the counter unit (400) is a component that measures probability pulses output from a plurality of probabilistic operation units (300) and converts them into binary data.

[0061] The counter unit (400) accumulates and counts pulses occurring during a predetermined clock interval and converts the probability value into integer binary data.

[0062] Multiple adders / subtractors (500) receive output data from the counter unit (400) and perform summation in a hierarchical structure.

[0063] As illustrated in FIG. 3, the plurality of adders / subtractors (500) have a step-by-step structure such as a 9-bit adder / subtractor (510), a 10-bit adder / subtractor (520), and an 11-bit adder / subtractor (530). That is, the bit width is expanded step-by-step in the form of n-bit + n-bit → (n+1)-bit.

[0064] Saturation logic is applied at the final stage of the multiple adders / subtractors (500). That is, if an overflow occurs in the upper bit, the output value is fixed to the maximum value. This saturation operation is combined with the statistical distribution of the probabilistic operation to form a non-linear curve in which the output gradually saturates. As a result, characteristics similar to a sigmoid activation function are implemented without a separate activation function operator.

[0065] Meanwhile, as shown in FIG. 3, a latch may be placed between the counter unit (400) and the plurality of adders / subtractors (500). Through this, data path delay reduction, high-speed clock operation, and throughput improvement are possible.

[0066] The probabilistic computation-based neural network accelerator device of the present invention operates in the following order.

[0067] In the neural network accelerator device based on probabilistic operation according to the present invention, a pseudo-random number bitstream is first generated by a single random number generator (100). The generated random number bitstream is transmitted to a random number allocation wiring unit (200), and the random number allocation wiring unit (200) divides the random number bitstream into a plurality of bit regions and assigns the divided bit regions differently to each probabilistic operation unit (300). Subsequently, each probabilistic operation unit (300) generates a probability pulse by comparing the assigned random number bit with an input signal, a weight signal, and a variable reduction factor, and performs probability multiplication by performing a logical AND operation on the probability pulse. The probability pulse output from the probabilistic operation unit (300) is transmitted to a counter unit (400), and the counter unit (400) accumulates the probability pulse during a predetermined clock interval and converts it into binary data. Next, the binary data output from the counter unit (400) is input to a plurality of adders / subtractors (500), and the plurality of adders / subtractors (500) sum the binary data in a hierarchical structure and perform saturation processing in the final stage. As a result, the output of the plurality of adders / subtractors (500) exhibits a non-linear characteristic combining probabilistic operation characteristics and saturation characteristics, and accordingly, a final output having characteristics similar to a sigmoid activation function is generated.

[0068] Hereinafter, another embodiment of the present invention is described in which a plurality of adders / subtractors (500) are replaced with a single sequential adder / subtractor (600).

[0069] Referring to FIG. 4, the probabilistic operation-based neural network accelerator device according to the present embodiment is configured to perform cumulative operations on binary data output from a counter unit (400) using a single sequential adder / subtractor (600) instead of a plurality of adders / subtractors.

[0070] A multiplexer (MUX) or input selection logic for supplying multiple channel data in time division may be placed at the input terminal of a single sequential adder / subtractor (600), and this operates in synchronization according to a channel selection signal of a control unit.

[0071] A single sequential adder / subtractor (600) is a single adder / subtractor operation unit, and is a binary data per channel generated from a plurality of probabilistic operation units (300) and converted through a counter unit (400). Calculate the cumulative sum by processing ) sequentially in time.

[0072] The counter unit (400) accumulates the probability pulses output from the probabilistic operation unit (300) for a predetermined clock interval and converts them into binary data for each channel. At this time, the probabilistic operation takes a certain amount of time (e.g., 256, 128, or 64 clock cycles) depending on the length of the bit stream.

[0073] In this embodiment, a single sequential adder / subtractor (600) is not idle during the bitstream processing time, and sequentially receives binary data from each channel and performs an accumulation operation.

[0074] Specifically, a single sequential adder / subtractor (600) is the previous accumulated result ( ) and current input value( Receives ) as input and performs the operation as in the following mathematical formula 2.

[0075]

[0076] The final cumulative sum is calculated by repeating this operation for all channels.

[0077] A single sequential adder / subtractor (600) has a bit width sufficient to accommodate the cumulative operation results of all channels, and can be set to, for example, an (n+7) bit level.

[0078] Here, n represents the number of input channels, and the additional bit is used as a spare bit to prevent overflow that may occur during the accumulation process.

[0079] A single sequential adder / subtractor (600) is controlled by a control unit (not shown), and the control unit is configured to sequentially input binary data of each channel according to a predetermined order.

[0080] In addition, the accumulated result from each operation step is stored in a register or latch and is reused as the previous accumulated value in the next operation.

[0081] Accordingly, multiple channel data are processed by temporally dividing them through a single adder / subtractor.

[0082] According to the present embodiment, the following effects can be obtained by using a single sequential adder / subtractor (600) instead of configuring a plurality of adders / subtractors (500) in parallel.

[0083] First, there is a hardware resource saving effect. That is, the number of adders and subtractors can be reduced to one, which can significantly reduce circuit area and power consumption.

[0084] Second, it is possible to reuse temporal resources by utilizing the characteristics of probabilistic operations. Since probabilistic operations require a relatively long processing time depending on the bitstream length, the accumulation operation of all channels can be performed using a single adder / subtractor during this time.

[0085] Third, efficient computation is possible without a decrease in throughput. In other words, even when using a sequential computation structure, cumulative computation is completed within the delay time of probabilistic computation, so there is no substantial impact on the overall system's processing performance.

[0086] FIG. 5 is a graph illustrating the output characteristics of a probabilistic computation-based neural network accelerator device according to one embodiment of the present invention.

[0087] As shown in FIG. 5, the graph is composed of two subgraphs, (a) and (b), each representing the distribution or activation characteristics of the output value according to the input value.

[0088] First, FIG. 5(a) shows the distribution or non-linear transformation characteristics of output data generated through a probabilistic operation structure according to the present invention. In the graph (a), the output value shows a tendency to gradually change within a specific range depending on the change in the input value, and in particular, the characteristic of the output value saturating near the upper and lower limits is confirmed. This is due to the saturation logic performed in a plurality of adders and subtractors, reflecting the characteristic that the output value is limited and does not increase further when it exceeds a certain range.

[0089] Next, Figure 5(b) may represent a reference characteristic for comparison with the result of (a), for example, an output characteristic generated by an ideal sigmoid activation function or another operation method. In the graph of (b) as well, the output changes non-linearly depending on the input value, having a slope that is relatively close to linear in the central section, and then gradually saturates as it approaches both ends.

[0090] At this time, by comparing (a) and (b) of FIG. 5, it can be confirmed that the probabilistic operation-based structure according to the present invention can effectively implement non-linear characteristics similar to a sigmoid function without separate complex activation function operations. In particular, by accumulating and summing the probability pulses generated in the probabilistic operation unit through a counter unit and a plurality of adders and subtractors, and applying saturation logic in the final stage, a sigmoid-shaped output curve is naturally formed.

[0091] Accordingly, Figure 5 is a diagram that empirically demonstrates that the device of the present invention can implement the non-linear activation characteristics required in neural networks without increasing hardware complexity.

[0092] FIG. 6 is a graph showing how similar the output generated by a probabilistic computation-based neural network accelerator device according to one embodiment of the present invention is to an ideal sigmoid activation function.

[0093] Figure 6 consists of two subgraphs, (a) and (b), each showing the results when a probabilistic operation is performed under the same input conditions, but the length of the random number bitstream or the internal operation conditions are different.

[0094] In each graph of FIG. 6, the curve indicated by the dotted line represents the ideal sigmoid function value, and the points indicated by the scatter plot represent the probabilistic calculation results generated by the device of the present invention. At this time, each data point represents an output value calculated for a specific input value through a probabilistic calculation unit, a counter unit, and a plurality of adders and subtractors.

[0095] In particular, Figure 6 (a) illustrates the case where a relatively short length random bitstream is used, and accordingly, it can be seen that the output values ​​are distributed around an ideal sigmoid curve, but the variance is large in some sections. This is because statistical variability increases when the number of samples is limited due to the nature of probabilistic operations.

[0096] On the other hand, Figure 6(b) shows the case where a longer random number bitstream or improved operation conditions are applied, and it can be seen that the output data converges more closely to an ideal sigmoid curve. Accordingly, the mean absolute error (MAE) is reduced, and the overall approximation accuracy is improved.

[0097] Accordingly, FIG. 6 shows that the probabilistic operation result of the present invention gradually approximates an ideal sigmoid function depending on the random bitstream length or operation condition, and demonstrates that the device of the present invention can effectively implement non-linear activation characteristics in a statistical manner.

[0098] FIGS. 7 to 9 are graphs showing changes in output characteristics according to various computation conditions or parameter settings in a probabilistic computation-based neural network accelerator device according to an embodiment of the present invention.

[0099] FIGS. 7 to 9 each show results according to different probabilistic operation conditions, such as the length of a random number bitstream, a set value of a variable reduction factor, or the configuration of a probabilistic operation unit.

[0100] In each graph, the dotted line represents the ideal sigmoid function value, and the scatter plot represents the output value generated by the device of the present invention.

[0101] Referring to Fig. 7, when using relatively limited computational resources or a short bitstream, the output value shows a somewhat large deviation from the ideal sigmoid curve, and the error tends to increase, especially in sections where the slope changes rapidly.

[0102] In Figure 8, as the operation conditions are improved, it can be seen that the output values ​​are distributed closer to the ideal sigmoid curve and the overall error is reduced.

[0103] In addition, Figure 9 shows a case where additional parameter adjustments or optimized settings are applied, in which the output value is aligned more closely with the ideal sigmoid function, and particularly shows a high degree of alignment in both the central and saturation sections.

[0104] As such, FIGS. 7 to 9 show that the device of the present invention can flexibly adjust output characteristics according to various computation conditions and parameter settings, and can implement high-accuracy sigmoid approximation characteristics through appropriate settings.

[0105] The embodiments disclosed in this specification have been described above with reference to the accompanying drawings. The embodiments illustrated in each drawing should not be interpreted restrictively and may be combined with one another by those skilled in the art who have read the contents of this specification; in such cases, it may be interpreted that some components may be omitted.

[0106] Herein, terms or words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a sense and concept consistent with the technical ideas disclosed in this specification.

[0107] Therefore, it should be understood that the embodiments described in this specification and the configurations illustrated in the drawings are merely embodiments disclosed in this specification and do not represent all technical ideas disclosed in this specification, and that various equivalents and modifications that can replace them may exist at the time of filing this application. Explanation of the symbols

[0109] 100: Single random number generator 200: Random number allocation wiring unit 300: Multiple probabilistic operation units 310: First comparator 320: 2nd comparator 330: 3rd comparator 400: Counter section 500: Multiple adders / subtractors 510: 9-bit adder / subtractor 520: 10-bit adder / subtractor 530: 11-bit adder / subtractor 600: Single sequential adder / subtractor

Claims

Claim 1 A probabilistic operation-based neural network accelerator device comprising: a single random number generator that generates a pseudo-random number bitstream; a random number allocation wiring unit that divides the random number bitstream into a plurality of bit regions and selectively allocates some bits of the bit regions for each operation path; a plurality of probabilistic operation units that generate a probability pulse and perform a logical AND operation by comparing the allocated random number bits with an input signal, a weight signal, and a variable reduction factor, and selectively bypass the variable reduction factor according to external control to variably perform 2-input or 3-input probability multiplication; a counter unit that converts the output pulse of the probabilistic operation units into binary data; and a plurality of adders / subtractors that sum the binary data and form sigmoid activation function characteristics through a step-by-step bit expansion structure and final stage saturation logic. Claim 2 A probabilistic computation-based neural network accelerator device according to claim 1, wherein the random number allocation wiring unit divides the random number bitstream into a plurality of predefined bit intervals and selectively allocates a portion of the bit intervals to each computation path to reduce random number correlation between computation units. Claim 3 A probabilistic computation-based neural network accelerator device according to claim 2, wherein the random number allocation wiring unit rearranges the order of bits selected from the bit interval using a cross-wiring or position shift method and supplies them to each computation path. Claim 4 A probabilistic operation-based neural network accelerator device according to claim 1, wherein the single random number generator comprises a linear feedback shift register (LFSR) or an XOR-based random number generator using a previous state value. Claim 5 A neural network accelerator device based on probabilistic operation according to claim 1, wherein the probabilistic operation unit is configured such that the comparator output corresponding to the variable reduction coefficient is fixed to a logic 'High' value in bypass mode, and performs a 2-input probabilistic multiplication of the input signal and the weight signal. Claim 6 A probabilistic computation-based neural network accelerator device according to claim 1, characterized in that the variable reduction coefficient is applied commonly to a plurality of the probabilistic computation units and operates as a Global Gain parameter that controls the magnitude of the total computation output. Claim 7 A probabilistic computation-based neural network accelerator device according to claim 6, characterized in that the frequency of probability pulse generation is adjusted according to the value of the variable reduction coefficient, and the slope of the sigmoid activation function is variably adjusted. Claim 8 A probabilistic computation-based neural network accelerator device according to claim 1, wherein the counter unit accumulates and measures the output pulses of the probabilistic computation unit that occur during a predetermined clock cycle and converts them into binary data. Claim 9 A probabilistic operation-based neural network accelerator device according to claim 1, characterized in that the plurality of adders and subtractors are arranged in a hierarchical tree structure and configured to have a bit width that is 1 bit longer than the bit width of the input data at each stage. Claim 10 A probabilistic operation-based neural network accelerator device according to claim 9, characterized in that, in the final stage of the above-mentioned adder / subtractor, saturation logic is applied to fix the output value to the maximum value when an upper bit exceeding a predetermined bit width occurs. Claim 11 A probabilistic operation-based neural network accelerator device according to claim 10, characterized in that the saturation logic is combined with distribution characteristics generated by probabilistic operation to form a continuous non-linear output curve, thereby implementing characteristics similar to a sigmoid activation function. Claim 12 A probabilistic operation-based neural network accelerator device according to claim 1, characterized in that a latch or flip-flop for pipeline processing is disposed between the probabilistic operation unit, the counter unit, and the adder / subtractor to minimize data path delay. Claim 13 A probabilistic operation-based neural network accelerator device according to claim 1, characterized in that, instead of the plurality of adders / subtractors, it includes a single sequential adder / subtractor that calculates a cumulative sum by sequentially processing binary data output from the counter unit in time. Claim 14 A probabilistic operation-based neural network accelerator device according to claim 13, wherein the single sequential adder / subtractor includes an input selection logic that sequentially selects and supplies one of a plurality of input channels according to a channel selection signal provided from a control unit, and is configured to sequentially accumulate binary data for a plurality of input channels during the processing time of a bitstream generated by a probabilistic operation.

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