Amplifier Circuit

Abstract

An amplifier circuit according to an exemplary embodiment of the present disclosure comprises an operational amplifier having a first amplifier input terminal connected as an input to an inverter circuit and an amplifier output terminal connected as an output to a folded cascode circuit, a feedback capacitor and a reset switch connected in parallel to the amplifier input terminal and the amplifier output terminal, respectively.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to an amplifier circuit, and more specifically, to an amplifier circuit having an enhanced ICMR (Input Common Mode Range). Background Technology

[0002] With the development of industry today, various technologies are being proposed in various industrial fields to acquire images of subjects and process information based on those images.

[0003] Among these, the X-ray detector converts X-rays into analog electrical signals and acquires X-ray images based on them. Amplifier circuits are used to amplify the electrical signals for acquiring X-ray images and to improve the signal-to-noise ratio (SNR).

[0004] In general amplifier circuits, it is important to reduce distortion and maintain stable operation during the process of amplifying the input signal and outputting it.

[0005] To this end, various techniques are used, and diverse amplifier circuits are utilized to improve signal quality. However, in conventional circuit structures, noise and nonlinearity can occur during signal transmission, and there may be a trade-off between ICMR and noise performance. The problem to be solved

[0006] The problem that the technical concept of the present disclosure aims to solve is to enable securing a wide ICMR even with improved noise performance by proposing a structure including a charging capacitor, a feedback capacitor, and a reset switch. means of solving the problem

[0007] An amplifier circuit according to an exemplary embodiment of the present disclosure comprises an operational amplifier having a first amplifier input terminal connected as an input to an inverter circuit and an amplifier output terminal connected as an output to a folded cascode circuit, a feedback capacitor and a reset switch connected in parallel to the amplifier input terminal and the amplifier output terminal, respectively.

[0008] Additionally, the operational amplifier includes a driving voltage terminal and a ground voltage terminal, and the amplifier circuit further includes an input charging circuit connected to the driving voltage terminal and the ground voltage terminal, comprising a charging capacitor and capacitor switches connected in pairs across the charging capacitor and switching at the same timing.

[0009] Additionally, the capacitor switch includes a first capacitor switch and a second capacitor switch, and both the first capacitor switch and the second capacitor switch perform a switching operation in which they are connected to a source voltage, or both the first capacitor switch and the second capacitor switch perform a switching operation in which they are connected to the driving voltage terminal and the ground voltage terminal, respectively.

[0010] Meanwhile, the capacitor switches perform a turn-on switching operation to supply the charge stored in the feedback capacitor to the operational amplifier in response to receiving a signal indicating the turn-on of the operational amplifier.

[0011] Meanwhile, the above reset switch performs a turn-on switching operation at the same timing as the above capacitor switches.

[0012] Meanwhile, the above operational amplifier further includes a second amplifier input terminal receiving a reference voltage and further includes a signal switch connected to the first amplifier input terminal.

[0013] In addition, the signal switch is turned on so that the operational amplifier receives the TFT signal when the capacitor switches are turned on and the reset switch is turned off.

[0014] Meanwhile, the above operational amplifier includes the above folded cascode circuit, and the above folded cascode circuit is,

[0015] It includes a first mirror cascode module and a second mirror cascode module, and is connected in parallel with the first mirror cascode module and the second mirror cascode module to receive a differential input from the inverter circuit.

[0016] In addition, the inverter circuit includes inverter transistors, each having its gate terminal connected to one another.

[0017] The above inverter transistors output a signal to the above folded cascode circuit.

[0018] Meanwhile, the above inverter circuit includes a first inverter module and a second inverter module, and when a voltage higher than the operating voltage of the first inverter module is applied as the input voltage of the operational amplifier, the second inverter module operates based on the current supply of the first mirror cascode module.

[0019] Meanwhile, the above cascode circuit further includes a third mirror cascode module, wherein one end of the third mirror cascode module connected to one end of the second mirror cascode module is connected to a shared gate node of the first mirror cascode module, and the other end of the second mirror cascode module connected to the other end of the second mirror cascode module is connected to the amplifier output terminal.

[0020] An amplifier circuit according to an exemplary embodiment of the present disclosure may include a feedback capacitor connected to a first amplifier input terminal connected as an input to an inverter circuit and an amplifier output terminal connected as an output to a folded cascode circuit, and a reset switch connected in parallel with said feedback capacitor.

[0021] Additionally, the operational amplifier includes a driving voltage terminal and a ground voltage terminal, and the amplifier circuit may further include an input charging circuit connected to the driving voltage terminal and the ground voltage terminal, and comprising a charging capacitor and capacitor switches connected in pairs to both ends of the charging capacitor and switching operation at the same timing.

[0022] Additionally, the capacitor switch includes a first capacitor switch and a second capacitor switch, and both the first capacitor switch and the second capacitor switch may perform a switching operation in which they are connected to a source voltage, or both the first capacitor switch and the second capacitor switch may perform a switching operation in which they are connected to the driving voltage terminal and the ground voltage terminal, respectively.

[0023] Meanwhile, the capacitor switches may be characterized by performing a turn-on switching operation in response to receiving a signal indicating the turn-on of the operational amplifier.

[0024] Meanwhile, the above operational amplifier further includes a second amplifier input terminal receiving a reference voltage, and may further include a signal switch connected to both ends of the photodiode of the TFT panel and the first amplifier input terminal.

[0025] In addition, the signal switch can be turned on so that the operational amplifier receives the TFT signal when the capacitor switches are turned on and the reset switch is turned off.

[0026] Meanwhile, the amplifier output stage can be formed as a single-ended output stage.

[0027] Meanwhile, the above operational amplifier includes the above folded cascode circuit, and the above folded cascode circuit includes a first mirror cascode module and a second mirror cascode module, and is connected in parallel with the first mirror cascode module and the second mirror cascode module to receive a differential input from the inverter circuit. Effects of the invention

[0028] An amplifier circuit according to an exemplary embodiment of the present disclosure can secure a wide ICMR while having improved noise performance.

[0029] An amplifier circuit according to an exemplary embodiment of the present disclosure can improve the complexity and integration of the circuit by excluding an external power supply to the feedback capacitor based on a wide ICMR.

[0030] An amplifier circuit according to an exemplary embodiment of the present disclosure can reduce the power consumption of the amplifier circuit and the electronic system by turning off the capacitor switch after a preset time after the signal switch is turned off, thereby stopping the operation of the operational amplifier while no meaningful signal is output from the TFT panel. Brief explanation of the drawing

[0031] FIG. 1 is a system diagram according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram according to an exemplary embodiment of the present disclosure. FIG. 3 is a circuit diagram for explaining an amplifier circuit according to an exemplary embodiment of the present disclosure. FIG. 4 is a timing diagram according to an exemplary embodiment of the present disclosure. FIG. 5 is a circuit diagram for explaining an operational amplifier internal circuit according to an exemplary embodiment of the present disclosure. FIG. 6 is a comparative example for illustrating an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0032] The transistor described below is based on a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) for the sake of convenience; however, the technical concept is not limited thereto and may include various switching devices of a similar nature. For example, the gate terminal can be interpreted as the control terminal of the switching device, and the source / drain terminals as the current-carrying terminals of the switching device.

[0033] Furthermore, although the units and numerical values ​​expressed in the following description are result values ​​based on simulation results, the effect of the technical concept is not to be interpreted restrictively based on said units and numerical values.

[0034] In the following, it goes without saying that, according to Ohm's law, an electrical signal expressed in voltage can be interpreted by substituting it with current, and conversely, an electrical signal expressed in current can be interpreted by substituting it with voltage.

[0035] Meanwhile, the meaning of connection below can be interpreted in various ways depending on the context, such as electrical, structural, or physical connections.

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0038] FIG. 1 is a system diagram according to an exemplary embodiment of the present disclosure.

[0039] Referring to FIG. 1, the electronic system includes a detector (1) and an X-ray generator (2), the detector (1) may include a scintillator (10), a TFT (Thin Film Transistor) panel (20) and an ROIC (Read Out Integrated Circuit) (30), and the ROIC (30) may include at least one amplifier circuit (100).

[0040] The subject is positioned between the detector (1) and the X-ray generator (2), and the detector (1) receives X-rays generated from the X-ray generator (2), and the detector (1) can process and generate image data based on the received X-rays. In this disclosure, the electronic system is described as an X-ray-based system, but is not limited thereto and can be applied to various image acquisition devices such as visible light-based CMOS systems.

[0041] The scintillator (10) converts X-rays that have passed through the subject into visible light according to internal crystal structure and material properties, the TFT panel (20) generates and stores charges in each pixel in proportion to the intensity of the converted visible light, and the ROIC (30) reads the charge signals stored in each pixel, converts them into digital signals, and then generates an image based on them.

[0042] Here, the ROIC (30) may include an amplifier circuit (100). The ROIC (30) can amplify the signal and improve noise to generate an X-ray image.

[0043] For example, the ROIC (30) includes a plurality of amplifier circuits (100) as many times as the number of output lines extending from a plurality of pixels included in the TFT panel (20).

[0044] According to an exemplary embodiment of the present disclosure, an amplifier circuit (100) with improved complexity and volume is proposed, thereby improving the integration density of the ROIC (30). Additionally, an amplifier circuit with improved ICMR is provided, thereby enabling processing of various signal strengths output from the TFT panel (20), allowing for stable amplification of a wide range of signals, reduced signal distortion, and a high signal-to-noise ratio (SNR).

[0046] FIG. 2 is a block diagram according to an exemplary embodiment of the present disclosure.

[0047] Referring to FIG. 2, the amplifier circuit (100) can be operated by a control signal (SIG) of a controller (200). For example, the switching operation of switches included in the amplifier circuit (100) can be turned on or turned off based on the control signal (SIG).

[0048] The controller (200) may be included within an electronic system in the form of electronic hardware, software, or firmware. Alternatively, it may be included in an external server device to wirelessly transmit control signals (SIG). For example, the controller (200) may be included outside the ROIC (30) as an internal component of the detector (1), but is not limited thereto.

[0049] In the following, a signal required to control the amplifier circuit (100) may be included as a sub-command of the control signal (SIG).

[0051] FIG. 3 is a circuit diagram for explaining an amplifier circuit according to an exemplary embodiment of the present disclosure.

[0052] Referring to FIG. 3, the amplifier circuit (100) may include an input charging circuit (ICC), an operational amplifier (A1), a reset switch (SR), and a feedback capacitor (CF).

[0053] The input charging circuit (ICC) includes a charging capacitor (CP) and a capacitor switch (SC), and the capacitor switch (SC) includes a first capacitor switch (SC1) and a second capacitor switch (SC2). The input charging circuit (ICC) can receive a source voltage (VS) and provide a voltage that can drive the operational amplifier (A1).

[0054] Here, the first capacitor switch (SC1) and the second capacitor switch (SC2) are connected to both ends of the charging capacitor (CP) and can perform switching operations at the same timing. For example, the first capacitor switch (SC1) and the second capacitor switch (SC2) may both be in a turned-on state at the same timing, or the first capacitor switch (SC1) and the second capacitor switch (SC2) may both be in a turned-off state at the same timing. The description regarding the turned-on state and the turned-off state of the capacitor switch (SC) will be provided later.

[0055] The operational amplifier (A1) can receive a driving voltage (VDD) and a ground voltage (VSS) based on an input charging circuit (ICC).

[0056] The operational amplifier (A1) can provide an output voltage through the amplifier output terminal (VO) based on the voltage received at the first amplifier input terminal (VN) and the second amplifier input terminal (VP). The electronic system can generate an X-ray image based on the output voltage. Here, the first amplifier input terminal (VN) and the second amplifier input terminal (VP) can be represented as an inverting input terminal and a non-inverting input terminal, respectively, but conversely, they can also be implemented as a non-inverting input terminal and an inverting input terminal, respectively.

[0057] A reference voltage (VREF) may be applied from inside or outside the amplifier circuit (100). The amplifier circuit (100) may generate an output voltage based on a TFT signal (e.g., which can be expressed as a voltage) applied from the first amplifier input terminal (VN) and a reference voltage (VREF) applied from the second amplifier input terminal (VP).

[0058] The TFT panel (20) can generate a TFT signal by means of a photodiode (PD) and can determine whether to output the TFT signal based on a signal switch (ST). In other words, both ends of the signal switch (ST) can be connected to the photodiode (PD) and the first amplifier input terminal (VN), respectively. The TFT signal can serve as the basis for an X-ray image generated by an electronic system. Meanwhile, the TFT panel (20) may include a signal switch (ST), but is not limited thereto, and may also be included in the ROIC (30). Additionally, the signal switch (ST) may be located between the TFT panel (20) and the ROIC (30).

[0059] The operational amplifier (A1) can be fed back through the first amplifier input terminal (VN) and the amplifier output terminal (VO). The reset switch (SR) and the feedback capacitor (CF) can be connected in parallel. When the reset switch (SR) is turned on, the path containing the reset switch (SR) is short-circuited so that all the charge of the feedback capacitor (CF) leaks out and the potential difference becomes zero, and when the reset switch (SR) is turned off, the feedback capacitor (CF) can have a potential difference of a certain level.

[0061] FIG. 4 is a timing diagram according to an exemplary embodiment of the present disclosure.

[0062] Referring to FIG. 4, the horizontal axis of the timing diagram represents time, and the logic high level and logic low level of the signal switch (ST), capacitor switch (SC), and reset switch (SR) shown in the timing diagram indicate the turn-on and turn-off states, respectively, and the output voltage of the amplifier output terminal (VO) shown in the timing diagram indicates the value of the analog level.

[0063] Meanwhile, the turn-off state of the capacitor switch (SC) means that it is electrically connected to the source voltage (VS), and the turn-on state means that it is connected to the driving voltage (VDD) terminal and the ground voltage (VSS) terminal.

[0064] Specifically, the first capacitor switch (SC1) and the second capacitor switch (SC2) may both be in a turned-off state connected to the source voltage (VS) at the same timing, and the first capacitor switch (SC1) and the second capacitor switch (SC2) may both be in a turned-on state connected to the driving voltage (VDD) terminal and the ground voltage (VSS) terminal, respectively, at the same timing.

[0065] Meanwhile, the turn-on state of the reset switch (SR) and the signal switch (ST) means a short-circuit state, and the turn-off state means an open state.

[0066] In addition, the turn-on state of the reset switch (SR) may indicate that a reset operation is being performed, and the turn-on state of the capacitor switch (SC) may indicate that the operational amplifier (A1) is being operated.

[0067] The capacitor switches (SC), reset switch (SR), and signal switch (ST) can perform switching operations by means of a control signal (SIG) of the controller (200). For example, the controller (200) can generate a control signal (SIG) including a signal indicating the start of operation of the operational amplifier (A1) (i.e., a signal indicating turn-on) and provide it to the first capacitor switch (SC1) and the second capacitor switch (SC2).

[0068] Before the first time interval (T1), the capacitor switch (SC) is in the turned-off state, and the charging capacitor (CP) can be charged by the source voltage (VS).

[0069] In the first time interval (T1), the capacitor switch (SC) and the reset switch (SR) are in the turned-on state, and the signal switch (ST) may be in the turned-off state. At this time, the first capacitor switch (SC1) and the second capacitor switch (SC2) are both in the same turned-on state. In other words, the first capacitor switch (SC1), the second capacitor switch (SC2), and the reset switch (SR) can be transitioned from the turned-off state to the turned-on state by the control signal (SIG) at the same timing.

[0070] In addition, as the reset switch (SR) is turned on, the potential difference of the feedback capacitor (CF) can be reset to 0.

[0071] Meanwhile, in response to the reset switch (SR) transitioning from turn-off to turn-on during the first time interval (T1), the output voltage (VO) can rise from any reset level. The output voltage (VO) can enter a normal state after the reset switch is turned on and before it is turned off.

[0072] The second time interval (T2) may mean a state ready to output actual data. As the output voltage (VO) reaches a normal state value indicating a reset state, the reset switch (SR) can be turned off as the intended purpose of the reset operation has been achieved.

[0073] The third time interval (T3) may refer to a state in which the operational amplifier (A1) outputs actual data.

[0074] In the third time interval (T3), the signal switch (ST) is turned on so that the voltage of the TFT signal output by the photodiode (PD) can be applied to the operational amplifier (A1). As a result, the output voltage (VO) can be linearly lowered in voltage level, and the output voltage (VO) can have a value according to the TFT signal of the photodiode (PD). In other words, the level of the output voltage (VO) can be lowered by the charge output from the TFT panel (20).

[0075] Meanwhile, in the third time interval (T3), the output voltage (VO) has a high slope like the solid line when a relatively large amount of charge is input from the TFT panel (20), but can have a low slope like the dashed line when a relatively small amount of charge is input.

[0076] In other words, when the capacitor switches (SC) are turned on and the reset switch (SR) is turned off, the controller (200) can turn on the signal switch (ST) so that the operational amplifier (A1) receives the TFT signal.

[0077] Meanwhile, in the third time interval (T3), the time and voltage range during which the output voltage level decreases according to the rising level of the reference voltage (VREF) can be expressed as ICMR.

[0078] Meanwhile, the signal switch (ST) can be turned off during the fourth time interval (T4). The output voltage (VO) can be clipped to the level at the moment the signal switch (ST) is turned off.

[0079] After this, when the capacitor switch (SC) is turned off in the fifth time interval (T5), the driving voltage (VDD) provided to the operational amplifier (A1) disappears, and the operational amplifier (A1) is not driven. As a result, the level of the output voltage (VO) can drop to 0 (zero) or the ground voltage level.

[0080] An amplifier circuit according to an exemplary embodiment of the present disclosure can reduce the power consumption of the amplifier circuit and the electronic system by turning off the capacitor switch (SC) after a preset time (e.g., a fourth time interval (T4)) following the signal switch (ST) being turned off, thereby stopping the operation of the operational amplifier (A1) while no meaningful signal is output from the TFT panel (20). On the other hand, a conventional circuit continuously provides a driving voltage even when no meaningful signal is output from the TFT panel (20), thereby consuming unnecessary power.

[0081] After this, the controller (200) can turn on the capacitor switch (SC) and the reset switch (SR) to bring the operational amplifier (A1) back into operation.

[0083] FIG. 5 is a circuit diagram for explaining an operational amplifier internal circuit according to an exemplary embodiment of the present disclosure.

[0084] The operational amplifier (A1) may include an input stage and an output stage. The input stage may include an inverter circuit configuration. The output stage may include a folded cascode circuit configuration. Additionally, the operational amplifier (A1) may include transistors (M3, M4) that can be replaced with current sources.

[0085] The operational amplifier (A1) may include a first inverter module (M1), a second inverter module (M2), a transistor (M3), a transistor (M4), a first mirror cascode module (M5), a second mirror cascode module (M6), a third mirror cascode module (M7), and a fourth mirror cascode module (M8).

[0086] Each of the first inverter module (M1), the second inverter module (M2), the first mirror cascode module (M5), the second mirror cascode module (M6), the third mirror cascode module (M7), and the fourth mirror cascode module (M8) may include a pair of inverter transistors (M1A, M1B), a pair of inverter transistors (M2A, M2B), a pair of transistors (M5A, M5B), a pair of transistors (M6A, M6B), a pair of transistors (M7A, M7B), and a pair of transistors (M8A, M8B).

[0087] For example, the gate terminals of the inverter transistors (M1A, M2A) included in each of the first inverter module (M1) and the second inverter module (M2) can be connected to each other, and the source / drain terminals of a pair of inverter transistors (M1A, M1B) included in the first inverter module (M1) can be connected to each other. Additionally, the gate terminals of the transistors included in each of the mirror cascode modules (M5, M6) or mirror cascode modules (M7, M8) can be connected to each other.

[0088] The first amplifier input terminal (VN) and the second amplifier input terminal (VP) may be inputs to an inverter circuit. For example, one of the source / drain terminals of a pair of inverter transistors (M1B, M2B) is connected to each other, their gate terminals are connected to each other, and the first amplifier input terminal (VN) is connected to the node of the shared gate terminal.

[0089] The amplifier output stage (VO) can be configured as a single-ended output stage. That is, the complexity of the amplifier circuit is improved by converting the signal from the differential input terminals (e.g., the first amplifier input stage (VN) and the second amplifier input stage (VP)) into a single output signal.

[0090] As previously explained, the amplifier output terminal (VO) and the first amplifier input terminal (VN) can be fed back to each other. In other words, the amplifier circuit may include a feedback capacitor (CF) and a reset switch (SR) connected in parallel to the first amplifier input terminal (VN) and the amplifier output terminal (VO), respectively.

[0091] The amplifier output stage (VO) can be connected as the output of a folded cascode circuit.

[0092] The output stage can be implemented as a folded cascode circuit by a third mirror cascode module (M7) and a fourth mirror cascode module (M8), each having their respective source / drain terminals connected. Here, the third mirror cascode module (M7) and the fourth mirror cascode module (M8) can each be composed of a mirror pair of the first mirror cascode module (M5) and the second mirror cascode module (M6).

[0093] Additionally, the amplifier output terminal (VO) can be connected to the source / drain terminals of the second mirror cascode module (M6) and the third mirror cascode module (M7) respectively to form a node (ODB).

[0094] The amplifier circuit may include a folded cascode circuit. Here, the folded cascode circuit includes a first mirror cascode module (M5) and a second mirror cascode module (M6), and the input stage may be connected in parallel with the first mirror cascode module (M5) and the second mirror cascode module (M6) to transmit a differential input.

[0095] Here, an inverter circuit may refer to a form in which the gate terminals of an inverter transistor (M1A) and an inverter transistor (M2A) are connected, and one of their source / drain terminals is connected to another. The output of the inverter circuit may be a signal provided at the node of the source / drain terminal where the inverter transistor (M1A) and the inverter transistor (M2A) are connected to each other.

[0096] Furthermore, the differential input from the inverter circuit may include a signal output from the source / drain terminal connected to the inverter transistor (M1A) and the inverter transistor (M2A) and provided to the source / drain terminal of the transistors (M5A, M6A), and a signal output from the source / drain terminal connected to the inverter transistor (M1B) and the inverter transistor (M2B) and provided to the source / drain terminal of the transistors (M5B, M6B). Due to this circuit connection structure, noise removal performance is improved, the ICMR is widened, and the circuit size can be reduced.

[0097] The input stage includes a first inverter module (M1) and a second inverter module (M2). Each of the inverter modules (M1, M2) may have a preset operating range, which is a range of voltage levels at which operation is possible, and the inverter modules (M1, M2) may receive various levels of voltage from amplifier input terminals (VP, VN). For example, the preset operating range may be a range of levels higher than 0.4 V, which is the ICMR of a conventional current reuse circuit, and lower than 1.1 V. When a voltage lower than the preset operating range is applied from the amplifier input terminals (VP, VN), the inverter transistors (M2A, M2B) of the second inverter module (M2) are turned off, preventing current from flowing to the inverter transistors (M1A, M1B) of the first inverter module (M1), and thus the operational amplifier (A1) does not operate. Here, when a voltage higher than the preset operating range is applied from the amplifier input terminals (VP, VN), the inverter transistors (M1A, M1B) of the first inverter module (M1) are turned off, but current flows through the inverter transistors (M2A, M2B) of the second inverter module (M2) via the first mirror cascode module (M5), thereby enabling the operational amplifier (A1) to operate even when a voltage higher than the preset operating range is applied compared to the conventional circuit. Therefore, while a wider ICMR can be obtained compared to the conventional current reuse circuit, the improved noise performance, which is an advantage of the conventional current reuse circuit, can also be obtained. The conventional current reuse circuit could have an ICMR of 0.4 to 1.1 V, but the proposed circuit can have a wide ICMR of 0.5 to 1.6 V. In addition, the noise intensity could be reduced to half the level compared to the conventional folded cascode circuit.

[0098] Meanwhile, feedback connections can be formed between the components included in the cascode circuit.

[0099] Specifically, the source / drain terminals connected to the second mirror cascode module (M6) and the third mirror cascode module (M7) can form a node (ODA) together with the shared gate terminal of the first mirror cascode module (M5).

[0101] FIG. 6 is a comparative example for illustrating an exemplary embodiment of the present disclosure.

[0102] Specifically, the amplifier circuit according to the comparative example has a feedback capacitor ( ) First, the first reset switch ( ) is a voltage source ( It is connected to the feedback capacitor ( At the other end, there is a second reset switch ( ) each has two voltage sources ( , It is connected to ). In the amplifier circuit according to the comparative example, the VCM voltage is formed to half the level of the operational amplifier's driving voltage by the narrow ICMR, and accordingly, the feedback capacitor ( To increase the charge collection rate of the feedback capacitor ( Multiple voltage sources at the other end ( , The circuit size increased because terminals to which ) are applied are required.

[0103] On the other hand, according to an exemplary embodiment of the present disclosure, multiple switches are no longer required due to the increased ICMR, and accordingly, the integration density of the entire circuit could be improved.

[0105] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An operational amplifier comprising: a first amplifier input terminal connected as an input to an inverter circuit; a second amplifier input terminal receiving a reference voltage; and an amplifier output terminal connected as an output to a folded cascode circuit; a feedback capacitor and a reset switch connected in parallel to the first amplifier input terminal and the amplifier output terminal, respectively; and a signal switch connected to the first amplifier input terminal. Claim 2 An amplifier circuit according to claim 1, wherein the operational amplifier comprises a driving voltage terminal and a ground voltage terminal, and the amplifier circuit further comprises an input charging circuit connected to the driving voltage terminal and the ground voltage terminal, and comprising a charging capacitor and capacitor switches connected in pairs to both ends of the charging capacitor and switching operation at the same timing. Claim 3 An amplifier circuit according to claim 2, wherein the capacitor switches include a first capacitor switch and a second capacitor switch, and both the first capacitor switch and the second capacitor switch perform a switching operation connected to a source voltage, or both the first capacitor switch and the second capacitor switch perform a switching operation connected to the driving voltage terminal and the ground voltage terminal, respectively. Claim 4 An amplifier circuit according to claim 2, wherein the capacitor switches perform a turn-on switching operation to supply the charge stored in the charging capacitor to the operational amplifier in response to receiving a signal indicating the turn-on of the operational amplifier. Claim 5 An amplifier circuit according to claim 3, wherein the reset switch performs a turn-on switching operation at the same timing as the capacitor switches. Claim 6 delete Claim 7 An amplifier circuit according to claim 1, wherein the signal switch is turned on so that the operational amplifier receives a TFT signal when the capacitor switches are turned on and the reset switch is turned off. Claim 8 An amplifier circuit according to claim 1, wherein the operational amplifier comprises the folded cascode circuit, and the folded cascode circuit comprises a first mirror cascode module and a second mirror cascode module, and is connected in parallel with the first mirror cascode module and the second mirror cascode module to receive a differential input from the inverter circuit. Claim 9 In claim 8, the inverter circuit comprises inverter transistors, each having its gate terminal connected to one another, and the inverter transistors output a signal to the folded cascode circuit, characterized in that the amplifier circuit is characterized in that. Claim 10 In claim 9, the inverter circuit comprises a first inverter module and a second inverter module, and is characterized in that when a voltage higher than the operable voltage of the first inverter module is applied as the input voltage of the operational amplifier, the second inverter module operates based on the current supply of the first mirror cascode module. Claim 11 In claim 8, the folded cascode circuit further comprises a third mirror cascode module, wherein one end of the third mirror cascode module connected to one end of the second mirror cascode module is connected to a shared gate node of the first mirror cascode module, and the other end of the third mirror cascode module connected to the other end of the second mirror cascode module is connected to the amplifier output terminal. Claim 12 An operational amplifier comprising: a first amplifier input terminal connected as an input to an inverter circuit, a driving voltage terminal, a ground voltage terminal, and an amplifier output terminal connected as an output to a folded cascode circuit; a feedback capacitor and a reset switch connected in parallel to the first amplifier input terminal and the amplifier output terminal, respectively; and an input charging circuit comprising a charging capacitor and a first capacitor switch and a second capacitor switch connected to both ends of the charging capacitor, respectively, wherein both the first capacitor switch and the second capacitor switch perform a switching operation connected to a source voltage, or both the first capacitor switch and the second capacitor switch perform a switching operation connected to the driving voltage terminal and the ground voltage terminal, respectively, and the reset switch performs a turn-on switching operation at the same timing as the first capacitor switch and the second capacitor switch. Claim 13 delete Claim 14 delete Claim 15 An amplifier circuit according to claim 12, wherein the first capacitor switch and the second capacitor switch perform a turn-on switching operation in response to receiving a signal indicating the turn-on of the operational amplifier. Claim 16 An amplifier circuit according to claim 12, wherein the operational amplifier further includes a second amplifier input terminal receiving a reference voltage, and further includes a signal switch connected to both ends of a photodiode of a TFT panel and the first amplifier input terminal, respectively. Claim 17 In claim 16, the amplifier circuit is characterized in that the signal switch is turned on so that the operational amplifier receives a TFT signal when the first capacitor switch and the second capacitor switch are turned on and the reset switch is turned off. Claim 18 An amplifier circuit according to claim 12, wherein the amplifier output stage is formed as a single-ended output stage. Claim 19 In claim 12, the operational amplifier comprises the folded cascode circuit, and the folded cascode circuit comprises a first mirror cascode module and a second mirror cascode module, and is connected in parallel with the first mirror cascode module and the second mirror cascode module to receive a differential input from the inverter circuit.

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