Semiconductor package

Abstract

A semiconductor package according to the concept of the present invention comprises: a redistribution substrate, wherein the redistribution substrate includes a first surface and a second surface opposite to each other; a first semiconductor chip provided on the first surface of the redistribution substrate; external terminals provided on the second surface of the redistribution substrate; a second semiconductor chip provided on the first semiconductor chip; external connection members provided below the second semiconductor chip, each of the external connection members including a conductive bump pattern and a solder pattern on the conductive bump pattern; and conductive pillars electrically connecting the external connection members and the redistribution substrate, wherein the second semiconductor chip includes a semiconductor substrate and a device layer, a wiring layer, and a redistribution layer stacked sequentially on the semiconductor substrate, wherein the wiring layer includes intermetallic insulating films stacked sequentially, wiring interposed between the intermetallic insulating films, and a conductive pad connected to the uppermost wiring among the wirings, and the redistribution layer comprises: a first redistribution insulating film covering the wiring layer; A first redistribution pattern that penetrates the first redistribution insulating film and is connected to the conductive pad and extends over the first redistribution insulating film; and a second redistribution insulating film covering the first redistribution pattern and the first redistribution insulating film, wherein the vertical distance between the semiconductor substrate and the conductive pillars may be smaller than the vertical distance between the first semiconductor chip and the external terminals.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, and more specifically, to a semiconductor package comprising stacked semiconductor chips. Background Technology

[0002] In the semiconductor industry, the increasing demand for high capacity, thinness, and miniaturization of semiconductor devices and electronic products utilizing them has led to the rapid emergence of various related packaging technologies. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, there is a growing demand for high functionality, high speed, and miniaturization of semiconductor packages. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved electrical characteristics. means of solving the problem

[0004] A semiconductor package according to the concept of the present invention comprises: a redistribution substrate, wherein the redistribution substrate includes a first surface and a second surface opposite to each other; a first semiconductor chip provided on the first surface of the redistribution substrate; external terminals provided on the second surface of the redistribution substrate; a second semiconductor chip provided on the first semiconductor chip; external connection members provided below the second semiconductor chip, each of the external connection members including a conductive bump pattern and a solder pattern on the conductive bump pattern; and conductive pillars electrically connecting the external connection members and the redistribution substrate, wherein the second semiconductor chip includes a semiconductor substrate and a device layer, a wiring layer, and a redistribution layer stacked sequentially on the semiconductor substrate, wherein the wiring layer includes intermetallic insulating films stacked sequentially, wiring interposed between the intermetallic insulating films, and a conductive pad connected to the uppermost wiring among the wirings, and the redistribution layer comprises: a first redistribution insulating film covering the wiring layer; A first redistribution pattern that penetrates the first redistribution insulating film and is connected to the conductive pad and extends over the first redistribution insulating film; and a second redistribution insulating film covering the first redistribution pattern and the first redistribution insulating film, wherein the vertical distance between the semiconductor substrate and the conductive pillars may be smaller than the vertical distance between the first semiconductor chip and the external terminals.

[0005] A semiconductor package according to another concept of the present invention comprises: a redistribution substrate, wherein the redistribution substrate includes a first surface and a second surface opposite to each other; a first semiconductor chip on the first surface of the redistribution substrate; a second semiconductor chip on the first semiconductor chip, wherein a portion of the second semiconductor chip is vertically superimposed with the first semiconductor chip; connection terminals between the first semiconductor chip and the redistribution substrate; external connection members below the second semiconductor chip; and conductive pillars extending vertically from the redistribution substrate to the external connection members, wherein the second semiconductor chip comprises a semiconductor substrate and a device layer, a wiring layer, and a redistribution layer stacked thereon in sequence, wherein the wiring layer comprises intermetallic insulating films stacked in sequence, wiring interposed between the intermetallic insulating films, and a conductive pad connected to the uppermost wiring among the wirings, and the redistribution layer comprises: a first redistribution insulating film covering the wiring layer; and a first redistribution pattern extending over the first redistribution insulating film, connected to the conductive pad, penetrating the first redistribution insulating film. The apparatus includes a first redistribution pattern and a second redistribution insulating film covering the first redistribution insulating film, wherein each of the external connection members includes a conductive bump pattern in contact with the first redistribution pattern and a solder pattern on the conductive bump pattern, the pitch between the connection terminals is smaller than the pitch between the external connection members, and the maximum width of each of the connection terminals may be smaller than the maximum width of each of the external connection members.

[0006] A semiconductor package according to another concept of the present invention comprises: a redistribution substrate, wherein the redistribution substrate includes a first surface and a second surface opposite to each other; wherein the redistribution substrate includes a first redistribution insulating film, a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern provided sequentially within the first redistribution insulating film in a direction from the second surface of the redistribution substrate toward the first surface; a first semiconductor chip provided on the first surface of the redistribution substrate; a second semiconductor chip provided on the first semiconductor chip, wherein a portion of the second semiconductor chip is vertically superimposed with the first semiconductor chip; connection terminals provided between the first semiconductor chip and the redistribution substrate; external connection members provided on the second semiconductor chip, wherein each of the external connection members includes a conductive bump pattern and a solder pattern on the conductive bump pattern; conductive pillars electrically connecting the solder pattern and the redistribution substrate; and a molding film covering the first semiconductor chip and the second semiconductor chip. and external terminals provided on the second surface of the redistribution substrate, wherein the second semiconductor chip comprises a semiconductor substrate and a device layer, a wiring layer, and a redistribution layer stacked sequentially on the semiconductor substrate, and the wiring layer comprises intermetallic insulating films stacked sequentially, wirings interposed between the intermetallic insulating films, and a conductive pad connected to the uppermost wiring among the wirings, and the redistribution layer comprises: a second redistribution insulating film covering the wiring layer; and a fourth redistribution pattern extending over the second redistribution insulating film, connected to the conductive pad through the second redistribution insulating film.and includes a third redistribution insulating film covering the fourth redistribution pattern and the second redistribution insulating film, wherein the fourth redistribution pattern includes a contact portion connected to the conductive pad by penetrating the second redistribution insulating film, a pad portion on the second redistribution insulating film, and a line portion connecting the contact portion and the pad portion, wherein the pad portion contacts the under-bump pattern, and each of the first to third redistribution patterns includes a wiring portion extending in a direction parallel to the first surface of the redistribution substrate and a via portion protruding from the wiring portion toward the second surface of the redistribution substrate, wherein the width of the via portion decreases as it moves from the first surface of the redistribution substrate toward the second surface, and the vertical distance between the semiconductor substrate and the conductive pillars may be smaller than the vertical distance between the first semiconductor chip and the external terminals. Effects of the invention

[0007] According to the present invention, the redistribution layer of the second semiconductor chip can be formed through an in-fab process rather than a post-fab process. That is, the redistribution layer of the second semiconductor chip can be formed by utilizing the semiconductor chip manufacturing process as is. This provides the advantage of being able to form the redistribution layer of the second semiconductor chip without separate equipment investment in the post-fab process.

[0008] According to the present invention, a second semiconductor chip can be placed at a higher level than the first semiconductor chip using conductive pillars such that a portion of the second semiconductor chip overlaps vertically with the first semiconductor chip. As a result, the size of the semiconductor package can be reduced compared to when the second semiconductor chip is placed at the same level as the first semiconductor chip. Consequently, a miniaturized semiconductor package can be provided.

[0009] In addition, since the redistribution layer of the second semiconductor chip is formed using an in-fab process, it is possible to form external connection members corresponding to the pitch between the conductive pillars without forming a separate redistribution substrate. As a result, it becomes easier to miniaturize the semiconductor package using the conductive pillars.

[0010] According to embodiments of the present invention, since the redistribution layer of the second semiconductor chip is formed using an in-fab process, the problem of performance degradation of the semiconductor chip due to high temperature heat can be prevented. As a result, the electrical characteristics of the semiconductor package can be improved. In addition, the manufacturing process can be further simplified because the process of forming a redistribution pattern using a plating process in the post-fab process can be omitted. Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view showing a semiconductor package according to embodiments of the present invention. FIG. 2 is a schematic plan view of a semiconductor package of FIG. 1 according to embodiments of the present invention. Figure 3 is an enlarged view of the P1 region of Figure 1 or a cross-sectional view along the line A-A' of Figure 2. FIG. 4 is a schematic plan view of a semiconductor package according to embodiments of the present invention. FIGS. 5a to 5l are cross-sectional views for explaining a method for manufacturing a semiconductor package according to embodiments of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor package according to embodiments of the present invention. Specific details for implementing the invention

[0012] FIG. 1 is a cross-sectional view showing a semiconductor package according to embodiments of the present invention. FIG. 2 is a schematic plan view of the semiconductor package of FIG. 1 according to embodiments of the present invention. FIG. 3 is an enlarged view of region P1 of FIG. 1 or a cross-sectional view along line A-A' of FIG. 2.

[0013] Referring to FIG. 1, a semiconductor package according to embodiments of the present invention may include a first redistribution substrate (100). The first redistribution substrate (100) may include redistribution insulating films (101, 102, 103), a first redistribution pattern (110), a second redistribution pattern (120), and a third redistribution pattern (130).

[0014] The first redistribution board (100) may include a first surface (100a) and a second surface (100b) that are opposite to each other. For example, the first surface (100a) of the first redistribution board (100) may be the upper surface of the first redistribution board (100), and the second surface (100b) of the first redistribution board (100) may be the lower surface of the first redistribution board (100).

[0015] The redistribution insulating films (101, 102, 103) may include a first redistribution insulating film (101), a second redistribution insulating film (102), and a third redistribution insulating film (103) that are sequentially stacked in a direction toward the first surface (100a) from the second surface (100b) of the first redistribution substrate (100). In other words, the first to third redistribution insulating films (101, 102, 103) may be sequentially stacked in a direction perpendicular to the first surface (100a) of the first redistribution substrate (100) (i.e., a third direction (D3)). The first redistribution substrate (100) may be referred to as a wiring structure. The first surface (100a) of the first redistribution substrate (100) may be the upper surface of the third redistribution insulating film (103). The second surface (100b) of the first redistribution substrate (100) may be the lower surface of the first redistribution insulating film (101).

[0016] A first redistribution pattern (110) may be disposed on a first redistribution insulating film (101). The first redistribution pattern (110) may be provided on a bump pattern (350) to be described later. The first redistribution insulating film (101) may be the lowest redistribution insulating film. The lower surface of the first redistribution pattern (110) may be located at substantially the same level as the second surface (100b) of the first redistribution substrate (100). The first redistribution insulating film (101) may comprise, for example, an organic material such as a photosensitive polymer or a photosensitive dielectric (PID) resin. In this specification, the photosensitive polymer may comprise, for example, at least one of a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer.

[0017] A second redistribution insulating film (102) may be disposed on the first redistribution insulating film (101). The second redistribution insulating film (102) may contain the same material as the first redistribution insulating film (101). For example, the second redistribution insulating film (102) may contain an organic material such as a photosensitive polymer or a photosensitive insulating resin.

[0018] The first rewiring pattern (110) may include a first via portion (110V) and a first wiring portion (110W). The first wiring portion (110W) may be placed within the second rewiring insulating film (102). The first wiring portion (110W) may be placed on the upper surface of the first rewiring insulating film (101). The first wiring portion (110W) may be in contact with the second rewiring pattern (120) to be described later. The first via portion (110V) may be in contact with the bump pattern (350) to be described later. The first via portion (110V) may be connected to the first wiring portion (110W). The first via portion (110V) may be a portion protruding from the first wiring portion (110W) in a direction perpendicular to the first surface (100a) of the first rewiring board (100). Specifically, the first via portion (110V) may be a portion protruding from the first wiring portion (110W) in a direction toward the second surface (100b) from the first surface (100a) of the first rewiring board (100). The first wiring portion (110W) may have a greater width or a longer length than the first via portion (110V). The first via portion (110V) may be provided within the first rewiring insulating film (101).

[0019] The first redistribution pattern (110) may include a first seed pattern (111) and a first conductive layer (113). The first conductive layer (113) may be provided on the upper surface of the first redistribution insulating film (101) and within the first redistribution insulating film (101). The first conductive layer (113) may include a metal such as copper. The first seed pattern (111) may be interposed between the bump pattern (350) to be described later and the first conductive layer (113), and between the first redistribution insulating film (101) and the first conductive layer (113). The first seed pattern (111) may be in contact with the bump pattern (350) to be described later. The first seed pattern (111) may include a conductive material such as copper, titanium, and / or an alloy thereof.

[0020] Each of the first via portion (110V) and the first wiring portion (110W) may include a first seed pattern (111) and a first conductive layer (113). The first seed pattern (111) of the first via portion (110V) may be directly connected to the first seed pattern (111) of the first wiring portion (110W) without an interface. The first seed pattern (111) may be provided between the lower surface of the first conductive layer (113) of the first via portion (110V) and the bump pattern (350) to be described later, and may be interposed between the sidewall of the first conductive layer (113) of the first via portion (110V) and the first redistribution insulating film (101), and between the lower surface of the first conductive layer (113) of the first wiring portion (110W) and the first redistribution insulating film (101). The first seed pattern (111) may not extend onto the sidewalls and upper surfaces of the first conductive layer (113) of the first wiring portion (110W). The first conductive layer (113) of the first via portion (110V) may be directly connected to the first conductive layer (113) of the first wiring portion (110W).

[0021] A second redistribution pattern (120) may be placed on the first redistribution pattern (110). The second redistribution pattern (120) may be electrically connected to the first redistribution pattern (110).

[0022] A third redistribution insulating film (103) may be disposed on the second redistribution insulating film (102). The third redistribution insulating film (103) may contain the same material as the first redistribution insulating film (101). For example, the third redistribution insulating film (103) may contain an organic material such as a photosensitive polymer or a photosensitive insulating resin.

[0023] The second rewiring pattern (120) may include a second via portion (120V) and a second wiring portion (120W). The second wiring portion (120W) may be disposed within the third rewiring insulating film (103). The second wiring portion (120W) may be disposed on the upper surface of the second rewiring insulating film (102). The second wiring portion (120W) may be in contact with the third rewiring pattern (130) to be described later. The second via portion (120V) may be in contact with the first rewiring pattern (110) and may be connected to the second wiring portion (120W). The second via portion (120V) may be a portion protruding from the second wiring portion (120W) in a direction perpendicular to the first surface (100a) of the first rewiring board (100). Specifically, the second via portion (120V) may be a portion protruding from the second wiring portion (120W) in a direction toward the second surface (100b) from the first surface (100a) of the first redistribution board (100). The second wiring portion (120W) may have a greater width or a longer length than the second via portion (120V). The second via portion (120V) may be provided within the second redistribution insulating film (102).

[0024] The second redistribution pattern (120) may include a second seed pattern (121) and a second conductive layer (123). The second conductive layer (123) may be provided on the upper surface of the second redistribution insulating film (102) and within the second redistribution insulating film (102). The second conductive layer (123) may include a metal such as copper. The second seed pattern (121) may be interposed between the first redistribution pattern (110) and the second conductive layer (123), and between the second redistribution insulating film (102) and the second conductive layer (123). The second seed pattern (121) may be in contact with the first redistribution pattern (110). The second seed pattern (121) may include a conductive material such as copper, titanium, and / or an alloy thereof.

[0025] Each of the second via portion (120V) and the second wiring portion (120W) may include a second seed pattern (121) and a second conductive layer (123). The second seed pattern (121) of the second via portion (120V) may be directly connected to the second seed pattern (121) of the second wiring portion (120W) without an interface. The second seed pattern (121) may be provided between the lower surface of the second conductive layer (123) of the second via portion (120V) and the first redistribution pattern (110), and may be interposed between the sidewall of the second conductive layer (123) of the second via portion (120V) and the second redistribution insulating film (102), and between the lower surface of the second conductive layer (123) of the second wiring portion (120W) and the second redistribution insulating film (102). The second seed pattern (121) may not extend onto the sidewalls and upper surfaces of the second conductive layer (123) of the second wiring portion (120W). The second conductive layer (123) of the second via portion (120V) may be directly connected to the second conductive layer (123) of the second wiring portion (120W).

[0026] A third redistribution pattern (130) may be placed on the second redistribution pattern (120). The third redistribution pattern (130) may be electrically connected to the second redistribution pattern (120).

[0027] The third rewiring pattern (130) may include a third via portion (130V) and a third wiring portion (130W). The third wiring portion (130W) may be placed on the upper surface of the third rewiring insulating film (103). The third wiring portion (130W) may be placed within the molding film (300) to be described later. The third wiring portion (130W) may be in contact with either the connection terminals (230) or the conductive pillars (250) to be described later. The third via portion (130V) may be in contact with the second rewiring pattern (120) and may be connected to the third wiring portion (130W). The third via portion (130V) may be a portion protruding from the third wiring portion (130W) in a direction perpendicular to the first surface (100a) of the first rewiring board (100). Specifically, the third via portion (130V) may be a portion protruding from the third wiring portion (130W) in a direction toward the second surface (100b) from the first surface (100a) of the first redistribution board (100). The third wiring portion (130W) may have a greater width or a longer length than the third via portion (130V). The third via portion (130V) may be provided within the third redistribution insulating film (103).

[0028] The third redistribution pattern (130) may include a third seed pattern (131) and a third conductive layer (133). The third conductive layer (133) may be provided on the upper surface of the third redistribution insulating film (103) and within the third redistribution insulating film (103). The third conductive layer (133) may include a metal such as copper. The third seed pattern (131) may be interposed between the second redistribution pattern (120) and the third conductive layer (133), and between the third redistribution insulating film (103) and the third conductive layer (133). The third seed pattern (131) may be in contact with the second redistribution pattern (120). The third seed pattern (131) may include a conductive material such as copper, titanium, and / or an alloy thereof.

[0029] The width of each of the first to third via portions (110V, 120V, 130V) may decrease as it goes from the first surface (100a) of the first redistribution board (100) toward the second surface (100b).

[0030] A first semiconductor chip (210) may be disposed on a first surface (100a) of a first rewiring substrate (100). The first semiconductor chip (210) may include an inactive surface (210a) and an active surface (210b) that are opposite to each other. The first semiconductor chip (210) may include an active portion (210c) adjacent to its active surface (210b). The active portion (210c) of the first semiconductor chip (210) may include a plurality of transistors constituting an integrated circuit. The first semiconductor chip (210) may be a memory chip such as a DRAM or VNAND, or a logic chip such as a System on Chip (SOC).

[0031] Connection terminals (230) may be provided between the first semiconductor chip (210) and the first redistribution board (100). Specifically, each of the connection terminals (230) may be interposed between the third redistribution pattern (130) and the first semiconductor chip (210). Each of the connection terminals (230) may include solder, bumps, pillars, and / or a combination thereof. For example, the connection terminal (230) may include a solder material. The first semiconductor chip (210) and the first redistribution board (100) may be electrically connected by the connection terminals (230).

[0032] A second semiconductor chip (220) may be placed on a first surface (100a) of a first rewiring board (100). The second semiconductor chip (220) may be placed on the first semiconductor chip (210). The second semiconductor chip (220) may be placed at a higher level than the first semiconductor chip (210). A portion of the second semiconductor chip (220) may be vertically overlapped with the first semiconductor chip (210). The second semiconductor chip (220) may be a memory chip such as DRAM or VNAND, or a logic chip such as an SOC (System on Chip).

[0033] Referring to FIG. 3, the second semiconductor chip (220) may include a semiconductor substrate (221), a device layer (222), a wiring layer (223), and a redistribution layer (224) stacked sequentially on the semiconductor substrate (221). The semiconductor substrate (221) may include an inactive surface (221a) and an active surface (221b) that are opposite to each other. The semiconductor substrate (221) may include an active portion (221c) adjacent to its active surface (221b).

[0034] The device layer (222) may include a plurality of source / drain patterns (SD) within an active portion (221c) of a semiconductor substrate (221), a plurality of gate electrodes (GE) on the active portion (221c) of the semiconductor substrate (221), and a plurality of active contacts (AC) each connected to the source / drain patterns (SD). The gate electrodes (GE) may be provided on the active surface (221a) of the semiconductor substrate (221). Each gate electrode (GE) may be interposed between a pair of adjacent source / drain patterns (SD). The active portion (221c) including the gate electrodes (GE) and the source / drain patterns (SD) may constitute a plurality of transistors.

[0035] The above transistors and contacts can be formed through a front-end process during the manufacturing process of the second semiconductor chip (220). That is, the above transistors and contacts can constitute a front-end process structure (FEOL) of the second semiconductor chip (220).

[0036] A wiring layer (223) may be provided on a device layer (222). The wiring layer (223) may include intermetallic insulating films (ILD) stacked in sequence, wiring (74) interposed between said intermetallic insulating films (ILD), and a conductive pad (225) connected to the uppermost wiring (74t) among the wirings (74). The intermetallic insulating films (ILD) may cover the device layer (222). For example, the intermetallic insulating films (ILD) may include silicon oxide. Each of the wirings (74) and the conductive pad (225) may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The conductive pad (225) may be disposed within the uppermost intermetallic insulating film (ILD). The upper surface of the conductive pad (225) may be exposed by the uppermost intermetallic insulating film (ILD).

[0037] A redistribution layer (224) may be provided on the wiring layer (223). The redistribution layer (224) may include a fourth redistribution insulating film (227) covering the wiring layer (223), a fourth redistribution pattern (226) that penetrates the fourth redistribution insulating film (227) and is connected to a conductive pad (225) and extends over the fourth redistribution insulating film (227), and a fifth redistribution insulating film (228) covering the fourth redistribution insulating film (227) and the fourth redistribution pattern (226).

[0038] The fourth redistribution insulating film (227) may include a first contact hole (CNH1) that exposes at least a portion of the upper surface of the conductive pad (225). The fourth redistribution insulating film (227) may include a silicon oxide film or a silicon oxynitride film. In another embodiment of the present invention, the fourth redistribution insulating film (227) may include a plurality of stacked insulating films.

[0039] At least one fourth redistribution pattern (226) may be disposed on the fourth redistribution insulating film (227). The fourth redistribution pattern (226) may include a contact portion (226a) that fills at least a portion of the first contact hole (CNH1), a pad portion (226c) connected to a conductive bump pattern (241a) to be described later, and a line portion (226b) extending from the contact portion (226a) to the pad portion (226c).

[0040] Through the contact portion (226a), the fourth redistribution pattern (226) can be connected to the conductive pad (225). The contact portion (226a) may include a recessed area on its upper side while filling the first contact hole (CNH1). For example, the bottom of the recessed area may be lower than the upper surface of the fourth redistribution insulating film (227).

[0041] The line portion (226b) may have a line shape extending in the first direction (D1) on the upper surface of the fourth redistribution insulating film (227). The thickness of the line portion (226b) may be substantially the same as the thickness of the contact portion (226a).

[0042] The fourth redistribution pattern (226) may include a metal material capable of deposition and etching processes. As an example, the fourth redistribution pattern (226) may include aluminum (Al).

[0043] A fifth redistribution insulating film (228) may be provided on the fourth redistribution pattern (226). The fifth redistribution insulating film (228) may also cover the upper surface of the fourth redistribution insulating film (227) where the fourth redistribution pattern (226) is not placed. The fifth redistribution insulating film (228) may include a first opening (OPN1) that exposes the contact portion (226a) of the fourth redistribution pattern (226) and a second opening (OPN2) that exposes the pad portion (226c) of the fourth redistribution pattern (226).

[0044] The fifth redistribution insulating film (228) may include a lower insulating film (228a) and an upper insulating film (228b). The upper insulating film (228b) may be provided on the lower insulating film (228a). The thickness of the lower insulating film (228a) may be smaller than the thickness of the upper insulating film (228b). The lower insulating film (228a) may include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. The upper insulating film (228b) may include an organic polymer film. For example, the upper insulating film (228b) may include polyimide, resin, or synthetic rubber. The lower insulating film (228a) may function as an adhesion promoting film between the upper insulating film (228b) and the fourth redistribution insulating film (227), for example.

[0045] The wiring layer (223) and the redistribution layer (224) can form a back-end process structure. That is, the wiring layer (223) and the redistribution layer (224) can be formed through a back-end of line (BEOL) process during the manufacturing process of the second semiconductor chip (220).

[0046] An insulating film (229) may be provided on the fifth redistribution insulating film (228). The insulating film (229) may fill the first opening (OPN1) and the second opening (OPN2) of the fifth redistribution insulating film (228). As an example, the insulating film (229) may include an organic polymer film.

[0047] The insulating film (229) may include a second contact hole (CNH2) that exposes at least a portion of the upper surface of the pad portion (226c) of the fourth redistribution pattern (226). The second contact hole (CNH2) may be formed within the insulating film (229) that fills the second opening (OPN2). The diameter of the second contact hole (CNH2) may be smaller than the diameter of the second opening (OPN2).

[0048] An external connection member (240) connected to a fourth redistribution pattern (226) may be provided on an insulating film (229). The external connection member (240) may include a conductive bump pattern (241) and a solder pattern (242) on the conductive bump pattern (241). The conductive bump pattern (241) may be provided on the insulating film (229) to fill a second contact hole (CNH2). In other words, the conductive bump pattern (241) may be connected to a pad portion (226c) of the fourth redistribution pattern (226) through the second contact hole (CNH2). The conductive bump pattern (241) within the second contact hole (CNH2) may be separated from the fifth redistribution insulating film (228) by the insulating film (229).

[0049] The conductive bump pattern (241) may include a seed pattern (241a) and a conductive pattern (241b) on the seed pattern (241a). The seed pattern (241a) may cover the underside of the conductive pattern (241b). The seed pattern (241a) may be interposed between the insulating film (229) and the conductive pattern (241b). For example, the seed pattern (241a) may include a conductive material such as copper, titanium, and alloys thereof. The seed pattern (241a) may also function as a barrier layer to prevent the diffusion of metal within the conductive pattern (241b). As an example, the conductive pattern (241b) may include copper.

[0050] A solder pattern (242) of an external connection member (240) may be placed on a conductive bump pattern (241). The conductive bump pattern (241) may function as a pad of the solder pattern (242). Forming the solder pattern (242) may include performing a solder ball attachment process on the conductive bump pattern (241).

[0051] The insulating film (229) and the external connection member (240) can be formed in a packaging process, i.e., a post-fab process. According to embodiments of the present invention, a redistribution layer (224) including a fourth redistribution pattern (226) can be formed through an in-fab process (more specifically, a post-process of the second semiconductor chip (220)) rather than a post-fab process. That is, since the redistribution layer (224) can be formed by utilizing the semiconductor chip manufacturing process as is, there is an advantage in that the redistribution layer (224) can be formed without separate equipment investment in the post-fab process.

[0052] Referring again to FIG. 1, conductive pillars (250) that electrically connect the second semiconductor chip (220) and the first redistribution substrate (100) may be provided. Specifically, the conductive pillars (250) may extend vertically between the external connection member (240) and the third redistribution pattern (130). The upper surface of each conductive pillar (250) may be in direct contact with the solder pattern (242) of the external connection member (240). The conductive pillars (250) may be placed within a molding film (300) to be described later. Each of the conductive pillars (250) may include a metallic material such as copper or tungsten.

[0053] A molding film (300) may cover the first semiconductor chip (210) and the second semiconductor chip (220). The molding film (300) may cover the top surface and side walls of the first semiconductor chip (210) and the top surface and side walls of the second semiconductor chip (220). The molding film (300) may be provided between the first semiconductor chip (210) and the first redistribution substrate (100), between the second semiconductor chip (220) and the first redistribution substrate (100), and between the first semiconductor chip (210) and the second semiconductor chip (220). The molding film (300) may be in contact with the side walls of the conductive pillars (250). The molding film (300) may include an insulating polymer such as an epoxy-based polymer.

[0054] A plurality of bump patterns (350) and a plurality of external terminals (400) may be disposed on a second surface (100b) of a first redistribution board (100). Each of the bump patterns (350) may be electrically connected to the first redistribution pattern (110). Each of the bump patterns (350) may include a conductive metal material. External terminals (400) may be provided below each of the bump patterns (350). Although not illustrated, the external terminals (400) may be connected to an external board (e.g., a PCB board). As an example, each of the external terminals (400) may be a solder ball.

[0055] Referring to FIG. 2, the second semiconductor chip (220) may include a first region (R1) that is vertically overlapping with the first semiconductor chip (210) and a second region (R2) that is horizontally offset from the first semiconductor chip (210). External connection members (240) may be disposed on the second region (R2) of the second semiconductor chip (220). External connection members (240) may not be disposed on the first region (R1) of the second semiconductor chip (220). That is, the external connection members (240) may be horizontally offset from the first semiconductor chip (210). Connection terminals (230) may be horizontally offset from the second semiconductor chip (220). As another example, at least one of the connection terminals (230) may be vertically overlapping with the second semiconductor chip (220). Unlike what is depicted, the number and arrangement of the connection terminals (230) and external connection members (240) can be freely changed.

[0056] According to embodiments of the present invention, a second semiconductor chip (220) may be positioned at a higher level than the first semiconductor chip (210). The second semiconductor chip (220) may be positioned using conductive pillars (250) such that a portion of the second semiconductor chip (220) overlaps vertically with the first semiconductor chip (210). By doing so, the size of the semiconductor package can be reduced compared to when the second semiconductor chip (220) is positioned at the same level as the first semiconductor chip (210). Consequently, a miniaturized semiconductor package can be provided.

[0057] Referring again to FIG. 1, the pitch between the connection terminals (230) may be a first pitch (D10). The pitch between the external connection members (240) may be a second pitch (D20). The pitch between the external terminals (400) may be a third pitch (D30). The second pitch (D20) may be larger than the first pitch (D10). The third pitch (D30) may be larger than the second pitch (D20). The pitch between the conductive pillars (250) may be a fourth pitch (D40). The fourth pitch (D40) may be substantially the same as the second pitch (D20).

[0058] The maximum width of the connection terminal (230) may be a first width (W1). The maximum width of the external connection member (240) may be a second width (W2). The second width (W2) may be larger than the first width (W1).

[0059] According to embodiments of the present invention, the redistribution layer (224) of the second semiconductor chip (220) can be formed using an in-fab process. This makes it possible to form external connecting members (240) corresponding to the pitch between the conductive pillars (250) without forming a separate redistribution substrate. As a result, it becomes easier to miniaturize the semiconductor package using the conductive pillars (250).

[0060] The vertical distance between the semiconductor substrate (221) of the second semiconductor chip (220) and the conductive pillar (250) may be a first distance (H1). Specifically, the first distance (H1) may be the minimum distance between the active surface (221b) of the semiconductor substrate (221) and the upper surface of the conductive pillar (250). For example, the first distance (H1) may be 5 μm to 10 μm. The vertical distance between the first semiconductor chip (210) and the external terminal (400) may be a second distance (H2). Specifically, the second distance (H2) may be the minimum distance between the active surface (210b) of the first semiconductor chip (210) and the external terminal (400).

[0061] When connecting the second semiconductor chip (220) to the conductive pillars (250), a separate redistribution substrate is not formed, so the first distance (H1) can be smaller than the second distance (H2). When forming a redistribution substrate containing an organic material such as a photosensitive polymer or a photosensitive insulating (PID) resin, applying high-temperature heat is essential during the manufacturing process, which causes a problem of degraded performance of the semiconductor chip. According to embodiments of the present invention, since the redistribution layer (224) of the second semiconductor chip (220) is formed using an in-fab process, the problem of degraded performance of the semiconductor chip due to high-temperature heat can be prevented. As a result, the electrical characteristics of the semiconductor package can be improved. In addition, the process of forming a redistribution pattern using a plating process in the post-fab process can be omitted, so the manufacturing process can be further simplified.

[0063] FIG. 4 is a schematic plan view of a semiconductor package according to embodiments of the present invention.

[0064] Referring to FIG. 4, the first semiconductor chip (210) and the second semiconductor chip (220) may intersect each other in a planar view. For example, the first semiconductor chip (210) may extend in a first direction (D1), and the second semiconductor chip (220) may extend in a second direction (D2).

[0065] The second semiconductor chip (220) may include a first region (R1) that is vertically overlapping with the first semiconductor chip (210) and a second region (R2) that is horizontally offset from the first semiconductor chip (210). Multiple second regions (R2) may be provided. Each of the second regions (R2) may be adjacent to the first region (R1) in a second direction (D2). The first region (R1) may be provided between multiple second regions (R2).

[0066] The external connection member (240) may be horizontally offset from the first semiconductor chip (210). The external connection member (240) may be placed on a plurality of second regions (R2). At least one of the connection terminals (230) may be vertically overlapped with the first region (R1). Unlike what is illustrated, the arrangement of the first semiconductor chip (210), the second semiconductor chip (220), the connection terminals (230), and the external connection member (240) may be freely changed.

[0068] FIGS. 5a to 5l are cross-sectional views for explaining a method for manufacturing a semiconductor package according to embodiments of the present invention. FIGS. 5a to 5e are cross-sectional views along the P1 region of FIG. 2 and the line A-A' of FIG. 3, for explaining a manufacturing process of a second semiconductor chip (220).

[0069] Referring to FIG. 5a, a plurality of source / drain patterns (SD) can be formed on the upper part of the active portion (221c) of the semiconductor substrate (221) through a shearing process. A plurality of gate electrodes (GE) can be formed on the active portion (221c) of the semiconductor substrate (221). A plurality of active contacts (AC) connected to each of the source / drain patterns (SD) can be formed. Thus, a device layer (222) can be formed on the semiconductor substrate (221).

[0070] Subsequently, a subsequent process may be performed to form a wiring layer (223) on the device layer (222). Specifically, forming the wiring layer (223) may include forming intermetallic insulating films (ILD) and forming wirings (74) within the intermetallic insulating films (ILD). A conductive pad (225) may be formed within the uppermost intermetallic insulating film (ILD). The upper surface of the conductive pad (225) may be exposed by the uppermost intermetallic insulating film (ILD).

[0071] Referring to FIG. 5b, a fourth redistribution insulating film (227) and a preliminary redistribution pattern (226P) may be formed on the device layer (223). Specifically, the fourth redistribution insulating film (227) may be formed on the uppermost intermetallic insulating film (ILD) through a deposition process. By patterning the fourth redistribution insulating film (227), a first contact hole (CNH1) exposing a conductive pad (225) may be formed.

[0072] A preliminary redistribution pattern (226P) can be formed on the fourth redistribution insulating film (227) through a deposition process. The preliminary redistribution pattern (226P) can be formed using a physical vapor deposition (PVD) process, for example, sputtering. The preliminary redistribution pattern (226P) can also be formed within the first contact hole (CNH1) and connected to the conductive pad (225). The preliminary redistribution pattern (226P) can be formed from a depositable metal such as aluminum.

[0073] Referring to FIG. 5c, a hard mask pattern (700) can be formed on a preliminary redistribution pattern (226P). The hard mask pattern (700) can be formed using a photolithography process. A fourth redistribution pattern (226) can be formed by patterning the preliminary redistribution pattern (226P) using the hard mask pattern (700) as an etching mask.

[0074] The patterning process for forming the fourth redistribution pattern (226) may include dry etching. For example, BCl3, SF6, or a combination thereof may be used as the etching gas for the dry etching. The fourth redistribution pattern (226) may include a contact portion (226a), a pad portion (226c) within the first contact hole (CNH1), and a line portion (226b) extending from the contact portion (226a) to the pad portion (226c).

[0075] Referring to FIG. 5d, the hard mask pattern (700) can be optionally removed. Through a subsequent process, a fifth redistribution insulating film (228) can be formed on the fourth redistribution pattern (226) and the fourth redistribution insulating film (227). Specifically, forming the fifth redistribution insulating film (228) may include forming a lower insulating film (228a) and forming an upper insulating film (228b) on the lower insulating film (228a).

[0076] The lower insulating layer (228a) can be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The upper insulating layer (228b) can be formed by coating a polymer material, such as polyimide, resin, or synthetic rubber, or a precursor thereof, onto the lower insulating layer (228a).

[0077] A patterning process using photolithography can be performed on the fifth redistribution insulating film (228) to form a first opening (OPN1) and a second opening (OPN2). The first opening (OPN1) can expose the contact portion (226a) of the fourth redistribution pattern (226), and the second opening (OPN2) can expose the pad portion (226c) of the fourth redistribution pattern (226).

[0078] By forming a fifth redistribution insulating film (228) having first and second openings (OPN1, OPN2), a redistribution layer (224) can be finally formed. That is, the downstream process of the second semiconductor chip (220) can be completed. The manufactured second semiconductor chip (220) can be fab out.

[0079] Referring to FIG. 5e, a post-fab process, which is a packaging process, can be performed on the second semiconductor chip (220) that has been fab-out. Specifically, an insulating film (229) can be formed on the redistribution layer (224). The insulating film (229) can be formed by coating an organic polymer material onto the fifth redistribution insulating film (228).

[0080] A second contact hole (CNH2) can be formed by performing a patterning process using photolithography on an insulating film (229). The second contact hole (CNH2) can be formed to penetrate the insulating film (229) that fills the second opening (OPN2). At least a portion of the upper surface of the pad portion (226c) of the fourth redistribution pattern (226) can be exposed by the second contact hole (CNH2).

[0081] Referring again to FIG. 3, an external connection member (240) can be formed through a post-fab process. Specifically, a seed pattern (241a) can be formed on the second contact hole (CNH2). A plating process can be performed to form a conductive pattern (241b) on the seed pattern (241a). The seed pattern (241a) and the conductive pattern (241b) can form a conductive bump pattern (241). A solder ball attachment process can be performed on the conductive bump pattern (241) to form a solder pattern (242). The conductive bump pattern (241) and the solder pattern (242) can form the external connection member (240).

[0082] When the fourth rewiring pattern (226) is formed in a post-fab process, the fourth rewiring pattern (226) must be formed of copper using a plating process. If the fourth rewiring pattern (226) is formed by a plating process, there is a problem that reliability is reduced compared to the embodiment of the present invention and an additional wiring process is required.

[0083] The method for manufacturing a semiconductor package according to embodiments of the present invention can form a fourth redistribution pattern (226) through an in-fab process using inexpensive aluminum, which utilizes a deposition process, instead of gold or copper, which utilizes a plating process. Therefore, it is possible to implement the manufacturing process more economically compared to using a plating process. In addition, since the fourth redistribution pattern (226) is formed using deposition and patterning processes rather than a plating process, the downstream processes and equipment of the semiconductor chip can be utilized as is. Thus, an efficient semiconductor manufacturing process can be implemented.

[0084] Referring to FIG. 5f, a first redistribution insulating film (101) may be formed on a first carrier substrate (900). The first redistribution insulating film (101) may cover the first carrier substrate (900). The formation of the first redistribution insulating film (101) may be carried out by a coating process, such as spin coating or slit coating, for example. The first redistribution insulating film (101) may comprise, for example, an organic material such as a photosensitive polymer or a photosensitive dielectric (PID) resin.

[0085] A first redistribution insulating film (101) may be patterned so that a first hole (109) can be formed within the first redistribution insulating film (101). The patterning of the first redistribution insulating film (101) may be carried out by an exposure process and a development process. The first hole (109) may expose one side of the first carrier substrate (900). The first hole (109) may have a tapered shape. For example, the upper diameter of the first hole (109) may be larger than the lower diameter of the first hole (109). The inner wall of the first redistribution insulating film (101) may be defined by the first hole (109).

[0086] A first seed layer (111P), a first resist pattern (171), and first conductive layers (113) may be formed on the upper surface of the first redistribution insulating film (101). According to embodiments, the first seed layer (111P) may conformally cover the upper surface of the first redistribution insulating film (101), the inner wall of the first redistribution insulating film (101), and the exposed upper surface of the first carrier substrate (900).

[0087] A first resist pattern (171) may be formed on the first seed layer (111P). Forming the first resist pattern (171) may include applying a photoresist material onto the first seed layer (111P). The first resist pattern (171) may be patterned to form first openings. The patterning of the first resist pattern (171) may be carried out by an exposure and development process. The first openings may overlap vertically with the first holes (109), respectively. The widths of the first openings may be greater than the widths of the corresponding first holes (109). The sidewalls of each of the first openings may be substantially perpendicular to the bottom surface. Each of the first openings may expose a portion of the first seed layer (111P).

[0088] First conductive layers (113) may be formed within each of the first holes (109) to cover the first seed layer (111P). The first conductive layers (113) may fill the lower portions of the first openings. For example, the first conductive layers (113) may fill each of the first holes (109) but may not extend onto the upper surface of the first resist pattern (171). The first conductive layers (113) may be formed by performing an electroplating process using the first seed layer (111P) as an electrode. During the formation process of the first conductive layers (113), a separate planarization process may not be performed.

[0089] Referring to FIG. 5g, the first resist pattern (171) can be removed to expose the upper surface of the first portion of the first seed layer (111P). The removal of the first resist pattern (171) can be performed by a strip process.

[0090] An exposed first portion of the first seed layer (111P) can be removed to form first seed patterns (111). The removal of the first portion of the first seed layer (111P) can be performed by an etching process. The etching process may be a wet etching process. In the etching process, the first conductive layers (113) may have etch selectivity with respect to the first seed layer (111P). Second portions of the first seed layer (111P) may be placed on the lower surface of the first conductive layers (113) so as not to be exposed to the etching process. After the etching process is completed, the remaining second portions of the first seed layer (111P) may form first seed patterns (111). Accordingly, first redistribution patterns (110) may be formed. The first redistribution patterns (110) may be spaced apart from each other. The first rewiring patterns (110) may each include first seed patterns (111) and first conductive layers (113). The first conductive layers (113) may each be disposed on the first seed patterns (111). Each of the first rewiring patterns (110) may include a first via portion (110V) and a first wiring portion (110W). The first via portion (110V) may be provided within any one of the first holes (109).

[0091] Referring to FIG. 5h, a second redistribution insulating film (102) is formed on the first redistribution insulating film (101) to cover the first redistribution insulating film (101) and the first redistribution patterns (110). For example, the second redistribution insulating film (102) can cover the upper surfaces and side walls of the first redistribution patterns (110).

[0092] Second redistribution patterns (120) may be formed within second holes formed on the second redistribution insulating film (102). The second redistribution patterns (120) may extend onto the upper surface of the second redistribution insulating film (102). The second redistribution patterns (120) may be spaced apart from each other. Forming the second redistribution patterns (120) may be performed by the same method as forming the first redistribution patterns (110). For example, forming the second redistribution patterns (120) may include forming a second seed layer, forming a second resist pattern having a second opening on the second seed layer, forming second conductive layers (123) within the second holes and the second openings, removing the second resist pattern to expose a portion of the second seed layer, and etching the exposed portion of the second seed layer to form the second seed patterns (121). The second redistribution patterns (120) may each include the second seed patterns (121) and the second conductive layers (123). The second conductive layers (123) may each be disposed on the second seed patterns (121). Each of the second redistribution patterns (120) may include a second via portion (120V) and a second wiring portion (120W).

[0093] A third redistribution insulating film (103) is formed on the second redistribution insulating film (102) to cover the second redistribution insulating film (102) and the second redistribution patterns (120). For example, the third redistribution insulating film (103) can cover the upper surfaces and side walls of the second redistribution patterns (120).

[0094] Third redistribution patterns (130) may each be formed within third holes formed on the third redistribution insulating film (103). The third redistribution patterns (130) may extend over the upper surface of the third redistribution insulating film (103). The third redistribution patterns (130) may be spaced apart from each other. Forming the third redistribution patterns (130) may be performed by the same method as forming the first redistribution patterns (110). For example, forming the third redistribution patterns (130) may include forming a third seed layer, forming a third resist pattern having a third opening on the third seed layer, forming third conductive layers (133) within the third holes and third openings, removing the third resist pattern to expose the third seed layer, and etching a portion of the exposed third seed layer to form the third seed patterns (131). The third rewiring patterns (130) may each include third seed patterns (131) and third conductive layers (133). Each of the third rewiring patterns (130) may include a third via portion (130V) and a third wiring portion (130W).

[0095] A plurality of conductive pillars (250) may each be formed on a portion of the third redistribution patterns (130). Each of the conductive pillars (250) may include a conductive metal material. The conductive pillars (250) may extend in a third direction (D3).

[0096] Referring to FIG. 5i, a first semiconductor chip (210) may be placed on a first redistribution substrate (100). Connection terminals (230) may be interposed between the first semiconductor chip (210) and a third redistribution pattern (130). The pitch between the connection terminals (230) may be a first pitch (D10). The maximum width of the connection terminals (230) may be a first width (W1).

[0097] A first molding portion (301) covering a first semiconductor chip (210) may be formed on a first redistribution substrate (100). The first molding portion (301) may include, for example, an insulating polymer such as an epoxy-based polymer. The first molding portion (301) may cover conductive pillars (250). A grinding process may be performed on the first molding portion (301). Accordingly, the upper surface of the first molding portion (301) may be flat. The upper surface of the first molding portion (301) may form a co-surface with the upper surface of the conductive pillar (250). The upper surface of the conductive pillar (250) may be located at a higher level than the upper surface of the first semiconductor chip (210).

[0098] Referring to FIG. 5j, a second semiconductor chip (220) can be placed on the first molding part (310). Specifically, the second semiconductor chip (220) manufactured using the manufacturing process of FIG. 5a to 5e and FIG. 3 can be flipped and placed on the first molding part (301).

[0099] A second semiconductor chip (220) may be positioned so that external connecting members (240) correspond to each conductive pillar (250). The solder pattern (242) of the external connecting member (240) may come into direct contact with the conductive pillar (250). For example, connecting the external connecting member (240) to the conductive pillar (250) may be performed using a thermal compression process.

[0100] The pitch between the external connecting members (240) may be a second pitch (D20). The pitch between the conductive columns (250) may be a fourth pitch (D40). The fourth pitch (D40) may be substantially the same as the second pitch (D20). The maximum width of the external connecting member (240) may be a second width (W2). The second width (W2) may be greater than the first width (W1).

[0101] Referring to FIG. 5k, a second molding portion (302) covering a second semiconductor chip (220) may be formed on a first molding portion (301). The second molding portion (302) may, for example, include the same material as the first molding portion (301). For example, the first molding portion (301) may include an insulating polymer such as an epoxy-based polymer. As another example, the second molding portion (302) may include a material different from the first molding portion (301).

[0102] The first molding part (301) and the second molding part (302) may form a molding film (300). Unlike what is illustrated, if the first molding part (301) and the second molding part (302) contain the same material, the interface between them may not be visible. A grinding process may be performed on the upper surface of the molding film (300). The upper surface of the molding film (300) may be flat.

[0103] Referring to FIG. 5L, a second carrier substrate (901) can be placed on the upper surface of the molding film (300). Afterward, the semiconductor package can be flipped and the first carrier substrate (900) can be removed. As the first carrier substrate (900) is removed, the first redistribution pattern (110) can be exposed.

[0104] Bump patterns (350) can be formed on the exposed first rewiring pattern (110). External terminals (400) can be formed on each of the bump patterns (350). As a result, the semiconductor package described with reference to FIG. 1 can be manufactured.

[0105] For the sake of simplification, a single semiconductor package has been illustrated and described; however, the semiconductor package manufacturing method of the present invention is not limited to wafer-level manufacturing. For example, the semiconductor package may be manufactured at the panel level.

[0107] FIG. 6 is a cross-sectional view showing a semiconductor package according to embodiments of the present invention. In this embodiment, details that overlap with those described with reference to FIG. 1 to 3 are omitted, and the differences are described in detail.

[0108] Referring to FIG. 6, a second semiconductor chip (220) may be provided on a first semiconductor chip (210) of a first rewiring substrate (100). The second semiconductor chip (220) may include an inactive surface (220a) and an active surface (220b) opposite each other. The second semiconductor chip (220) may include an active portion (220c) adjacent to its active surface (220b). The second semiconductor chip (220) may include chip pads (255) adjacent to its active surface (220b). The lower surface of the chip pad (255) may be exposed by the second semiconductor chip (220). The chip pad (255) may include a conductive metal material.

[0109] A second redistribution substrate (500) may be provided below the second semiconductor chip (220). The second redistribution substrate (500) may include a sixth redistribution insulating film (501), a seventh redistribution insulating film (502), an eighth redistribution insulating film (503), a fifth redistribution pattern (510), a sixth redistribution pattern (520), and a seventh redistribution pattern (530).

[0110] The second redistribution substrate (500) may include a sixth redistribution insulating film (501), a seventh redistribution insulating film (502), and an eighth redistribution insulating film (503) that are sequentially stacked in a direction from the first surface (100a) of the first redistribution substrate (100) toward the second surface (100b).

[0111] A fifth redistribution pattern (510) may be disposed below the sixth redistribution insulating film (501). The fifth redistribution pattern (510) may be provided on the chip pad (255). The sixth redistribution insulating film (501) may comprise, for example, an organic material such as a photosensitive polymer or a photosensitive dielectric (PID) resin. In this specification, the photosensitive polymer may comprise, for example, at least one of a photosensitive polyimide, polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer.

[0112] A seventh redistribution insulating film (502) may be placed below the sixth redistribution insulating film (501). The seventh redistribution insulating film (502) may contain the same material as the sixth redistribution insulating film (501).

[0113] The fifth rewiring pattern (510) may include a fourth via portion (510V) and a fourth wiring portion (510W). The fifth rewiring pattern (510) may include a fourth seed pattern (511) and a fourth conductive layer (513).

[0114] A sixth redistribution pattern (520) may be placed below the fifth redistribution pattern (510). The sixth redistribution pattern (520) may be electrically connected to the fifth redistribution pattern (510). The sixth redistribution pattern (520) may include a fifth via portion (520V) and a fifth wiring portion (520W). The sixth redistribution pattern (520) may include a fifth seed pattern (521) and a fifth conductive layer (523).

[0115] The eighth redistribution insulating film (503) may be placed below the seventh redistribution insulating film (502). The eighth redistribution insulating film (503) may contain the same material as the sixth redistribution insulating film (501).

[0116] A seventh redistribution pattern (530) may be placed below the sixth redistribution pattern (520). The seventh redistribution pattern (530) may include a sixth via portion (530V) and a sixth wiring portion (530W). The seventh redistribution pattern (530) may include a sixth seed pattern (531) and a sixth conductive layer (533).

[0117] The width of each of the 4th to 6th via portions (510V, 520V, 530V) may increase as it goes from the first surface (100a) of the 1st redistribution board (100) toward the second surface (100b). The 2nd redistribution board (500) is substantially the same as the 1st redistribution board (100) described with reference to FIG. 1, except that the vertical positional relationship may be reversed.

[0118] An external connecting member (240) may be interposed between the seventh redistribution pattern (530) and the conductive column (250). Unlike described with reference to FIG. 3, the external connecting member (240) may not include a conductive bump pattern (241). The external connecting member (240) may be in direct contact with the conductive column (250).

[0120] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A redistribution substrate, wherein the redistribution substrate comprises a first surface and a second surface opposite to each other; a first semiconductor chip provided on the first surface of the redistribution substrate; external terminals provided on the second surface of the redistribution substrate; a second semiconductor chip provided on the first semiconductor chip; external connection members provided below the second semiconductor chip, each of the external connection members comprising a conductive bump pattern and a solder pattern on the conductive bump pattern; and conductive pillars electrically connecting the external connection members and the redistribution substrate, wherein the second semiconductor chip comprises a semiconductor substrate and a device layer, a wiring layer, and a redistribution layer stacked sequentially on the semiconductor substrate, wherein the wiring layer comprises intermetallic insulating films stacked sequentially, wiring interposed between the intermetallic insulating films, and a conductive pad connected to the uppermost wiring among the wirings, and wherein the redistribution layer comprises: a first redistribution insulating film covering the wiring layer; a first redistribution pattern penetrating the first redistribution insulating film, connected to the conductive pad, and extending onto the first redistribution insulating film; A semiconductor package comprising a first redistribution pattern and a second redistribution insulating film covering the first redistribution insulating film, wherein the vertical distance between the semiconductor substrate and the conductive pillars is smaller than the vertical distance between the first semiconductor chip and the external terminals, the external connecting members are disposed between the second semiconductor chip and the conductive pillars, the solder patterns include solder balls, and the solder patterns are in contact with the conductive pillars. Claim 2 delete Claim 3 A semiconductor package according to claim 1, wherein the vertical distance between the semiconductor substrate and the conductive pillars is 5 μm to 10 μm. Claim 4 A semiconductor package according to claim 1, further comprising connection terminals provided between the first semiconductor chip and the redistribution board, wherein the pitch between the connection terminals is smaller than the pitch between the external connection members. Claim 5 In paragraph 4, the semiconductor package in which the maximum width of each of the above-mentioned connection terminals is smaller than the maximum width of each of the above-mentioned external connection members. Claim 6 In claim 1, a portion of the second semiconductor chip is a semiconductor package that is vertically overlapped with the first semiconductor chip. Claim 7 In claim 1, the second semiconductor chip comprises a first region vertically overlapping with the first semiconductor chip and a second region horizontally offset from the first semiconductor chip, wherein the external connection members are a semiconductor package provided on the second region. Claim 8 A semiconductor package according to claim 1, wherein the pitch between the external terminals is larger than the pitch between the external connection members. Claim 9 A semiconductor package according to claim 1, wherein the pitch between the conductive pillars is substantially the same as the pitch between the external connecting members. Claim 10 In claim 1, the rewiring substrate includes second rewiring patterns that electrically connect the first semiconductor chip and the second semiconductor chip to the external terminals, wherein each of the second rewiring patterns includes a wiring portion extending in a direction parallel to the first surface of the rewiring substrate and a via portion protruding from the wiring portion toward the second surface of the rewiring substrate, and the width of the via portion decreases as it goes from the first surface of the rewiring substrate toward the second surface.

Images