Operation method of memory device, and operation method of memory controller controlling memory device

Abstract

A method of operation of a memory device comprising a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate includes: a step of performing a first erase operation on a ground selection transistor among the plurality of cell transistors; a step of performing a first program operation on an erase control transistor located between the substrate and the ground selection transistor among the plurality of cell transistors after the first erase operation; a step of performing a second program operation on the ground selection transistor after the first program operation; and a step of performing a second erase operation on the erase control transistor after the second program operation.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory, and more specifically to a method of operating a memory device and a method of operating a memory controller that controls the memory device. Background Technology

[0002] Semiconductor memory is classified into volatile memory devices, such as SRAM and DRAM, in which stored data is lost when the power supply is cut off, and non-volatile memory devices, such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when the power supply is cut off.

[0003] Flash memory devices can store data by controlling the threshold voltage of cell transistors. Due to various factors, the threshold voltage of the cell transistors may change, and in this case, the operational reliability of the flash memory device may be reduced. The problem to be solved

[0004] The objective of the present invention is to provide a method of operation for a memory device having improved reliability and a method of operation for a memory controller that controls the memory device. means of solving the problem

[0005] According to one embodiment of the present invention, a method of operating a memory device comprising a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate may include: a step of performing a first erase operation on a ground selection transistor among the plurality of cell transistors; a step of performing a first program operation on an erase control transistor located between the substrate and the ground selection transistor among the plurality of cell transistors after the first erase operation; a step of performing a second program operation on the ground selection transistor after the first program operation; and a step of performing a second erase operation on the erase control transistor after the second program operation.

[0006] According to one embodiment of the present invention, a method of operation of a memory device including a memory block comprising a plurality of lines stacked in a direction perpendicular to a substrate may include the steps of: applying a first erase voltage to a common source line and applying a first word line erase voltage to a ground selection line among the plurality of lines; applying a first erase verification voltage to the ground selection line; applying a first program voltage to an erase control line located between the ground selection line and the substrate among the plurality of lines; applying a first program verification voltage to the erase control line; applying a second program voltage to the ground selection line; applying a second program verification voltage to the ground selection line; applying a second erase voltage to the common source line and applying a second word line erase voltage to the erase control line; and applying a second erase verification voltage to the erase control line.

[0007] According to one embodiment of the present invention, a method of operation of a memory controller configured to control a memory device comprising a plurality of cell transistors stacked in a direction perpendicular to a substrate comprises: a step of transmitting a first command for a cell counting operation for ground selection transistors among the plurality of cell transistors to the memory device; a step of receiving a cell counting result for the ground selection transistors from the memory device; and a step of performing a dispersion improvement operation for the ground selection transistors based on the cell counting result, wherein the dispersion improvement operation may include a step of transmitting a first erase command to the memory device for erasing the ground selection transistors; a step of transmitting a first program command to the memory device for programming erase control transistors located between the ground selection transistor and the substrate among the plurality of cell transistors; a step of transmitting a second program command to the memory device for programming the ground selection transistors; and a step of transmitting a second erase command to the memory device for erasing the erase control transistors. Effects of the invention

[0008] According to the present invention, the threshold voltage dispersion of ground selection transistors or other unused cell transistors of a memory device can be improved. Accordingly, a method of operation of a memory device having improved reliability and a method of operation of a memory controller controlling the memory device are provided. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing one of the memory blocks among the plurality of memory blocks included in the memory cell array of FIG. 1. Figure 3 is a diagram showing the scatter plot for the threshold voltage of the ground select transistor of the memory block of Figure 2. Figure 4 is a conceptual drawing showing a vertical cross-sectional view of a memory block included in the memory cell array of Figure 1. Figure 5 is a diagram illustrating the dispersion improvement operation for the ground selection transistor of the memory block of Figure 4. Figure 6 is a flowchart showing the operation of the memory device of Figure 1. Figure 7 is a diagram showing the bias conditions for each step of the flowchart of Figure 6. Figure 8 is a diagram showing the threshold voltage dispersion of ground selection transistors and erase control transistors according to the operation of the flowchart of Figure 6. Figure 10 is a flowchart showing the operation of the memory device of Figure 1. FIG. 11 is a diagram for explaining the operation according to the flowchart of FIG. 10. FIGS. 12a and 12b are conceptual drawings showing a vertical cross-sectional view of a memory block included in the memory cell array of FIG. 1. FIG. 13 is a drawing showing a vertical cross-sectional view of a memory block included in the memory cell array of FIG. 1. FIG. 14 is a block diagram showing a memory system according to an embodiment of the present invention. Figure 15 is a flowchart showing the operation of the memory system of Figure 14. FIG. 16 is a flowchart showing the operation of step S1500 of FIG. 15 in detail. Figure 17 is a flowchart showing the operation of the memory controller of Figure 14. FIG. 18 is a cross-sectional view showing a memory device according to one embodiment of the present disclosure. FIG. 19 is a block diagram showing a host-storage system (3000) according to an exemplary embodiment of the present invention. Specific details for implementing the invention

[0010] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0011] FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device (100) may include a memory cell array (110), an address decoder (120), a page buffer circuit (130), an input / output circuit (140), a control logic and a voltage generation circuit (150). In one embodiment, the memory device (100) may be a non-volatile memory device including NAND flash memory cells.

[0012] A memory cell array (110) may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings, and each of the plurality of cell strings may include a plurality of cell transistors. The plurality of cell transistors may be serially connected between bit lines (BL) and a common source line (CSL), and may be connected to string select lines (SSL), word lines (WL), and ground select lines (GSL). In one embodiment, some of the plurality of cell transistors may be connected to an erase control line (ECL) and may be used for the erase operation of each of the plurality of memory blocks. Each of the plurality of memory blocks is described in more detail with reference to FIG. 2.

[0013] The address decoder (120) can be connected to the memory cell array (110) via string select lines (SSL), word lines (WL), ground select lines (GSL), and erase control lines (ECL). The address decoder (120) can receive an address (ADDR) from an external device (e.g., a memory controller) and can decode the received address (ADDR). Based on the decoding result, the address decoder (120) can control the string select lines (SSL), word lines (WL), ground select lines (GSL), and erase control lines (ECL).

[0014] The page buffer circuit (130) can be connected to the memory cell array (110) through bit lines (BL). The page buffer circuit (130) can read data stored in the memory cell array (110) by detecting a voltage change in the bit lines (BL). The page buffer circuit (130) can store data in the memory cell array (110) by controlling the voltage of the bit lines (BL).

[0015] The input / output circuit (140) can receive data (DATA) from an external device (e.g., a memory controller) and transfer the received data to the page buffer circuit (130). The input / output circuit (140) can receive data (DATA) from the page buffer circuit (130) and provide the received data (DATA) to the external device.

[0016] The control logic and voltage generation circuit (150) receives a command (CMD) and a control signal (CTRL) from an external device (e.g., a memory controller) and can control various components of the memory device (100) in response to the received signals.

[0017] The control logic and voltage generation circuit (150) can generate various operating voltages required for the memory device (100) to operate. For example, the various operating voltages can generate various voltages such as multiple program voltages, multiple pass voltages, multiple verification voltages, multiple read voltages, multiple non-select read voltages, multiple erase voltages, multiple erase verification voltages, etc. The various voltages described in the following embodiments can be generated by the control logic and voltage generation circuit (150).

[0018] FIG. 2 is a circuit diagram showing one of a plurality of memory blocks included in the memory cell array of FIG. 1. With reference to FIG. 2, a memory block with a three-dimensional structure is described, but the scope of the present invention is not limited thereto. A memory block according to the present invention may have a structure of a memory block with a two-dimensional structure. With reference to FIG. 2, one memory block (BLK) is described, but the scope of the present invention is not limited thereto, and each of the other memory blocks may have a structure similar to the memory block (BLK) described with reference to FIG. 2.

[0019] In one embodiment, the memory block (BLK) described with reference to FIG. 2 may be a physical erase unit of the memory device (100). However, the scope of the present invention is not limited thereto, and the memory device (100) may perform erase operations in the form of a page unit, a wordline unit, a sub-block unit, a plane unit, etc.

[0020] Referring to FIG. 2, the memory block (BLK) includes a plurality of cell strings (CS11, CS12, CS21, CS22). The plurality of cell strings (CS11, CS12, CS21, CS22) can be arranged along the row direction and column direction to form rows and columns.

[0021] Each of the plurality of cell strings (CS11, CS12, CS21, CS22) includes a plurality of cell transistors. For example, each of the plurality of cell strings (CS11, CS12, CS21, CS22) may include string select transistors (SSTu, SSTd), a plurality of memory cells (MC1~MC7), a ground select transistor (GST), dummy memory cells (DMC1, DMC2), and erase control transistors (ECT1, ECT2). In one embodiment, each of the plurality of cell transistors included in the plurality of cell strings (CS11, CS12, CS21, CS22) may be a charge trap flash (CTF) memory cell.

[0022] Multiple memory cells (MC1 to MC7) are connected in series and stacked in the height direction, which is perpendicular to the plane or substrate formed by the row and column directions. String select transistors (SSTd, SSTu) are connected in series, and the serially connected string select transistors (SSTa, SSTb) are provided between the multiple memory cells (MC1 to MC7) and the bit line (BL1 or BL2). A ground select transistor (GST) is provided between the multiple memory cells (MC1 to MC7) and the common source line (CSL).

[0023] In one embodiment, a first dummy memory cell (DMC1) may be provided between a plurality of memory cells (MC1 to MC7) and a ground select transistor (GST). In one embodiment, a second dummy memory cell (DMC2) may be provided between a plurality of memory cells (MC1 to MC7) and string select transistors (SSTd, SSTu).

[0024] In one embodiment, a first erase control transistor (ECT1) may be provided between the ground select transistor (GST) and the common source line (CSL). A second erase control transistor (ECT2) may be provided between the string select transistors (SSTd, SSTu) and the bit line (BL1 or BL2). The erase control transistors (ECT1, ECT2) may be used to charge the channels of the cell strings (CS11, CS12, CS21, CS22) to an erase voltage or to erase the memory block (BLK) based on the gate-induced drain leakage (GIDL) phenomenon.

[0025] The first erase control transistors (ECT1) of the cell strings (CS11, CS12, CS21, CS22) may be commonly connected to the first erase control line (ECL1). However, the scope of the present invention is not limited thereto, and the first erase control transistors (ECT1) of the cell strings (CS11, CS12, CS21, CS22) may be connected to different erase control lines.

[0026] Among ground select transistors (GSTs) of the same height, ground select transistors in the same row may be connected to the same ground select line, and ground select transistors in different rows may be connected to different ground select lines. For example, ground select transistors (GSTs) of cell strings (CS11, CS12) of the first row may be connected to the first ground select line (GSL1), and ground select transistors (GSTs) of cell strings (CS21, CS22) of the second row may be connected to the second ground select line (GSL2). However, the scope of the present invention is not limited thereto, and ground select transistors of the same height may be connected to the same ground select line. Alternatively, among ground select transistors of the same height, ground select transistors of at least two rows may be connected to the same ground select line, and ground select transistors of at least two different rows may be connected to different ground select lines. Alternatively, ground select transistors of different heights may be connected to the same ground select line.

[0027] Memory cells of the same height from the substrate or ground select transistor (GST) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, the first to seventh memory cells (MC1 to MC7) of cell strings (CS11, CS12, CS21, CS22) are each commonly connected to the seventh to seventh word lines (WL1 to WL7).

[0028] Among the first string select transistors (SSTd) of the same height, the string select transistors in the same row are connected to the same string select line, and the string select transistors in different rows are connected to different string select lines. For example, the first string select transistors (SSTd) of the cell strings (CS11, CS12) of the first row are connected in common to the string select line (SSL1d), and the first string select transistors (SSTd) of the cell strings (CS21, CS22) of the second row are connected in common to the string select line (SSL1d).

[0029] Likewise, among the second string select transistors (SSTu) of the same height, the string select transistors in the same row are connected to the same string select line, and the string select transistors in different rows are connected to different string select lines. For example, the second string select transistors (SSTu) of the first row of cell strings (CS11, CS12) are connected in common to the string select line (SSL1u), and the second string select transistors (SSTu) of the second row of cell strings (CS21, CS22) are connected in common to the string select line (SSL2u).

[0030] In one embodiment, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to different dummy word lines. For example, the first dummy memory cells (DMC1) are connected to the first dummy word line (DWL1), and the second dummy memory cells (DMC2) are connected to the second dummy word line (DWL2).

[0031] The second erase control transistors (ECT2) of the cell strings (CS11, CS12, CS21, CS22) may be commonly connected to the second erase control line (ECL2). However, the scope of the present invention is not limited thereto, and the second erase control transistors (ECT2) of the cell strings (CS11, CS12, CS21, CS22) may be connected to different erase control lines.

[0032] In one embodiment, the memory block (BLK) illustrated in FIG. 2 is a simple example, and the number of cell strings may increase or decrease, and the number of rows and columns formed by the cell strings may increase or decrease depending on the number of cell strings. Additionally, the number of cell transistors (GST, MC, DMC, SST, ECT, etc.) of the memory block (BLK) may each increase or decrease, and the height of the memory block (BLK) may increase or decrease depending on the number of cell transistors. Additionally, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may increase or decrease depending on the number of cell transistors.

[0033] FIG. 3 is a diagram showing a scatter plot of the threshold voltage of the ground select transistor of the memory block of FIG. 2. Referring to FIG. 1 to FIG. 3, the memory device (100) can control the cell transistors of the memory block (BLK) by applying various operating voltages to various lines (e.g., ECL, SSL, WL, DWL, GSL, etc.).

[0034] For example, the ground select transistors (GST) of the memory block (BLK) may have a first GST state (ST_GSTa) as illustrated in FIG. 3. That is, the ground select transistors (GST) of the memory block (BLK) may have a threshold voltage higher than the off voltage (VOFF) and lower than the on voltage (VON). Thus, when the off voltage (VOFF) is applied to the ground select line (GSL1 or GSL2), the ground select transistors (GST) can be normally turned off, and when the on voltage (VON) is applied to the ground select line (GSL1 or GSL2), the ground select transistors (GST) can be normally turned on. Accordingly, various operations of the memory device (100) (e.g., program operation, read operation, or erase operation, etc.) can be performed normally.

[0035] In one embodiment, as the memory device (100) performs various operations (e.g., program operation, read operation, or erase operation), the ground select transistors (GST) of the memory block (BLK) degrade, and thus the threshold voltage of the ground select transistors (GST) may change.

[0036] For example, as illustrated in FIG. 3, as the ground select transistors (GST) degrade, the threshold voltage of the ground select transistors (GST) may change to a second GST state (ST_GSTb), and the threshold voltage of some of the ground select transistors (GST) may become higher than the on voltage (VON). In this case, even if the on voltage (VON) is applied to the ground select line (GSL1 or GSL2), some of the ground select transistors (GST) may not turn on.

[0037] Alternatively, as illustrated in FIG. 3, as the ground select transistors (GST) degrade, the threshold voltage of the ground select transistors (GST) may change to a third GST state (ST_GSTc), and the threshold voltage of some of the ground select transistors (GST) may become lower than the off voltage (VOFF). In this case, some of the ground select transistors (GST) may not turn off even if the off voltage (VOFF) is applied to the ground select line (GSL1 or GSL2).

[0038] As described above, as the ground select transistor (GST) deteriorates, the ground select transistor (GST) may not be driven to the intended operating state (i.e., turn-on or turn-off), and accordingly, the operational reliability of the memory device (100) may be reduced. Therefore, to ensure the operational reliability of the memory device (100), the dispersion of the threshold voltage of the ground select transistor (GST) must be maintained within a certain range. Accordingly, the memory device (100) can perform a dispersion improvement operation for the ground select transistor (GST).

[0039] FIG. 4 is a conceptual diagram showing a vertical cross-sectional view of a memory block included in the memory cell array of FIG. 1. FIG. 5 is a diagram for explaining the dispersion improvement operation for the ground select transistor of the memory block of FIG. 4. Referring to FIG. 1, FIG. 4, and FIG. 5, the memory block (BLK) may include a, b, c, and d cell strings (CSa, CSb, CSc, CSd). The a, b, c, and d cell strings (CSa, CSb, CSc, CSd) may be located in the same row and may be connected to the same bit line (BL). Each of the a, b, c, and d cell strings (CSa, CSb, CSc, CSd) may have a structure similar to the cell strings (CS11~CS22) of the memory block (BLK) of FIG. 2, and a detailed description thereof is omitted.

[0040] The erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) of the cell strings (CSa~CSd) can be commonly connected to the first erase control line (ECL1). The ground select transistors (GSTa, GSTb) of the cell strings (CSa, CSb) can be commonly connected to the first ground select line (GSL1), and the ground select transistors (GSTc, GSTd) of the cell strings (CSc, CSd) can be commonly connected to the second ground select line (GSL2). The dummy memory cells (DMC1a, DMC1b, DMC1c, DMC1d) of the cell strings (CSa~CSd) can be commonly connected to the first dummy word line (DWL1). The memory cells (MC1a, MC1b, MC1c, MC1d) of the cell strings (CSa~CSd) can be commonly connected to the first word line (WL1). The string selection transistors (SST1a, SST1b, SST1c, SST1d) of the cell strings (CSa~CSd) can be each connected to the string selection lines (SSLa, SSLb, SSLc, SSLd). The erase control transistors (ECT2a, ECT2b, ECT2c, ECT2d) of the cell strings (CSa~CSd) can be commonly connected to the second erase control line (ECL2).

[0041] As previously described, for the operational reliability of the memory device (100), a dispersion improvement operation may be performed on the ground select transistors (GSTa~GSTd). For example, as shown in FIG. 5, a programming operation may be performed on the ground select transistor (GSTa) of the a cell string (CSa) to improve the threshold voltage dispersion of the ground select transistor (GSTa) of the a cell string (CSa). For the programming operation on the ground select transistor (GSTa) of the a cell string (CSa), the erase transistors (ECT1a, ECT1b, ECT1c, ECT1d) of the cell strings (CSa~CSd) may be turned off. To this end, a first off voltage (VOFF1) may be provided to the first erase control line (ECL1).

[0042] In one embodiment, the erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) of the cell strings (CSa~CSd) may degrade similarly to the ground select transistors (GSTa, GSTb, GSTc, GSTd). Accordingly, the erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) may have an ECT state (ST_ECT) as shown in FIG. 5, and some of the erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) (e.g., ECT1b, ECT1d) may not be turned off by the first off voltage (VOFF1).

[0043] In this case, some ground select transistors may be programmed unintentionally. For example, if cell string a (CSa) is the selected cell string and the ground select transistor (GSTa) of cell string a (CSa) is programmed, the remaining cell strings (CSb, CSc, CSd) are the unselected cell strings and the ground select transistors (GSTb, GSTc, GSTd) of the remaining cell strings (CSb, CSc, CSd) should be programme inhibited. However, as the erase control transistors (ECT1a~ECT1d) degrade, some erase control transistors (e.g., ECT1b, ECT1d) may not be normally turned off by the first off voltage (VOFF1). In this case, leakage current may occur through some erase control transistors (e.g., ECT1b, ECT1d), and as the boosting level of the channel corresponding to some erase control transistors (e.g., ECT1b, ECT1d) decreases, the ground select transistors of the corresponding channel (e.g., GSTb, GSTd) may be unintendedly programmed.

[0044] Due to an unintended program of the ground selection transistor (i.e., the ground selection transistor that is prohibited from programming being programmed), the dispersion of the threshold voltages of the ground selection transistors may exceed a certain range. This may reduce the operational reliability of the memory device (100), as previously described.

[0045] FIG. 6 is a flowchart showing the operation of the memory device of FIG. 1. Referring to FIG. 1, FIG. 2, FIG. 4, and FIG. 6, the memory device (100) can perform a dispersion improvement operation for the ground select transistor (GST) by performing the operations of steps S110 through S140.

[0046] In step S110, the memory device (100) can perform an erase operation on the ground select transistor (GST). For example, the memory device (100) can perform an erase operation on the ground select transistor (GST) of the memory block (BLK) such that the ground select transistors (GST) of the memory block (BLK) have a threshold voltage lower than the first verification voltage (VVFY1).

[0047] In step S120, the memory device (100) can perform a programming operation for the erase control transistor (ECT). For example, the memory device (100) can perform a programming operation for the erase control transistor (ECT) of the memory block (BLK) such that the erase control transistors (ECT) of the memory block (BLK) have a threshold voltage higher than the second verification voltage (VVFY2).

[0048] In step S130, the memory device (100) can perform a program operation on the ground select transistor (GST). For example, the memory device (100) can perform a program operation on the ground select transistor (GST) of the memory block (BLK) such that the ground select transistor (GST) of the memory block (BLK) has a threshold voltage higher than the third verification voltage (VVFY3).

[0049] In step S140, the memory device (100) can perform an erase operation on the erase control transistor (ECT). For example, the memory device (100) can perform an erase operation on the erase control transistor (ECT) of the memory block (BLK) such that the erase control transistor (ECT) of the memory block (BLK) has a threshold voltage lower than the fourth verification voltage (VVFY4).

[0050] According to the flowchart of FIG. 6, the memory device (100) may first perform a program operation for the erase control transistor (ECT) before performing a program operation for the ground select transistor (GST). In this case, by the program operation for the erase control transistor (ECT), the erase control transistors (ECT) of the memory block (BLK) may have a threshold voltage higher than the second verification voltage (VVFY2). In one embodiment, the second verification voltage (VVFY2) may be at a level higher than or equal to the first off voltage (VOFF1) provided to the erase control line during the program operation for the ground select transistor (GST).

[0051] That is, by performing a program operation for the erase control transistor (ECT) first before a program operation for the ground select transistor (GST), the erase control transistors (ECT) can have a threshold voltage higher than or equal to the first off voltage (VOFF1), and accordingly, the erase control transistors (ECT) can be normally turned off during the program operation for the ground select transistor (GST). Thus, unintended programming of the ground select transistors (GST) can be prevented, and the threshold voltage dispersion of the ground select transistors (GST) can be included within a predetermined range.

[0052] FIG. 7 is a diagram showing bias conditions for each step of the flowchart of FIG. 6. Referring to FIG. 1, FIG. 2, FIG. 4, FIG. 6, and FIG. 7, the memory device (100) can perform an erase operation for the ground select transistor (GST) of the memory block (BLK), a program operation for the erase control transistor (ECT), a program operation for the ground select transistor (GST), and an erase operation for the erase control transistor (ECT) based on the bias conditions as shown in FIG. 7.

[0053] For example, the memory device (100) may repeatedly perform a GST erase loop including a GST erase step (GST ERS) and a GST erase verification step (GST ERS VFY) for an erase operation on a ground select transistor (GST). During the GST erase step (GST ERS), the memory device (100) may apply an erase voltage (VERS) to a common source line (CSL), apply a wordline erase voltage (VERS_WL) to a first erase control line (ECL1), apply a wordline erase voltage (VERS_WL) to a first ground select line (GSL1), and float (FTL) a first dummy wordline (DWL1), a plurality of wordlines (WLs), a second dummy wordline (DWL2), string select lines (SSL1d, SSL1u), and a second erase control line (ECL2). In one embodiment, string select lines (SSL1d, SSL1u) may be floated when the common source line (CSL) reaches a first voltage (V1), and the second erase control line (ECL2) may be floated when the common source line (CSL) reaches a second voltage (V2). The threshold voltage of the ground select transistor (GST) may be lowered by the bias condition for the above-described GST erase step (GST ERS).

[0054] Subsequently, during the GST erase verification step (GST ERS VFY), the memory device (100) may apply a first verification voltage (VVFY1) to the first erase control line (ECL1) and the first ground select line (GSL1), and apply a first on voltage (VON1) to the first dummy word line (DWL1), a plurality of word lines (WLs), the second dummy word line (DWL2), string select lines (SSL1d, SSL1u), and the second erase control line (ECL2). In one embodiment, the first on voltage (VON1) may be a high voltage that turns on the cell transistors connected to the first dummy word line (DWL1), the plurality of word lines (WLs), the second dummy word line (DWL2), string select lines (SSL1d, SSL1u), and the second erase control line (ECL2).

[0055] In one embodiment, if the ground select transistor (GST) is not properly erased in the GST erase verification step (GST ERS VFY), the memory device (100) may repeat the GST erase loop including the GST erase step (GST ERS) and the GST erase verification step (GST ERS VFY). In one embodiment, if the GST erase loop is repeated, the erase voltage applied to the common source line (CSL) in the previous GST erase loop may be increased.

[0056] A memory device (100) may repeatedly perform an ECT program loop including an ECT program step (ECT PGM) and an ECT program verification step (ECT PGM VFY) for a program operation on an erase control transistor (ECT). During the ECT program step (ECT PGM), the memory device (100) may apply a first program voltage (VPGM1) to a first erase control line (ECL1), apply a first pass voltage (VPASS1) to a first ground select line (GSL1), a first dummy word line (DWL1), a plurality of word lines (WLs), and a second dummy word line (DWL2), and apply a second pass voltage (VPASS2) to string select lines (SSL1d, SSL1d) and a second erase control line (ECL2). In one embodiment, the first pass voltage (VPASS1) may be higher than the second pass voltage (VPASS2). Through the ECT program step (ECT PGM), the threshold voltage of the erase control transistors (ECT) connected to the first erase control line (ECL1) can be increased.

[0057] During the ECT program verification step (ECT PGM VFY), the memory device (100) may apply a second verification voltage (VVFY2) to a first erase control line (ECL1), apply a second on voltage (VON2) to a first ground select line (GSL1), a first dummy word line (DWL1), a plurality of word lines (WLs), and a second dummy word line (DWL2), and apply a third on voltage (VON3) to string select lines (SSL1d, SSL1u) and a second erase control line (ECL2). Through the ECT program verification step (ECT PGM VFY), it may be determined whether the threshold voltage of the erase control transistors (ECT) connected to the first erase control line (ECL1) is higher than the second verification voltage (VVFY2).

[0058] If the threshold voltage of the erase control transistors (ECT) connected to the first erase control line (ECL1) is not higher than the second verification voltage (VVFY2) (i.e., not a program pass), the memory device (100) can perform the next ECT program loop. In this case, the memory device (100) can provide a program voltage higher than the first program voltage (VPGM1) used in the previous program loop to the first erase control line (ECL1).

[0059] The memory device (100) may perform a GST program loop including a GST program step (GST PGM) and a GST program verification step (GST PGM VFY) for a program operation on a ground select transistor (GST). During the GST program step (GST PGM), the memory device (100) may apply a first off voltage (VOFF1) to a first erase control line (ECL1), apply a second program voltage (VPGM2) to a first ground select line (GSL1), apply a first pass voltage (VPASS1) to a first dummy word line (DWL1), a plurality of word lines (WL), and a second dummy word line (DWL2), and apply a second pass voltage (VPASS2) to string select lines (SSL1d, SSL1u) and a second erase control line (ECL2). Through the GST program stage (GST PGM), the threshold voltage of the ground select transistors (GST) connected to the first ground select line (GSL1) can be raised.

[0060] During the GST program verification step (GST PGM VFY), the memory device (100) may apply a second ON voltage (VON2) to a first erase control line (ECL1), apply a third verification voltage (VVFY3) to a first ground select line (GSL1), apply a second ON voltage (VON2) to a first dummy word line (DWL1), a plurality of word lines (WL), and a second dummy word line (DWL2), and apply a third ON voltage (VON3) to string select lines (SSL1d, SSL1u). Through the GST program verification step (GST PGM VFY), it may be determined whether the threshold voltage of the ground select transistors connected to the first ground select line (GSL1) is higher than the third verification voltage (VVFY3).

[0061] In one embodiment, through a programming operation for the erase control transistors (ECT), the threshold voltage of the erase control transistors (ECT) connected to the first erase control lines (ECL1) may be higher than the second verification voltage (VVFY2). The second verification voltage (VVFY2) may be higher than or equal to the first off voltage (VOFF1). In this case, during the GST programming step (GST PGM), the erase control transistors connected to the first erase control line (ECL1) may be normally turned off by applying the first off voltage (VOFF1) to the first erase control line (ECL1). Thus, it may be prevented that unselected erase control transistors or erase control transistors that are prohibited from programming are unintendedly programmed.

[0062] The memory device (100) may perform ECT erase loops including an ECT erase step (ECT ERS) and an ECT erase verification step (ECT ERS VFY) for an erase operation on an erase control transistor (ECT). During the ECT erase step (ECT ERS), the memory device (100) may apply an erase voltage to a common source line (CSL), apply a wordline erase voltage (VERS_WL) to a first erase control line (ECL1), and float (FLT) a first ground select line (GSL1), a first dummy wordline (DWL1), a plurality of wordlines (WLs), a second dummy wordline (DWL2), string select lines (SSL1d, SSL1u), and a second erase control line (ECL2). In one embodiment, string select lines (SSL1d, SSL1u) may be floated when the voltage of the common source line (CSL) reaches a first voltage (V1), and the second erase control line (ECL2) may be floated when the voltage of the common source line (CSL) reaches a second voltage (V2). Through the erase step of the ECT erase operation, the threshold voltage of the erase control transistors connected to the first erase control line (ECL1) may be lowered. In one embodiment, the word line erase voltage (VERS_WL) may be at a lower level than the voltage of the other floating word lines.

[0063] During the ECT erase verification step (ECT ERS VFY), the memory device (100) may apply a fourth verification voltage (VVFY4) to a first erase control line (ECL1) and apply a first on voltage (VON1) to a first ground select line (GSL1), a first dummy word line (DWL1), a plurality of word lines (WLs), a second dummy word line (DWL2), string select lines (SSL1d, SSL1u), and a second erase control line (ECL2). Through the ECT erase verification step (ECT ERS VFY), it may be determined whether the threshold voltage of the erase control transistors connected to the first erase control line (ECL1) is lower than the fourth verification voltage (VVFY4).

[0064] In one embodiment, the memory device (100) may perform one programming step or one erasure step instead of repeating multiple loops in each operation when performing the above-described programming operations and erasure operations (i.e., each verification step may be omitted).

[0065] In one embodiment, the memory device (100) may apply a wordline erase voltage (VERS_WL) or a voltage lower than that of other wordlines instead of floating the first dummy wordline (DWL1) during an erase operation for the ground select transistor (GST). In this case, dummy memory cells connected to the first dummy wordline (DWL1) may be erased together.

[0066] FIG. 8 is a diagram showing the threshold voltage dispersion of ground select transistors and erase control transistors according to the operation of the flowchart of FIG. 6. Referring to FIG. 1, FIG. 2, FIG. 3, FIG. 6, and FIG. 8, before the memory device (100) performs a dispersion improvement operation for the ground select transistor (GST), the ground select transistors (GST) may have a first GST state (ST_GST1), and the erase control transistors (ECT) may have a first ECT state (ST_ECT1).

[0067] First, the memory device (100) may perform an erase operation on the ground select transistor (GST) to lower the threshold voltage of the ground select transistors. When the erase operation on the ground select transistor (GST) is performed, the ground select transistors (GST) may have a second GST state (ST_GST2). The upper limit of the second GST state (ST_GST2) may be lower than or equal to the first verification voltage (VVFY1).

[0068] Subsequently, the memory device (100) may perform a programming operation on the erase control transistors (ECT) to raise the threshold voltage of the erase control transistors (ECT). When the programming operation on the erase control transistors (ECT) is performed, the erase control transistors (ECT) may have a second ECT state (ST_ECT2). The lower limit value of the second ECT state (ST_ECT2) may be higher than or equal to the second verification voltage (VVFY2).

[0069] Subsequently, the memory device (100) may perform a programming operation on the ground select transistors (GST) to raise the threshold voltage of the ground select transistors (GST). When the programming operation on the ground select transistors (GST) is performed, the ground select transistors (GST) may have a third GST state (ST_GST3). The lower limit value of the third GST state (ST_GST3) may be higher than or equal to the third verification voltage (VVFY3).

[0070] Subsequently, the memory device (100) may perform an erase operation on the erase control transistors (ECT) to lower the threshold voltage of the erase control transistors (ECT). When an erase operation is performed on the erase control transistors (ECT), the erase control transistors (ECT) may have a third ECT state (ST_ECT3). The upper limit value of the third ECT state (ST_ECT3) may be lower than or equal to the fourth verification voltage (VVFY4).

[0071] As described above, since the erase control transistors (ECT) are programmed first prior to programming the ground select lines (GST), the erase control transistors (ECT) can be normally turned off during programming operation for the ground select lines (GST). Accordingly, leakage current can be prevented in the unselected cell strings or cell strings that are prohibited from programming, and the threshold voltage dispersion of the ground select transistors (GST) can be contained within a certain range.

[0072] FIG. 9 is a flowchart showing the operation of the memory device of FIG. 1. In one embodiment, the memory device (100) may perform a dispersion improvement operation on other cell transistors (e.g., DMC, SST, etc.) as well as the ground select transistor (GST) to improve the operational reliability of the memory device (100). For example, in the embodiments described with reference to FIG. 1 to 8, the memory device (100) performs a dispersion improvement operation on the ground select transistor (GST). In the embodiment of FIG. 9, the memory device (100) may perform a dispersion improvement operation on dummy memory cells.

[0073] For example, as illustrated in FIG. 9, in step S210, the memory device (100) may perform an erase operation on the ground select transistor (GST). In step S220, the memory device (100) may perform a program operation on the erase control transistor (ECT). In step S230, the memory device (100) may perform a program operation on the ground select transistor (GST). In step S240, the memory device (100) may perform an erase operation on the erase control transistor (ECT). Since the operations of steps S210 through S240 are similar to the operations of steps S110 through S140 of FIG. 6, a detailed description thereof is omitted.

[0074] In step S250, the memory device (100) may perform an erase operation on the dummy memory cell (DMC). In step S260, the memory device (100) may perform a program operation on the dummy memory cell (DMC). For example, it is assumed that a dispersion improvement operation is performed on the first dummy memory cell (DMC1) adjacent to the ground select transistor (GST). The dispersion improvement operation on the first dummy memory cell (DMC1) may be performed through an erase operation and a program operation on the first dummy memory cell (DMC1).

[0075] The erase operation for the first dummy memory cell (DMC1) can be performed similarly to the erase operation for the ground select transistor (GST) of FIG. 7. In this case, the bias conditions for the remaining lines are the same, except that the word line erase voltage (VERS_WL) is provided instead of the first dummy word line (DWL1) being floated, so a detailed description thereof is omitted.

[0076] The programming operation for the first dummy memory cell (DMC1) can be performed similarly to the programming operation for the ground select transistor (GST) of FIG. 7. In this case, the bias conditions for the remaining lines are the same, except that the second program voltage (VPGM2) and the third verification voltage (VVFY3) are provided to the first dummy word line (DWL1), and the first pass voltage (VPASS1) and the second on voltage (VON2) are provided to the first ground select line (GSL1), so a detailed description thereof is omitted.

[0077] As described above, according to embodiments of the present invention, the memory device (100) can improve operational reliability by performing a dispersion improvement operation for ground select transistors. In one embodiment, the memory device (100) can perform a dispersion improvement operation for other cell transistors (e.g., other cell transistors excluding a plurality of word lines) as well as ground select transistors (GST).

[0078] For example, it is assumed that a memory device (100) performs a dispersion improvement operation on a second dummy memory cell (DCM2). In this case, the memory device (100) may perform an erase operation on the second dummy memory cell (DMC2), perform a program operation on the first erase control transistor (ECT1), perform a program operation on the second dummy memory cell (DMC2), and perform an erase operation on the first erase control transistor (ECT1). That is, the memory device (100) may first perform a program operation on the erase control transistors before performing a program operation on the cell transistor that is the target of the dispersion improvement operation. Accordingly, when the dispersion improvement operation is performed, the erase control transistor (ECT) is normally turned off, thereby improving the threshold voltage dispersion of the cell transistor that is the target of the dispersion improvement operation.

[0079] FIG. 10 is a flowchart showing the operation of the memory device of FIG. 1. FIG. 11 is a diagram for explaining the operation according to the flowchart of FIG. 10. Referring to FIG. 1, FIG. 10, and FIG. 11, the memory device (100) can perform a dispersion improvement operation for the ground select transistor (GST) through the operations of steps S310 to S330.

[0080] In step S310, the memory device (100) can perform an erase operation on the ground select transistor (GST). Since the operation of step S310 has been described through the operation of step S110 of FIG. 6 and the bias conditions for the erase operation on the ground select transistor (GST) of FIG. 7, a detailed description thereof is omitted.

[0081] In step S320, the memory device (100) can change the bias condition for the first erase control line (ECL1). In step S330, the memory device (100) can perform a program operation for the ground select transistor (GST) using the changed bias condition.

[0082] For example, as shown in FIG. 11, erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) may have an ECT state (ST_ECT). When a first off voltage (VOFF1) is applied to the first erase control line (ECL1), some erase control transistors (e.g., ECT1b, ECT1d, etc.) may not be turned off normally.

[0083] On the other hand, if the bias condition (e.g., off voltage) provided to the first erase control line (ECL1) is changed from the first off voltage (VOFF1) to the second off voltage (VOFF2) or lowered, the erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) can be normally turned off by the second off voltage (VOFF2). Therefore, when the ground select transistors (GST) are programmed using the changed bias condition, the erase control transistors (ECT1a, ECT1b, ECT1c, ECT1d) are normally turned off, so leakage in the non-select cell strings can be prevented and the threshold voltage dispersion of the ground select transistors (GST) can be improved.

[0084] FIGS. 12a and FIGS. 12b are conceptual drawings showing a vertical cross-sectional view of a memory block included in the memory cell array of FIG. 1. In one embodiment, the memory block of FIGS. 12a and FIGS. 12b is similar to the memory block described with reference to FIG. 4, and the differences are described below with emphasis. In the memory block of FIG. 12a, the ground select transistors (GSTa~GSTd) of a plurality of cell strings (CSa~CSd) are commonly connected to a single ground select line (GSL). In the memory block of FIG. 12b, the ground select transistors (GSTa~GSTd) of a plurality of cell strings (CSa~CSd) are each connected to different ground select lines (GSLa, GSLb, GSLc, GSLd). As described above, the ground select transistors (GSTa~GSTd) and ground select lines can be connected in various structures. Even if the ground selection transistors (GSTa~GSTd) and ground selection lines are connected in various structures, the memory device (100) can program the ground selection transistors using the operation method and bias conditions described with reference to FIGS. 6 and 7.

[0085] FIG. 13 is a drawing showing a vertical cross-sectional view of a memory block included in the memory cell array of FIG. 1. Referring to FIG. 13, the memory block (BLK) may include a first structure (STR1) and a second structure (STR2). The first structure (STR1) may include some of the cell transistors of a plurality of cell strings (CSa~CSd), and the second structure (STR2) may include the remaining cell transistors.

[0086] A first structure (STR1) may be formed on a substrate, and a second structure (STR2) may be formed on top of the first structure (STR2). For example, as shown in FIG. 13, the first structure (STR1) may be formed on the substrate of an N-well. In one embodiment, peripheral circuits (e.g., the address decoder (120), page buffer circuit (130), input / output circuit (140), and control logic circuit (150) of FIG. 1) may be formed on the lower part of the substrate of the N-well. That is, the memory device (100) may have a Cell-on-Peripheral (CoP) structure or a CMOS under Array (CUA) structure. In this case, the substrate to which the string is joined may be N-type. However, the scope of the present invention is not limited thereto, and the substrate to which the string is joined may be P-type.

[0087] A second structure (STR2) may be formed on top of a first structure (STR1). In this case, as illustrated in FIG. 13, the channel diameter may change in the region where the first structure (STR1) and the second structure (STR2) are electrically connected. For example, the channel of the first structure (STR1) may be formed to penetrate vertically stacked lines (ECL1, GSL1, DWL1, WL1~WL4) on the substrate, and the channel of the second structure may be formed to penetrate the stacked lines (WL5~WL7, DWL2, SSLd, SSLu, ECL2) on the first structure (STR1). The channel of the first structure (STR1) and the channel of the second structure (STR2) may be electrically connected in the junction region. That is, as illustrated in FIG. 13, in the region where the first structure (STR1) and the second structure (STR2) are electrically connected, the channel diameter of the second structure (STR2) may be smaller than the channel diameter of the first structure (STR1).

[0088] Depending on the change in channel diameter, cell transistors adjacent to the region where the first and second structures (STR1, STR2) are joined may not be used to store actual user data for operational reliability. That is, word lines adjacent to the region where the first and second structures (STR1, STR2) are joined (e.g., WL4, WL5, etc.) may be used as dummy word lines.

[0089] In one embodiment, according to embodiments of the present invention, a memory device (100) can perform a dispersion improvement operation for cell transistors connected to word lines (e.g., WL4, WL5, etc.) adjacent to the region where the first and second structures (STR1, STR2) are joined.

[0090] FIG. 14 is a block diagram showing a memory system according to an embodiment of the present invention. Referring to FIG. 14, the memory system (1000) may include a memory device (1100) and a memory controller (1200). The memory system (1000) may be a storage device, such as an SSD, configured to store user data in a computing system. In one embodiment, the memory device (1100) may be a memory device described with reference to FIG. 1 through 13 or may operate based on the operation method described with reference to FIG. 1 through 13.

[0091] The memory controller (1200) can store data in the memory device (1100) or read data stored in the memory device (1100). For example, the memory controller (1200) can transmit various signals (e.g., nCE, CLE, ALE, nRE, nWE, nR / B, etc.) to the memory device (1100) and can exchange data signals (e.g., DQ, DQS, etc.) with the memory device (1100). As a more detailed example, the memory device (1100) can receive a chip enable signal (nCE) from the memory controller (1200). When the chip enable signal (nCE) is in an enable state (e.g., low level), the memory device (1100) can transmit and receive signals with the memory controller (1200).

[0092] The memory controller (1200) can transmit a chip enable signal (nCE) to the memory device (1100). The memory controller (1200) can transmit and receive signals with the memory device (1100) through the chip enable signal (nCE).

[0093] The memory controller (1200) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (1100) along with a toggling write enable signal (nWE). The memory controller (1200) can transmit a data signal (DQ) containing a command (CMD) to the memory device (1100) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (1100) by transmitting an address latch enable signal (ALE) having an enable state.

[0094] The memory controller (1200) can transmit a read enable signal (nRE) to the memory device (1100). The memory controller (1200) can receive a data strobe signal (DQS) from the memory device (1100) or transmit a data strobe signal (DQS) to the memory device (1100).

[0095] In the data (DATA) output operation of the memory device (1100), the memory controller (1200) may generate a toggling read enable signal (nRE) and transmit the read enable signal (nRE) to the memory device (1100). For example, the memory controller (1200) may generate a read enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) may be generated in the memory device (1100) based on the read enable signal (nRE). The memory controller (1200) may receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the memory device (1100). The memory controller (1200) can obtain data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0096] In the data (DATA) input operation of the memory device (1100), the memory controller (1200) may generate a toggling data strobe signal (DQS). For example, the memory controller (1200) may generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the memory controller (1200) may transmit a data signal (DQ) containing the data (DATA) to the memory device (1100).

[0097] The memory controller (1200) can receive a ready / busy output signal (nR / B) from the memory device (1100). The memory controller (1200) can determine the status information of the memory device (1100) based on the ready / busy output signal (nR / B).

[0098] In one embodiment, the memory controller (1200) can control the general operations of the memory device (1100). For example, the memory controller (1200) can control the memory device (1100) so that the memory device (1100) performs the operations described with reference to FIGS. 1 to 13.

[0099] FIG. 15 is a flowchart showing the operation of the memory system of FIG. 14. Referring to FIG. 14 and FIG. 15, in step S1100, the memory controller (1200) can transmit an erase command (Erase CMD) to the memory device (1100). In step S1200, the memory device (1100) can perform an erase operation on a selected memory block in response to the erase command (Erase CMD).

[0100] In step S1300, the memory controller (1200) and the memory device (1100) can perform a cell counting operation for the ground select transistors (GST). For example, the memory controller (1200) can transmit a command for cell-counting to the memory device (1100). The memory device (1100) can perform a cell-counting operation for the ground select transistors in response to the received command. The cell counting operation can be performed by applying a reference voltage to the ground select line connected to the ground select transistors. In one embodiment, the reference voltage may be higher than the first verification voltage (VVFY1) (i.e., the verification voltage used in the erase operation for the ground select transistors). The memory device (1100) can transmit the result of the cell counting to the memory controller (1200). In one embodiment, the result of cell counting may indicate the number of ground select transistors having a threshold voltage higher than the reference voltage among the ground select transistors (i.e., the number of off-cells).

[0101] In step S1400, the memory controller (1200) can determine whether the cell counting result (i.e., the number of off-cells) is greater than a reference value. For example, if the cell counting result (i.e., the number of off-cells) is greater than the reference value, it may mean that degradation of the ground select transistors (GST) has occurred.

[0102] In this case (i.e., when the cell counting result is greater than the reference value), in step S1500, the memory controller (1200) and the memory device (1100) can perform a dispersion improvement operation for the ground select transistor (GST).

[0103] In one embodiment, the reference value may have different values ​​for each memory block included in the memory device (1100). Alternatively, the reference value may differ for each cell string or plane of the same memory block.

[0104] In one embodiment, the memory controller (1200) may perform a dispersion improvement operation on other unused cell transistors (e.g., DMC) as well as on the ground select transistor (GST) of the memory device (1100). In this case, the memory controller (1200) may further perform a cell counting operation on the unused cell transistors (e.g., DMC). In one embodiment, the reference voltage used for the cell counting operation on the dummy memory cells (DMC) may be different from the reference voltage used for the cell counting operation on the ground select transistors (GST). For example, the reference voltage used for the cell counting operation on the dummy memory cells (DMC) may be higher than the reference voltage used for the cell counting operation on the ground select transistors (GST).

[0105] FIG. 16 is a flowchart showing in detail the operation of step S1500 of FIG. 15. Referring to FIG. 14 through 16, the memory controller (1200) and the memory device (1100) can perform a dispersion improvement operation for the ground select transistors (GST) through the operations of steps S1510 through S1580.

[0106] For example, in step S1510, the memory controller (1200) may transmit an erase command to the memory device (1100) to erase the ground select transistor (GST). In step S1520, the memory device (1100) may perform an erase operation on the ground select transistor (GST) in response to the erase command to erase the ground select transistor (GST). In one embodiment, the operation of step S1520 is described through the bias of step S110 of FIG. 6 and the erase operation on the ground select transistor (GST) of FIG. 7, so a detailed description thereof is omitted.

[0107] In step S1530, the memory controller (1200) may transmit a program command to the memory device (1100) for programming the erase control transistor (ECT). In step S1540, the memory device (1100) may perform a programming operation for the erase control transistor (ECT) in response to the program command for programming the erase control transistor (ECT). In one embodiment, the operation of step S1540 is described through the bias of step S120 of FIG. 6 and the programming operation for the erase control transistor (ECT) of FIG. 7, so a detailed description thereof is omitted.

[0108] In step S1550, the memory controller (1200) may transmit a program command to the memory device (1100) to program the ground select transistor (GST). In step S1560, the memory device (1100) may perform a program operation for the ground select transistor (GST) in response to the program command to program the ground select transistor (GST). In one embodiment, the operation of step S1560 is described through the bias of step S130 of FIG. 6 and the program operation for the ground select transistor (GSST) of FIG. 7, so a detailed description thereof is omitted.

[0109] In step S1570, the memory controller (1200) may transmit an erase command to the memory device (1100) to erase the erase control transistor (ECT). In step S1580, the memory device (1100) may perform an erase operation on the erase control transistor (ECT) in response to the erase command to erase the erase control transistor (ECT). In one embodiment, the operation of step S1580 is described through step S140 of FIG. 6 and the bias of the erase operation on the erase control transistor (ECT) of FIG. 7, so a detailed description thereof is omitted.

[0110] As described above, the memory device (1100) receives various commands from the memory controller (1200) and, in response to the received commands, can perform an erase operation for the ground select transistor (GST), a program operation for the erase control transistor (ECT), a program operation for the ground select transistor (GST), and an erase operation for the erase control transistor (ECT), respectively. However, the scope of the present invention is not limited thereto, and the memory controller (1200) can control the memory controller (1100) to perform the operations described above by using a manufacturer's command, a reserve command, or a predetermined command.

[0111] In one embodiment, the memory controller (1200) can change various operating conditions of the memory device (1100) using a SET FEATURE COMMAND. That is, the memory controller (1200) can perform the operation of step S320 of FIG. 10 (i.e., changing the bias) using a SET FEATURE COMMAND.

[0112] FIG. 17 is a flowchart showing the operation of the memory controller of FIG. 14. Referring to FIG. 14 and FIG. 17, in step S2100, the memory controller (1200) can manage the program and erase cycles of the memory device (1100). For example, the memory controller (1200) can manage the program and erase cycles for each of the plurality of memory blocks included in the memory device (1100).

[0113] In step S2200, the memory controller (1200) can determine whether the program and erase cycles of a specific memory block are equal to a reference value (i.e., whether the reference value has been reached).

[0114] When the program and erase cycles of a specific memory block reach a reference value, in step S2300, the memory controller (1200) may perform a program operation for the ground select transistor (GST). In one embodiment, the memory controller (1200) may perform the operation of step S2300 based on the method described with reference to FIG. 16.

[0115] In one embodiment, the reference value compared with the program and erase cycles may be one or more. That is, the memory controller (1200) may perform a dispersion improvement operation for the ground select transistor (GST) at least once during the entire lifespan improvement of the memory device (1100).

[0116] In the above-described embodiment, the memory controller (1200) is described as performing a dispersion improvement operation for the ground select transistor (GST) when the program and erase cycles of the memory device (1100) reach a reference value, but the scope of the present invention is not limited thereto. For example, when a program fail, read error, read reclaim, etc., for a specific memory block of the memory device (1100) occurs a predetermined number of times, the memory controller (1200) may perform cell counting for the specific memory block and perform a dispersion improvement operation according to the cell counting result.

[0117] As described above, according to embodiments of the present invention, a memory device may perform a dispersion improvement operation on cell transistors (e.g., dummy memory cells, string selection transistors, etc.) connected to ground selection transistors or unused word lines of a memory block to ensure operational reliability.

[0118] FIG. 18 is a cross-sectional view showing a memory device according to one embodiment of the present disclosure. Referring to FIG. 18, the memory device (2600) may have a C2C (chip to chip) structure. A C2C structure may mean fabricating an upper chip including a cell region (CELL) on a first wafer, fabricating a lower chip including a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0119] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (2600) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA). The peripheral circuit region (PERI) may include a first substrate (2710), an interlayer insulating layer (2715), a plurality of circuit elements (2720a, 2720b, 2720c) formed on the first substrate (2710), a first metal layer (2730a, 2730b, 2730c) connected to each of the plurality of circuit elements (2720a, 2720b, 2720c), and a second metal layer (2740a, 2740b, 2740c) formed on the first metal layer (2730a, 2730b, 2730c). In one embodiment, the first metal layer (2730a, 2730b, 2730c) may be formed of tungsten, which has relatively high resistance, and the second metal layer (2740a, 2740b, 2740c) may be formed of copper, which has relatively low resistance.

[0120] In this specification, only the first metal layer (2730a, 2730b, 2730c) and the second metal layer (2740a, 2740b, 2740c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (2740a, 2740b, 2740c). At least some of the one or more metal layers formed on the upper part of the second metal layer (2740a, 2740b, 2740c) may be formed of aluminum or the like, having a lower resistance than the copper forming the second metal layer (2740a, 2740b, 2740c).

[0121] The interlayer insulating layer (2715) is disposed on a first substrate (2710) to cover a plurality of circuit elements (2720a, 2720b, 2720c), a first metal layer (2730a, 2730b, 2730c), and a second metal layer (2740a, 2740b, 2740c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0122] A lower bonding metal (2771b, 2772b) may be formed on the second metal layer (2740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2771b, 2772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2871b, 2872b) of the cell region (CELL) by a bonding method, and the lower bonding metal (2771b, 2772b) and the upper bonding metal (2871b, 2872b) may be formed of aluminum, copper, or tungsten, etc. The upper bonding metal (2871b, 2872b) of the cell region (CELL) may be referred to as the first metal pads, and the lower bonding metal (2771b, 2772b) of the peripheral circuit region (PERI) may be referred to as the second metal pads.

[0123] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (2810) and a common source line (2820). On the second substrate (2810), a plurality of word lines (2831-838; 830) may be stacked along a direction perpendicular to the upper surface of the second substrate (2810) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower sides of each of the word lines (2830), and a plurality of word lines (2830) may be disposed between the string selection lines and the ground selection lines.

[0124] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (2810) and penetrate word lines (2830), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer (2850c) and the second metal layer (2860c). For example, the first metal layer (2850c) may be a bitline contact, and the second metal layer (2860c) may be a bitline. In one embodiment, the bitline may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (2810).

[0125] In one embodiment illustrated in FIG. 18, the area where the channel structure (CH) and bitlines are placed may be defined as a bitline bonding area (BLBA). The bitlines may be electrically connected to circuit elements (2720c) that provide a page buffer (2893) in the peripheral circuit area (PERI) in the bitline bonding area (BLBA). As an example, the bitlines may be connected to upper bonding metals (2871c, 2872c) in the peripheral circuit area (PERI), and the upper bonding metals (2871c, 2872c) may be connected to lower bonding metals (2771c, 2772c) that are connected to circuit elements (2720c) of the page buffer (2893).

[0126] In the wordline bonding area (WLBA), wordlines (2830) may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate (2810) and may be connected to a plurality of cell contact plugs (2841-847; 840). The wordlines (2830) and the cell contact plugs (2840) may be connected to each other at pads provided by extending at least some of the wordlines (2830) at different lengths along the second direction (X-axis direction). A first metal layer (2850b) and a second metal layer (2860b) may be connected in sequence to the upper portion of the cell contact plugs (2840) connected to the wordlines (2830). The cell contact plugs (2840) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (2871b, 2872b) of the cell area (CELL) and the lower bonding metal (2771b, 2772b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0127] Cell contact plugs (2840) may be electrically connected to circuit elements (2720b) ​​that provide a row decoder (2894) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (2720b) ​​that provide the row decoder (2894) may be different from the operating voltage of the circuit elements (2720c) that provide the page buffer (2893). For example, the operating voltage of the circuit elements (2720c) that provide the page buffer (2893) may be greater than the operating voltage of the circuit elements (2720b) ​​that provide the row decoder (2894).

[0128] A common source line contact plug (2880) may be disposed in the external pad bonding area (PA). The common source line contact plug (2880) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source line (2820). A first metal layer (2850a) and a second metal layer (2860a) may be sequentially laminated on top of the common source line contact plug (2880). For example, the area where the common source line contact plug (2880), the first metal layer (2850a), and the second metal layer (2860a) are disposed may be defined as the external pad bonding area (PA).

[0129] Meanwhile, input / output pads (2705, 2805) may be disposed in the external pad bonding area (PA). Referring to FIG. 18, a lower insulating film (2701) covering the lower surface of the first substrate (2710) may be formed on the lower surface of the first substrate (2710), and a first input / output pad (2705) may be formed on the lower insulating film (2701). The first input / output pad (2705) is connected to at least one of a plurality of circuit elements (2720a, 2720b, 2720c) disposed in the peripheral circuit area (PERI) through a first input / output contact plug (2703), and may be separated from the first substrate (2710) by the lower insulating film (2701). Additionally, a side insulating film is disposed between the first input / output contact plug (2703) and the first substrate (2710) to electrically separate the first input / output contact plug (2703) and the first substrate (2710).

[0130] Referring to FIG. 18, an upper insulating film (2801) covering the upper surface of the second substrate (2810) may be formed on the upper surface of the second substrate (2810), and a second input / output pad (2805) may be disposed on the upper insulating film (2801). The second input / output pad (2805) may be connected to at least one of a plurality of circuit elements (2720a, 2720b, 2720c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (2803).

[0131] According to the embodiments, the second substrate (2810) and common source line (2820), etc., may not be placed in the area where the second input / output contact plug (2803) is placed. Additionally, the second input / output pad (2805) may not overlap with the word lines (2830) in the third direction (Z-axis direction). Referring to FIG. 18, the second input / output contact plug (2803) is separated from the second substrate (2810) in a direction parallel to the upper surface of the second substrate (2810) and may be connected to the second input / output pad (2805) by penetrating the interlayer insulating layer (2815) of the cell area (CELL).

[0132] According to embodiments, the first input / output pad (2705) and the second input / output pad (2805) may be formed optionally. For example, the memory device (2600) may include only the first input / output pad (2705) disposed on the upper part of the first substrate (2710), or only the second input / output pad (2805) disposed on the upper part of the second substrate (2810). Alternatively, the memory device (2600) may include both the first input / output pad (2705) and the second input / output pad (2805).

[0133] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0134] The memory device (2600) may form a lower metal pattern (2773a) of the same shape as the upper metal pattern (2872a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (2872a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (2773a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern of the same shape as the lower metal pattern of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern formed on the upper metal layer of the peripheral circuit region (PERI).

[0135] A lower bonding metal (2771b, 2772b) may be formed on the second metal layer (2740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2771b, 2772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2871b, 2872b) of the cell region (CELL) by a bonding method.

[0136] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (2892) of the same shape as the lower metal pattern (2752) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (2752) formed on the upper metal layer of the peripheral circuit area (PERI). In an exemplary embodiment, a contact may not be formed on the upper metal pattern (2892) formed on the upper metal layer of the cell area (CELL).

[0137] In an exemplary embodiment, corresponding to a metal pattern formed on the uppermost metal layer of one of the cell region (CELL) and peripheral circuit region (PERI), a reinforced metal pattern having the same cross-sectional shape as the formed metal pattern may be formed on the uppermost metal layer of the other of the cell region (CELL) and peripheral circuit region (PERI). Contacts may not be formed in the reinforced metal pattern.

[0138] In one embodiment, the memory device (2600) of FIG. 18 is shown not to include an erase control line and an erase control transistor, but the scope of the present invention is not limited thereto. The memory device (2600) may further include an erase control line and an erase control transistor and may operate based on the operation method described with reference to FIG. 1 to FIG. 13.

[0139] FIG. 19 is a block diagram showing a host-storage system (3000) according to an exemplary embodiment of the present invention.

[0140] A host-storage system (3000) may include a host (3100) and a storage device (3200). Additionally, the storage device (3200) may include a storage controller (3210) and a non-volatile memory (NVM) (3220). Additionally, according to an exemplary embodiment of the present invention, the host (3100) may include a host controller (3110) and a host memory (3120). The host memory (3120) may function as a buffer memory for temporarily storing data to be transmitted to the storage device (3200) or data transmitted from the storage device (3200).

[0141] The storage device (3200) may include storage media for storing data in response to a request from the host (3100). As an example, the storage device (3200) may include at least one of a Solid State Drive (SSD), embedded memory, and removable external memory. If the storage device (3200) is an SSD, the storage device (3200) may be a device conforming to the NVMe (non-volatile memory express) standard. If the storage device (3200) is embedded memory or external memory, the storage device (3200) may be a device conforming to the UFS (universal flash storage) or eMMC (embedded multi-media card) standard. The host (3100) and the storage device (3200) may each generate and transmit packets according to the adopted standard protocol.

[0142] When the non-volatile memory (3220) of the storage device (3200) includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device (3200) may include various other types of non-volatile memory. For example, the storage device (3200) may be equipped with MRAM (Magnetic RAM), Spin-Transfer Torque MRAM (Spin-Transfer Torque MRAM), Conductive Bridging RAM (CBRAM), FeRAM (Ferroelectric RAM), PRAM (Phase RAM), Resistive RAM, and various other types of memory.

[0143] According to one embodiment, the host controller (3110) and the host memory (3120) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (3110) and the host memory (3120) may be integrated on the same semiconductor chip. As an example, the host controller (3110) may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (3120) may be an embedded memory provided within the application processor, or a non-volatile memory or memory module placed outside the application processor.

[0144] The host controller (3110) can manage the operation of storing data (e.g., write data) of the buffer area of ​​the host memory (3120) in the non-volatile memory (3220), or storing data (e.g., read data) of the non-volatile memory (3220) in the buffer area.

[0145] The storage controller (3210) may include a host interface (3211), a memory interface (3212), and a central processing unit (CPU) (3213). Additionally, the storage controller (3210) may further include a Flash Translation Layer (FTL) (3214), a packet manager (3215), a buffer memory (3216), an error correction code (ECC) (3217) engine, and an advanced encryption standard (AES) engine (3218). The storage controller (3210) may further include a working memory (not shown) on which the Flash Translation Layer (FTL) (3214) is loaded, and data writing and reading operations for non-volatile memory (3220) may be controlled by the CPU (3213) executing the Flash Translation Layer.

[0146] The host interface (3211) can transmit and receive packets with the host (3100). The packet transmitted from the host (3100) to the host interface (3211) may include a command or data to be written to the non-volatile memory (3220), and the packet transmitted from the host interface (3211) to the host (3100) may include a response to the command or data read from the non-volatile memory (3220). The memory interface (3212) can transmit data to be written to the non-volatile memory (3220) to the non-volatile memory (3220) or receive data read from the non-volatile memory (3220). This memory interface (3212) may be implemented to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0147] The flash conversion layer (3214) can perform various functions such as address mapping, wear-leveling, and garbage collection. Address mapping is an operation that converts a logical address received from the host (3100) into a physical address used to actually store data in the non-volatile memory (3220). Wear-leveling is a technique to prevent excessive degradation of a specific block by ensuring that blocks in the non-volatile memory (3220) are used evenly, and can be implemented, for example, through firmware technology that balances the erase counts of physical blocks. Garbage collection is a technique to secure usable capacity in the non-volatile memory (3220) by copying the valid data of a block to a new block and then erasing the existing block.

[0148] The packet manager (3215) can generate packets according to the protocol of the interface agreed upon with the host (3100) or parse various information from packets received from the host (3100). Additionally, the buffer memory (3216) can temporarily store data to be written to the non-volatile memory (3220) or data to be read from the non-volatile memory (3220). The buffer memory (3216) may be a configuration provided within the storage controller (3210), but it may be placed outside the storage controller (3210).

[0149] The ECC engine (3217) can perform error detection and correction functions for read data read from the non-volatile memory (3220). More specifically, the ECC engine (3217) can generate parity bits for the write data to be written to the non-volatile memory (3220), and the parity bits thus generated can be stored in the non-volatile memory (3220) together with the write data. When reading data from the non-volatile memory (3220), the ECC engine (3217) can correct errors in the read data using the parity bits read from the non-volatile memory (3220) together with the read data, and output the read data with the errors corrected.

[0150] The AES engine (3218) can perform at least one of the encryption and decryption operations on data input to the storage controller (3210) using a symmetric-key algorithm.

[0151] In one embodiment, the storage device (4200) may operate based on the operation method described with reference to FIGS. 1 to 17.

[0152] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention.

Claims

Claim 1 A method of operation of a memory device comprising a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the method comprising: a step of performing a first erase operation on a ground selection transistor among the plurality of cell transistors; a step of performing a first program operation on an erase control transistor located between the substrate and the ground selection transistor among the plurality of cell transistors after the first erase operation; a step of performing a second program operation on the ground selection transistor after the first program operation; and a step of performing a second erase operation on the erase control transistor after the second program operation. Claim 2 In claim 1, the step of performing a first erase operation for the ground select transistor comprises: applying an erase voltage to a common source line, applying a first wordline erase voltage to a ground select line connected to the ground select transistor and an erase control line connected to the erase control transistor, and floating a plurality of wordlines and a plurality of string select lines connected to the remaining cell transistors among the plurality of cell transistors; and applying a first erase verification voltage to the ground select line. Claim 3 In claim 2, the step of performing a first program operation for the erase control transistor comprises: applying a first program voltage to the erase control line and applying a first pass voltage to the ground select line and the lines; and applying a first program verification voltage to the erase control line. Claim 4 In claim 3, the operation method in which the first program verification voltage is higher than the first erasure verification voltage. Claim 5 In claim 3, the step of performing a second program operation for the ground selection transistor comprises: applying a second program voltage to the ground selection line, applying a first off voltage lower than or equal to the first program verification voltage to the erase control line, and applying a second pass voltage to the lines; and applying a second program verification voltage to the ground selection line. Claim 6 In claim 5, the step of performing a second erase operation for the erase control transistor comprises: applying an erase voltage to the common source line, applying a second word line erase voltage to the erase control line, and floating the ground select line and the lines; and applying a second erase verification voltage to the erase control line. Claim 7 In claim 6, the second erasure verification voltage is lower than or equal to the second program verification voltage. Claim 8 In claim 1, the step of performing a first erase operation for the ground select transistor comprises: applying an erase voltage to a common source line, applying a first wordline erase voltage to a ground select line connected to the ground select transistor, an erase control line connected to the erase control transistor, and a dummy wordline connected to a dummy memory cell among the plurality of cell transistors, and floating a plurality of wordlines and a plurality of string select lines connected to the remaining cell transistors among the plurality of cell transistors; and applying a first erase verification voltage to the ground select line, wherein the dummy memory cell is adjacent to the ground select transistor. Claim 9 A method of operation according to claim 1, further comprising: a step of performing a third erase operation on a dummy memory cell adjacent to the erase control transistor among the plurality of cell transistors after the second erase operation on the erase control transistor; and a step of performing a third program operation on the dummy memory cell. Claim 10 A method of operation according to claim 1, further comprising the step of performing an erase operation on memory cells located between the ground select transistor and the bit line among the cell transistors before performing the first erase operation on the ground select transistor. Claim 11 A method of operation of a memory device comprising a memory block including a plurality of lines stacked in a direction perpendicular to a substrate, the method comprising: a step of applying a first erase voltage to a common source line and applying a first word line erase voltage to a ground selection line among the plurality of lines; a step of applying a first erase verification voltage to the ground selection line; a step of applying a first program voltage to an erase control line located between the ground selection line and the substrate among the plurality of lines; a step of applying a first program verification voltage to the erase control line; a step of applying a second program voltage to the ground selection line; a step of applying a second program verification voltage to the ground selection line; a step of applying a second erase voltage to the common source line and applying a second word line erase voltage to the erase control line; and a step of applying a second erase verification voltage to the erase control line. Claim 12 A method of operation according to claim 11, wherein while the second program voltage is applied to the ground selection line, a first off voltage lower than or equal to the first program verification voltage is applied to the erase control line. Claim 13 In claim 11, the second erasure verification voltage is lower than or equal to the second program verification voltage. Claim 14 A method of operation according to claim 11, wherein the memory block comprises a plurality of cell strings commonly connected to a single bit line, the ground select line is connected to ground select transistors included in each of some of the plurality of cell strings, and the erase control line is connected to erase control transistors included in each of the plurality of cell strings. Claim 15 A method of operation according to claim 11, wherein while applying a first wordline erase voltage to the ground selection line, the first wordline erase voltage is applied to a dummy wordline adjacent to the ground selection line among the plurality of lines, and while applying the first erase verification voltage to the ground selection line, the first erase verification voltage is applied to the dummy wordline. Claim 16 A method of operation according to claim 15, further comprising the step of applying a third program voltage to the dummy word line; and the step of applying a third program verification voltage to the dummy word line. Claim 17 A method of operation according to claim 11, further comprising the steps of: applying a third erase voltage to the common source line and applying a third word line erase voltage to a dummy word line adjacent to the ground selection line among the plurality of lines; applying a third erase verification voltage to the dummy word line; applying a third program voltage to the dummy word line; and applying a third program verification voltage to the dummy word line. Claim 18 A method of operation of a memory controller configured to control a memory device comprising a plurality of cell transistors stacked in a direction perpendicular to a substrate, the method comprising: transmitting a first command for a cell counting operation for ground select transistors among the plurality of cell transistors to the memory device; receiving a cell counting result for the ground select transistors from the memory device; and performing a dispersion improvement operation for the ground select transistors based on the cell counting result, wherein the dispersion improvement operation comprises: transmitting a first erase command to the memory device for erasing the ground select transistors; transmitting a first program command to the memory device for programming erase control transistors located between the ground select transistor and the substrate among the plurality of cell transistors; transmitting a second program command to the memory device for programming the ground select transistors; and transmitting a second erase command to the memory device for erasing the erase control transistors. Claim 19 A method of operation according to claim 18, further comprising the step of transmitting a third erase command to erase memory cells among the plurality of cell transistors before transmitting the first command to the memory device. Claim 20 A method of operation according to claim 18, further comprising the step of managing program and erase cycles of the memory device, wherein when the program and erase cycles reach a reference value, the first command is transmitted to the memory device.

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