Semiconductor device

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same, comprising lower electrodes on a substrate, a lower support pattern provided between the lower electrodes, an upper support pattern on the lower electrodes, an upper electrode covering the lower electrodes, the lower support pattern and the upper support pattern, and a dielectric film interposed between the lower electrodes and the upper electrode, between the lower support pattern and the upper electrode, and between the upper support pattern and the upper electrode, wherein the upper support pattern comprises a first portion on the upper surfaces of the lower electrodes and a second portion filling the internal space of each of the lower electrodes.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor memory device including a capacitor and a method for manufacturing the same. Background Technology

[0003] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements.

[0004] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. The problem to be solved

[0006] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability, and a method for manufacturing the same.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0009] To solve the aforementioned technical problems, a semiconductor device according to an embodiment of the present invention comprises lower electrodes on a substrate, a lower support pattern provided between the lower electrodes, an upper support pattern on the lower electrodes, an upper electrode covering the lower electrodes, the lower support pattern and the upper support pattern, and a dielectric film interposed between the lower electrodes and the upper electrode, between the lower support pattern and the upper electrode, and between the upper support pattern and the upper electrode, wherein the upper support pattern may include a first portion on the upper surfaces of the lower electrodes and a second portion filling the internal space of each of the lower electrodes.

[0010] Additionally, a semiconductor device according to embodiments of the present invention comprises lower electrodes on a substrate, a lower support pattern provided between the lower electrodes, an upper support pattern on the lower electrodes, an upper electrode covering the lower electrodes, the lower support pattern and the upper support pattern, and a dielectric film interposed between the lower electrodes and the upper electrode, between the lower support pattern and the upper electrode, and between the upper support pattern and the upper electrode, wherein each of the lower electrodes includes a horizontal portion and a vertical portion extending vertically from the horizontal portion, the horizontal portion and the vertical portion define an internal space of each of the lower electrodes, the upper support pattern covers the upper surfaces of the lower electrodes, and at least a portion of the upper support pattern may extend into the internal space of each of the lower electrodes.

[0011] A substrate including an active pattern, an impurity region provided within the active pattern, a word line provided within the substrate and extending across the active pattern, a bit line provided on the substrate and extending in a direction intersecting the word line, a storage node contact provided on the substrate and electrically connected to the impurity region, a landing pad electrically connected to the storage node contact, a lower electrode electrically connected to the landing pad, a lower support pattern and an upper support pattern provided between the lower electrode and an adjacent lower electrode in a planar view, the lower electrode, an upper electrode covering the lower support pattern and the upper support pattern, and a dielectric film interposed between the lower electrode and the upper electrode, between the lower support pattern and the upper electrode, and between the upper support pattern and the upper electrode, wherein the upper support pattern may include a first portion on the upper surface of the lower electrode and a second portion filling the internal space of the lower electrode. Effects of the invention

[0013] According to the semiconductor device of the present invention, lower electrodes can be physically supported through a plurality of support patterns located at different levels.

[0014] Furthermore, according to the method for manufacturing a semiconductor device of the present invention, interference between lower electrodes can be prevented by recessing the lower electrode film to a level lower than the lower surface of the upper support pattern, and the process can be simplified and process variation reduced by omitting the process of depositing a separate insulating film on the sidewall of the upper support pattern. As a result, defects in the capacitor of the semiconductor device according to the present invention can be reduced, and accordingly, electrical characteristics and reliability can be improved. Brief explanation of the drawing

[0016] FIG. 1 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 2, FIGS. 3, and FIGS. 4 are cross-sectional views for explaining a semiconductor device according to embodiments of the present invention, each corresponding to a cross-section of FIG. 1 cut along the line AA'. FIGS. 5 to 10 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention, each corresponding to a cross-section of FIG. 1 cut along the line AA'. FIG. 11 is a block diagram for explaining a semiconductor device according to embodiments of the present invention. FIG. 12 is an enlarged view for explaining a part of a cell block of a semiconductor device according to embodiments of the present invention, corresponding to part P1 of FIG. 11. FIG. 13 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, corresponding to the cross-section of FIG. 12 cut along the line AA'. Specific details for implementing the invention

[0017] Hereinafter, a semiconductor device and a method for manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

[0019] FIG. 1 is a plan view for explaining a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, corresponding to the cross section cut by the line AA' in FIG. 1.

[0020] Referring to FIGS. 1 and 2, a substrate (10) may be provided. The substrate (10) may be a semiconductor substrate. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate (10) may have an upper surface parallel to a first direction (D1) and a second direction (D2) and orthogonal to a third direction (D3). The first to third directions (D1, D2, D3) may be directions orthogonal to each other.

[0021] An interlayer insulating film (12) may be provided on a substrate (10). The interlayer insulating film (12) may cover at least a portion of the upper surface of the substrate (10). The interlayer insulating film (12) may comprise, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride. According to embodiments, the interlayer insulating film (12) may be an empty region.

[0022] Conductive contacts (14) may be provided within the interlayer insulating film (12). The conductive contacts (14) may be spaced apart in a first direction (D1) and a second direction (D2). The conductive contacts (14) may comprise, for example, at least one of an impurity-doped semiconductor material (e.g., polycrystalline silicon), a metal-semiconductor compound (e.g., tungsten silicide), a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride, etc.), or a metal (e.g., titanium, tungsten, or tantalum, etc.). The conductive contacts (14) may be electrically connected to impurity regions (e.g., source / drain terminals) formed within the substrate (10).

[0023] An etch-stop pattern (420) may be provided on the interlayer insulating film (12). The etch-stop pattern (420) may cover the interlayer insulating film (12) and expose conductive contacts (14). The etch-stop pattern (420) may include, for example, at least one of silicon oxide, SiCN, or SiBN.

[0024] Lower electrodes (BE) may be provided within conductive contact holes (CH) on the conductive contacts (14). Each of the lower electrodes (BE) may penetrate the etch-stop pattern (420) and may be electrically connected to each of the conductive contacts (14). Each of the lower electrodes (BE) may have a width that increases toward, for example, a third direction (D3). The lower electrodes (BE) may include a conductive material. The lower electrodes (BE) may comprise, for example, at least one of a metallic material (e.g., cobalt, titanium, nickel, tungsten and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaAlN) and tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru) and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo) or a metal silicide.

[0025] The lower electrodes (BE) may be spaced apart from each other in a first direction (D1) and a second direction (D2). In a planar view according to FIG. 1, the lower electrodes (BE) may be arranged to have a honeycomb shape. More specifically, with one lower electrode (BE) at the center, six lower electrodes (BE) may be provided to surround the one lower electrode (BE) in a hexagonal shape.

[0026] Each of the lower electrodes (BE) may include, for example, a horizontal portion (BEh) in contact with any one of the conductive contacts (14) and a vertical portion (BEv) extending from the horizontal portion (BEh) in a third direction (D3). The horizontal portion (BEh) may be located at a level lower than the lower support pattern (BS). The horizontal portion (BEh) and the vertical portion (BEv) may define the internal space (IS) of each of the lower electrodes (BE). The internal space (IS) of each of the lower electrodes (BE) may increase in width and then decrease as it moves in the third direction (D3) (i.e., away from the substrate (10)). The upper surface (BEt) of each of the lower electrodes (BE) may have a donut shape.

[0027] A lower support pattern (BS), an intermediate support pattern (MS), and an upper support pattern (TS) may be provided on a substrate (10). The lower support pattern (BS) and the intermediate support pattern (MS) may be spaced apart from each other in a third direction (D3). The intermediate support pattern (MS) and the upper support pattern (TS) may be spaced apart from each other in a third direction (D3). The intermediate support pattern (MS) may be provided between the lower support pattern (BS) and the upper support pattern (TS). The lower support pattern (BS) and the intermediate support pattern (MS) may be provided between the lower electrodes (BE). The lower support pattern (BS) and the intermediate support pattern (MS) may surround and contact the outer wall (OSW) of each of the lower electrodes (BE). The upper support pattern (TS) may cover the upper surface (BEt) of each of the lower electrodes (BE). The lower support pattern (BS), the intermediate support pattern (MS), and the upper support pattern (TS) may physically support the lower electrodes (BE). The lower support pattern (BS), the middle support pattern (MS), and the upper support pattern (TS) may include, for example, at least one of silicon nitride, SiBN, or SiCN. According to the embodiments, additional support patterns spaced apart from each of the lower support pattern (BS), the middle support pattern (MS), and the upper support pattern (TS) in a third direction (D3) may also be provided. In this case, the support pattern provided on the top layer may also be referred to as the upper support pattern (TS).

[0028] The upper support pattern (TS) may include a first portion (610) on the upper surface (BEt) of each of the lower electrodes (BE), a second portion (630) filling the internal space (IS) of each of the lower electrodes (BE), and a third portion (650) between the first portion (610) and the second portion (630). The first portion (610) may surround the through holes (PH) described later. The thickness of the first portion (610) in the third direction (D3) may be greater than the thickness of the third portion (650) in the third direction (D3). The thickness of the first portion (610) in the third direction (D3) may be greater than the thickness of the intermediate support pattern (MS) and the lower support pattern (BS) in the third direction (D3). The second portion (630) may contact the inner wall (ISW) of each of the lower electrodes (BE) and physically support each of the lower electrodes (BE). The second part (630) may increase in width and then decrease as it moves toward the third direction (D3), for example. The second part (630) may overlap the lower support pattern (BS) and the middle support pattern (MS) in a horizontal direction (i.e., the first direction (D1) and the second direction (D2)). The third part (650) may connect the first part (610) and the second part (630). The side wall of the third part (650) may be aligned with the outer wall (OSW) of each of the lower electrodes (BE). The width of the third part (650) may be less than or equal to the upper width of each of the lower electrodes (BE).

[0029] The lower surface (610b) of the first part (610) of the upper support pattern (TS) may be spaced apart from the upper surface (BEt) of each of the lower electrodes (BE) in a third direction (D3). In other words, the lower surface (610b) of the first part (610) of the upper support pattern (TS) may be located at a higher level than the upper surface (BEt) of each of the lower electrodes (BE). The upper surface (BEt) of each of the lower electrodes (BE) may be located at a higher level than the upper surface of the intermediate support pattern (MS). The upper surface (BEt) of each of the lower electrodes (BE) may be located at substantially the same level as the lower surface (650b) of the third part (650) of the upper support pattern (TS). The height difference (HD) between the lower surface (610b) of the first part (610) of the upper support pattern (TS) and the upper surface (BEt) of each of the lower electrodes (BE) can be, for example, about 10 Å to about 150 Å.

[0030] A semiconductor device according to the present invention may have through holes (PH) that penetrate a first portion (610) of an upper support pattern (TS), an intermediate support pattern (MS), and a lower support pattern (BS), and expose an etching stop pattern (420). Each of the through holes (PH) may be located between adjacent lower electrodes (BE). Each of the through holes (PH) may be located between three adjacent lower electrodes (BE). The upper surface of each of the through holes (PH) may have a circular shape. However, this is merely illustrative and the present invention is not limited thereto, and each of the through holes (PH) may have various upper surface shapes and may be provided between a plurality of lower electrodes (BE).

[0031] A dielectric film (DL) may be provided on a lower support pattern (BS), an intermediate support pattern (BS), an upper support pattern (TS), and an etch stop pattern (420). The dielectric film (DL) may conformally cover the upper and lower surfaces of the lower support pattern (BS), the upper and lower surfaces of the intermediate support pattern (BS), the upper and lower surfaces and sidewalls of the upper support pattern (TS), the upper surface of the etch stop pattern (420), and the outer walls (OSW) of each of the lower electrodes (BE). The dielectric film (DL) may fill at least a portion of the through holes (PH). The dielectric film (DL) in contact with the outer walls (OSW) of the lower electrodes (BE) may have a crystal structure substantially identical to the crystal structure of the lower electrodes (BE). The dielectric film (DL) may have, for example, a tetragonal structure. The dielectric film (DL) may comprise a single film or a combination of such films, comprising, for example, a metal oxide such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, TiO2, a dielectric material having a perovskite structure such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, PLZT, or any one selected from combinations thereof.

[0032] An upper electrode (TE) may be provided on a dielectric film (DL). The upper electrode (TE) may include a barrier film (510) conformally covering the dielectric film (DL) and a conductive film (530) covering the barrier film (510). The barrier film (510) may include, for example, a metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride). The conductive film (530) may include, for example, impurity-doped polysilicon or impurity-doped silicon-germanium.

[0033] The upper electrode (TE) can fill the interior of each of the through holes (PH), between the etch stop pattern (420) and the lower support pattern (BS), between the lower support pattern (BS) and the intermediate support pattern (MS), and between the intermediate support pattern (MS) and the upper support pattern (TS). A dielectric film (DL) can be interposed between the outer wall (OSW) of the lower electrodes (BE) and the upper electrode (TE), between the lower support pattern (BS) and the upper electrode (TE), between the intermediate support pattern (MS) and the upper electrode (TE), and between the upper support pattern (TS) and the upper electrode (TE).

[0034] The lower electrodes (BE), dielectric film (DL), and upper electrode (TE) can constitute a capacitor (CAP). For example, the capacitor (CA) may be an information storage element for the semiconductor device according to the present invention to operate as a semiconductor memory device.

[0036] FIG. 3 is a cross-sectional view for illustrating a semiconductor device according to embodiments of the present invention, corresponding to the cross-section of FIG. 1 cut along the line AA'. Hereinafter, for convenience of explanation, descriptions of matters substantially identical to those described with reference to FIG. 1 and FIG. 2 are omitted, and the differences are described in detail.

[0037] Referring to FIGS. 1 and 3, the upper surface (BEt) of each of the lower electrodes (BE) may be located at substantially the same level as the lower surface (610b) of the first part (610) of the upper support pattern (TS) (i.e., the upper surface of the second part (630) of the upper support pattern (TS). According to embodiments, the upper surface (BEt) of each of the lower electrodes (BE) and the lower surface (610b) of the first part (610) of the upper support pattern (TS) may be located at different levels, but the height difference may be within about 10 Å. The third part (650) of the upper support pattern (TS), described with reference to FIGS. 1 and 2, may be omitted, and the upper support pattern (TS) may include only the first part (610) and the second part (630) connected thereto.

[0039] FIG. 4 is a cross-sectional view for illustrating a semiconductor device according to embodiments of the present invention, corresponding to the cross-section obtained by cutting FIG. 1 along the line AA'. Hereinafter, for convenience of explanation, descriptions of matters substantially identical to those described with reference to FIG. 1 and FIG. 2 are omitted, and the differences are described in detail.

[0040] Referring to FIGS. 1 and 4, the width of the third portion (650) of the upper support pattern (TS) spaced apart from each of the through holes (PH) may be greater than the upper width of each of the lower electrodes (BE). The sidewalls of the third portion (650) of the upper support pattern (TS) may be spaced apart from each other and may not be aligned with the outer wall (OSW) of each of the lower electrodes (BE). The lower surface (650b) of the third portion (650) of the upper support pattern (TS) may be in contact with the upper surface (BEt) of each of the lower electrodes (BE) and may extend horizontally from the upper surface (BEt) of each of the lower electrodes (BE). The sidewalls of the dielectric film (DL) and the sidewalls of the upper electrode (TE) adjacent to the third portion (650) of the upper support pattern (TS) may have a step.

[0042] FIGS. 5 to 10 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, each corresponding to a cross-section obtained by cutting FIG. 1 along the line AA'. Hereinafter, with reference to FIGS. 5 to 10 and again to FIGS. 1 and FIGS. 2, a method for manufacturing a semiconductor device according to embodiments of the present invention will be described in detail.

[0043] Referring to FIG. 5, a substrate (10) may be provided. An interlayer insulating film (12) may be formed on the substrate (10). Conductive contacts (14) may be formed within the interlayer insulating film (12). An etch stop film (420L) may be formed on the substrate (10). The etch stop film (420L) may cover the upper surface of the interlayer insulating film (12) and the upper surfaces of the conductive contacts (14).

[0044] A mold structure (20) may be formed on an etch stop layer (420L). The mold structure (20) may include mold layers and support layers that are alternately and repeatedly stacked. Forming the mold structure (20) may include, for example, stacking a first mold layer (21), a lower support layer (22), a second mold layer (23), an intermediate support layer (24), a third mold layer (25), and a preliminary upper support layer (26) in sequence on the etch stop layer (420L). The lower support layer (22) may be formed of a material having etch selectivity for the first mold layer (21) and the second mold layer (23). The intermediate support layer (24) may be formed of a material having etch selectivity for the second mold layer (23) and the third mold layer (25). The preliminary upper support layer (26) may be formed of a material having etch selectivity with respect to the third mold layer (25). Each of the first to third mold layers (21, 23, 25) may have a single layer structure or a multilayer structure including multiple different insulating layers. The lower support layer (22), the intermediate support layer (24), and the preliminary upper support layer (26) may include, for example, at least one of silicon nitride, SiBN, or SiCN.

[0045] Referring to FIGS. 5 and 6, a plurality of conductive contact holes (CH) can be formed penetrating the mold structure (20) and the etch stop layer (420L). Forming the conductive contact holes (CH) may include forming a mask pattern on a preliminary upper support layer (26) and anisotropically etching the mold structure (20) and the etch stop layer (420L) using the mask pattern as a mask. The conductive contact holes (CH) can penetrate the mold structure (20) and the etch stop layer (420L) in a third direction (D3) and expose the upper surfaces of the conductive contacts (14). Subsequently, a portion of the etch stop layer (420L) that remains unetched may be referred to as an etch stop pattern (420).

[0046] Referring to FIG. 7, a lower electrode film (30) filling the conductive contact holes (CH) can be formed on the mold structure (20). The lower electrode film (30) can cover the exposed upper surfaces of the conductive contacts (14) and the preliminary upper support film (26).

[0047] As the aspect ratio of the conductive contact holes (CH) increases, the entrance of the conductive contact holes (CH) is blocked before the lower electrode film (30) completely fills the conductive contact holes (CH), and accordingly, a seam (S) can be formed inside each of the conductive contact holes (CH). The lower electrode film (30) may be formed from at least one of, for example, a metal material (e.g., cobalt, titanium, nickel, tungsten and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaAlN) and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru) and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo) or a metal silicide.

[0048] Referring to FIGS. 7 and 8, a portion of the lower electrode film (30) may be removed, thereby forming lower electrodes (BE). Recesses (RC) may be defined by the side walls of the preliminary upper support film (26) and the upper surface (BEt) of each of the lower electrodes (BE). The core (S) inside each of the conductive contact holes (CH) may be connected to each of the recesses (RC). In other words, the inner wall of the lower electrodes (BE) may be exposed by the recesses (RC).

[0049] The upper surface (BEt) of each lower electrode (BE) exposed by the recesses (RC) may be located at a lower level than the lower surface (26b) of the preliminary upper support film (26). The upper surface (BEt) of each lower electrode (BE) may be located at a higher level than the upper surface of the intermediate support film (24). The height difference (HD) between the upper surface (BEt) of each lower electrode (BE) and the lower surface (26b) of the preliminary upper support film (26) may be, for example, about 10 Å to about 150 Å.

[0050] Referring to FIGS. 8 and 9, an upper support film (27) can be formed to fill each of the core (S) and recessed portions (RC) inside each of the conductive contact holes (CH). Each of the core (S) and recessed portions (RC) inside each of the conductive contact holes (CH) can be filled with the same material as the preliminary upper support film (26).

[0051] Referring to FIGS. 9 and 10, through holes (PH) penetrating the mold structure (20) may be formed. The outer wall of some of the lower electrodes (BE) and the upper surface of the etching stop pattern (420) may be exposed by the through holes (PH). After the through holes (PH) are formed, parts of the lower support film (22), intermediate support film (24), and upper support film (27) that remain unetched may be referred to as the lower support pattern (BS), intermediate support pattern (MS), and upper support pattern (TS), respectively. The first to third mold films (21, 23, 25) exposed by the through holes (PH) may be removed by an isotropic etching process (e.g., a wet etching process using phosphoric acid (H3PO4)), whereby the lower support pattern (BS), intermediate support pattern (MS), and upper support pattern (TS) may not be removed.

[0052] Referring again to FIGS. 1 and 2, a dielectric film (DL) can be formed conformally covering the upper and lower surfaces of the lower support pattern (BS), the upper and lower surfaces of the intermediate support pattern (BS), the upper and lower surfaces and sidewalls of the upper support pattern (TS), the upper surface of the etching stop pattern (420), and the outer wall (OSW) of each of the lower electrodes (BE). The dielectric film (DL) can be formed through a deposition technique with excellent step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0053] An upper electrode (TE) may be formed on the dielectric film (DL). The upper electrode (TE) may completely fill the through holes (PH) and cover the upper surface of the upper support pattern (TS). The upper electrode (TE) may cover at least a portion of the upper surface of some of the lower electrodes (BE). The upper electrode (TE) may fill the interior of each of the through holes (PH), between the etch stop pattern (420) and the lower support pattern (BS), between the lower support pattern (BS) and the intermediate support pattern (MS), and between the intermediate support pattern (MS) and the upper support pattern (TS).

[0055] FIG. 11 is a block diagram for explaining a semiconductor device according to embodiments of the present invention. FIG. 12 is an enlarged view for explaining a part of a cell block of a semiconductor device according to embodiments of the present invention, corresponding to part P1 of FIG. 11. FIG. 13 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, corresponding to the cross-section of FIG. 12 cut along the line AA'.

[0056] Referring to FIG. 11, the semiconductor device may include cell blocks (CB) and a surrounding block (PB) that surrounds each of the cell blocks (CB). The semiconductor device may be a memory device, and each of the cell blocks (CB) may include a cell circuit such as a memory integrated circuit. The cell blocks (CB) may be spaced apart from each other in a first direction (D1) and a second direction (D2) that intersects (e.g., orthogonal) the first direction (D1).

[0057] The peripheral block (PB) may include various peripheral circuits necessary for the operation of the cell circuit, and the peripheral circuits may be electrically connected to the cell circuit. The peripheral block (PB) may include sense amplifier circuits (SA) and sub-word line driver circuits (SWD). For example, the sense amplifier circuits (SA) may face each other with cell blocks (CB) in between, and the sub-word line driver circuits (SWD) may face each other with cell blocks (CB) in between. The peripheral block (PB) may further include power supply and ground driver circuits for driving the sense amplifier, but the concept of the present invention is not limited thereto.

[0058] Referring to FIGS. 12 and 13, a substrate (10) including a cell region may be provided. The cell region may be a region of the substrate (10) in which each of the cell blocks (CB) of FIG. 11 is provided. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0059] Active patterns (ACTs) may be provided on the cell region of the substrate (10). In a planar view, the active patterns (ACTs) may be spaced apart from each other along a first direction (D1) and a second direction (D2). The active patterns (ACTs) may have a bar shape extending in a fourth direction (D4) that is parallel to the upper surface of the substrate (10) and intersects the first direction (D1) and the second direction (D2). Any end of one of the active patterns (ACTs) may be arranged to be adjacent to the center of another active pattern (ACT) immediately adjacent in the second direction (D2). Each of the active patterns (ACTs) may be a part of the substrate (10) protruding from the substrate (10) along a third direction (D3).

[0060] A device isolation layer (120) may be provided between active patterns (ACTs). The device isolation layer (120) may be provided within the substrate (10) to define the active patterns (ACTs). The device isolation layer (120) may comprise, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0061] Word lines (WL) may be provided within the substrate (10) and may cross the active patterns (ACT) and the device isolation layer (120). Word lines (WL) may be provided within grooves formed in the active patterns (ACT) and the device isolation layer (120). Word lines (WL) may extend in a second direction (D2) and be spaced apart from each other along a first direction (D1). Word lines (WL) may be embedded within the substrate (10).

[0062] Impurity regions may be provided within active patterns (ACTs). The impurity regions may include first impurity regions (110a) and second impurity regions (110b). The second impurity regions (110b) may be provided adjacent to each of the two ends within each active pattern (ACT). Each of the first impurity regions (110a) may be provided between the second impurity regions (110b) within each active pattern (ACT). The first impurity regions (110a) may contain impurities of the same conductivity type (e.g., N-type) as the second impurity regions (110b).

[0063] A buffer pattern (305) may be provided on a cell region of the substrate (10). The buffer pattern (305) may cover active patterns (ACT), device isolation films (120), and word lines (WL). The buffer pattern (305) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0064] Bit lines (BL) may be provided on a substrate (10). The bit lines (BL) may extend along a first direction (D1) and may be spaced apart from each other along a second direction (D2). Each of the bit lines (BL) may include a first ohmic pattern (331) and a metal-containing pattern (330) stacked in turn. For example, the first ohmic pattern (331) may include a metal silicide. For example, the metal-containing pattern (330) may include a metal (tungsten, titanium, tantalum, etc.).

[0065] Polysilicon patterns (310) can be interposed between bit lines (BL) and buffer patterns (305).

[0066] Bit line contacts (DC) may be interposed between bit lines (BL) and first impurity regions (110a), respectively. Bit lines (BL) may be electrically connected to the first impurity regions (110a) by the bit line contacts (DC). The bit line contacts (DC) may comprise polysilicon that is impurity-doped or undoped.

[0067] Bit line contacts (DC) may be provided within a recess region (RE). The recess region (RE) may be provided above the first impurity regions (110a) and above the adjacent device isolation film (120). The first buried insulation pattern (314) and the second buried insulation pattern (315) may fill the remainder within the recess region (RE).

[0068] A bit line capping pattern (350) may be provided on the upper surface of each of the bit lines (BL). The bit line capping pattern (350) may extend along a first direction (D1) on each of the bit lines (BL) and may be spaced apart from adjacent bit line capping patterns (350) along a second direction (D2). The bit line capping pattern (350) may include a first bit line capping pattern (351), a second bit line capping pattern (352), and a third bit line capping pattern (353). The bit line capping pattern (350) may include silicon nitride. For example, the first bit line capping pattern (351), the second bit line capping pattern (352), and the third bit line capping pattern (353) may include silicon nitride.

[0069] Each sidewall of the polysilicon patterns (310), each upper sidewall of the bit line contacts (DC), each sidewall of the bit lines (BL), and the sidewall of the bit line capping pattern (350) may be covered by a bit line spacer (SP). The bit line spacer (SP) may extend along a first direction (D1) on each of the bit lines (BL).

[0070] The bit line spacer (SP) may include a first sub-spacer (321) and a second sub-spacer (325) spaced apart from each other. For example, the first sub-spacer (321) and the second sub-spacer (325) may be spaced apart by an air gap (AG). The first sub-spacer (321) may be in contact with each sidewall of the bit lines (BL) and may extend over the sidewall of the bit line capping pattern (350). The second sub-spacer (325) may be provided along the sidewall of the first sub-spacer (321). The first sub-spacer (321) and the second sub-spacer (325) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride and may have a single-layer or multi-layer structure. The first sub-spacer (321) and the second sub-spacer (325) may include the same material.

[0071] The fourth capping pattern (360) can cover the side wall of the first sub-spacer (321) and extend to the upper surface of the second sub-spacer (325). The fourth capping pattern (360) can further cover the air gap (AG).

[0072] Storage node contacts (BC) may be interposed between adjacent bit lines (BL) on the substrate (10). Bit line spacers (SP) may be interposed between the storage node contacts (BC) and the adjacent bit lines (BL). The storage node contacts (BC) may be spaced apart from each other in a first direction (D1) and a second direction (D2). Each of the storage node contacts (BC) may be electrically connected to a corresponding one of the second impurity regions (110b). The storage node contacts (BC) may comprise polysilicon that is impurity-doped or undoped.

[0073] A second ohmic pattern (341) may be provided on each of the storage node contacts (BC). The second ohmic pattern (341) may include a metal silicide.

[0074] The diffusion prevention pattern (342) may conformally cover the second ohmic pattern (341), the bit line spacer (SP), and the bit line capping pattern (350). The diffusion prevention pattern (342) may include a metal nitride such as titanium nitride or tantalum nitride. The second ohmic pattern (341) may be interposed between the diffusion prevention pattern (342) and each of the storage node contacts (BC).

[0075] Landing pads (LP) may be provided on each of the storage node contacts (BC). Each of the landing pads (LP) may be electrically connected to a corresponding one of the storage node contacts (BC). The landing pads (LP) may comprise a metal-containing material such as tungsten. The upper portion of the landing pads (LP) may be shifted in a second direction (D2) from the storage node contacts (BC). In a planar view, the landing pads (LP) may be spaced apart from each other in a first direction (D1) and a second direction (D2). For example, the landing pads (LP) may be spaced apart from each other in a zigzag pattern in the first direction (D1) and the second direction (D2). The landing pads (LP) may correspond to the conductive contacts (14) of FIG. 2.

[0076] A filling pattern (400) may wrap around each of the landing pads (LP). The filling pattern (400) may be interposed between adjacent landing pads (LP). For example, the filling pattern (400) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. As another example, the filling pattern (400) may be an empty space. The filling pattern (400) may correspond to the interlayer insulating film (12) of FIG. 2.

[0077] An etch-stopping pattern (420) may be provided on the filling pattern (400). The etch-stopping pattern (420) may expose the upper surfaces of the landing pads (LP), and lower electrodes (BE) may be provided on each of the upper surfaces of the landing pads (LP). Each of the lower electrodes (BE) may be electrically connected to a corresponding one of the landing pads (LP).

[0078] A support pattern may be provided on a substrate (10). The support pattern may include a lower support pattern (BS), an intermediate support pattern (MS), and an upper support pattern (TS) spaced apart from each other in a third direction (D3). In a planar view, the support pattern may be interposed between any one of the lower electrodes (BE) and an adjacent lower electrode (BE). An upper electrode (TE) may cover the lower electrodes (BE) and the support pattern. A dielectric film (DL) may be interposed between the lower electrodes (BE) and the upper electrode (TE) and between the support pattern and the upper electrode (TE). The lower electrodes (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CAP).

[0079] The description of the etching prevention pattern (420), lower electrodes (BE), lower support pattern (BS), intermediate support pattern (MS), upper support pattern (TS), dielectric film (DL), and upper electrode (TE) may be substantially the same as described above with reference to FIGS. 1 and FIGS. 2.

[0081] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: lower electrodes on a substrate; a lower support pattern provided between the lower electrodes; an upper support pattern on the lower electrodes; an upper electrode covering the lower electrodes, the lower support pattern, and the upper support pattern; and a dielectric film interposed between the lower electrodes and the upper electrode, between the lower support pattern and the upper electrode, and between the upper support pattern and the upper electrode, wherein the upper support pattern comprises a first portion on the upper surfaces of the lower electrodes and a second portion filling the internal space of each of the lower electrodes, and the second portion overlapping the lower support pattern in a horizontal direction. Claim 2 A semiconductor device according to claim 1, wherein the upper support pattern further comprises a third portion between the first portion and the second portion, the side wall of the third portion being aligned with the outer wall of each of the lower electrodes. Claim 3 In claim 2, the width of the third part is smaller than or equal to the upper width of each of the lower electrodes. Claim 4 In claim 2, the upper surfaces of the lower electrodes are located at a lower level than the lower surface of the first part, in a semiconductor device. Claim 5 In claim 2, the thickness of the third part is smaller than the thickness of the first part of the semiconductor device. Claim 6 A semiconductor device according to claim 1, wherein the upper surfaces of the lower electrodes and the lower surface of the first part are located at the same level. Claim 7 A semiconductor device according to claim 1, wherein the upper support pattern further comprises a third portion between the first portion and the second portion, the side wall of the third portion being spaced apart from the outer wall of each of the lower electrodes. Claim 8 In claim 7, a semiconductor device in which the width of the third part is greater than the upper width of each of the lower electrodes. Claim 9 In claim 1, the second portion is a semiconductor device whose width increases and then decreases as it moves away from the substrate. Claim 10 delete

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