Semiconductor package

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure; a second redistribution structure disposed on the molding layer and the first semiconductor device and including a second redistribution insulating layer and a second redistribution pattern; vertical connecting conductors disposed within the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the second redistribution structure, with a portion of which is vertically superimposed with the first semiconductor device; a heat dissipation pad structure in contact with the upper surface of the first semiconductor device; and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device in a first lateral direction.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor package. Background Technology

[0002] Due to the rapid development of the electronics industry and user demands, electronic devices are becoming increasingly smaller, multifunctional, and high-capacity. Accordingly, semiconductor packages containing multiple semiconductor chips are required. For example, methods may be used to mount various types of semiconductor chips side by side on a single package substrate, or to stack semiconductor chips and / or packages on a single package substrate. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor package including a plurality of semiconductor devices. means of solving the problem

[0004] To solve the above-mentioned problem, the technical concept of the present invention provides a semiconductor package comprising: a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure; a second redistribution structure disposed on the molding layer and the first semiconductor device and including a second redistribution insulating layer and a second redistribution pattern; vertical connecting conductors disposed within the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the second redistribution structure, with a portion of which is vertically superimposed with the first semiconductor device; a heat dissipation pad structure in contact with the upper surface of the first semiconductor device; and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device in a first lateral direction.

[0005] To solve the above-mentioned problem, the technical concept of the present invention provides a semiconductor package comprising: a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure and not covering the upper surface of the first semiconductor device; vertical connecting conductors disposed within the molding layer and electrically connected to the first redistribution pattern; a second semiconductor device disposed on the molding layer and electrically connected to the first redistribution pattern through the vertical connecting conductors; and a heat dissipation plate attached to the upper surface of the first semiconductor device and overlapped with the second semiconductor device in a first lateral direction.

[0006] To solve the aforementioned problem, the technical concept of the present invention comprises: a first redistribution structure including a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; chip connection bumps disposed between the first semiconductor device and the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure and having an upper surface coplanar with the upper surface of the first semiconductor device; a second redistribution structure disposed on the molding layer and the first semiconductor device and including a second redistribution insulating layer and a second redistribution pattern; vertical connection conductors vertically penetrating the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the second redistribution structure; and a heat dissipation pad structure disposed within the second redistribution insulating layer and in contact with the upper surface of the first semiconductor device. A semiconductor package is provided comprising: a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device in a first side direction; wherein the first semiconductor device comprises a logic chip and the second semiconductor device comprises a memory chip, and the heat dissipation plate is thermally coupled to the first semiconductor device through the heat dissipation pad structure, and a part of the first semiconductor device is vertically overlapped with the second semiconductor device and another part of the first semiconductor device is vertically overlapped with the heat dissipation plate, and the ratio between the total length of the first semiconductor device along the first side direction and the length of the part of the first semiconductor device vertically overlapped with the second semiconductor device along the first side direction is between 10% and 45%. Effects of the invention

[0007] According to exemplary embodiments of the present invention, a portion of the lower semiconductor device of the lower package is vertically overlapped with the upper semiconductor device, and another portion of the lower semiconductor device is thermally coupled with a heat dissipation plate, thereby providing a semiconductor package with improved heat dissipation characteristics while miniaturizing the footprint. Brief explanation of the drawing

[0008] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Figure 2 is a layout diagram of the main configuration of the semiconductor package of Figure 1. FIGS. 3a to 3h are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. FIG. 4 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 5 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 7 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 8 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 9 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 10 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 11 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 12 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. FIG. 13 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0010] FIG. 1 is a cross-sectional view showing a semiconductor package (10) according to exemplary embodiments of the present invention. FIG. 2 is a layout diagram of the main components of the semiconductor package (10) of FIG. 1.

[0011] Referring to FIGS. 1 and FIGS. 2, the semiconductor package (10) may include a lower package (LP1) and an upper package (UP). The semiconductor package (10) may be a package-on-package type package in which the upper package (UP) is stacked or attached on the lower package (LP1).

[0012] The lower package (LP1) may include a first redistribution structure (110), a first lower semiconductor device (120), a molding layer (151), vertical connecting conductors (155), a second redistribution structure (160), and a heat dissipation pad structure (171). The lower package (LP1) may be a fan-out structure package. The footprint of the first redistribution structure (110) may be larger than the footprint of the first lower semiconductor device (120). The footprint of the first redistribution structure (110) may be the same as the footprint of the semiconductor package (10).

[0013] The first redistribution structure (110) may be a package substrate for mounting a mounting component, such as a first lower semiconductor device (120). The first redistribution structure (110) may generally have a flat plate shape or a panel shape. The first redistribution structure (110) may include an upper surface and a lower surface opposite each other, and the upper surface and the lower surface of the first redistribution structure (110) may each be generally flat. In the following, the horizontal direction (e.g., X direction and / or Y direction) may be defined as a direction parallel to the upper surface or lower surface of the first redistribution structure (110), the vertical direction (e.g., Z direction) may be defined as a direction perpendicular to the upper surface or lower surface of the first redistribution structure (110), and the horizontal width may be defined as a length along the horizontal direction (e.g., X direction and / or Y direction).

[0014] The first redistribution structure (110) may include a plurality of first redistribution insulating layers (111) and a first conductive redistribution pattern (113).

[0015] A plurality of first redistribution insulating layers (111) may be stacked together in a vertical direction (e.g., Z direction). A plurality of first redistribution insulating layers (111) may be formed from an insulating polymer, epoxy, or a combination thereof. For example, a plurality of first redistribution insulating layers (111) may each be formed from a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI).

[0016] The first conductive redistribution pattern (113) may include first conductive layers (1131), first conductive via patterns (1133), and external connection pads (1135). Each of the first conductive layers (1131) may extend in a horizontal direction (e.g., X direction and / or Y direction) and be arranged at different vertical levels to form a multilayer structure. The first conductive layers (1131) may be placed on either the upper or lower surface of each of the plurality of first redistribution insulating layers (111). For example, the first conductive layers (1131) may include a line pattern extending in a line shape along either the upper or lower surface of any one of the first redistribution insulating layers (111) among the plurality of first redistribution insulating layers (111). A first conductive layer (1131) provided on the uppermost insulating layer among a plurality of first redistribution insulating layers (111) may include pads to which first chip connection bumps (143) are attached and pads to which vertical connection conductors (155) are attached. The first conductive via patterns (1133) may extend in a vertical direction (e.g., Z direction) through at least one layer among the plurality of first redistribution insulating layers (111). The first conductive via patterns (1133) may electrically connect the first conductive layers (1131) arranged at different vertical levels or electrically connect the first conductive layer (1131) and the external connection pad (1135). The external connection pads (1135) are placed on the lower surface of the first redistribution structure (110) and may be in contact with the external connection terminal (141). The external connection pads (1135) can be electrically connected to the first lower semiconductor device (120) and / or vertical connection conductors (155) through the first conductive redistribution pattern (113). In exemplary embodiments, when viewed in cross-section, the external connection pads (1135) may have a rectangular shape.

[0017] For example, the first conductive redistribution pattern (113) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof.

[0018] At least some of the plurality of first conductive layers (1131) may be formed together to form an integral part with some of the plurality of first conductive via patterns (1133). For example, some of the plurality of first conductive layers (1131) may be formed together to form an integral part with the corresponding first conductive via pattern (1133) that contacts the lower side thereof. For example, the first conductive layers (1131) and the first conductive via patterns (1133) connected to each other may be formed together through an electroplating process.

[0019] In exemplary embodiments, each of the plurality of first conductive via patterns (1133) may have a tapered shape in which the horizontal width narrows and extends from the upper side toward the lower side. The horizontal width of each of the plurality of first conductive via patterns (1133) may gradually decrease as it approaches the upper surface of the external connection pad (1135).

[0020] A seed metal layer (115) may be disposed on the surface of the first conductive layer (1131) and the surface of the first conductive via pattern (1133). For example, the seed metal layer (115) may be disposed between the bottom surface of the first conductive layer (1131) and the first redistribution insulating layer (111), and between the sidewall and bottom surface of the second conductive via pattern (1633) and the first redistribution insulating layer (111). Additionally, the seed metal layer (115) may be disposed between the first conductive via pattern (1133) and the external connection pad (1135). Additionally, the seed metal layer (115) may be disposed between the external connection pad (1135) and the external connection terminal (141) and may extend along the lower surface of the external connection pad (1135). For example, the seed metal layer (115) may include at least one of copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), and aluminum (Al). For example, the seed metal layer (115) may be formed through a physical vapor deposition process such as sputtering.

[0021] In exemplary embodiments, the external connection pad (1135) may have a rectangular shape when viewed in cross-section. In exemplary embodiments, the lower surface of the external connection pad (1135) may be generally coplanar with the lower surface of the first redistribution insulating layer (111). For example, the external connection pad (1135) may be formed through an electroplating process. In exemplary embodiments, the external connection pad (1135) may include a plurality of metal layers stacked in a vertical direction (e.g., Z direction).

[0022] External connection terminals (141) may be attached to the external connection pads (1135) of the first rewiring structure (110). The external connection terminals (141) may be configured to electrically and physically connect the first rewiring structure (110) and an external device. The external connection terminals (141) may be formed, for example, from a solder ball or a solder bump.

[0023] One or more passive components (149) may be attached to the lower side of the first redistribution structure (110). The passive components (149) may be attached to the lower side of the first redistribution structure (110) through a bump made of solder.

[0024] The first redistribution structure (110) may include a first region (R1) and a second region (R2) that are spaced apart from each other. The first region (R1) and the second region (R2) may be regions provided on the upper surface of the first redistribution structure (110) and may be spaced apart from each other in a horizontal direction (e.g., X direction and / or Y direction).

[0025] The first lower semiconductor device (120) may be mounted on the first region (R1) of the first redistribution structure (110). The first region (R1) of the first redistribution structure (110) is a region that is vertically superimposed with the first lower semiconductor device (120), and the footprint of the first redistribution structure (110) may be substantially the same as the footprint of the first lower semiconductor device (120).

[0026] The first lower semiconductor device (120) can be electrically and physically connected to the first conductive redistribution pattern (113) of the first redistribution structure (110) through the first chip connection bumps (143). The first chip connection bumps (143) can each be disposed between the first lower semiconductor device (120) and the first conductive layer (1131) provided on the uppermost insulating layer of the first redistribution insulating layer (111). The first chip connection bumps (143) may include solder bumps.

[0027] In exemplary embodiments, the first lower semiconductor device (120) may have a three-dimensional stacked structure comprising a plurality of semiconductor chips stacked together in a vertical direction (e.g., Z direction). For example, the first lower semiconductor device (120) may include a lower semiconductor chip (121) and an upper semiconductor chip (123) on the lower semiconductor chip (121). The lower semiconductor chip (121) may include a lower semiconductor substrate (1211), lower connection pads (1213) provided on the lower side of the lower semiconductor substrate (1211) and in contact with the first chip connection bumps (143), and upper connection pads (1215) provided on the upper side of the lower semiconductor substrate (1211). The lower semiconductor chip (121) may further include through electrodes that penetrate the lower semiconductor substrate (1211) and electrically connect the lower connection pads (1213) and the upper connection pads (1215). The upper semiconductor chip (123) may include an upper semiconductor substrate (1231) and lower connection pads (1233) provided on the lower side of the upper semiconductor substrate (1231). The upper connection pads (1215) of the lower semiconductor chip (121) may be electrically and physically connected to the lower connection pads (1233) of the upper semiconductor chip (123) through inter-chip connection bumps (125). A gap-fill insulating layer (127) surrounding the sidewalls of the inter-chip connection bumps (125) may be disposed between the lower semiconductor chip (121) and the upper semiconductor chip (123). The gap-fill insulating layer (127) may be formed from, for example, a non-conductive film (NCF).

[0028] The lower semiconductor substrate (1211) and the upper semiconductor substrate (1231) may be formed from a semiconductor wafer. The lower semiconductor substrate (1211) and the upper semiconductor substrate (1231) may include, for example, silicon (Si). Alternatively, the lower semiconductor substrate (1211) and the upper semiconductor substrate (1231) may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The lower semiconductor substrate (1211) and the upper semiconductor substrate (1231) may include a conductive region, for example, an impurity-doped well, or an impurity-doped structure. The lower semiconductor chip (121) may include a semiconductor element layer provided within and / or on the active surface of the lower semiconductor substrate (1211) (e.g., the lower surface of the lower semiconductor substrate (1211)), and the upper semiconductor chip (123) may include a semiconductor element layer provided within and / or on the active surface of the upper semiconductor substrate (1231) (e.g., the lower surface of the upper semiconductor substrate (1231)). The semiconductor element layer of the lower semiconductor chip (121) and the semiconductor element layer of the upper semiconductor chip (123) may each include individual elements. The individual elements may include, for example, transistors. The individual elements may include microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a large-scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active element, a passive element, etc.

[0029] In exemplary embodiments, the first lower semiconductor device (120) may include three or more semiconductor chips stacked in a vertical direction (e.g., Z direction) or may be composed of a single semiconductor chip.

[0030] A molding layer (151) may be disposed on a first rewiring structure (110). The molding layer (151) may cover at least a portion of the first lower semiconductor device (120) and the upper surface of the first rewiring structure (110). The molding layer (151) may extend along the side wall of the first lower semiconductor device (120) and surround the side wall of the first lower semiconductor device (120). The molding layer (151) may not cover the upper surface (129) of the first lower semiconductor device (120). The upper surface (129) of the first lower semiconductor device (120) may be the upper surface of the upper semiconductor chip (123). In exemplary embodiments, the upper surface (1511) of the molding layer (151) may be coplanar with the upper surface (129) of the first lower semiconductor device (120). Furthermore, the molding layer (151) can fill the gap between the first lower semiconductor device (120) and the first redistribution structure (110) and can surround the side walls of the first chip connection bumps (143).

[0031] For example, the molding layer (151) may include an epoxy-based molding resin or a polyimide-based molding resin, etc. In exemplary embodiments, the molding layer (151) may include an epoxy molding compound.

[0032] Vertical connecting conductors (155) may be placed on a second region (R2) of a first redistribution structure (110). The vertical connecting conductors (155) may be configured to electrically connect a first conductive redistribution pattern (113) of the first redistribution structure (110) and a second conductive redistribution pattern (163) of the second redistribution structure (160). The vertical connecting conductors (155) may penetrate the molding layer (151) in a vertical direction (e.g., Z direction). The lower portion of each of the vertical connecting conductors (155) may be in direct contact with a first conductive layer (1131) provided on the uppermost insulating layer of the first redistribution insulating layer (111), and the upper portion of each of the vertical connecting conductors (155) may be in direct contact with a second conductive redistribution pattern (163). In exemplary embodiments, the upper surfaces of the vertical connecting conductors (155) may be coplanar with the upper surface (1511) of the molding layer (151). The vertical connecting conductors (155) may include, for example, copper (Cu).

[0033] A second redistribution structure (160) may be disposed on a molding layer (151) and a first lower semiconductor device (120). The second redistribution structure (160) may at least partially cover the upper surface (1511) of the molding layer (151) and may partially cover the upper surface (129) of the first lower semiconductor device (120). In exemplary embodiments, the footprint of the second redistribution structure (160) may be the same as the footprint of the first redistribution structure (160). In exemplary embodiments, one side wall of the second redistribution structure (160) may be aligned perpendicularly (e.g., in the Z direction) to the corresponding side wall of the molding layer (151) and the corresponding side wall of the second redistribution structure (110).

[0034] The second redistribution structure (160) may include a plurality of second redistribution insulating layers (161) and a second conductive redistribution pattern (163).

[0035] A plurality of second redistribution insulating layers (161) may be stacked together in a vertical direction (e.g., Z direction). A plurality of second redistribution insulating layers (161) may be formed from an insulating polymer, epoxy, or a combination thereof. For example, a plurality of second redistribution insulating layers (161) may each be formed from PID or PSPI.

[0036] The second conductive redistribution pattern (163) may include second conductive layers (1631) and second conductive via patterns (1633). The second conductive layers (1631) may be disposed on either the upper or lower surface of any one of the second redistribution insulating layers (161) among the plurality of second redistribution insulating layers (161). The second conductive layers (1631) may be disposed at different vertical levels to form a multilayer structure. For example, the second conductive layers (1631) may include a line pattern extending in a line shape along the upper or lower surface of any one of the plurality of second redistribution insulating layers (161). The second conductive layer (1631) provided on the uppermost insulating layer among the plurality of second redistribution insulating layers (161) may include pads to which connection terminals (183) are attached. The second conductive layer (1631) at the bottom of the second conductive layers (1631) may include pads attached to vertical connecting conductors (155). The second conductive via patterns (1633) may extend in a vertical direction (e.g., Z direction) through at least one insulating layer of the plurality of second redistribution insulating layers (161). The second conductive via patterns (1633) may electrically connect the second conductive layers (1631) placed at different vertical levels or electrically connect the second conductive layer (1631) and the vertical connecting conductor (155). For example, the second conductive redistribution pattern (163) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof.

[0037] At least some of the plurality of second conductive layers (1631) may be formed together to form an integral part with some of the plurality of second conductive via patterns (1633). For example, some of the plurality of second conductive layers (1631) may be formed together to form an integral part with the corresponding second conductive via pattern (1633) that contacts the lower side thereof. For example, the second conductive layers (1631) and the second conductive via patterns (1633) connected to each other may be formed together through an electroplating process. A seed metal layer (165) may be disposed on the surface of the second conductive layer (1631) and the surface of the second conductive via pattern (1633). For example, the seed metal layer (165) may be disposed between the bottom surface of the second conductive layer (1631) and the second redistribution insulating layer (161), and between the sidewall and bottom surface of the second conductive via pattern (1633) and the second redistribution insulating layer (161), respectively. For example, the seed metal layer (165) may include at least one of copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), and aluminum (Al).

[0038] In exemplary embodiments, each of the plurality of second conductive via patterns (1633) may have a tapered shape that extends with a horizontal width that narrows from the upper side toward the lower side. In other words, the horizontal width of each of the plurality of second conductive via patterns (1633) may gradually decrease as it approaches the upper surface (1511) of the molding layer (151) or the upper surface of the vertical connecting conductor (155).

[0039] The heat dissipation pad structure (171) may contact the upper surface (129) of the first lower semiconductor device (120). The heat dissipation pad structure (171) may be thermally coupled to the first lower semiconductor device (120), but may not be electrically connected to the first lower semiconductor device (120), the second conductive redistribution pattern (163), and the vertical connecting conductors (155). The heat dissipation pad structure (171) may vertically penetrate the second redistribution insulating layer (161) of the second redistribution insulating layer (161) and directly contact the upper surface (129) of the first lower semiconductor device (120). The heat dissipation pad structure (171) may extend along a portion of the upper surface (129) of the first lower semiconductor device (120) and may cover a portion of the upper surface (129) of the first lower semiconductor device (120). For example, a portion of the upper surface (129) of the first lower semiconductor device (120) may be in direct contact with the heat dissipation pad structure (171), and another portion of the upper surface (129) of the first lower semiconductor device (120) may be in direct contact with the second redistribution insulating layer (161).

[0040] In exemplary embodiments, the heat dissipation pad structure (171) is disposed within a through hole of the second redistribution insulation layer (161) of the second redistribution structure (160) and can at least partially fill the through hole of the second redistribution insulation layer (161) of the second redistribution structure (160). For example, the heat dissipation pad structure (171) can completely fill the through hole of the second redistribution insulation layer (161) and can extend from the lower surface to the upper surface of the second redistribution insulation layer (161).

[0041] The heat dissipation pad structure (171) may include a material with excellent thermal conductivity, for example, a metal. In exemplary embodiments, the heat dissipation pad structure (171) may include copper (Cu), aluminum (Al), etc. The heat dissipation pad structure (171) may function to transfer heat generated from the first lower semiconductor device (120) to the outside of the semiconductor package (10) and / or to the heat dissipation plate (185). In exemplary embodiments, the heat dissipation pad structure (171) may be formed together with the second conductive redistribution pattern (163) of the second redistribution structure (160) through the same metal wiring process. In this case, the material and / or material composition of the heat dissipation pad structure (171) may be substantially the same as the material and / or material composition of the second conductive redistribution pattern (163). In exemplary embodiments, the heat dissipation pad structure (171) may be formed through a process different from the formation process of the second conductive redistribution pattern (163) of the second redistribution structure (160). In exemplary embodiments, the material and / or material composition of the heat dissipation pad structure (171) may be different from the material and / or material composition of the second conductive redistribution pattern (163).

[0042] An upper package (UP) may be disposed on a second redistribution structure (160). The upper package (UP) may include at least one upper semiconductor device (181) disposed on the second redistribution structure (160). The upper semiconductor device (181) may include a semiconductor chip and / or a package containing the semiconductor chip. For example, the upper semiconductor device (181) may include a semiconductor substrate (1811) and chip pads (1813). The chip pads (1813) of the upper semiconductor device (181) may be electrically and physically connected to a second conductive redistribution pattern (163) of the second redistribution structure (160) through connection terminals (183).

[0043] In exemplary embodiments, the first lower semiconductor device (120) and the upper semiconductor device (181) may include different types of semiconductor chips and may be electrically connected to each other through the first conductive redistribution pattern (113) of the first redistribution structure (110), vertical connecting conductors (155), and the second conductive redistribution pattern (163) of the second redistribution structure (160). The first lower semiconductor device (120) and the upper semiconductor device (181) may include memory chips, logic chips, System On Chip (SOC), Power Management Integrated Circuit (PMIC) chips, Radio Frequency Integrated Circuit (RFIC) chips, etc. The memory chips may include DRAM chips, SRAM chips, MRAM chips, NAND flash memory chips and / or High Bandwidth Memory (HBM) chips. The logic chip may include an Application Processor (AP), a microprocessor, a Central Processing Unit (CPU), a controller, and / or an Application Specific Integrated Circuit (ASIC). For example, the SOC may include at least two circuits among a logic circuit, a memory circuit, a digital integrated circuit (IC), a radio frequency integrated circuit (RFIC), and an input / output circuit.

[0044] A heat dissipation plate (185) may be vertically overlapped with a part of the first lower semiconductor device (120) and may be attached to a heat dissipation pad structure (171). The heat dissipation plate (185) may be spaced apart from the upper semiconductor device (181) in a lateral direction (e.g., X direction) and may be overlapped with the upper semiconductor device (181) in a lateral direction (e.g., X direction). The heat dissipation plate (185) may be thermally coupled to the first lower semiconductor device (120) through the heat dissipation pad structure (171). The heat dissipation plate (185) may include a heat sink, a heat pipe, and / or a heat slug. Heat generated in the first lower semiconductor device (120) may be released to the outside through the heat dissipation pad structure (171) and the heat dissipation plate (185). The heat dissipation plate (185) may include a thermally conductive material having high thermal conductivity. The thermal conductivity of the material constituting the heat dissipation plate (185) may be greater than the thermal conductivity of silicon. In other words, the thermal resistance of the material constituting the heat dissipation plate (185) may be smaller than the thermal resistance of silicon. For example, the heat dissipation plate (185) may include metals such as copper (Cu), aluminum (Al), etc., or carbon-containing materials such as graphene, graphite, and / or carbon nanotubes, etc.

[0045] A heat dissipation plate (185) can be attached to a first lower semiconductor device (120) through a thermally conductive adhesive layer (187). The thermally conductive adhesive layer (187) may include a material that is thermally conductive and electrically insulating. The thermally conductive adhesive layer (187) may include a thermal interface material, a polymer containing metal powder, thermal grease, or a combination thereof.

[0046] In exemplary embodiments, the amount of heat generated by the first lower semiconductor device (120) may be greater than the amount of heat generated by the upper semiconductor device (181). In exemplary embodiments, the first lower semiconductor device (120) may include a logic chip and / or an SOC. According to exemplary embodiments of the present invention, since the first lower semiconductor device (120), which has a relatively large amount of heat generated, is thermally coupled to the heat dissipation plate (185) through the heat dissipation pad structure (171), the heat dissipation characteristics for the first lower semiconductor device (120) may be improved, and the performance of electronic components surrounding the first lower semiconductor device (120) may be prevented from deteriorating due to the heat generated by the first lower semiconductor device (120).

[0047] The upper semiconductor device (181) may be vertically overlapped with a portion of the first lower semiconductor device (120). In exemplary embodiments, when viewed in a plane, a portion of the upper semiconductor device (181) may be vertically overlapped with a first region (R1) of the first redistribution structure (110) on which the first lower semiconductor device (120) is mounted, and another portion of the upper semiconductor device (181) may be vertically overlapped with a second region (R2) of the first redistribution structure (110) on which vertical connection conductors (155) are arranged.

[0048] In exemplary embodiments, when viewed in a plane, a first portion of the first lower semiconductor device (120) may be perpendicularly superimposed with the upper semiconductor device (181), and a second portion of the first lower semiconductor device (120) may not be perpendicularly superimposed with the upper semiconductor device (181). The second portion of the first lower semiconductor device (120) may be another portion of the first lower semiconductor device (120) excluding the first portion of the first lower semiconductor device (120). In exemplary embodiments, the ratio of the length (L2) of the first portion of the first lower semiconductor device (120) perpendicularly superimposed with the upper semiconductor device (181) to the total length (L1) of the first lower semiconductor device (120) in the first side direction (e.g., X direction) may be between 10% and 45%, between 20% and 40%, or between 25% and 35%.

[0049] In the semiconductor package (10), a signal provided from an external device (e.g., a data signal, a control signal, a power signal, and / or a ground signal) may be provided to a first lower semiconductor device (120) through a signal transmission path including an external connection terminal (141) and a first conductive redistribution pattern (113). A signal provided from an external device (e.g., a data signal, a control signal, a power signal, and / or a ground signal) may be provided to an upper semiconductor device (181) through a signal transmission path including an external connection terminal (141), a first conductive redistribution pattern (113), a vertical connection conductor (155), and a second conductive redistribution pattern (163). Between the first lower semiconductor device (120) and the upper semiconductor device (181), an electrical signal may be transmitted through the first conductive redistribution pattern (113), the vertical connection conductor (155), and the second conductive redistribution pattern (163).

[0050] In a typical semiconductor package, when semiconductor chips are arranged side-by-side along a package substrate, the dimensions of the semiconductor package (i.e., dimensions in the horizontal direction (X and / or Y direction)) may increase. Additionally, when a semiconductor chip from an upper package is overlapped on top of a semiconductor chip from a lower package, it is difficult to dissipate heat generated by the semiconductor chip in the lower package to the outside.

[0051] According to exemplary embodiments of the present invention, a portion of the first lower semiconductor device (120) is vertically overlapped with the upper semiconductor device (181), and another portion of the first lower semiconductor device (120) is thermally coupled with the heat dissipation plate (185), thereby providing a semiconductor package (10) with improved heat dissipation characteristics while miniaturizing the footprint.

[0052] FIGS. 3a to 3h are cross-sectional views illustrating a method for manufacturing a semiconductor package (10) according to exemplary embodiments of the present invention. Hereinafter, a method for manufacturing a semiconductor package (10) described with reference to FIGS. 1 and FIG. 2 will be described with reference to FIGS. 3a to 3h.

[0053] Referring to FIG. 3a, a first redistribution structure (110) is formed on a carrier substrate (CA). The first redistribution structure (110) may include a plurality of first redistribution insulating layers (111) stacked sequentially on the carrier substrate (CA), and a first conductive redistribution pattern (113) insulated by the plurality of first redistribution insulating layers (111). The first conductive redistribution pattern (113) may include an external connection pad (1135) extended along the upper surface of the carrier substrate (CA), first conductive layers (1131) extended along the upper surface of the plurality of first redistribution insulating layers (111), and a conductive via pattern extended through any one of the plurality of first redistribution insulating layers (111).

[0054] To form the first redistribution structure (110), an external connection pad (1135) can first be formed on a carrier substrate (CA). The external connection pad (1135) can be formed through a plating process. For example, after forming a seed metal layer (115) on the carrier substrate (CA), an external connection pad (1135) can be formed by performing a plating process using the seed metal layer (115). After forming the external connection pad (1135), a first step of forming an insulating film that covers the external connection pad (1135) and has via holes, and a second step of forming a first conductive via pattern (1133) that fills the via holes of the insulating film and a first conductive layer (1131) that extends along the upper surface of the insulating film can be performed. The second step of forming the first conductive via pattern (1133) and the first conductive layer (1131) may include a plating process using a seed metal layer (115). Subsequently, the first step of forming the insulating film and the second step of forming the first conductive layer (1131) may be repeated several times to form a first redistribution structure (110) having a multilayer wiring structure.

[0055] Referring to FIG. 3b, vertical connecting conductors (155) are formed on the first redistribution structure (110). The vertical connecting conductors (155) can be formed using a plating process.

[0056] Referring to FIG. 3c, a first lower semiconductor device (120) is mounted on a first rewiring structure (110). The first lower semiconductor device (120) can be mounted on the first rewiring structure (110) through first chip connection bumps (143).

[0057] Referring to FIG. 3d, a molding layer (151) covering a first lower semiconductor device (120) and vertical connecting conductors (155) is formed on a first redistribution structure (110). To form the molding layer (151), a molding material can be supplied onto a carrier substrate (CA) and then the molding material can be cured.

[0058] Referring to FIG. 3e, a portion of the molding layer (151) can be removed so that the first lower semiconductor device (120) and the vertical connecting conductors (155) are exposed. To remove a portion of the molding layer (151), a chemical mechanical polishing (CMP) process, a grinding process, etc., may be performed. For example, a portion of the molding layer (151), a portion of each of the vertical connecting conductors (155), and a portion of the first lower semiconductor device (120) may be removed through a polishing process. In exemplary embodiments, as a result of the polishing process, the polished upper surface (1511) of the molding layer (151) may be coplanar with the upper surface (129) of the first lower semiconductor device (120) and the upper surface of each of the vertical connecting conductors (155).

[0059] Referring to FIG. 3f, a second redistribution structure (160) is formed on the upper surface (1511) of the molding layer (151) and the upper surface (129) of the first lower semiconductor device (120). The second redistribution structure (160) may include a plurality of second redistribution insulating layers (161) stacked sequentially on the upper surface (1511) of the molding layer (151) and the upper surface (129) of the first lower semiconductor device (120), and a second conductive redistribution pattern (163) insulated by the plurality of second redistribution insulating layers (161). The first conductive redistribution pattern (113) may include an external connection pad (1135) extended along the upper surface of a carrier substrate (CA), first conductive layers (1131) extended along the upper surface of a plurality of first redistribution insulating layers (111), and a conductive via pattern extended through any one of the plurality of first redistribution insulating layers (111).

[0060] To form the second redistribution structure (160) above, a second conductive layer (1631) of the lowest layer connected to vertical connecting conductors (155) may be formed. For example, after forming a seed metal layer (165) on the vertical connecting conductors (155), a plating process using the seed metal layer (115) may be performed to form the second conductive layer (1631) of the lowest layer. Next, a first step may be performed to form an insulating film covering the second conductive layer (1631) of the lowest layer and having via holes, and a second step may be performed to form a second conductive via pattern (1633) filling the via holes of the insulating film and a second conductive layer (1631) extending along the upper surface of the insulating film. The second step of forming the second conductive via pattern (1633) and the second conductive layer (1631) may include a plating process using the seed metal layer (165). Afterwards, the first step of forming the insulating film and the second step of forming the second conductive layer (1631) can be repeated several times to form a second redistribution structure (160) having a multilayer wiring structure.

[0061] After forming the second redistribution structure (160) above, a through hole is formed in the second redistribution insulating layer (161), and a heat dissipation pad structure (171) is formed within the through hole of the second redistribution insulating layer (161). For example, to form the heat dissipation pad structure (171), a through hole is formed in the second redistribution insulating layer (161) that partially exposes the upper surface (129) of the first lower semiconductor device (120), and a conductive material can be filled into the through hole.

[0062] The first redistribution structure (110), the first lower semiconductor device (120), the vertical connecting conductors (155), the molding layer (151), the second redistribution structure (160), and the heat dissipation pad structure (171) can form a panel-shaped package structure (PS).

[0063] Referring to FIGS. 3f and 3g, the carrier substrate (CA) is removed from the first redistribution structure (110). Then, external connection terminals (141) and passive components (149) are attached to the lower side of the first redistribution structure (110).

[0064] Referring to FIG. 3h, the package structure (PS) can be cut along the cutting line (CL). Through the cutting process of the package structure (PS), the package structure (PS) can be separated into a number of lower packages (LP1).

[0065] Next, referring to FIG. 1, an upper package (UP) and a heat dissipation plate (185) are attached to a lower package (LP1) separated into individual units. The upper semiconductor device (181) constituting the upper package (UP) can be mounted on a second redistribution structure (160) so as to be vertically overlapped with a part of the first lower semiconductor device (120), and the heat dissipation plate (185) can be attached to a heat dissipation pad structure (171) through a thermally conductive adhesive layer (187).

[0066] FIG. 4 is a cross-sectional view showing a semiconductor package (11) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (11) shown in FIG. 4 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0067] Referring to FIG. 4, the lower package (LP2) of the semiconductor package (11) may include a conductive layer (191) provided on the upper surface (1511) of the molding layer (151). The conductive layer (191) may include conductive pads (1911) connected to the upper surfaces of vertical connecting conductors (155) and one or more dummy pads (1913) not connected to the vertical connecting conductors (155). One or more dummy pads (1913) may be disposed on the upper surface (1511) of the molding layer (151) and / or the upper surface (129) of the first lower semiconductor device (120). The material of the conductive layer (191) may be substantially the same or similar to the material of the first conductive layer (1131). The upper semiconductor device (181) of the upper package (UP) may be placed on the conductive pads (1911) of the conductive layer (191) and one or more dummy pads (1913) through connection terminals (183). The upper semiconductor device (181) may be electrically and physically connected to vertical connection conductors (155) through the conductive pads (1911) of the conductive layer (191). Additionally, in the semiconductor package (11), a heat dissipation plate (185) may be attached to the upper surface (129) of the first lower semiconductor device (120) by a thermally conductive adhesive layer (187).

[0068] FIG. 5 is a cross-sectional view showing a semiconductor package (12) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (12) shown in FIG. 5 will be described with a focus on the differences from the semiconductor package (11) described with reference to FIG. 4.

[0069] Referring to FIG. 5, in the lower package (LP3) of the semiconductor package (12), a heat dissipation pad structure (171) may be disposed on the upper surface (129) of the first lower semiconductor device (120). A heat dissipation plate (185) may be attached to the heat dissipation pad structure (171). The heat dissipation pad structure (171) may have a plate shape covering the upper surface (129) of the first lower semiconductor device (120). The heat dissipation pad structure (171) may be formed together with the conductive layer (191) through the same metal wiring process. The thickness of the heat dissipation pad structure (171) may be substantially the same as the thickness of the conductive layer (191). The material of the heat dissipation pad structure (171) may be substantially the same as the material of the conductive layer (191).

[0070] FIG. 6 is a cross-sectional view showing a semiconductor package (13) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (13) shown in FIG. 6 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0071] Referring to FIG. 6, in the semiconductor package (13), the lower package (LP4) may further include a second lower semiconductor device (131) mounted on a second region (R2 in FIG. 2) of the first rewiring structure (110). In exemplary embodiments, the second lower semiconductor device (131) may include any one of a memory chip, a logic chip, an SOC, a PMIC chip, and an RFIC chip.

[0072] The second lower semiconductor device (131) may include a semiconductor substrate (1311) and chip pads (1313). The second lower semiconductor device (131) may be mounted on the first redistribution structure (110) in a flip-chip manner. At this time, the lower surface of the semiconductor substrate (1311) may be the active surface of the semiconductor substrate (1311), and the upper surface of the semiconductor substrate (1311) may be the inactive surface of the semiconductor substrate (1311). The semiconductor device layer of the second lower semiconductor device (131) may be disposed on the lower surface of the semiconductor substrate (1311), and the chip pads (1313) may be provided on the lower surface of the second lower semiconductor device (131). Between the chip pads (1313) of the second lower semiconductor device (131) and the first rewiring structure (110), second chip connection bumps (145) configured to electrically connect the chip pads (1313) of the second lower semiconductor device (131) and the first conductive rewiring pattern (113) may be disposed. The second lower semiconductor device (131) may be spaced laterally (e.g., in the X direction) from the first lower semiconductor device (120) and may be vertically overlapped with the upper semiconductor device (181). The second lower semiconductor device (131) may be electrically connected to the first lower semiconductor device (120) through the first conductive rewiring pattern (113). The second lower semiconductor device (131) can be electrically connected to the upper semiconductor device (181) through the first conductive redistribution pattern (113), vertical connecting conductors (155), and the second conductive redistribution pattern (163).

[0073] FIG. 7 is a cross-sectional view showing a semiconductor package (14) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (14) shown in FIG. 7 will be described with a focus on the differences from the semiconductor package (13) described with reference to FIG. 6.

[0074] Referring to FIG. 7, in the lower package (LP5) of the semiconductor package (14), the second lower semiconductor device (131a) may be mounted face-up on the first rewiring structure (110). The lower surface of the semiconductor substrate (1311) may be the inactive surface of the semiconductor substrate (1311), and the upper surface of the semiconductor substrate (1311) may be the active surface of the semiconductor substrate (1311). The semiconductor device layer of the second lower semiconductor device (131a) may be disposed on the upper surface of the semiconductor substrate (1311), and the chip pad (1313) may be provided on the upper surface of the second lower semiconductor device (131a). In the second rewiring structure (160), some of the plurality of second conductive via patterns (1633) may penetrate the molding layer (151) and be connected to the chip pads (1313) of the second lower semiconductor device (131a). The second lower semiconductor device (131a) can be electrically connected to the upper semiconductor device (181) through the second conductive redistribution pattern (163).

[0075] FIG. 8 is a cross-sectional view showing a semiconductor package (15) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (15) shown in FIG. 8 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0076] Referring to FIG. 8, in the semiconductor package (15), the lower package (LP6) may further include a dummy chip (133) mounted on a second region (R2 in FIG. 2) of the first rewiring structure (110). The dummy chip (133) may be mounted on the first rewiring structure (110) via dummy connection bumps (146). The dummy chip (133) may include a dummy semiconductor substrate (1331), dummy connection pads (1333) provided on the lower surface of the dummy semiconductor substrate (1331) and connected to the dummy connection bumps (146), and vertical connection conductors (1335) extending through the dummy semiconductor substrate (1331). The dummy chip (133) provides an electrical signal path extending in a vertical direction (e.g., Z direction) in the semiconductor package (15), but does not include individual components such as transistors. The first lower semiconductor device (120) and the upper semiconductor device (181) can be electrically connected through a signal transmission path comprising a first conductive redistribution pattern (113), dummy connection bumps (146), dummy connection pads (1333), vertical connection conductors (1335), and a second conductive redistribution pattern (163).

[0077] FIG. 9 is a cross-sectional view showing a semiconductor package (16) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (16) shown in FIG. 9 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0078] Referring to FIG. 9, in the lower package (LP7) of the semiconductor package (16), the heat dissipation pad structure (172) may include heat dissipation pad layers (1721) and heat dissipation via patterns (1723).

[0079] The heat dissipation pad layers (1721) may be arranged at different vertical levels to form a multilayer structure. Each of the heat dissipation pad layers (1721) may have a plate shape that is generally parallel to the upper surface (129) of the first lower semiconductor device (120). Each of the heat dissipation pad layers (1721) may be located at the same vertical level as any one of the second conductive layers (1631). Each of the heat dissipation pad layers (1721) may have the same or similar thickness as the corresponding second conductive layer (1631) located at the same vertical level. The lowest heat dissipation pad layer (1721) among the heat dissipation pad layers (1721) may extend along the upper surface (129) of the first lower semiconductor device (120) and may be in contact with the upper surface (129) of the first lower semiconductor device (120). In exemplary embodiments, the lowest heat dissipation pad layer (1721) among the heat dissipation pad layers (1721) may cover the entire upper surface (129) of the first lower semiconductor device (120). Heat dissipation via patterns (1723) may extend in a vertical direction (e.g., Z direction) through at least one of the plurality of second redistribution insulating layers (161). Heat dissipation via patterns (1723) may connect between heat dissipation pad layers (1721) placed at different vertical levels. A seed metal layer (165) may be disposed on the surface of the heat dissipation pad layer (1721) and on the surface of the heat dissipation via patterns (1723). For example, the seed metal layer (165) may extend along the bottom surface of the heat dissipation pad layer (1721) or along the sidewall and bottom surface of the heat dissipation via pattern (1723). In exemplary embodiments, the heat dissipation pad structure (171) may be formed together with the second conductive redistribution pattern (163) of the second redistribution structure (160) through the same metal wiring process. In this case, the material and / or material composition of the heat dissipation pad structure (171) may be substantially the same as the material and / or material composition of the second conductive redistribution pattern (163).

[0080] FIG. 10 is a cross-sectional view showing a semiconductor package (17) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (17) shown in FIG. 10 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0081] Referring to FIG. 10, in the lower package (LP8) of the semiconductor package (17), the second redistribution structure (160) includes a through hole penetrating the second redistribution insulating layer (161), and a heat dissipation plate (185) can be accommodated within the through hole of the second redistribution insulating layer (161). The heat dissipation plate (185) can be attached to a portion of the upper surface (129) of the first lower semiconductor device (120) that overlaps the through hole of the second redistribution insulating layer (161) through a thermally conductive adhesive layer (187).

[0082] FIG. 11 is a cross-sectional view showing a semiconductor package (18) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (18) shown in FIG. 11 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0083] Referring to FIG. 11, in the lower package (LP9) of the semiconductor package (18), the first lower semiconductor device (120) can be directly connected to the first redistribution structure (110a).

[0084] The first conductive redistribution pattern (113a) of the first redistribution structure (110a) may include first conductive layers (1131a), first conductive via patterns (1133a), and external connection pads (1135a). The first conductive layers (1131a) may include line patterns extending along the lower surface of each of the plurality of first redistribution insulating layers (111). The first conductive via patterns (1133a) may electrically connect the first conductive layers (1131a) arranged at different vertical levels, or electrically connect the first conductive layer (1131a) and the lower connection pads of the first lower semiconductor device (120). The external connection pad (1135a) may protrude downward from the lower surface of the lowest insulating layer among the plurality of first redistribution insulating layers (111). The external connection pad (1135a) may include a portion extending along the lower surface of the lowest insulation layer among the plurality of first redistribution insulation layers (111) and a portion extending through the lowest insulation layer. In exemplary embodiments, each of the plurality of first conductive via patterns (1133a) may have a tapered shape in which the horizontal width narrows as it extends from the lower side toward the upper side. In other words, the horizontal width of each of the plurality of first conductive via patterns (1133a) may gradually decrease as it approaches the lower connection pad (1213) of the first lower semiconductor device (120).

[0085] FIG. 12 is a cross-sectional view showing a semiconductor package (19) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (19) shown in FIG. 12 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0086] Referring to FIG. 12, in the semiconductor package (19), the upper semiconductor device (181) may not be vertically overlapped with the first lower semiconductor device (120). For example, in a planar view, the first lower semiconductor device (120) may be within the first region (R1 in FIG. 2) of the first redistribution structure (110), and the upper semiconductor device (181) may be outside the first region (R1) of the first redistribution structure (110). In the lower package (LP10), the heat dissipation pad structure (171) may extend along the entire upper surface (129) of the first lower semiconductor device (120) and cover the entire upper surface (129) of the first lower semiconductor device (120).

[0087] FIG. 13 is a cross-sectional view showing a semiconductor package (20) according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package (20) shown in FIG. 13 will be described with a focus on the differences from the semiconductor package (10) described with reference to FIG. 1 and FIG. 2.

[0088] Referring to FIG. 13, the semiconductor package (20) may include a stiffener (193) disposed on a lower package (LP1). The stiffener (193) may be disposed on the lower package (LP1) so as to overlap the upper semiconductor device (181) and the heat dissipation plate (185) in a lateral direction (e.g., X direction). The stiffener (193) may be configured to improve the mechanical safety of the semiconductor package (20) by mechanically supporting the lower package (LP1). For example, the stiffener (193) may be configured to mitigate and suppress warpage caused by differences in the coefficients of thermal expansion of the individual components constituting the semiconductor package (20) by mechanically supporting the lower package (LP1). The stiffener (193) may include a metal such as steel or copper (Cu).

[0089] For example, the stiffener (193) may be attached to the second redistribution structure (160) through a layer of adhesive material. The stiffener (193) may be placed on the edge region of the second redistribution structure (160). The stiffener (193) may have a ring shape extending along the perimeter of the upper surface of the second redistribution structure (160). The stiffener (193) may consist of a single stiffener block or a plurality of stiffener blocks spaced apart from each other.

[0090] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0091] 10: Semiconductor package 110: First rewiring structure 120: First lower semiconductor device 151: Molding layer 155: Vertical connection conductor 160: Second redistribution structure 171: Thermal pad structure 181: Upper semiconductor device 185: Heat dissipation plate

Claims

Claim 1 A first redistribution structure comprising a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure; a second redistribution structure disposed on the molding layer and the first semiconductor device and comprising a second redistribution insulating layer and a second redistribution pattern; vertical connecting conductors disposed within the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the upper surface of the second redistribution structure, with a portion vertically overlapping with the first semiconductor device; and a heat dissipation pad structure in contact with the upper surface of the first semiconductor device. A semiconductor package comprising: a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device in a first lateral direction, wherein the heat dissipation pad structure is provided within a through hole penetrating the upper and lower surfaces of the second rewiring structure, and the lower surface of the second rewiring structure is in contact with the first semiconductor device. Claim 2 A semiconductor package according to claim 1, wherein the heat dissipation pad structure penetrates the second redistribution insulating layer vertically. Claim 3 A semiconductor package according to claim 1, characterized in that the upper surface of the molding layer is on the same plane as the upper surface of the first semiconductor device. Claim 4 A semiconductor package according to claim 1, characterized in that the ratio between the total length along the first side direction of the first semiconductor device and the length along the first side direction of a part of the first semiconductor device that is vertically superimposed with the second semiconductor device is between 10% and 45%. Claim 5 A semiconductor package according to claim 1, further comprising a third semiconductor device mounted on the first rewiring structure so as to be spaced laterally from the first semiconductor device, wherein the third semiconductor device is vertically superimposed with the second semiconductor device. Claim 6 A semiconductor package according to claim 5, further comprising chip connection bumps disposed between the third semiconductor device and the first rewiring structure. Claim 7 A semiconductor package according to claim 5, wherein the second rewiring pattern includes a conductive via pattern connected to a pad of the third semiconductor device provided on the upper surface of the third semiconductor device through the molding layer. Claim 8 A semiconductor package according to claim 1, further comprising a dummy semiconductor substrate disposed on the first redistribution structure so as to be spaced laterally from the first semiconductor device, wherein the vertical connecting conductors extend vertically within the dummy semiconductor substrate. Claim 9 A semiconductor package according to claim 1, wherein the heat dissipation pad structure comprises: a plurality of heat dissipation pad layers spaced apart in a vertical direction; and heat dissipation via patterns extending between the plurality of heat dissipation pad layers, wherein the heat dissipation pad layer at the bottom among the plurality of heat dissipation pad layers extends along the upper surface of the first semiconductor device. Claim 10 A semiconductor package according to claim 1, further comprising a stiffener disposed on the second rewiring structure. Claim 11 A first redistribution structure comprising a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure and not covering the upper surface of the first semiconductor device; vertical connecting conductors disposed within the molding layer and electrically connected to the first redistribution pattern; a second redistribution structure disposed on the molding layer and the first semiconductor device and comprising a second redistribution insulating layer and a second redistribution pattern; a second semiconductor device disposed on the upper surface of the second redistribution structure and electrically connected to the first redistribution pattern through the vertical connecting conductors; a heat dissipation plate disposed on the upper surface of the first semiconductor device and overlapped with the second semiconductor device in a first lateral direction; A semiconductor package comprising a heat dissipation pad structure disposed between the first semiconductor device and the heat dissipation plate and covering at least a portion of the upper surface of the first semiconductor device, wherein the heat dissipation pad structure is provided within a through hole that vertically penetrates the upper and lower surfaces of the second redistribution structure, and the lower surface of the second redistribution structure is in contact with at least one of the first semiconductor device and the molding layer. Claim 12 A first redistribution structure comprising a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure and not covering the upper surface of the first semiconductor device; a vertical connection conductor disposed within the molding layer and electrically connected to the first redistribution pattern; a second semiconductor device disposed on the molding layer and electrically connected to the first redistribution pattern through the vertical connection conductor; a heat dissipation plate attached to the upper surface of the first semiconductor device and superimposed with the second semiconductor device in a first lateral direction; a conductive pad disposed on the upper surface of the molding layer and connected to the vertical connection conductor; and one or more dummy pads disposed directly on the upper surface of the molding layer and not connected to the vertical connection conductor. A semiconductor package comprising: connection terminals disposed on the conductive pad and one or more dummy pads and connected to the pads of the second semiconductor device; wherein at least one portion of the conductive pad is disposed directly on the upper surface of the molding layer. Claim 13 A semiconductor package according to claim 11, wherein the heat dissipation plate is thermally coupled to the first semiconductor device through the heat dissipation pad structure. Claim 14 A first redistribution structure comprising a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure; a second redistribution structure disposed on the molding layer and the first semiconductor device, comprising a second redistribution insulating layer and a second redistribution pattern; vertical connecting conductors disposed within the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the upper surface of the second redistribution structure, with a portion of which is vertically superimposed with the first semiconductor device; and a thermally conductive adhesive layer in direct contact with the upper surface of the first semiconductor device. A semiconductor package comprising: a heat dissipation plate disposed on the thermally conductive adhesive layer and laterally spaced from the second semiconductor device; wherein the heat dissipation plate and the thermally conductive adhesive layer are received within a through hole that vertically penetrates the lower surface and the upper surface of the second redistribution structure, and the lower surface of the second redistribution structure is in contact with at least one of the first semiconductor device and the molding layer. Claim 15 delete Claim 16 A semiconductor package according to claim 11, further comprising a third semiconductor device mounted on the first rewiring structure, wherein a part of the second semiconductor device is vertically overlapped with the first semiconductor device and another part of the second semiconductor device is vertically overlapped with the third semiconductor device. Claim 17 A semiconductor package according to claim 11, further comprising a dummy semiconductor substrate disposed on the first redistribution structure, wherein the vertical connecting conductors vertically penetrate the dummy semiconductor substrate, a part of the second semiconductor device is vertically overlapped with the first semiconductor device, and another part of the second semiconductor device is vertically overlapped with the dummy semiconductor substrate. Claim 18 A semiconductor package according to claim 11, characterized in that a part of the first semiconductor device is vertically superimposed on the second semiconductor device, and another part of the first semiconductor device is vertically superimposed on the heat dissipation plate. Claim 19 A semiconductor package according to claim 11, wherein the first redistribution pattern comprises: a first conductive layer extending horizontally within the first redistribution insulating layer; an external connection pad to which an external connection terminal provided on the lower side of the first redistribution structure is attached; and a first conductive via pattern extending vertically between the first conductive layer and the external connection pad; wherein the first conductive via pattern has a tapered shape in which the horizontal width becomes narrower as it approaches the external connection pad. Claim 20 A first redistribution structure comprising a first redistribution insulating layer and a first redistribution pattern; a first semiconductor device mounted on the first redistribution structure; chip connection bumps disposed between the first semiconductor device and the first redistribution structure; a molding layer surrounding the first semiconductor device on the first redistribution structure and having an upper surface coplanar with the upper surface of the first semiconductor device; a second redistribution structure disposed on the molding layer and the first semiconductor device and comprising a second redistribution insulating layer and a second redistribution pattern; vertical connection conductors vertically penetrating the molding layer and electrically connecting the first redistribution pattern and the second redistribution pattern; a second semiconductor device mounted on the upper surface of the second redistribution structure; and a heat dissipation pad structure disposed within the second redistribution insulating layer and in contact with the upper surface of the first semiconductor device. A semiconductor package comprising: a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device in a first side direction; wherein the first semiconductor device comprises a logic chip, the second semiconductor device comprises a memory chip, the heat dissipation plate is thermally coupled to the first semiconductor device through the heat dissipation pad structure, a part of the first semiconductor device is vertically overlapped with the second semiconductor device, another part of the first semiconductor device is vertically overlapped with the heat dissipation plate, and the ratio between the total length of the first semiconductor device along the first side direction and the length of the part of the first semiconductor device vertically overlapped with the second semiconductor device along the first side direction is between 10% and 45%, and the heat dissipation pad structure is provided within a through hole that vertically penetrates the upper and lower surfaces of the second redistribution structure, and the lower surface of the second redistribution structure is in contact with at least one of the first semiconductor device and the molding layer.

Images