Semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a first semiconductor chip having a first TSV (Through Silicon Via); a second semiconductor chip having a second TSV formed on the same vertical line as the first TSV and disposed on the first semiconductor chip; a conductive pad formed on each of the first TSV and the second TSV to electrically connect the first semiconductor chip and the second semiconductor chip; and a metal structure for preventing warpage located on the upper surface of the first semiconductor chip or the second semiconductor chip, thereby improving the reliability of the semiconductor device by reducing warpage of the semiconductor device.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor packaging device. Background Technology

[0002] Recently, the demand for multi-chip stacking technology has been growing in the electronics industry, including the semiconductor industry, due to the need for high bandwidth and high capacity. Among multi-chip stacking technologies, the core process is the multi-chip bonding process. However, in the multi-chip bonding process, particularly when bonding chips equipped with TSVs (Through Silicon Via), forces are concentrated on the TSVs, conductive pads connecting to other chips, and micro-bumps. This can cause the chips to bend due to these forces during the bonding process. Alternatively, bending may occur due to the temperature rise of the semiconductor. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor device for preventing warpage of a semiconductor chip.

[0004] The problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A semiconductor device is provided comprising: a first semiconductor chip having a first Through Silicon Via (TSV); a second semiconductor chip disposed on the first semiconductor chip and having a second TSV formed on the same vertical line as the first TSV; conductive pads formed on the first TSV and the second TSV, respectively, to electrically connect the first semiconductor chip and the second semiconductor chip; and a metal structure for preventing warpage located on the upper surface of the first semiconductor chip or the second semiconductor chip.

[0006] A semiconductor device is provided comprising a plurality of internal substrates including semiconductor elements, a Through Silicon Via (TSV) formed to penetrate the plurality of internal substrates vertically, a protective layer positioned on the upper surface of the plurality of internal substrates to surround the side of the TSV, a conductive pad disposed on the TSV, and a metal structure for preventing warpage located on the protective layer of some of the internal substrates and not electrically connected to the semiconductor elements of the internal substrates.

[0007] A semiconductor device is provided comprising a plurality of internal substrates including semiconductor elements, a Through Silicon Via (TSV) formed to penetrate the plurality of internal substrates vertically, a protective layer formed on the upper surface of the plurality of internal substrates to surround the side of the TSV, a conductive pad formed on the TSV, a metal structure for preventing warpage located on the protective layer of the upper internal substrate or the lower internal substrate based on a virtual horizontal line dividing the plurality of internal substrates vertically, and not electrically connected to the semiconductor elements of the internal substrates, and an upper substrate disposed on the upper part of the plurality of internal substrates, electrically connected to the uppermost internal substrate among the plurality of internal substrates through the conductive pad, and having a thickness greater than the thickness of the internal substrates. Effects of the invention

[0008] Through the present invention, the reliability of a semiconductor device can be improved by reducing warpage occurring in the semiconductor device. Brief explanation of the drawing

[0009] FIGS. 1a and FIGS. 1b are side cross-sectional views for illustrating a semiconductor device according to one embodiment of the present invention. FIG. 1c is a side cross-sectional view for explaining a semiconductor device according to one embodiment of the present invention. Figure 2 is a side cross-sectional view of the AA plane of Figure 1b when viewed in the -Z direction. FIGS. 3a and 3b are cross-sectional views schematically illustrating the case where warpage occurs in a semiconductor device. FIG. 4 is an enlarged side cross-sectional view of a part of a semiconductor device that is an embodiment of the present invention. FIG. 5 is an enlarged side cross-sectional view of a part of a semiconductor device that is an embodiment of the present invention. FIGS. 6a to 6e are side cross-sectional views for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a side cross-sectional view showing a semiconductor device which is an embodiment of the present invention. FIG. 8 is a plan view of the XY plane between the semiconductor chip (200) and the semiconductor chip (210) in the semiconductor device of FIG. 7 when viewed in the -Z axis direction. FIG. 9 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 10 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 11 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 12 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 13 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 14 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 15 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 16 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. FIG. 17 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z-axis direction at the position shown in FIG. 8. Specific details for implementing the invention

[0010] Exemplary embodiments of the present invention are provided to more fully explain the invention to those skilled in the art to which the concept of the invention belongs, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the invention more faithful and complete and to fully convey the spirit of the invention to those skilled in the art.

[0011] Semiconductor chips that have undergone the front-end process of forming circuits on a wafer can proceed to the back-end process, which consists of packaging and testing. Although semiconductor chips integrate fine electrical circuits, they cannot perform their primary function on their own. The packaging process electrically connects the chip to the outside world to enable it to function properly and protects it from the external environment. Additionally, the package allows for the efficient dissipation of heat generated by the semiconductor.

[0012] Semiconductor packages can perform roles such as mechanical protection, electrical connection, and heat dissipation. In other words, a semiconductor chip can be wrapped in a packaging material, such as EMC (Epoxy Mold Compound), to protect it from external mechanical and chemical shocks. Through the package, the semiconductor chip is physically and electrically connected to a system to supply power for operation. Furthermore, it allows for the input and output of signals to enable the chip to perform desired functions, and can dissipate heat generated during the semiconductor product's operation.

[0013] Semiconductor packaging methods can be classified into Conventional Package, which applies the packaging process to individual chips separated from a wafer, and Wafer Level Package (WLP), where part or all of the process is carried out at the wafer stage and the chips are later cut into individual units.

[0014] Early packaging technology utilized the lead frame method, which connected chips and pads using gold wires. However, as device performance advanced, the lead frame structure reached its limits. Consequently, fBGA (Fine-Pitch Ball Grid Array), based on substrates with fine patterns, is now being adopted. This type of conventional package allows for the stacking of many chips, making it suitable for applications such as NAND and mobile DRAM where high capacity is critical.

[0015] To meet the requirements of memory products, the conventional package method, a traditional approach, is being developed while a new method called WLP is being introduced. WLP is a technology suitable for realizing high-performance products that allows for packaging at the chip's original size. Therefore, it has the advantage of minimizing the finished semiconductor product and reducing costs by eliminating the need for materials such as substrates or wires. The WLP process can be utilized for products such as High Bandwidth Memory (HBM) or Computing DRAM, which require high capacity. HBM is a 3D memory semiconductor formed by vertically connecting multiple DRAMs. Warpage may occur when semiconductor devices, including HBM, are heated. To solve the above problem, the semiconductor device of the present invention will be described in detail below with reference to the drawings.

[0016] FIGS. 1a and FIGS. 1b are side cross-sectional views schematically illustrating a semiconductor device according to one embodiment of the present invention.

[0017] Referring to FIGS. 1a and 1b, a semiconductor device according to one embodiment of the present invention comprises a substrate (100), a plurality of semiconductor chips (200, 210, 220, 230, 240, 250), and an upper semiconductor chip (300). The substrate (100) may be a silicon substrate based on a semiconductor wafer. As an exemplary embodiment, the substrate (100) may be a substrate for packaging and may be a printed circuit board (PCB). The substrate (100) includes a corresponding upper surface and a lower surface. A conductive bump (105) may be formed on the lower surface of the substrate (100) to electrically connect the semiconductor device according to various embodiments of the present invention to an external device. An electrical signal may be supplied to the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) and the upper semiconductor chip (300) through the conductive bump (105). At least one of the upper conductive pads (106) may be a ground pad and may be electrically connected to a ground line within the substrate (100).

[0018] A plurality of semiconductor chips (200, 210, 220, 230, 240, 250) are disposed on a substrate (100). For example, the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) may be sequentially stacked in a vertical direction to form a stacked structure. As an exemplary embodiment, the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) may include memory chips, logic chips, etc. For example, if at least one of the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) is a logic chip, at least one of the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) may be designed in various ways depending on the operation being performed. Meanwhile, for example, if at least one of the plurality of semiconductor chips (200, 210, 220, 230, 240, 250) is a memory chip, the memory chip may be, for example, a non-volatile memory chip. Specifically, the memory chip may be a flash memory chip. The memory chip may be either a NAND flash memory chip or a NOR flash memory chip. However, the form of the memory device according to the technical concept of the present invention is not limited thereto. In an embodiment of the present invention, the memory chip may include any one of PRAM (Phase-change Random-Access Memory), MRAM (Magneto-resistive Random-Access Memory), RRAM (Resistive Random-Access Memory), and DRAM (Dynamic Random-Access Memory).

[0019] A semiconductor chip (200) can be electrically connected to a substrate (100) by a lower conductive pad (207) formed on the lower surface of the semiconductor chip (200). That is, the lower conductive pad (207) can electrically connect the semiconductor chip (200) and the upper conductive pad (106) of the substrate (100). In some embodiments of the present invention, a conductive bump (205) may be interposed between the lower conductive pad (207) and the upper conductive pad (106) to facilitate the electrical connection between the lower conductive pad (207) and the upper conductive pad (106). In the drawing, the bump (205) is shown as a ball-shaped solder ball, but is not limited thereto.

[0020] An underfill material (400) that fills the space between the substrate (100) and the semiconductor chip (200) may be formed between the substrate (100) and the semiconductor chip (200). As an exemplary embodiment of the present invention, the underfill material (400) may cover at least a portion of the side of the semiconductor chip (200), or may cover the periphery of a plurality of semiconductor chips (200, 210, 220, 230, 240, 250). The underfill material (400) may include a non-conductive material that does not conduct electricity. The underfill material (400) may be, for example, a non-conductive film (NCF) or a die attach film (DAF), but is not limited thereto.

[0021] The semiconductor chip (200) includes an internal substrate (201) containing semiconductor elements, a TSV (Through Silicon Via) (204), and a protective layer (202). The internal substrate (201) may be a silicon substrate, similar to the substrate (100).

[0022] At least a portion of the TSV (204) provided in the semiconductor chip (200) is formed to penetrate the inner substrate (201) vertically. As an exemplary embodiment, the TSV (204) may be formed to protrude from the upper surface of the inner substrate (201). The side of the protruding TSV (204) may be surrounded by a protective layer (202) formed on the upper surface of the inner substrate (201).

[0023] The TSV (204) may include at least one metal. For example, the TSV (204) may include a wiring metal layer formed at its center and a barrier metal layer formed on the outer edge of the wiring metal layer. The wiring metal layer may include one or more of aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr), and the barrier metal layer may include one or more stacked structures selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).

[0024] One or more upper conductive pads (206) may be formed on the upper surface of the semiconductor chip (200). The upper conductive pads (206) formed on the upper surface of the semiconductor chip (200) may be electrically connected to the semiconductor chip (210) disposed on the semiconductor chip (200). Specifically, the upper conductive pads (206) may connect the semiconductor chip (210) with the TSV (204) formed within the semiconductor chip (200). A bump (215) may be interposed between the upper conductive pads (206) and the semiconductor chip (210) to facilitate the electrical connection between the upper conductive pads (206) and the semiconductor chip (210). As an exemplary embodiment, the bump (215) may be a micro bump.

[0025] The upper conductive pad (206) is formed on the upper surface of the TSV (204) and may overlap with a portion of the protective layer (202). That is, the lower surface of the upper conductive pad (206) may come into contact with both the upper surface of the TSV (204) and at least a portion of the upper surface of the protective layer (202). Meanwhile, in some embodiments of the present invention, the upper conductive pad (206) may include a metal. For example, the upper conductive pad (206) may be a plated pad that has undergone plating treatment and may include any one of Au, Ni / Au, and Ni / Pd / Au.

[0026] A metal structure (208) for preventing warpage may be located on the semiconductor chip (200). A protective layer (202) may be formed between the semiconductor chip (200) and the metal structure (208) for preventing warpage. FIG. 1a shows a case where the metal structure (208) for preventing warpage is not located on the semiconductor chip (200), and FIG. 1b shows a case where the metal structure (208) for preventing warpage is located on the semiconductor chip (200). The shape of the metal structure (208) for preventing warpage may be the same as or different from the shape of the upper conductive pad (206). The manufacturing method for cases where the shapes are the same or different will be described later. Since the metal structure (208) for preventing warpage is located on the protective layer (202), it may not be electrically connected to internal substrates containing semiconductor elements. Additionally, even if the protective layer (202) is absent, the anti-warpage metal structure (208) may be insulated and not electrically connected to internal substrates containing semiconductor devices. The anti-warpage metal structure (208) may contain the same material as the upper conductive pad (206). A TSV (204) may not be formed on the lower part of the anti-warpage metal structure (208).

[0027] The semiconductor chips (200, 210, 220, 230, 240, 250) placed on the semiconductor chip (200) can be formed similarly to the semiconductor chip (200) described above. That is, the semiconductor chips (200, 210, 220, 230, 240, 250) can be electrically connected to the semiconductor chips (200, 210, 220, 230, 240, 250) by lower conductive pads (217, 227, 237, 247, 257) formed on the lower surface of each semiconductor chip (200, 210, 220, 230, 240, 250). At this time, an underfill material (400) may be formed around the semiconductor chip (200, 210, 220, 230, 240, 250). The underfill material (400) may wrap part or all of the side of the semiconductor chip (200, 210, 220, 230, 240, 250).

[0028] Each semiconductor chip (200, 210, 220, 230, 240, 250) includes an internal substrate (201, 211, 221, 231, 241, 251), a TSV (204, 214, 224, 234, 244, 254), and a protective layer (202, 212, 222, 232, 242, 252). Additionally, one or more upper conductive pads (206, 216, 226, 236, 246, 256) may be located on the upper surface of each semiconductor chip (200, 210, 220, 230, 240, 250). One or more anti-warpage metal structures (208, 218, 228, 238, 248, 258) may be located on a protective layer (202, 212, 222, 232, 242, 252) of some of the semiconductor chips (200, 210, 220, 230, 240, 250).

[0029] The various components of the semiconductor chip (210, 220, 230, 240, 250) correspond to the configurations described regarding the semiconductor chip (200), and the various configurations of the semiconductor chip (210, 220, 230, 240, 250) have the same content as the configurations described regarding the corresponding semiconductor chip (200). Therefore, descriptions of the various configurations of the semiconductor chip (210, 220, 230, 240, 250) that overlap with the configurations described regarding the semiconductor chip (200) are omitted.

[0030] An upper semiconductor chip (300) is placed on a plurality of semiconductor chips (200, 210, 220, 230, 240, 250). For example, the upper semiconductor chip (300) may be additionally stacked on a stacked structure composed of a plurality of semiconductor chips (200, 210, 220, 230, 240, 250). For example, as shown in FIG. 1a and FIG. 1b, the upper semiconductor chip (300) may be electrically connected to a semiconductor chip (250) located at the top of the semiconductor chips through an upper conductive pad (256). The thickness of the upper semiconductor chip (300) may be thicker than the thickness of the semiconductor chips (200, 210, 220, 230, 240, 250). The upper semiconductor chip (300) may include a memory chip, a logic chip, etc., similar to the plurality of semiconductor chips (200, 210, 220, 230, 240, 250).

[0031] An underfill material (400) that fills the space between the semiconductor chip (250) and the upper semiconductor chip (300) may be formed between the semiconductor chip (250) and the upper semiconductor chip (300). As previously described, the underfill material (400) may cover at least a portion of the side of the semiconductor chip (250) and at least a portion of the side of the upper semiconductor chip (300). The underfill material (400) may include a non-conductive material that does not conduct electricity. The underfill material (400) may be, for example, a non-conductive film (NCF) or a die attach film (DAF), but is not limited thereto.

[0032] FIG. 1c is a side cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. Upper conductive pads (106, 206, 216, 226, 236, 246, 256) and lower conductive pads (207, 217, 227, 237, 247, 257, 307) may be made of a material containing Cu. Adjacent upper conductive pads and lower conductive pads may be joined to each other by copper-copper hybrid bonding. An insulating film (not shown) may be disposed between the upper surface and the lower surface of the semiconductor chip joined to each other by hybrid bonding. All embodiments of the present invention may also be applied to a semiconductor device having a hybrid bonding structure.

[0033] Figure 2 is a cross-sectional view of the AA plane of Figure 1b when viewed in the -Z direction.

[0034] Referring to FIG. 2, a protective layer (202) may be formed on the upper surface of a semiconductor chip (200). On the protective layer (202), an upper conductive pad (206) electrically connected to a TSV (204) and a conductive bump (215) for electrically connecting the lower conductive pad (217) shown in FIG. 1a and FIG. 1b may be positioned. The TSV (204), the upper conductive pad (206), and the conductive bump (215) may be distributed in multiple numbers on the upper surface of the semiconductor chip (200) and may be located in the center. FIG. 2 illustrates that the semiconductor chip (200) is square, and the upper conductive pad (206) and the conductive bump (215) are distributed in a square shape in the center of the semiconductor chip (200) in 64 numbers. FIG. 2 is an exemplary embodiment, and the arrangement, number, and shape of the TSV (204), the upper conductive pad (206), and the conductive bump (215) on the semiconductor chip (200) are not limited thereto.

[0035] The anti-warpage metal structure (208) may be in the shape of a square and may be placed along the periphery of the semiconductor chip (200) and the TSV (204), the upper conductive pad (206), the lower conductive pad (217), and the conductive bump (215) on the protective layer (202). FIG. 2 is an exemplary embodiment, and the number, shape, and arrangement of the anti-warpage metal structure (208) located on a single semiconductor chip are not limited by this embodiment.

[0036] The description of the semiconductor chip (200) described above can likewise be applied to the semiconductor chips (200, 210, 220, 230, 240, 250). Therefore, redundant descriptions of the semiconductor chips (200, 210, 220, 230, 240, 250) will be omitted.

[0037] FIGS. 3a and FIGS. 3b are schematic cross-sectional views illustrating the case where warpage occurs in a conventional semiconductor device.

[0038] Referring to FIGS. 3a and 3b, warpage may occur in a conventional semiconductor device due to the process of laminating by thermal compression bonding, or due to a rise in temperature during the operation of the semiconductor device. Warpage may occur due to differences in the coefficients of thermal expansion of the components and materials constituting the semiconductor device. As shown in FIG. 3a, warpage in the form of a cry shape may occur, in which the center of the semiconductor device is raised compared to other parts, i.e., an upwardly convex shape, due to a rise in temperature. Alternatively, the cry shape warpage can be described as the first semiconductor chip (200, 210, 220) bending convexly toward the second semiconductor chip (230, 240, 250). Alternatively, warpage in the form of a smile shape may occur, in which the center of the semiconductor device is lower compared to other parts, i.e., a downwardly convex shape, due to a rise in temperature, as shown in FIG. 3b. Alternatively, a smile-shaped warpage can be described as the second semiconductor chip (230, 240, 250) being bent convexly toward the first semiconductor chip (200, 210, 220). When such a warpage occurs in the semiconductor device, stress may be generated inside the semiconductor device due to the warpage.

[0039] When considering a semiconductor device as a type of beam, the warpage of the semiconductor device can be viewed as the bending or curvature of the beam. Stress may occur due to the bending of the beam. This stress resulting from the bending of the beam is called bending stress. When a beam bends, a neutral axis may exist within the beam. The neutral axis refers to a line connecting the parts where no tension or compression occurs when the members forming the beam are compressed or stretched due to the bending of the beam.

[0040] The warpage prevention metal structure (208) may be positioned on an upper semiconductor chip or a lower semiconductor chip based on a virtual horizontal line (500). The virtual horizontal line (500) may be the neutral axis described above.

[0041] In one embodiment of the present invention, when a virtual horizontal line (500) is a neutral axis, the semiconductor device may receive tensile stress or compressive stress based on the neutral axis. When a warpage in the shape of a cry that is convex upward as shown in FIG. 3a occurs, the semiconductor chips above the virtual horizontal line (500) may receive tensile stress, and the semiconductor chips below the virtual horizontal line (500) may receive compressive stress. When a warpage in the shape of a smile that is convex downward as shown in FIG. 3b occurs, the semiconductor chips below the virtual horizontal line (500) may receive tensile stress, and the semiconductor chips above the virtual horizontal line (500) may receive compressive stress.

[0042] Since the warpage prevention metal structure (208, 218, 228, 238, 248, 258) is made of metal, the thermal expansion coefficient of the warpage prevention metal structure (208, 218, 228, 238, 248, 258) may be greater than the overall thermal expansion coefficient of the semiconductor device. When the semiconductor device is heated, the warpage prevention metal structure (208, 218, 228, 238, 248, 258) may undergo greater thermal expansion compared to other components constituting the semiconductor device. As a result, the semiconductor chip to which the warpage prevention metal structure (208, 218, 228, 238, 248, 258) is attached may receive tensile stress from the warpage prevention metal structure (208) when the semiconductor device is heated.

[0043] As shown in FIG. 3a, if a warpage in the form of a cry with an upwardly convex shape occurs, and the virtual horizontal line (500) is the neutral axis, compressive stress may be applied to the semiconductor chip located below the virtual horizontal line (500) as previously explained. As shown in FIG. 1b, a metal structure (208, 218, 228, 238, 248, 258) for preventing warpage may be placed on the upper surface of the semiconductor chip located below the virtual horizontal line (500). As previously explained, the metal structure (208, 218, 228, 238, 248, 258) for preventing warpage has a higher coefficient of thermal expansion compared to other components constituting the semiconductor device, so it may expand relatively compared to the other components due to temperature increase. As the above-mentioned metal structure for preventing warpage (208, 218, 228, 238, 248, 258) applies tensile stress to the semiconductor chip while heating, the compressive stress applied to the semiconductor chip located below due to the heating can be reduced. Therefore, compared to a semiconductor device in which the metal structure for preventing warpage (208, 218, 228, 238, 248, 258) is not located, the degree of warpage occurrence in a semiconductor device in which the metal structure for preventing warpage (208, 218, 228, 238, 248, 258) is located can be reduced.

[0044] In the case where a warpage in the shape of a smile, which is convex downward as shown in FIG. 3b, occurs, if the virtual horizontal line (500) is the neutral axis, compressive stress may be applied to the semiconductor chip located above the virtual horizontal line (500) as previously explained. As shown in FIG. 1a, a metal structure for preventing warpage may be placed on the upper surface of the semiconductor chip located above the virtual horizontal line (500). As previously explained, the metal structure for preventing warpage applies tensile stress while elongating relative to the semiconductor chip, thereby reducing compressive stress caused by temperature rise. Therefore, compared to a semiconductor device without a metal structure for preventing warpage, the degree of warpage occurrence in a semiconductor device with a metal structure for preventing warpage can be reduced.

[0045] As described above, the virtual horizontal line (500) may be a neutral axis in the bending of the beam, but the virtual horizontal line (500) may be a line that divides the semiconductor device equally in the horizontal direction, or any horizontal line. Therefore, the setting of the virtual horizontal line (500) as an embodiment of the present invention is not limited.

[0046] As an additional explanation, when a metal structure for warpage prevention is positioned on an upper or lower semiconductor chip based on a virtual horizontal line (500), the proportion of metal in the upper and lower parts of the semiconductor device may differ.

[0047] In the event that a warpage in the form of a cry with an upwardly convex shape occurs as shown in FIG. 3a, a metal structure (208, 218, 228) for preventing warpage can be positioned on the lower semiconductor chip (200, 210, 220) with respect to a virtual horizontal line (500) as shown in FIG. 1b. With respect to the virtual horizontal line (500), the proportion of metal in the lower part of the semiconductor device may be relatively higher than that in the upper part. Metal has a relatively higher coefficient of thermal expansion compared to the semiconductor device. Therefore, the average coefficient of thermal expansion in the lower part of the semiconductor device is higher than that in the upper part. That is, when the semiconductor device is heated, the upper part of the semiconductor device may expand more than when there is no metal structure (208, 218, 228) for preventing warpage. Therefore, compared to when there is no metal structure (208, 218, 228) for preventing warpage, when there is a metal structure (208, 218, 228) for preventing warpage, the degree of warpage occurring in the semiconductor device can be reduced.

[0048] In the case where a smile-shaped warpage with a downward convex shape occurs as in FIG. 3b, a metal structure (238, 248, 258) for preventing warpage can be positioned on the upper semiconductor chip (230, 240, 250) based on a virtual horizontal line (500) as in FIG. 1a. Based on the virtual horizontal line (500), the proportion of metal in the upper part of the semiconductor device may be relatively higher than in the lower part. Metal has a relatively higher coefficient of thermal expansion compared to the semiconductor device. Therefore, the average coefficient of thermal expansion in the upper part of the semiconductor device is higher than in the lower part. That is, when the semiconductor device is heated, the upper part of the semiconductor device may expand more than when there is no metal structure (238, 248, 258) for preventing warpage. Therefore, compared to when there is no metal structure (238, 248, 258) for preventing warpage, the degree of warpage can be reduced when there is a metal structure (238, 248, 258) for preventing warpage.

[0049] As previously explained, by selectively positioning the metal structures (208, 218, 228, 238, 248, 258) for preventing warpage on the semiconductor chip based on a virtual horizontal line (500), the degree of warpage that may occur depending on the semiconductor device can be reduced. When warpage occurs in a semiconductor device, the electrical connections of the internal components of the semiconductor device may be severed, or damage or defects may occur in the semiconductor chip. Therefore, through the present invention, warpage in the semiconductor device can be reduced, thereby improving the reliability of the semiconductor device.

[0050] FIG. 4 is an enlarged side cross-sectional view of part B, which is part of the semiconductor device of FIG. 1a, and FIG. 5 is an enlarged side cross-sectional view of part C, which is part of the semiconductor device of FIG. 1a.

[0051] Referring to FIG. 4, the height in the Z-axis direction of the warpage prevention metal structure (248) formed on the upper surface of the semiconductor chip (240) may be the same as the height in the Z-axis direction of the upper conductive pad (246) formed on the upper surface of the first TSV (244) of the first semiconductor chip (240). Additionally, the width in the X-axis direction of the warpage prevention metal structure (248) formed on the upper surface of the semiconductor chip (240) may be the same as the width in the X-axis direction of the upper conductive pad (246) formed on the upper surface of the TSV (244). Likewise, referring to FIG. 5, the height and width of the warpage prevention metal structure (258) formed on the upper surface of the second semiconductor chip (230) may be the same as the height in the Z-axis direction and the width in the X-axis direction of the warpage prevention metal structure (258) formed on the upper surface of the TSV (254) of the second semiconductor chip (250). If the relative position between the semiconductor chips is above, it can be called the second semiconductor chip, and if the relative position is below, it can be called the first semiconductor chip. The first semiconductor chip and the second semiconductor chip may each include a plurality of semiconductor chips. The first semiconductor chip is not limited to the semiconductor chip (240), and the second semiconductor chip is not limited to the semiconductor chip (250).

[0052] Referring to FIG. 5, the semiconductor device of FIG. 1a may further include semiconductor chips (200, 210, 220, 230), and upper conductive pads (106, 206, 216, 226, 236, 246, 256) formed on the upper surface of each TSV of the semiconductor chips (200, 210, 220, 230, 240, 250) may be formed on the same vertical line. In other words, a connection portion formed for electrical connection between a plurality of semiconductor chips (200, 210, 220, 230, 240, 250) may be formed on the same vertical line. Additionally, the anti-warpage metal structures (208, 218, 228, 238, 248, 258) that can be formed on each upper surface of the semiconductor chips (200, 210, 220, 230, 240, 250) may be formed on the same vertical line. The shape and size of the anti-warpage metal structures (208, 218, 228, 238, 248, 258) are not limited thereto.

[0053] FIGS. 6a to 6e are drawings illustrating steps for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0054] Referring to FIG. 6a, a TSV (204) can be formed by recessing the upper surface of a semiconductor chip (200). The TSV (204) may protrude relative to the upper surface of the semiconductor chip (200). Additionally, depending on the method of forming the TSV (204), the TSV (204) may not protrude. In some embodiments of the present invention, forming the TSV (204) by recessing the upper surface of a semiconductor chip (220) may include recessing the upper surface of the semiconductor chip (200) using a dry etching process.

[0055] Referring to FIG. 6b, a protective layer (202) covering the TSV (204) can be formed on the upper surface of the semiconductor chip (200).

[0056] Referring to FIG. 6c, the protective layer (202) can be flattened to expose the TSV (204). As an exemplary embodiment, the protective layer (202) can be flattened through a Chemical Mechanical Polishing (CMP) process to expose the TSV (204).

[0057] Referring to FIG. 6d, an upper conductive pad (206) can be formed on the upper surface of the exposed TSV (204), and a metal structure (208) for preventing warpage, having the same height as the upper conductive pad (206), can be formed on the protective layer (202).

[0058] In some embodiments, the upper conductive pad (206) and the anti-warpage metal structure (208) may be formed together. As a result, the upper conductive pad (206) and the anti-warpage metal structure (208) may be formed of the same height and the same material.

[0059] In some embodiments, the anti-warpage metal structure (208) may be formed in a shape or material that is not the same as the upper conductive pad (206). The method of forming the upper conductive pad (206) and the anti-warpage metal structure (208) is the same, but they may be formed at a different height or in a different shape through separate steps, and may be formed with a different material. The anti-warpage metal structure (208) may be formed first, followed by the upper conductive pad (206), or the upper conductive pad (206) may be formed first, followed by the anti-warpage metal structure (208), in the reverse order.

[0060] Referring to FIG. 6e, a second semiconductor chip (210) having a TSV (214) formed on the same vertical line as the TSV (204) can be placed on the semiconductor chip (200). In an embodiment of the present invention, placing the semiconductor chip (210) on the semiconductor chip (200) may include thermally pressing the second semiconductor chip (210) onto the first semiconductor chip (210). Similar to the process described above, the upper surface of the semiconductor chip (220) is recessed to protrude the TSV (214). In some embodiments of the present invention, forming the TSV (214) by recessing the upper surface of the semiconductor chip (220) may include recessing the upper surface of the semiconductor chip (210) using a dry etching process. A protective layer (212) covering the TSV (214) is formed on the upper surface of the semiconductor chip (210). The protective layer (212) can be flattened to expose the TSV (214). In some embodiments of the present invention, flattening the protective layer (212) to expose the TSV (214) may include flattening the protective layer (212) using a Chemical Mechanical Polishing (CMP) process. An upper conductive pad (216) is formed on the upper surface of the exposed TSV (214), and a warpage-preventing metal structure (218) having the same height as the upper conductive pad (216) is formed on the protective layer (212). In an exemplary embodiment, forming an upper conductive pad (216) on the upper surface of an exposed TSV (214) and forming a warpage prevention metal structure (218) having the same height as the upper conductive pad (216) on a protective layer (212) may include forming a barrier metal layer on the upper surface of a semiconductor chip (210), forming a photoresist pattern covering the portion where the upper conductive pad (216) and the warpage prevention metal structure (218) are to be formed, and etching the barrier metal layer using the photoresist pattern as a mask.The shape of each photoresist forming a photoresist pattern covering the portion where the upper conductive pad (216) and the metal structure (218) for preventing warpage are to be formed may be identical to each other.

[0061] A metal structure (218) for preventing warpage can be formed with a shape or material that is not the same as the upper conductive pad (216). Similar to the description above, a barrier metal layer can be formed on the upper surface of the semiconductor chip (210), and a photoresist pattern can be formed to cover the portion where the upper conductive pad (216) is to be formed. Then, the barrier metal layer can be etched using the photoresist pattern as a mask. Next, a barrier metal layer can be formed again on the upper surface of the semiconductor chip (210), but the material of the barrier metal layer can be different so that the material forming the metal structure (218) for preventing warpage can be different from the material forming the upper conductive pad (216). A photoresist pattern can be formed to cover the portion where the metal structure (218) for preventing warpage is to be formed, and the barrier metal layer can be etched using the pattern as a mask. If the shape of each barrier metal layer is different, the shapes of the upper conductive pad (216) and the anti-warpage metal structure (218) may not be identical. The order of the above process may be such that the anti-warpage metal structure (218) is formed first, and then the upper conductive pad (216) is formed.

[0062] In the method described in FIGS. 6a to 6e, semiconductor chips (220, 230, 240, 250) and an upper semiconductor chip (300) are formed sequentially on a semiconductor chip (210). The thickness of the upper semiconductor chip (300) may be thicker than the thickness of the semiconductor chips (200, 210, 220, 230, 240, 250). Forming the semiconductor chip (230) and the upper semiconductor chip (300) on the semiconductor chip (220) may include thermally pressing and bonding the semiconductor chip (230) onto the semiconductor chip (220), and then thermally pressing and bonding the upper semiconductor chip (300) onto the semiconductor chip (230).

[0063] Forming semiconductor chips (220, 230, 240, 250) and an upper semiconductor chip (300) on a semiconductor chip (210) may include forming an underfill material (400) that fills the space between the semiconductor chip (200) and the semiconductor chip (210), and an underfill material (400) that fills the space between the semiconductor chips (220, 230, 240, 250) and the upper semiconductor chip (300). The underfill material (400) may wrap at least a portion of the side of the semiconductor chips (200, 210, 220, 230, 240, 250) and at least a portion of the side of the upper semiconductor chip (300). The underfill material (400) may include a Nonconductive Film (NCF).

[0064] FIG. 7 is a side cross-sectional view showing a semiconductor device that is an embodiment of the present invention, and FIG. 8 is a plan view of the XY plane between the semiconductor chip (200) and the semiconductor chip (210) in the semiconductor device that is an embodiment of the present invention of FIG. 7 when viewed in the -Z axis direction.

[0065] Referring to FIGS. 7 and 8, the anti-warpage metal structures (208, 218, 228) may be positioned on each semiconductor chip (200, 210, 220) with different areas. When warpage occurs in a semiconductor chip, relatively more stress may be applied to the center of the semiconductor chip compared to the periphery. This is because relatively less deformation may occur at the left and right ends of the semiconductor device compared to the center. Therefore, the shape of the anti-warpage metal structures (208, 218, 228) may be configured such that the area in the XY plane or the thickness in the Z-axis direction of the anti-warpage metal structures closer to the center of the semiconductor chip is larger than that of the anti-warpage metal structures farther from the center, in order to offset more stress in the center. Referring to FIG. 7, three anti-warpage metal structures (208, 218, 228) may be positioned on the left and right sides of each semiconductor chip cross-section. And the X-axis length of the anti-warpage metal structure near the TSV (204, 214, 224) can be configured to be long so that the area of ​​the anti-warpage metal structure in the XY plane is large. The area in the XY plane of the anti-warpage metal structure (208a) located far from the TSV (204) may be smaller than the area in the XY plane of the anti-warpage metal structure (208c) located close to the TSV (204). The area in the XY plane of the anti-warpage metal structure (208b) located between the anti-warpage metal structure (208a) and the anti-warpage metal structure (208c) may be larger than the area of ​​the anti-warpage metal structure (208a) and smaller than the area of ​​the anti-warpage metal structure (208c). A metal structure for preventing warpage, as described above, may also be located on the semiconductor chip (210, 220), and descriptions within the overlapping scope are omitted.Due to the embodiment of the present invention of FIG. 7, the arrangement, number, and shape of the metal structures (208, 218, 228) for preventing warpage are not limited. Additionally, if necessary, the metal structures (208) for preventing warpage may be positioned above or below a virtual horizontal line (500).

[0066] FIG. 9 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z-axis direction from the same position as FIG. 8. Referring to FIG. 9, a metal structure (208d, 208e) for preventing warpage may be located on a protective layer (202) formed on the upper surface of a semiconductor chip (200, not shown). A TSV (204, not shown) may be located at the lower end of the upper conductive pad (206) in the Z-axis direction. The metal structure (208e) for preventing warpage may be configured in a frame shape that surrounds the periphery of the TSVs (204, not shown) formed in the center of the semiconductor chip (200). The metal structure (208d) for preventing warpage may be configured in a frame shape that surrounds the TSVs (204) formed in the center of the semiconductor chip (200) and the metal structure (208e) for preventing warpage that surrounds the TSVs (204). The metal structures (208d, 208e) for preventing warpage in FIG. 9 are rectangular in shape and may have a shape similar to the perimeter of a semiconductor chip (200). That is, the metal structures (208d, 208e) for preventing warpage may each have two sides in the X-axis direction and two sides in the Y-axis direction. Therefore, even if the direction in which warpage occurs is not uniform, warpage can be reduced through the metal structures (208d, 208e) for preventing warpage. Additionally, if necessary, the metal structures (208d, 208e) for preventing warpage may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the metal structures (208d, 208e) for preventing warpage described above are not limited by this embodiment.

[0067] FIG. 10 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z-axis direction at the position shown in FIG. 8. Referring to FIG. 10, a metal structure for preventing warpage (208f, 208g, 208h) may be located on a protective layer (202) formed on the upper surface of a semiconductor chip (200, not shown). A TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The metal structure for preventing warpage (208h) may be configured in a frame shape that surrounds the TSVs (204) formed in the center of the semiconductor chip (200). The metal structure for preventing warpage (208g) may be configured in a frame shape that surrounds the TSVs (214) formed in the center of the semiconductor chip (200) and the metal structure for preventing warpage (208h) that surrounds the TSVs (214). The anti-warpage metal structure (208f) may be configured in a frame shape that surrounds the TSVs (204) formed in the center of the semiconductor chip (200) and the frame-shaped anti-warpage metal structure (208g) surrounding the TSVs (204). The anti-warpage metal structures (208d, 208e) in FIG. 9 are rectangular in shape and may have a shape similar to the perimeter of the semiconductor chip (200). That is, the anti-warpage metal structures (208f, 208g, 208h) may each have two sides in the X-axis direction and two sides in the Y-axis direction. Therefore, even if the direction in which warpage occurs is not uniform, warpage can be reduced through the anti-warpage metal structures (208f, 208g, 208h). Additionally, if necessary, a metal structure (208f, 208g, 208h) for preventing warpage may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the metal structure (208f, 208g, 208h) for preventing warpage described above are not limited by this embodiment.

[0068] FIG. 11 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction from the position shown in FIG. 8. Referring to FIG. 11, a metal structure (208i, 208j) for preventing warpage may be located on a protective layer (202) formed on the upper surface of a semiconductor chip (200, not shown). A TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The metal structure (208j) for preventing warpage may be located around the TSVs (204) formed in the center of the semiconductor chip (200). The metal structure (208j) for preventing warpage may have an 'L' shape, similar to the shape of the corners of the semiconductor chip (200). The metal structure (208j) for preventing warpage may be located between the four corners of the semiconductor chip (200) and the TSV (204). The anti-warpage metal structure (208i) may have an 'L' shape, similar to the shape of the corners of the semiconductor chip (200). The anti-warpage metal structure (208i) may be positioned between the four corners of the semiconductor chip (200) and the anti-warpage metal structure (208j). Additionally, the anti-warpage metal structure (208i, 208j) may be positioned above or below a virtual horizontal line (500) as needed. The shape, thickness, and length of the anti-warpage metal structure (208i, 208j) are not limited by this embodiment.

[0069] FIG. 12 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z-axis direction from the position shown in FIG. 8. Referring to FIG. 12, a metal structure (208) for preventing warpage may be located on a semiconductor chip of an HBM that includes a TSV array among the semiconductor devices. A TSV array may refer to an area on a semiconductor chip where TSVs are aligned and densely packed in a specific area. FIG. 12 to 17 illustrate embodiments of the present invention for a semiconductor device including a TSV array. A TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The metal structure (208) for preventing warpage may be located in a rectangular shape along the perimeter of the semiconductor chip around the TSV (204) constituting the TSV array. Additionally, if necessary, a metal structure (208i, 208j) for preventing warpage may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the metal structure (208i, 208j) for preventing warpage are not limited by this embodiment.

[0070] FIGS. 13 and 14 are plan views of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the position shown in FIG. 8. Referring to FIG. 13, the anti-warpage metal structure (208k) may be configured such that the length in one axis (Y-axis) direction is longer than the length in another axis (X-axis) direction. The TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The anti-warpage metal structure (208k) may be located on the surface of a portion of the TSV array where no TSVs are formed. As shown in FIG. 13, one or more anti-warpage metal structures (208k) may be located to the left or right in the X-axis direction relative to the TSVs (204).

[0071] Referring to FIG. 14, the anti-warpage metal structure (208n) can be configured such that the length in one axis (Y-axis) is longer than the length in another axis (X-axis), similar to the anti-warpage metal structure (208k) in FIG. 13. However, two or more anti-warpage metal structures (208n) may be positioned in one axis (Y-axis) direction. One or more anti-warpage metal structures (208n) may be positioned to the left or right in the X-axis direction relative to the TSVs (not shown, 204).

[0072] If necessary, a metal structure (208k, 208n) for preventing warpage may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the metal structure (208k, 208n) for preventing warpage are not limited by this embodiment.

[0073] FIG. 15 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction from the position shown in FIG. 8. Referring to FIG. 15, the warpage prevention metal structure (208m) may be configured such that the length in one axis (X-axis) direction is longer than the length in another axis (Y-axis) direction. The warpage prevention metal structure (208m) may be positioned at regular intervals in the Y-axis direction in the parts where TSVs are not formed on the left and right sides of the TSV array relative to the X-axis direction. The TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The warpage prevention metal structure (208p) may be positioned on the upper or lower surface in the Y-axis direction of the TSV array where TSVs (204) are not formed on the protective layer (202) formed on the semiconductor chip (200). The anti-warpage metal structure (208p) may be configured to have a longer length in the direction of one axis (X-axis) compared to the anti-warpage metal structure (208n). If necessary, the anti-warpage metal structure (208m) may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the anti-warpage metal structure (208m) are not limited by this embodiment.

[0074] FIG. 16 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z axis direction at the same position as FIG. 8. Referring to FIG. 16, a metal structure (208r, 208q) for preventing warpage may be located on a protective layer (202) formed on the upper surface of a semiconductor chip (200, not shown). A TSV (204, not shown) may be located below the upper conductive pad (206) in the Z-axis direction. The metal structure (208q) for preventing warpage may be configured in a frame shape that surrounds the TSVs (204) of the previously described TSV array. The metal structure (208r) for preventing warpage may be configured in a frame shape that surrounds the TSV array and the frame-shaped metal structure (208q) for preventing warpage. The metal structures (208q, 208r) for preventing warpage in FIG. 16 are rectangular in shape and may have a shape similar to the perimeter of a semiconductor chip (200, not shown). That is, the metal structures (208q, 208r) for preventing warpage may each have two sides in the X-axis direction and two sides in the Y-axis direction. Therefore, even if the direction in which warpage occurs is not uniform, warpage can be reduced through the metal structures (208q, 208r) for preventing warpage. Additionally, if necessary, the metal structures (208q, 208r) for preventing warpage may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the metal structures (208q, 208r) for preventing warpage described above are not limited by this embodiment.

[0075] FIG. 17 is a plan view of a semiconductor device, which is an embodiment of the present invention, when viewed in the -Z-axis direction at the position shown in FIG. 8. Referring to FIG. 17, the anti-warpage metal structure may be configured in a grid shape that surrounds the TSVs (204) constituting the TSV array. The grid shape may be formed by an arrangement of squares consisting of an anti-warpage metal structure (208t) in the direction of one axis (X-axis) and an anti-warpage metal structure (208s) in the direction of the other axis (Y-axis). The size and shape of the squares may vary depending on the shape of the surface of the semiconductor chip and the location of the TSVs. Additionally, if necessary, the anti-warpage metal structure (208s, 208t) may be positioned above or below a virtual horizontal line (500). The shape, thickness, and length of the anti-warpage metal structure (208q, 208r) described above are not limited by this embodiment. Although embodiments of the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above are illustrative in all respects and should not be understood as restrictive. Explanation of the symbols

[0076] 100, 200, 210, 220, 230, 240, 250: Semiconductor chip 300: Upper semiconductor chip 201, 211, 221, 231, 241, 251: Internal boards 102, 202, 212, 222, 232, 242, 252: Protection layer 103, 203, 213, 223, 233, 243, 253: Through-Screening Via (TSV) 105, 205, 215, 225, 235, 245, 255: Challenging bumps 106, 206, 216, 226, 236, 246, 256: Upper conductive pad 107, 207, 217, 227, 237, 247, 257, 307: Lower conductive pad 208, 218, 228, 238, 248, 258: Metal structures for warpage prevention 400: Underfill material 500: Imaginary Horizon

Claims

Claim 1 A semiconductor device comprising: a substrate; a plurality of first semiconductor chips sequentially stacked and provided on the substrate, wherein a first TSV (Through Silicon Via) is provided through the substrate; a plurality of second semiconductor chips sequentially stacked and disposed on the plurality of first semiconductor chips, wherein a second TSV formed on the same vertical line as the first TSV is provided through the substrate; a conductive pad formed on each of the first TSV and the second TSV to electrically connect the plurality of first semiconductor chips and the plurality of second semiconductor chips; an upper semiconductor chip provided on the plurality of second semiconductor chips; and a metal structure for preventing warpage, which is selectively provided on either the upper surface of the plurality of first semiconductor chips or the upper surface of the plurality of second semiconductor chips; wherein the coefficient of thermal expansion of the metal structure for preventing warpage is greater than the coefficient of thermal expansion of the plurality of first semiconductor chips and the plurality of second semiconductor chips. Claim 2 A semiconductor device according to claim 1, comprising a metal structure for preventing warpage located on the upper surface of the plurality of first semiconductor chips or the plurality of second semiconductor chips, and positioned to surround the periphery of the first TSV or the second TSV. Claim 3 A semiconductor device according to claim 2, comprising a metal structure for preventing warpage configured in a frame shape, positioned to surround the periphery of the first TSV or the second TSV. Claim 4 In claim 1, the metal structure for preventing warpage is a semiconductor device having the same height as the conductive pad. Claim 5 A semiconductor device according to claim 1, further comprising a conductive bump positioned between the conductive pad formed at the top of the first TSV and the conductive pad formed at the bottom of the second TSV, and electrically connected to each conductive pad. Claim 6 A semiconductor device comprising: a substrate; a plurality of internal substrates provided on the substrate and including semiconductor elements and sequentially stacked; an upper substrate provided on the plurality of internal substrates; a Through Silicon Via (TSV) formed to vertically penetrate each of the plurality of internal substrates; a protective layer located on the upper surface of the plurality of internal substrates to surround the side of the TSV; a conductive pad disposed on the TSV; and a metal structure for preventing warpage located on the protective layer of some of the internal substrates among the plurality of internal substrates and not electrically connected to the semiconductor elements of the internal substrates; wherein the plurality of internal substrates are divided into upper internal substrates and lower internal substrates by a virtual horizontal line separating the plurality of internal substrates, and the metal structure for preventing warpage is provided on one of the upper internal substrates or the lower internal substrates, the coefficient of thermal expansion of the metal structure for preventing warpage is greater than the coefficient of thermal expansion of the plurality of internal substrates, and the plurality of internal substrates includes four or more internal substrates. Claim 7 A semiconductor device according to claim 6, wherein the area of ​​the anti-warpage metal structure becomes narrower as the position of the anti-warpage metal structure is closer to the perimeter of the upper internal substrates or the lower internal substrates. Claim 8 delete Claim 9 In claim 6, the metal structure for preventing warpage has a rod shape that is long in one direction, and each of the metal structures for preventing warpage is arranged to be parallel to each other with respect to the long direction of one direction in a semiconductor device. Claim 10 In claim 6, the warpage prevention metal structure has a grid shape formed by weaving the warpage prevention metal structures extending in one axial direction or another axial direction, and is a semiconductor device arranged along the shape of the plurality of internal substrates around the TSV.

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