Circuit board for smart IC and chip package including the same

Abstract

A circuit board according to an embodiment includes an insulating layer; and a circuit pattern layer disposed on the insulating layer, wherein the circuit pattern layer includes a first surface facing the insulating layer and a second surface opposite to the first surface, and the first surface of the circuit pattern layer has an arithmetic mean roughness (Ra) in the range of 0.5 μm to 0.9 μm, and the arithmetic mean roughness of the second surface of the circuit pattern layer is smaller than the arithmetic mean roughness of the first surface of the circuit pattern layer.

Description

Technology Field

[0001] The embodiment relates to a circuit board, and in particular to a circuit board applied to a smart IC and a chip package including the same. Background Technology

[0002] A smart IC card is a card embedded with at least one integrated circuit chip or chip module. More specifically, a smart IC card refers to a device capable of performing simple tasks independently by embedding a central processing unit, such as a microprocessor, which is typically made of a plastic-based resin in the shape of a thin card, and a memory unit capable of storing information of a predetermined capacity, as well as inputting, outputting, and processing information without a separate power supply. To implement such a smart IC card, a chip package is required in which a thin semiconductor chip is mounted on a circuit pattern of a printed circuit board, and a contact terminal is formed on the opposite side of the printed circuit board so that a circuit pattern electrically connected to the semiconductor chip can be connected to an external card reader or the like in a contact- or contactless manner; and a card body on which the chip package is mounted is required.

[0003] The smart IC card described above is widely used in various fields, such as credit cards, USIM cards, security cards, and identification cards. The circuit board applied to such a smart IC card includes an insulating layer and a circuit pattern layer disposed on the insulating layer.

[0004] At this time, the circuit pattern layer includes a bonding portion and a contact portion. The bonding portion may refer to the upper surface or a first surface of the circuit pattern layer. For example, the bonding portion may refer to a surface of the circuit pattern layer connected to an IC chip. Additionally, the contact portion may refer to a lower surface or a second surface of the circuit pattern layer. For example, the contact portion may refer to a surface of the circuit pattern layer that contacts an external device (e.g., a card reader).

[0005] In addition, a surface treatment layer is disposed on the bonding portion and the contact portion of the circuit pattern layer, respectively. The surface treatment layer is formed to impart wire bondability, corrosion resistance, oxidation resistance, wear resistance, and hardness to the bonding portion and the contact portion of the circuit pattern layer at a certain level or higher.

[0006] However, conventional circuit boards as described above necessarily require the formation of a surface treatment layer on the circuit pattern layer, which leads to problems such as a complex manufacturing process and increased manufacturing costs. Additionally, conventional circuit boards have the problem of increasing the overall thickness by the thickness of the surface treatment layer.

[0007] (Patent Document 1) KR 10-2002-0011361 A The problem to be solved

[0008] In the embodiment, a circuit board of a new structure and a chip package including the same are to be provided.

[0009] In addition, the embodiment provides a circuit board in which a surface treatment layer on at least one of the bonding portion and contact portion of a circuit pattern layer is removed, and a chip package including the same.

[0010] In addition, the embodiment aims to provide a circuit board capable of being slimmed down by drastically reducing the overall thickness and a chip package including the same.

[0011] In addition, the embodiment aims to provide a circuit board including a circuit pattern layer having different surface roughness on the top, side, and bottom surfaces, and a chip package including the same. means of solving the problem

[0012] A circuit board for a smart IC according to an embodiment comprises an insulating layer having at least one first through hole; and a circuit pattern layer disposed on the insulating layer, wherein the circuit pattern layer comprises a first surface having an adhesive portion facing the insulating layer and superimposed perpendicularly to the insulating layer, and a bonding portion superimposed perpendicularly to the first through hole and exposed through the first through hole, and a second surface opposite to the first surface, wherein the first surface of the circuit pattern layer has an arithmetic mean roughness (Ra) in the range of 0.5 μm to 0.9 μm, and the arithmetic mean roughness of the second surface of the circuit pattern layer satisfies a range between 0.03 μm and 0.08 μm.

[0013] In addition, the arithmetic mean roughness of the second surface of the circuit pattern layer satisfies a range between 0.03㎛ and 0.08㎛.

[0014] In addition, the first surface of the circuit pattern layer has a 10-point average roughness (Rz) in the range of 1.5 μm to 2.5 μm, and the second surface of the circuit pattern layer has a 10-point average roughness in the range of 0.1 μm to 0.4 μm.

[0015] Additionally, the circuit pattern layer includes a third surface which is a side between the first surface and the second surface, and the arithmetic mean roughness of the third surface of the circuit pattern layer is smaller than the arithmetic mean roughness of the first surface of the circuit pattern layer and larger than the calculated average roughness of the second surface of the circuit pattern layer.

[0016] In addition, the arithmetic mean roughness of the third surface of the circuit pattern layer satisfies the range of 0.1㎛ to 0.3㎛.

[0017] In addition, the 10-point average illuminance of the third surface of the circuit pattern layer is smaller than the 10-point average illuminance of the first surface of the circuit pattern layer and larger than the 10-point average illuminance of the second surface of the circuit pattern layer.

[0018] In addition, the 10-point average roughness of the third surface of the circuit pattern layer satisfies the range of 0.8㎛ to 1.3㎛.

[0019] Additionally, the circuit pattern layer is formed of an alloy, and the alloy comprises a first metal having a content in the range of 60 weight% to 80 weight%, a second metal having a content in the range of 10 weight% to 22 weight%, a third metal having a content in the range of 3 weight% to 20 weight%, and a fourth metal having a content in the range of 3 weight% to 10 weight%, wherein the first metal comprises either nickel (Ni) or iron (Fe), the second metal comprises chromium (Cr), the third metal comprises one other than the first metal among nickel (Ni) and iron (Fe), and the fourth metal comprises any one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy.

[0020] In addition, the alloy further comprises a fifth metal having a content in the range of 1 weight% to 5 weight%, and the fifth metal is any one of manganese (Mn), tin (Sn), zinc (Zn), and an alloy comprising at least two of these.

[0021] Additionally, the insulating layer includes at least one first through hole, and the area of ​​the first surface of the circuit pattern layer that overlaps perpendicularly with the first through hole is a bonding portion, and the second surface of the circuit pattern layer is a contact portion.

[0022] Additionally, the circuit board includes a bonding sheet disposed between the insulating layer and the circuit pattern layer, and the bonding sheet includes a second through hole that overlaps vertically with the first through hole.

[0023] Meanwhile, a chip package according to an embodiment includes an insulating layer having at least one first through hole; a circuit pattern layer disposed on the insulating layer and having a first surface facing the insulating layer and a second surface opposite to the first surface; an IC chip attached to the lower surface of the insulating layer; and a connecting member connecting the IC chip and the circuit pattern layer, wherein the first surface of the circuit pattern layer has an arithmetic mean roughness (Ra) in the range of 0.5 μm to 0.9 μm, and the second surface of the circuit pattern layer has an arithmetic mean roughness in the range of 0.03 μm to 0.08 μm, and the connecting member is directly connected to the second surface of the circuit pattern layer that is vertically superimposed with the first through hole.

[0024] In addition, the first surface of the circuit pattern layer has a 10-point average roughness (Rz) in the range of 1.5 μm to 2.5 μm, and the second surface of the circuit pattern layer has a 10-point average roughness in the range of 0.1 μm to 0.4 μm. Effects of the invention

[0025] In the embodiment, a circuit pattern layer is formed using an alloy manufactured through a rolling process. At this time, the circuit pattern layer has a problem in that its adhesion to the insulating layer is reduced as it is manufactured through a rolling process. Accordingly, in the embodiment, a surface roughness of a certain level or higher is applied to the lower surface of the circuit pattern layer, which faces the insulating layer, among the upper and lower surfaces. Furthermore, the upper surface of the circuit pattern in the embodiment is the outermost exposed part in an application where the circuit board of the embodiment is applied. Accordingly, in the embodiment, the upper surface of the circuit pattern layer is made to have a surface roughness smaller than that of the lower surface of the circuit pattern layer. Accordingly, in the embodiment, by applying a surface roughness of a certain level or higher to the lower surface of the circuit pattern layer, adhesion between the circuit pattern layer and the insulating layer can be secured, thereby improving the physical reliability of the circuit board and the chip package. Additionally, in the embodiment, by making the upper surface of the circuit pattern layer have a surface roughness smaller than that of the lower surface of the circuit pattern layer, design problems in the application's usage environment can be resolved. In addition, in the embodiment, if the upper surface of the circuit pattern layer has a certain level or higher, problems such as causing injury to the user's body in the application usage environment can be resolved. Through this, the embodiment can ensure product stability and further improve user satisfaction.

[0026] Meanwhile, in the embodiment, a circuit pattern layer is formed using an alloy comprising nickel (Ni), chromium (Cr), and iron (Fe), and including at least one metal among silver (Ag), silicon (Si), and alloys thereof. Accordingly, the circuit pattern layer in the embodiment may have wear resistance, corrosion resistance, oxidation resistance, and hardness above a certain level. Through this, in the embodiment, the surface treatment layer that must be formed on the contact portion of the circuit pattern layer may be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs. Furthermore, the circuit pattern layer in the embodiment may have wire bonding properties above a certain level. Through this, in the embodiment, not only the surface treatment layer that must be formed on the contact portion of the circuit pattern layer but also the surface treatment layer that must be formed on the bonding portion of the circuit pattern layer may be omitted or removed, thereby further simplifying the manufacturing process of the circuit board and further reducing manufacturing costs. Brief explanation of the drawing

[0027] Figure 1 is a diagram showing a chip package according to a comparative example. FIG. 2 is a drawing showing a circuit board according to a first embodiment. Figure 3 is a top view of the circuit board of Figure 2. Figure 4 is a plan view of the circuit board of Figure 2 viewed from the bottom. FIG. 5 is a diagram illustrating a method for imparting surface roughness to a circuit pattern layer according to an embodiment. Figure 6 is a drawing showing a surface roughness image of a circuit pattern layer according to an embodiment. Figure 7 is a diagram showing the surface roughness of a circuit pattern layer according to an embodiment. FIGS. 8 and 9 are drawings illustrating a method for measuring the surface roughness of a circuit pattern layer according to an embodiment. FIG. 10 is a drawing showing a circuit board according to a second embodiment. FIG. 11 is a drawing showing a chip package according to an embodiment. Specific details for implementing the invention

[0028] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" for components used in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate easy understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0029] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0030] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0031] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0032] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0035] - Comparison Example -

[0036] Before describing the embodiments, we will describe a comparative example that is compared with the circuit board of the embodiments of the present invention.

[0038] Figure 1 is a diagram showing a chip package according to a comparative example.

[0039] Referring to FIG. 1, a chip package according to a comparative example includes an insulating layer (10), a circuit pattern layer (20), a first surface treatment layer (30), a second surface treatment layer (40), an adhesive layer (50), an IC chip (60), and a connecting member (70).

[0040] A chip package of a comparative example includes an insulating layer (10), and a circuit pattern layer (20) is disposed on at least one surface of the insulating layer (10).

[0041] At this time, the circuit pattern layer (20) in the comparative example is a copper layer containing pure copper.

[0042] The insulating layer (10) includes at least one through hole (15). The circuit pattern layer (20) includes a bonding portion that overlaps vertically with the through hole (15). For example, at least a portion of the circuit pattern layer (20) overlaps vertically with the through hole (15), and the lower surface of the circuit pattern layer (20) that overlaps vertically with the through hole (15) functions as a bonding portion that is electrically connected to an IC chip (60).

[0043] In addition, the upper surface of the circuit pattern layer (20) functions as a contact part, such as a connector, that contacts an external device (e.g., a card reader).

[0044] At this time, different characteristics are required for the bonding portion and the contact portion of the circuit pattern layer (20).

[0045] For example, the bonding portion of the circuit pattern layer (20) requires a wire bonding capability of a certain level or higher for bonding a connecting member (70) that is electrically connected to the IC chip (60).

[0046] In addition, the contact portion of the circuit pattern layer (20) is exposed outside the chip package, and accordingly, corrosion resistance, oxidation resistance, wear resistance, and hardness of a certain level or higher are required for continuous connection with an external device.

[0047] Accordingly, in the circuit board of the comparative example, a first surface treatment layer (30) is formed on the bonding portion of the circuit pattern layer (20), and a second surface treatment layer (40) is formed on the contact portion of the circuit pattern layer (20). The first surface treatment layer (30) and the second surface treatment layer (40) each include a nickel metal layer (Ni) and a gold metal layer (Au).

[0048] The nickel metal layer above acts as a barrier that prevents the oxidation of copper (Cu) forming the circuit pattern layer (20) and prevents the copper (Cu) from diffusing into the gold metal layer. Additionally, the gold metal layer of the first surface treatment layer (30) is formed on the outermost surface of the bonding portion of the circuit pattern layer (20), thereby providing wire bonding properties of a certain level or higher to the bonding portion. Furthermore, the gold metal layer of the second surface treatment layer (40) is formed on the outermost surface of the contact portion of the circuit pattern layer (20), thereby providing corrosion resistance, oxidation resistance, wear resistance, and hardness of a certain level or higher to the contact portion.

[0049] However, the circuit board of the comparative example above must necessarily form a first surface treatment layer (30) and a second surface treatment layer (40) on the bonding portion and the contact portion of the circuit pattern layer (20), respectively, and there is a problem that the manufacturing process becomes complex and the manufacturing cost increases accordingly.

[0050] In addition, the circuit board of the comparative example reduces the thickness of the gold metal layer of the second surface treatment layer (40) for the purpose of reducing the manufacturing cost. However, when the thickness of the gold metal layer is reduced, wear of the gold metal layer occurs during long-term use of the circuit board, which causes a problem that damages the product design.

[0052] Meanwhile, in the comparative example, the circuit pattern layer (20) is formed from an aluminum alloy to remove at least one of the first and second surface treatment layers as described above. However, the aluminum alloy has low strength. Accordingly, in order for the contact portion of the circuit pattern layer to have corrosion resistance, oxidation resistance, wear resistance, and hardness of a certain level or higher, the thickness of the aluminum alloy must be 80 μm or more.

[0053] And, if the thickness of the aluminum alloy exceeds 80㎛, the overall thickness of the circuit board increases accordingly, and the line width or pitch of the circuit pattern layer (20) increases, thereby reducing the circuit integration density.

[0055] Accordingly, the embodiment provides a new circuit board to solve the problems of the comparative example described above. For example, the embodiment allows for the reduction of the overall thickness of the circuit board, the simplification of the manufacturing process of the circuit board, and the reduction of manufacturing costs. Furthermore, the embodiment enables the removal of at least one surface treatment layer among the surface treatment layers disposed on the bonding portion and the contact portion of the circuit pattern layer. For example, the embodiment enables the removal of the surface treatment layer by forming the circuit pattern layer using a metal alloy layer that satisfies wire bondability, corrosion resistance, oxidation resistance, wear resistance, and hardness at a certain level or higher.

[0057] Hereinafter, a circuit board according to an embodiment and a chip package including the same will be described. At this time, the chip package can be applied to various applications. For example, the chip package can be applied to electronic devices including smart chips, printers, camera modules, etc. Furthermore, the electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited thereto, and it is understood that it may be any other electronic device that processes data in addition to these.

[0059] - Example of Implementation -

[0060] FIG. 2 is a drawing showing a circuit board according to a first embodiment, FIG. 3 is a plan view of the circuit board of FIG. 2 viewed from the top, and FIG. 4 is a plan view of the circuit board of FIG. 2 viewed from the bottom.

[0062] Referring to FIGS. 2 to 4, the circuit board according to the first embodiment includes an insulating layer (110) and a circuit pattern layer (120).

[0063] The insulating layer (110) comprises an insulating material. For example, the insulating layer (110) may comprise any one of the insulating materials PET (polyethylene terephthalate), PC (polycarbonate), PES (polyether sulfone), PI (polyimide), or PMMA (polymethyl methacrylate). Alternatively, the insulating layer (110) may comprise a reel-type prepreg made of glass fabric and epoxy resin, but is not limited thereto.

[0064] The insulating layer (110) has a thickness in the range of 60 µm to 120 µm, or a thickness in the range of 70 µm to 110 µm, or a thickness in the range of 80 µm to 100 µm.

[0065] If the thickness of the insulating layer (110) is less than 60 μm, the rigidity of the circuit board is weakened, and accordingly, the bending characteristics of the circuit board may be reduced. If the thickness of the insulating layer (110) is less than 60 μm, the circuit pattern layer (120) may not be stably formed on the circuit board. For example, if the thickness of the insulating layer (110) is less than 60 μm, the processability in the process of forming the circuit pattern layer (120) may be reduced.

[0066] If the thickness of the insulating layer (110) exceeds 120 μm, the overall thickness of the circuit board increases, and the thickness of the chip package may increase accordingly.

[0067] The insulating layer (110) includes at least one through hole (115).

[0068] The through hole (115) penetrates the upper and lower surfaces of the insulating layer (110). The through hole (115) can be formed by any one of mechanical, laser, and chemical processing methods.

[0069] A circuit pattern layer (120) is formed on the insulating layer (110). The circuit pattern layer (120) may be formed on a first surface or an upper surface of the insulating layer (110).

[0070] The circuit pattern layer (120) is an alloy layer. For example, the circuit pattern layer (120) is formed from an alloy with nickel (Ni) or iron (Fe) as the main component. For example, the circuit pattern layer (120) may be an alloy layer formed by a rolling method.

[0071] The circuit pattern layer (120) has a thickness in the range of 20 µm to 50 µm. For example, the circuit pattern layer (120) has a thickness in the range of 25 µm to 45 µm. For example, the circuit pattern layer (120) has a thickness of 30 µm to 40 µm. If the thickness of the circuit pattern layer (120) is less than 20 µm, the resistance value of the circuit pattern layer (120) increases, and the signal loss may increase accordingly. For example, if the thickness of the circuit pattern layer (120) is less than 20 µm, the signal transmission characteristics of the circuit board may be degraded. If the thickness of the circuit pattern layer (120) exceeds 50 µm, it is difficult to miniaturize the circuit pattern layer (120), and the circuit integration density may decrease accordingly. The thickness of the circuit pattern layer (120) exceeds 50 μm, and the thickness of the circuit pattern layer (120) increases, and the overall thickness of the circuit board can increase accordingly.

[0072] In this embodiment, the thickness of the circuit pattern layer (120) is 50 μm or less, and the surface treatment layer formed on at least one of the bonding portion and the contact portion of the circuit pattern layer (120) can be omitted or removed. This can be achieved by the characteristics of the alloy forming the circuit pattern layer (120) described below.

[0073] Meanwhile, the circuit pattern layer (120) includes a first surface, a second surface, and a third surface. The first surface of the circuit pattern layer (120) refers to a surface facing the insulating layer (110). For example, the first surface of the circuit pattern layer (120) may be a surface facing the upper surface of the insulating layer (110). For example, the first surface of the circuit pattern layer (120) may refer to the lower surface (120S2) of the circuit pattern layer (120). The second surface of the circuit pattern layer (120) refers to a surface opposite to the first surface of the circuit pattern layer (120). For example, the second surface of the circuit pattern layer (120) may refer to the upper surface (120S1) opposite to the lower surface (120S2) of the circuit pattern layer (120). For example, the third surface of the circuit pattern layer (120) refers to the side surface (120S3) between the upper surface (120S1) and the lower surface (120S2).

[0074] Specifically, the circuit pattern layer (120) includes an upper surface (120S1), a lower surface (120S2), and a side surface (120S3). The lower surface (120S2) of the circuit pattern layer (120) may correspond to a 'bonding portion'. The upper surface (120S1) of the circuit pattern layer (120) may correspond to a 'contact portion' described below.

[0075] At this time, the circuit pattern layer (120) may be formed as a metal layer manufactured by a rolling method. For example, the circuit pattern layer (120) includes a rolled alloy. At this time, the alloy forming the circuit pattern layer (120) refers to either a first alloy having nickel (Ni) as the main component or a second alloy having iron (Fe) as the main component.

[0076] The circuit pattern layer (120) refers to a lower surface (120S2) or a bonding portion that is connected to an IC chip (160) in a chip package. For example, the bonding portion of the circuit pattern layer (120) refers to a portion that overlaps vertically with a through hole (115) in the lower surface (120S2) of the circuit pattern layer (120).

[0077] Additionally, the upper surface (120S1) or contact portion of the circuit pattern layer (120) refers to an area positioned at the outermost edge on the circuit board and chip package. For example, the upper surface (120S1) or contact portion of the circuit pattern layer (120) may refer to an area exposed to the outside from the circuit board and chip package.

[0078] That is, the lower surface (120S2) of the circuit pattern layer (120) that overlaps vertically with the through hole (115) of the insulating layer (110) functions as a bonding part, and the upper surface (120S1) of the circuit pattern layer (120) functions as a contact part.

[0080] At this time, the circuit pattern layer (120) is required to have wire bonding properties, corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level. For example, the lower or bonding portion of the circuit pattern layer (120) is required to have wire bonding properties above a certain level. In addition, the upper surface (120S1) or contact portion of the circuit pattern layer (120) is required to have corrosion resistance, oxidation resistance, wear resistance, and hardness above a certain level.

[0081] Accordingly, in the comparative example, a first surface treatment layer (30) is formed on the bonding portion of the circuit pattern layer, and a second surface treatment layer (40) is formed on the contact portion of the circuit pattern layer.

[0082] Alternatively, in the embodiment, a circuit pattern layer (120) is formed using either of the first and second alloys having a certain level of corrosion resistance, oxidation resistance, wear resistance, hardness, and Y-bonding properties. Through this, in the embodiment, the surface treatment layer formed on the bonding portion and contact portion of the circuit pattern layer (120) can be omitted or removed.

[0083] That is, in the embodiment, by changing the content of metals in the alloy forming the circuit pattern layer (120), the circuit pattern layer (120) itself is made to have a certain level of corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties without the surface treatment layer. This can be achieved by the types of metals constituting the circuit pattern layer (120) and their content as described below.

[0084] Below, the composition ratio of metals in the alloy forming the circuit pattern layer (120) will be explained.

[0085] At this time, the circuit pattern layer (120) may be formed from either the first alloy or the second alloy. The first alloy has nickel (Ni) as its main component, and the second alloy has iron (Fe) as its main component.

[0087] In the embodiment, the circuit pattern layer (120) formed from either the first alloy or the second alloy may have a resistance value in the range of 0.07 Ω to 0.35 Ω. Additionally, in the embodiment, the circuit pattern layer (120) formed from either the first alloy or the second alloy may have an etching rate (㎛ / min) in the range of 30 ㎛ / min to 70 ㎛ / min. Additionally, in the embodiment, the circuit pattern layer (120) formed from either the first alloy or the second alloy may have a surface roughness change rate in the range of 0.2% to 6.0%. Furthermore, in the embodiment, the circuit pattern layer (120) formed from either the first alloy or the second alloy may have a wire bonding property of 4 gf or more. Additionally, in the embodiment, the circuit pattern layer (120) formed from either the first alloy or the second alloy may have a value of 0.28 ㎛ / cm 2The nickel leaching amount may be less than / week, and furthermore, the leached nickel may not be detected at all. In addition, the circuit pattern layer (120) formed from either the first alloy or the second alloy in the embodiment may have a plating adhesion strength of 5B or higher. This can be achieved by the content of the metals constituting the first alloy and the content of the metals constituting the second alloy as described below. This will be explained in detail.

[0089] - First Alloy -

[0090] The circuit pattern layer (120) in the first embodiment can be formed from a first alloy having nickel (Ni) as the main component.

[0091] The first alloy has corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties above a certain level.

[0092] That is, the first alloy forming the circuit pattern layer (120) has nickel (Ni) as its main component. For example, the nickel (Ni) content in the first alloy forming the circuit pattern layer (120) satisfies the range of 60 wt% to 80 wt%. For example, the nickel (Ni) content of the first alloy is 65 wt% to 78 wt% or 70 wt% to 75 wt%.

[0093] If the nickel (Ni) content in the first alloy is less than 60 weight%, the corrosion resistance, oxidation resistance, wear resistance, hardness, and wire bonding properties of the circuit pattern layer (120) may be reduced. Accordingly, a surface treatment layer must be formed on the upper surface (120S1) or contact portion of the circuit pattern layer (120), which necessitates a complex manufacturing process, an increase in the thickness of the circuit board, and an increase in manufacturing costs.

[0094] Specifically, if the nickel (Ni) content in the first alloy is less than 60 weight%, the change rate (%) of the surface roughness of the circuit pattern layer (120) may exceed 10%. The change rate (%) of the surface roughness is related to the corrosion resistance, oxidation resistance, and wear resistance of the circuit pattern layer (120).

[0095] Accordingly, as the nickel (Ni) content in the first alloy forming the circuit pattern layer (120) has a range of 60 weight% to 80 weight%, the surface roughness change rate (%) can be 10% or less, preferably 8% or less, and more preferably 5% or less.

[0096] In addition, if the nickel (Ni) content in the first alloy exceeds 80 weight%, the etching rate (μm / min) in the process of forming the circuit pattern layer (120) using the first alloy may decrease. That is, if the nickel (Ni) content in the first alloy exceeds 80 weight%, the hardness of the first alloy is too high, so an etching rate (μm / min) within a certain range may not be obtained in the process of forming the circuit pattern layer (120). In addition, if the nickel (Ni) content in the first alloy exceeds 80 weight%, a problem may occur in which nickel ions leach out to the surface of the circuit pattern layer (120) formed by the first alloy. That is, if the nickel (Ni) content in the first alloy exceeds 80 weight%, the effect of preventing nickel ion leachation by chromium (Cr), which is described below, may decrease. In addition, if the nickel (Ni) content in the first alloy is less than 60 weight% or exceeds 80 weight%, the content of other metals (e.g., chromium or iron) decreases or increases accordingly, and as a result, a problem arises because the content of the other metals does not satisfy the range described below.

[0097] Meanwhile, the first alloy forming the circuit pattern layer (120) includes chromium (Cr). The content of chromium (Cr) in the first alloy satisfies a range of 10 wt% to 22 wt%. For example, the content of chromium (Cr) in the first alloy may satisfy a range of 11 wt% to 21 wt%, or 12 wt% to 18 wt%.

[0098] If the chromium (Cr) content in the first alloy is less than 10 weight%, the amount of nickel leaching to the surface of the circuit pattern layer (120) formed from the first alloy may increase. That is, a surface treatment layer is not formed on the upper surface (120S1) or the contact portion of the circuit pattern layer (120) in the embodiment. Accordingly, the upper surface (120S1) or the contact portion of the circuit pattern layer (120) in the embodiment is exposed to the outside. Specifically, in the usage environment of an application to which the circuit board and chip package of the embodiment are applied, the upper surface (120S1) or the contact portion of the circuit pattern layer (120) is exposed to the user as is. At this time, if nickel ions leach out from the circuit pattern layer (120), reliability problems occur. Specifically, if the nickel ions leach out, it causes problems such as causing skin allergies in the user. Accordingly, as in the embodiment, when the circuit pattern layer (120) is formed from an alloy containing nickel (Ni) and the surface treatment layer disposed on the contact portion of the circuit pattern layer (120) is removed, nickel ions must not be leached to the surface of the circuit pattern layer (120). At this time, the ionization energy of the chromium (Cr) is smaller than the ionization energy of the nickel (Ni). Accordingly, when metal ions constituting the first alloy are leached to the surface of the circuit pattern layer (120), the chromium ions are leached before the nickel ions. And, as the chromium ions are leached before the nickel ions, it is possible to prevent the nickel ions from leaching out to the outside. That is, the chromium (Cr) functions to prevent the nickel (Ni) from leaching to the surface of the circuit pattern layer (120).

[0099] At this time, if the content of chromium (Cr) in the first alloy is less than 10 weight%, the effect of preventing nickel (Ni) from leaching out by the chromium (Cr) is reduced, and consequently, product reliability issues may arise due to nickel ions leaching out to the outside. Accordingly, the first alloy forming the circuit pattern layer (120) in the embodiment may contain chromium (Cr) with a content of 10 weight% or more.

[0100] Meanwhile, if the chromium (Cr) content in the first alloy exceeds 22 weight%, the hardness of the circuit pattern layer (120) increases, and the etching rate (㎛ / min) of the circuit pattern layer (120) may decrease accordingly. Additionally, if the chromium (Cr) content of the circuit pattern layer (120) exceeds 22 weight%, the wire bonding performance of the circuit pattern layer (120) may decrease. Furthermore, if the wire bonding performance of the circuit pattern layer (120) decreases, the surface treatment layer on the lower surface (120S2) or the bonding portion of the circuit pattern layer (120) may not be omitted or removed.

[0101] In addition, if the content of chromium (Cr) in the first alloy is less than 10 weight% or exceeds 22 weight%, the content of other metals (e.g., nickel or iron) decreases or increases by a corresponding amount, and as a result, a problem arises in that the content of other metals does not satisfy the optimal range described herein.

[0102] Meanwhile, the first alloy forming the circuit pattern layer (120) comprises iron (Fe). The content of iron (Fe) in the first alloy satisfies a range of 3 wt.% to 20 wt.%. The content of iron (Fe) in the first alloy may satisfy a range of 5 wt.% to 15 wt.%, or 7 wt.% to 11 wt. In the first embodiment, the iron (Fe) functions to improve the rollability (or ductility) of the first alloy.

[0103] At this time, if the iron (Fe) content in the first alloy is less than 3 weight%, the rollability of the first alloy is reduced, and accordingly, it may be difficult to manufacture the thickness of the first alloy, and furthermore the thickness of the circuit pattern layer (120), to 50 μm or less.

[0104] In addition, if the iron (Fe) content in the first alloy exceeds 20 weight%, the nickel (Ni) or iron (Fe) content decreases accordingly, and the nickel leaching amount or the rate of change in surface roughness (%) may increase. In addition, if the iron (Fe) content in the first alloy is less than 3 weight% or exceeds 20 weight%, the content of other metals (e.g., nickel or chromium) decreases or increases by a corresponding amount, and as a result, a problem arises in that the content of other metals does not satisfy the optimal range described herein.

[0105] Meanwhile, the first alloy forming the circuit pattern layer (120) comprises any one of the metals silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy. The silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) may enable the first alloy to have wire bonding properties of a certain level or higher. For example, the wire bonding property (gf) of the circuit pattern layer (120) formed from the first alloy including the silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy is 5gf or higher. Furthermore, the wire bonding property (gf) of the circuit pattern layer (120) formed from the first alloy may be 7gf or higher. Furthermore, the wire bonding property (gf) of the circuit pattern layer (120) formed from the first alloy may be 9gf or higher.

[0106] Accordingly, the first alloy may be any one of a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag) alloy, a nickel (Ni)-chromium (Cr)-iron (Fe)-silicon (Si) alloy, and a nickel (Ni)-chromium (Cr)-iron (Fe)-silver (Ag)-silicon (Si) alloy.

[0107] Any one of the metals in the first alloy above—silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy—has a content in the range of 3 weight% to 10 weight%.

[0108] If the content of any one of the metals among silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy in the first alloy is less than 3 weight%, the wire bonding properties of the lower surface (120S2) or bonding portion of the circuit pattern layer (120) may be less than 4gf, and accordingly, the surface treatment layer to be formed on the lower surface (120S2) or bonding portion of the circuit pattern layer (120) may not be omitted or removed.

[0109] In the first alloy constituting the circuit pattern layer (120), if the content of any one of silver (Ag), silicon (Si), and silver (Ag)-silicon (Si) alloy exceeds 10 weight%, the content of nickel (Ni), chromium (Cr), or iron (Fe) decreases accordingly, and as a result, a problem may occur in at least one of the characteristics of the circuit pattern layer (220), such as resistance (Ω), etching rate (㎛ / min), surface roughness change rate, and nickel leaching amount.

[0110] Meanwhile, the first alloy constituting the circuit pattern layer (120) may include at least one additive.

[0111] For example, the first alloy forming the circuit pattern layer (120) may include any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these. For example, any one additive selected from manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these may be added to refine the structure of the alloy constituting the circuit pattern layer (120) to achieve solid solution strengthening.

[0112] Specifically, the content of any one additive selected from the above manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these satisfies a range of 1 weight% to 5 weight%.

[0113] That is, if the content of any one additive selected from the above-mentioned manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these is less than 1 weight%, the solid solution strengthening effect is insufficient, and consequently, the wear resistance, oxidation resistance, and corrosion resistance of the circuit pattern layer (220) may be reduced. Specifically, if the content of any one additive selected from the above-mentioned manganese (Mn), tin (Sn), zinc (Zn), and alloys containing at least two of these is less than 1 weight%, during the process of manufacturing the first alloy, the metal elements nickel (Ni), chromium (Cr), and iron (Fe) do not mix well with each other, making it difficult to achieve crystal structuring, and as a result, a problem may occur in which the crystalline phase of the alloy becomes larger (e.g., a problem in which it is difficult to refine the crystalline phase).

[0114] In addition, if the content of any one additive selected from the above manganese (Mn), tin (Sn), zinc (Zn) and alloys including at least two of these exceeds 5 weight%, the resistance characteristics of the circuit pattern layer (120) increase, and the signal loss may increase accordingly.

[0115] In addition, if the content of any one additive selected from the above manganese (Mn), tin (Sn), zinc (Zn) and an alloy containing at least two of these exceeds 5 weight%, the hardness of the circuit pattern layer (120) increases, and the etching rate (㎛ / min) may decrease accordingly.

[0117] - Second Alloy -

[0118] Meanwhile, the circuit pattern layer (120) can be formed from a second alloy having iron (Fe) as the main component.

[0119] At this time, the second alloy may include the metals constituting the first alloy. However, the content of each metal in the second alloy may differ from the content of each metal in the first alloy. For example, the first alloy may have nickel as its main component, and the second alloy may have iron as its main component. Accordingly, the content of nickel (Ni), iron (Fe), and chromium (Cr) in the second alloy may differ from the content of nickel (Ni), iron (Fe), and chromium (Cr) in the first alloy.

[0120] That is, the second alloy forming the circuit pattern layer (120) has iron (Fe) as its main component. For example, the iron (Fe) content in the second alloy satisfies a range of 60 wt% to 80 wt%, or 61 wt% to 78 wt%, or 63 wt% to 75 wt%. The optimal range for the iron (Fe) content in the second alloy is 63 wt% to 75 wt%.

[0121] If the iron (Fe) content in the second alloy is less than 60 weight%, the rollability of the second alloy is reduced, and accordingly, the thickness of the second alloy increases, and furthermore, the thickness of the circuit pattern layer (120) may increase. If the iron (Fe) content in the second alloy exceeds 80 weight%, the wear resistance, corrosion resistance, and oxidation resistance of the circuit pattern layer (120) formed by the second alloy may decrease. In addition, if the iron (Fe) content in the second alloy exceeds 80 weight%, the resistance (Ω) of the circuit pattern layer (120) formed by the second alloy increases, and accordingly, the signal transmission loss may increase. In addition, if the iron (Fe) content in the second alloy is less than 60 weight% or exceeds 80 weight%, the content of other metals (e.g., nickel or chromium) decreases or increases by a corresponding amount, and as a result, a problem arises in that the content of other metals does not satisfy the optimal range described herein.

[0122] Meanwhile, the chromium (Cr) content in the second alloy satisfies a range of 10 wt% to 22 wt%, or 13 wt% to 21 wt%, or 15 wt% to 20 wt%. That is, the optimal range of the chromium (Cr) content in the second alloy is 15 wt% to 20 wt%.

[0123] If the chromium (Cr) content in the second alloy is less than 10 weight%, the amount of nickel leaching to the surface of the second alloy may increase. Additionally, if the chromium (Cr) content in the second alloy is less than 10 weight%, the hardness of the circuit pattern layer (120) formed by the second alloy is lowered, and consequently, oxidation resistance, wear resistance, and corrosion resistance may be reduced. On the other hand, if the chromium (Cr) content in the second alloy exceeds 22 weight%, the hardness of the second alloy increases, and consequently, the etching rate (μm / min) in the etching process for forming the circuit pattern layer (120) using the second alloy may decrease. Additionally, if the chromium (Cr) content in the second alloy exceeds 22 weight%, wire bonding performance may decrease. In addition, if the wire bonding properties of the circuit pattern layer (120) are reduced, the surface treatment layer formed on the lower surface (120S2) or the bonding portion of the circuit pattern layer (120) may not be omitted or removed. Furthermore, if the content of chromium (Cr) in the second alloy is less than 10 weight% or exceeds 22 weight%, the content of other metals (e.g., nickel or iron) decreases or increases by a corresponding amount, and as a result, a problem arises in which the content of other metals does not satisfy the optimal range described herein.

[0124] Meanwhile, the nickel (Ni) content in the second alloy satisfies a range of 3 wt.% to 20 wt.%, or 5 wt.% to 18 wt.%, or 7 wt.% to 15 wt.%. That is, the optimal range of the nickel (Ni) content in the second alloy is 7 wt.% to 15 wt.%.

[0125] If the nickel (Ni) content in the second alloy is less than 3 weight%, the change rate (%) of the surface roughness of the circuit pattern layer (120) may exceed 10%. Additionally, if the nickel (Ni) content in the second alloy exceeds 20 weight%, the etching rate (μm / min) in the etching process for forming the circuit pattern layer (120) using the second alloy may decrease. Furthermore, if the nickel (Ni) content in the second alloy is less than 3 weight% or exceeds 20 weight%, the content of other metals (e.g., iron or chromium) decreases or increases by the corresponding amount, and as a result, a problem arises in which the content of the other metals does not satisfy the optimal range described herein.

[0127] Accordingly, when the circuit pattern layer (120) is formed with either the first alloy or the second alloy, the circuit pattern layer (120) has a resistance value in the range of 0.07Ω to 0.35Ω, an etching rate (μm / min) in the range of 30μm / min to 70μm / min, a surface roughness change rate in the range of 0.2% to 6.0%, wire bonding properties of 5gf or more, and 0.28μg / cm 2 It can have a nickel leaching amount of less than / week and a plating adhesion of 5B or higher.

[0129] Meanwhile, the first alloy and the second alloy forming the circuit pattern layer (120) can be manufactured through a rolling process.

[0130] At this time, when forming a circuit pattern layer using an alloy manufactured by a rolling process, the surface roughness of the circuit pattern layer is below a certain level (for example, an arithmetic mean roughness (Ra) of 0.06 μm or less or a 10-point average roughness (Rz) of 0.31 μm or less).

[0131] Accordingly, when manufacturing a circuit board using an alloy produced by the above rolling process, a problem may occur with the adhesion between the circuit pattern layer and the insulating layer, and the physical reliability of the circuit board may be reduced as a result.

[0132] At this time, the surface roughness required on the upper surface (120S1) and the lower surface (120S2) of the circuit pattern layer (120) is different from each other. For example, the lower surface (120S2) of the circuit pattern layer (120) requires a surface roughness of a certain level or higher to improve adhesion with the insulating layer (110). In contrast, the upper surface (120S1) of the circuit pattern layer (120) is a surface that is exposed to the outside without contacting the insulating layer (110). Accordingly, if the upper surface (120S1) of the circuit pattern layer (120) has a surface roughness corresponding to that of the lower surface (120S2), reliability issues may arise in terms of design or usage environment.

[0133] Accordingly, in the embodiment, different surface roughness is applied to the upper surface (120S1) and the lower surface (120S2) of the circuit pattern layer (120).

[0134] Specifically, the surface roughness of the upper surface (120S1), the surface roughness of the lower surface (120S2), and the surface roughness of the side surface (120S3) of the circuit pattern layer (120) in the embodiment are different from each other.

[0135] For example, the surface roughness of the upper surface (120S1) of the circuit pattern layer (120) is smaller than the surface roughness of the lower surface (120S2) and the surface roughness of the side surface (120S3) of the circuit pattern layer (120).

[0136] For example, the surface roughness of the lower surface (120S2) of the circuit pattern layer (120) is greater than the surface roughness of the upper surface (120S1) of the circuit pattern layer (120) and the surface roughness of the side surface (120S3) of the circuit pattern layer (120).

[0137] For example, the surface roughness of the side surface (120S3) of the circuit pattern layer (120) is greater than the surface roughness of the upper surface (120S1) of the circuit pattern layer (120) and smaller than the surface roughness of the lower surface (120S2) of the circuit pattern layer (120).

[0139] FIG. 5 is a drawing for explaining a method for imparting surface roughness to a circuit pattern layer according to an embodiment, and FIG. 6 is a drawing showing a surface roughness image of a circuit pattern layer according to an embodiment.

[0140] In the embodiment, the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) have different surface roughness.

[0141] First, it will be explained that the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) in the embodiment have different surface roughness.

[0143] In the embodiment, the surface roughness of the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) can be imparted by a rolling roll in a rolling process, or alternatively, by performing a separate etching process.

[0144] That is, the upper surface (120S1), lower surface (120S2), and side surface of the circuit pattern layer (120) may have a surface roughness in the range described below by a rolling roll in a rolling process. Alternatively, the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) may have a surface roughness in the range described below by etching at least one surface of the alloy produced through the rolling process.

[0145] Specifically, the surface roughness of the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) described below can satisfy the range described below by performing either a rolling process or an etching process using a rolling roll.

[0146] However, if the surface roughness is imparted by either the rolling process or the etching process using the above-mentioned rolling roll, the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) may not each have a surface roughness within the target range. For example, if the surface roughness is imparted only through either the rolling process or the etching process, the etching time, the height of the protrusions of the rolling roll, etc., must be increased in order for the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) to each have a target surface roughness, and the process time or manufacturing cost may increase accordingly. Accordingly, in the embodiment, both the rolling process and the etching process using the rolling roll are applied so that the upper surface (120S1), lower surface (120S2), and side surface (120S3) of the circuit pattern layer (120) can each have a surface roughness of the following target range.

[0147] Specifically, as shown in FIG. 5 (a), the alloy forming the circuit pattern layer (120) can be manufactured by performing a rolling process using a rolling roll.

[0148] At this time, the rolling roll includes a first rolling roll (210) facing the lower surface (120S2) of the circuit pattern layer (120) and a second rolling roll (220) facing the upper surface (120S1) of the circuit pattern layer (120).

[0149] In addition, the first rolling roll (210) may include a protrusion (210a) having a certain height. The protrusion (210a) has a height such that the arithmetic mean roughness (Ra) of the lower surface (120S2) of the circuit pattern layer (120) satisfies a range between 0.5㎛ and 0.9㎛, or the 10-point average roughness (Rz) satisfies a range between 1.5㎛ and 2.5㎛.

[0150] Meanwhile, the second rolling roll (220) may also include a protrusion (not shown), but the height of the protrusion included in the second rolling roll (220) is lower than the protrusion (210a) included in the first rolling roll (210). Accordingly, the surface roughness of the upper surface (120S1) and the lower surface (120S2) of the circuit pattern layer (120) in the embodiment are given differently from each other.

[0151] Additionally, as shown in FIG. 5(b), in the embodiment, a process of etching at least one surface of the alloy produced through the rolling process may be performed. Specifically, the upper surface (120S1) of the circuit pattern layer (120) may have a surface roughness within the target range by performing the rolling process alone. In contrast, the lower surface (120S2) of the circuit pattern layer (120) may not have a surface roughness within the target range by performing the rolling process alone.

[0152] For example, FIG. 6(a) is a drawing showing a surface roughness image scanned from the lower surface (120S2) of the circuit pattern layer (120) formed through the rolling process. And, as shown in FIG. 6(a), it may be difficult for the lower surface (120S2) of the circuit pattern layer (120) to have a target range of surface roughness only through the rolling process. And, in order for the lower surface (120S2) of the circuit pattern layer (120) to have a target range of surface roughness only through the rolling process, the height of the protrusion (210a) of the first rolling roll (210) must be increased, and the rolling processability may be reduced accordingly.

[0153] In the above etching process, a mask (230) may be placed on the upper surface (120S1) of the circuit pattern layer (120), and accordingly, the etching process may be performed only on the lower surface (120S2) excluding the upper surface (120S1) of the circuit pattern layer (120). At this time, the side surface (120S3) of the circuit pattern layer (120) may be exposed to the etching solution during the etching process of the lower surface (120S2), and etching may proceed accordingly. However, the degree of etching of the side surface (120S3) of the circuit pattern layer (120) is lower than the degree of etching of the lower surface (120S2) of the circuit pattern layer (120), and accordingly, the surface roughness of the side surface (120S3) of the circuit pattern layer (120) is lower than the surface roughness of the lower surface (120S2) of the circuit pattern layer (120).

[0155] Below, the surface roughness of each surface of the circuit pattern layer (120) applied through the above method will be described.

[0156] Figure 7 is a diagram showing the surface roughness of a circuit pattern layer according to an embodiment.

[0157] As shown in FIG. 7(a), the arithmetic mean roughness (Ra) of the upper surface (120S1) of the circuit pattern layer (120) satisfies the range of 0.03㎛ to 0.08㎛ or 0.04㎛ to 0.07㎛. The 10-point average roughness (Rz) of the upper surface (120S1) of the circuit pattern layer (120) satisfies the range between 0.1㎛ to 0.4㎛ or 0.2㎛ to 0.3㎛.

[0158] If the arithmetic mean roughness (Ra) of the upper surface (120S1) of the circuit pattern layer (120) is less than 0.03 μm or the 10-point average roughness (Rz) is less than 0.1 μm, the circuit pattern layer (120) may not satisfy wear resistance, corrosion resistance, oxidation resistance, and hardness above a certain level. For example, if the arithmetic mean roughness (Ra) of the upper surface (120S1) of the circuit pattern layer (120) is less than 0.03 μm or the 10-point average roughness (Rz) is less than 0.1 μm, the rolling processability of the alloy forming the circuit pattern layer (120) may be reduced.

[0159] If the arithmetic mean roughness (Ra) of the upper surface (120S1) of the circuit pattern layer (120) exceeds 0.08 μm or the 10-point average roughness (Rz) exceeds 0.4 μm, the circuit pattern layer (120) may not satisfy a certain level of wear resistance, corrosion resistance, oxidation resistance, and hardness. If the arithmetic mean roughness (Ra) of the upper surface (120S1) of the circuit pattern layer (120) exceeds 0.08 μm or the 10-point average roughness (Rz) exceeds 0.4 μm, design problems may occur due to an increase in the surface roughness of the upper surface (120S1) of the circuit pattern layer (120) or the contact part. For example, the upper surface (120S1) of the circuit pattern layer (120) is a part exposed to the outside, and accordingly, it may come into contact with the user's body in the usage environment of an application including it. Accordingly, if the surface roughness of the upper surface (120S1) of the circuit pattern layer (120) is greater than the above range, it may cause reliability problems such as causing injury to the user's body.

[0160] Meanwhile, as shown in FIG. 7(b), the side surface (120S3) of the circuit pattern layer (120) may have a surface roughness in the range between the surface roughness of the upper surface (120S1) and the surface roughness of the lower surface (120S2). The surface roughness of the side surface (120S3) of the circuit pattern layer (120) may have a surface roughness corresponding to the etching factor performed in the circuit pattern patterning process. Additionally, the side surface (120S3) of the circuit pattern layer (120) is provided with a surface roughness different from that of the upper surface (120S1) and lower surface (120S2) of the circuit pattern layer (120) during the process of providing surface roughness to the upper surface (120S1) and lower surface (120S2) of the circuit pattern layer (120).

[0161] Additionally, the arithmetic mean roughness (Ra) of the side (120S3) of the circuit pattern layer (120) satisfies a range between 0.1 μm and 0.3 μm. Additionally, the 10-point average roughness (Rz) of the side (120S3) of the circuit pattern layer (120) satisfies a range between 0.8 μm and 1.3 μm.

[0162] In addition, as shown in FIG. 7(c), the arithmetic mean roughness (Ra) of the lower surface (120S2) of the circuit pattern layer (120) satisfies a range between 0.5㎛ and 0.9㎛ or between 0.6㎛ and 0.8㎛. In addition, the 10-point average roughness (Rz) of the lower surface (120S2) of the circuit pattern layer (120) satisfies a range between 1.5㎛ and 2.5㎛ or between 1.7㎛ and 2.3㎛.

[0163] If the arithmetic mean roughness (Ra) of the lower surface (120S2) of the circuit pattern layer (120) is less than 0.5 μm or the 10-point average roughness (Rz) is less than 1.5 μm, the adhesion between the circuit pattern layer (120) and the insulating layer (110) may be reduced. Accordingly, in the usage environment of the circuit board, a physical reliability problem may occur in which the circuit pattern layer (120) separates from the insulating layer (110).

[0164] Additionally, if the arithmetic mean roughness (Ra) of the lower surface (120S2) of the circuit pattern layer (120) exceeds 0.9 μm or the 10-point average roughness (Rz) exceeds 2.5 μm, the manufacturing time of the alloy constituting the circuit pattern layer (120) may increase or the manufacturing cost may increase. For example, the surface roughness of the lower surface (120S2) of the circuit pattern layer (120) can be imparted by performing a rolling process with protrusions (described later) and / or an etching process. At this time, if the arithmetic mean roughness (Ra) or the 10-point average roughness (Rz) of the lower surface (120S2) of the circuit pattern layer (120) is greater than the above range, the etching time and the height of the rolling roll protrusions must be increased to impart the corresponding surface roughness, and there is a problem that the manufacturing process time increases accordingly, and the manufacturing cost increases accordingly.

[0165] As described above, the circuit pattern layer (120) in the embodiment includes an upper surface (120S1), a lower surface (120S2), and a side surface (120S3), and the surface roughness of each of these is different. Through this, in the embodiment, even if the circuit pattern layer (120) is an alloy layer manufactured through a rolling process, it is possible to ensure adhesion with the insulating layer (110), and thereby improve the physical reliability of the circuit board.

[0166] Meanwhile, in the embodiment, the arithmetic mean roughness (Ra) of the lower surface (120S2) of the circuit pattern layer (120) satisfies a range between 0.5㎛ and 0.9㎛, and the 10-point average roughness (Rz) satisfies a range between 1.7㎛ and 2.3㎛, thereby improving the adhesion strength (e.g., peel strength) between the insulating layer (110) and the circuit pattern layer (120). Specifically, it was confirmed that the adhesion strength (peel strength) between the insulating layer (110) and the circuit pattern layer (120) exceeds 150gf / min when the lower surface (120S2) of the circuit pattern layer (120) in the embodiment satisfies the above range. This is a higher value than when the circuit pattern layer is formed with a general copper foil, as in the comparative example. Accordingly, in the embodiment, it was confirmed that even if a rolled alloy layer is used as the circuit pattern layer (120), it is possible to secure adhesion between the circuit pattern layer (120) and the insulating layer (110).

[0168] FIGS. 8 and 9 are drawings illustrating a method for measuring the surface roughness of a circuit pattern layer according to an embodiment.

[0169] As shown in FIG. 8, in the embodiment, the surface roughness of the circuit pattern layer (120) was measured using the NV series NanoView measuring equipment from Nano Systems Co., Ltd.

[0170] The measurement method involves extracting a sample with an area of ​​622㎛*470㎛ from the rolled alloy forming the circuit pattern layer (120), and obtaining the scanned image of FIG. 8 by scanning the extracted sample using the nanoview measurement equipment.

[0171] Subsequently, in the embodiment, the average value of the surface roughness measured at an arbitrary straight line in the length direction (e.g., x-axis direction) and the surface roughness measured at an arbitrary straight line in the width direction (e.g., y-axis direction) in the scanned image is determined as the surface roughness of the circuit pattern layer (120).

[0172] Specifically, as shown in FIG. 8, in the embodiment, surface roughness is measured for lines (A, B, C) of different length directions in the scanned image. At this time, the surface roughness measured at line A, line B, and line C, respectively, is as shown in FIG. 9 (a).

[0173] Subsequently, in the embodiment, the surface roughness is measured for each of the lines (a, b, c) in different width directions in the scanned image, as shown in FIG. 8. At this time, the surface roughness measured at each of the lines a, b, and c is as shown in FIG. 9 (b).

[0174] In addition, in the embodiment, the average value of the surface roughness measured at each of the six lines (A, B, C, a, b, c) is determined as the surface roughness of the circuit pattern layer (120).

[0176] FIG. 10 is a drawing showing a circuit board according to a second embodiment.

[0177] Referring to FIG. 10, the circuit board includes an insulating layer (110), a circuit pattern layer (120), and a first adhesive layer (140). The first adhesive layer (140) may be disposed between the circuit pattern layer (120) and the insulating layer (110).

[0178] The first adhesive layer (140) may be a bonding sheet. For example, the first adhesive layer (140) may be an epoxy-based bonding sheet, but is not limited thereto.

[0179] The first adhesive layer (140) is disposed between the upper surface of the insulating layer (110) and the lower surface (120S2) of the circuit pattern layer (120).

[0180] The first adhesive layer (140) can function to improve the adhesion between the insulating layer (110) and the circuit pattern layer (120).

[0181] At this time, the planar area of ​​the first adhesive layer (140) may be the same as the planar area of ​​the insulating layer (110). For example, the through hole (115) may penetrate the first adhesive layer (140) together with the insulating layer (110).

[0182] In the embodiment, by placing a first adhesive layer (140) between the insulating layer (110) and the circuit pattern layer (120), the adhesion between the insulating layer (110) and the circuit pattern layer (120) can be secured, thereby improving the physical reliability of the circuit board.

[0184] FIG. 11 is a drawing showing a chip package according to an embodiment.

[0185] Referring to FIG. 11, the chip package may include a circuit board of either one of the circuit boards shown in FIG. 2 and FIG. 10.

[0186] The above chip package includes a second adhesive layer (150) disposed on the lower surface of the insulating layer (110) of the circuit board. The second adhesive layer (150) is intended to bond an IC chip (160) to the lower surface of the insulating layer (110). The second adhesive layer (150) may be epoxy, a thermosetting adhesive, and a UV adhesive, but is not limited thereto.

[0187] An IC chip (160) is attached to the second adhesive layer (150). The IC chip (160) is electrically connected to the bonding portion of the circuit pattern layer (120) through a connecting member (170), such as a wire. Specifically, one end of the connecting member (170) is connected to a terminal (not shown) of the IC chip (160), and the other end can be connected to the lower surface (120S2) of the circuit pattern layer (120) which is vertically superimposed with the through hole (115). At this time, the circuit pattern layer (120) in the embodiment is formed from a first alloy or a second alloy having a wire bonding property of a certain level or higher. Accordingly, the surface treatment layer placed on the lower surface (120S2) of the circuit pattern layer (120) in the embodiment can be omitted or removed. Through this, the other end of the connecting member in the comparative example is connected to the surface treatment layer placed on the lower surface of the circuit pattern layer. In contrast, the other end of the connecting member (170) in the embodiment is directly connected to the lower surface (120S2) of the circuit pattern layer (120).

[0188] Meanwhile, the chip package includes a molding layer (180). The molding layer (180) may be an EMC (Epoxy Molding Compound), but is not limited thereto. The molding layer (180) is disposed on the lower surface of the insulating layer (110). The molding layer (180) can mold the IC chip (160) and the connecting member (180).

[0190] In the embodiment, a circuit pattern layer is formed using an alloy manufactured through a rolling process. At this time, the circuit pattern layer has a problem in that its adhesion to the insulating layer is reduced as it is manufactured through a rolling process. Accordingly, in the embodiment, a surface roughness of a certain level or higher is applied to the lower surface of the circuit pattern layer, which faces the insulating layer, among the upper and lower surfaces. Furthermore, the upper surface of the circuit pattern in the embodiment is the outermost exposed part in an application where the circuit board of the embodiment is applied. Accordingly, in the embodiment, the upper surface of the circuit pattern layer is made to have a surface roughness smaller than that of the lower surface of the circuit pattern layer. Accordingly, in the embodiment, by applying a surface roughness of a certain level or higher to the lower surface of the circuit pattern layer, adhesion between the circuit pattern layer and the insulating layer can be secured, thereby improving the physical reliability of the circuit board and the chip package. Additionally, in the embodiment, by making the upper surface of the circuit pattern layer have a surface roughness smaller than that of the lower surface of the circuit pattern layer, design problems in the application's usage environment can be resolved. In addition, in the embodiment, if the upper surface of the circuit pattern layer has a certain level or higher, problems such as causing injury to the user's body in the application usage environment can be resolved. Through this, the embodiment can ensure product stability and further improve user satisfaction.

[0191] Meanwhile, in the embodiment, a circuit pattern layer is formed using an alloy comprising nickel (Ni), chromium (Cr), and iron (Fe), and including at least one metal among silver (Ag), silicon (Si), and alloys thereof. Accordingly, the circuit pattern layer in the embodiment may have wear resistance, corrosion resistance, oxidation resistance, and hardness above a certain level. Through this, in the embodiment, the surface treatment layer that must be formed on the contact portion of the circuit pattern layer may be omitted or removed, thereby simplifying the manufacturing process of the circuit board and reducing manufacturing costs. Furthermore, the circuit pattern layer in the embodiment may have wire bonding properties above a certain level. Through this, in the embodiment, not only the surface treatment layer that must be formed on the contact portion of the circuit pattern layer but also the surface treatment layer that must be formed on the bonding portion of the circuit pattern layer may be omitted or removed, thereby further simplifying the manufacturing process of the circuit board and further reducing manufacturing costs.

[0193] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0194] Although the above description has focused on embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art to which the embodiments pertain will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 An insulating layer having at least one first through hole; and includes a circuit pattern layer disposed on the insulating layer, wherein the circuit pattern layer is a rolled alloy having the highest content of nickel or iron, and the rolled alloy includes a first surface comprising an adhesive portion facing the insulating layer and superimposed perpendicularly to the insulating layer, and a bonding portion superimposed perpendicularly to the first through hole and exposed through the first through hole, a second surface opposite to the first surface, and a third surface which is a side connecting the first surface and the second surface, wherein the bonding portion of the first surface is a bonding surface in contact with a wire, and the second surface is a contact surface in contact with an external device, wherein the arithmetic mean roughness of the first surface including the bonding surface is greater than the arithmetic mean roughness of the second surface including the contact surface, and the arithmetic mean roughness of the third surface is smaller than the arithmetic mean roughness of the first surface and greater than the calculated average roughness of the second surface of the circuit pattern layer, and the arithmetic mean roughness of the first surface is in the range of 0.5㎛ to 0.9㎛. A circuit board for a smart IC, satisfying the condition that the arithmetic mean roughness of the second surface satisfies the range between 0.03㎛ and 0.08㎛. Claim 2 A circuit board for a smart IC according to claim 1, wherein the rolled alloy has a resistance value in the range of 0.07Ω to 0.35Ω, an etching rate (㎛ / min) in the range of 30㎛ / min to 70㎛ / min, a surface roughness change rate between 0.2% and 6.0%, and wire bonding properties of 4gf or more. Claim 3 A circuit board for a smart IC according to claim 1, wherein the first surface of the rolled alloy has a 10-point average roughness (Rz) in the range of 1.5 μm to 2.5 μm, and the second surface of the rolled alloy has a 10-point average roughness in the range of 0.1 μm to 0.4 μm. Claim 4 delete Claim 5 A circuit board for a smart IC according to claim 1, wherein the arithmetic mean roughness of the third surface of the rolled alloy satisfies the range of 0.1㎛ to 0.3㎛. Claim 6 A circuit board for a smart IC according to claim 1, wherein the 10-point average roughness of the third surface of the rolled alloy is smaller than the 10-point average roughness of the first surface of the rolled alloy and larger than the 10-point average roughness of the second surface of the rolled alloy. Claim 7 A circuit board for a smart IC according to claim 6, wherein the 10-point average roughness of the third surface of the rolled alloy satisfies the range of 0.8㎛ to 1.3㎛. Claim 8 A circuit board for a smart IC according to any one of claims 1 to 3, wherein the rolled alloy comprises a first metal having a content in the range of 60 wt% to 80 wt%, a second metal having a content in the range of 10 wt% to 22 wt%, a third metal having a content in the range of 3 wt% to 20 wt%, and a fourth metal having a content in the range of 3 wt% to 10 wt%, wherein the first metal comprises either nickel (Ni) or iron (Fe), the second metal comprises chromium (Cr), the third metal comprises one other than the first metal among nickel (Ni) and iron (Fe), and the fourth metal comprises any one of silver (Ag), silicon (Si), and a silver (Ag)-silicon (Si) alloy. Claim 9 A circuit board for a smart IC according to claim 8, wherein the rolled alloy further comprises a fifth metal having a content in the range of 1 weight% to 5 weight%, and the fifth metal is any one of manganese (Mn), tin (Sn), zinc (Zn), and an alloy comprising at least two of these. Claim 10 delete Claim 11 A circuit board for a smart IC according to claim 1, comprising a bonding sheet disposed between the insulating layer and the circuit pattern layer, wherein the bonding sheet comprises a second through hole that overlaps perpendicularly with the first through hole, and the adhesive portion of the first surface of the circuit pattern layer contacts the bonding sheet. Claim 12 An insulating layer comprising at least one first through hole; a circuit pattern layer disposed on the insulating layer and comprising a first surface facing the insulating layer and a second surface opposite to the first surface; and an IC chip attached to the lower surface of the insulating layer; and includes a connecting member connecting the IC chip and the circuit pattern layer, wherein the circuit pattern layer is a rolled alloy having the highest content of nickel or iron, and the rolled alloy includes a first surface comprising an adhesive portion facing the insulating layer and superimposed perpendicularly to the insulating layer, and a bonding portion superimposed perpendicularly to the first through hole and exposed through the first through hole, a second surface opposite to the first surface, and a third surface which is a side connecting the first surface and the second surface, wherein the bonding portion of the first surface is a bonding surface in contact with a wire, and the second surface is a contact surface in contact with an external device, wherein the arithmetic mean roughness of the first surface including the bonding surface is greater than the arithmetic mean roughness of the second surface including the contact surface, and the arithmetic mean roughness of the third surface is smaller than the arithmetic mean roughness of the first surface and greater than the calculated average roughness of the second surface of the circuit pattern layer, and the arithmetic mean roughness of the first surface is 0.5 μm to A chip package satisfying a range of 0.9㎛, wherein the arithmetic mean roughness of the second surface satisfies a range between 0.03㎛ and 0.08㎛, and wherein the connecting member is directly connected to the bonding portion of the circuit pattern layer inside the first through hole. Claim 13 A chip package according to claim 12, wherein the first surface of the rolled alloy has a 10-point average roughness (Rz) in the range of 1.5 μm to 2.5 μm, and the second surface of the rolled alloy has a 10-point average roughness in the range of 0.1 μm to 0.4 μm.

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