Simulation device and method of mac operator for deep neural network calculation

Abstract

A simulation device and method for a MAC operator for deep neural network computation are disclosed. A simulation device for a MAC operator for deep neural network computation according to one embodiment of the present invention comprises one or more processors and a memory for storing one or more programs executed by the one or more processors. The simulation device for a MAC operator for deep neural network computation includes an input module that receives approximate computation information including bit width information, an approximate computation adder, and an approximate computation multiplier; a simulation module that performs simulations for a plurality of deep neural network models using previously stored training data and test data based on the received approximate computation information; and a result providing module that performs a performance evaluation for each deep neural network model based on the results of each simulation when each simulation is performed.

Description

Technology Field

[0001] Embodiments of the present invention relate to a simulation device for a MAC computer for deep neural network computation. Background Technology

[0003] Deep neural networks are making remarkable progress by utilizing the continuous addition of layers and efficient computational algorithms. These deep neural networks are widely used in various machine learning applications, such as large-scale image classification and pattern recognition.

[0004] These deep neural networks require learning based on vast amounts of data, and in this process, they must perform a large number of addition and multiplication operations. Accordingly, chip structures that perform operations for deep neural networks must be equipped with multiple operation circuits, such as multiply-accumulate operators (MACs).

[0005] Multiply-Accumulate (MAC) operations are the fundamental arithmetic of deep neural network computation, and millions of MAC operations are performed in a typical deep neural network. Therefore, deep neural network accelerators integrate a significant number of MAC hardware devices, each consisting of an adder and a multiplier, into an array. In this regard, efficient MAC hardware devices must be designed to improve the overall energy efficiency of deep neural network accelerators.

[0006] Meanwhile, deep neural networks have built-in error resilience against the uncertainty of the network model. In other words, adding a certain level of approximation during deep neural network computation does not significantly affect the overall accuracy performance of the network. In this regard, approximation computing techniques are being applied to deep neural network hardware design to improve power and energy efficiency.

[0007] However, there is a problem in designing an optimized MAC operator that strikes a balance between the performance of deep neural networks and the degree of approximation of the MAC operator. Prior art literature

[0009] Korean Patent Publication No. 10-2020-0121497 (October 26, 2020) The problem to be solved

[0010] Embodiments of the present invention are intended to provide a simulation device and method for a MAC (Multiplication and Accumulation) calculator for designing a MAC calculator that minimizes area without significantly reducing accuracy by approximating MAC operations.

[0011] In addition, embodiments of the present invention are intended to provide a simulation device and method for a MAC operator that can be written using CUDA to design a MAC operator and perform simulations for multiple deep neural network models through a Python-based framework. means of solving the problem

[0013] According to an exemplary embodiment of the present invention, a simulation device for a MAC operator for deep neural network computation is provided, comprising one or more processors and a memory for storing one or more programs executed by said one or more processors, wherein the simulation device comprises: an input module for receiving approximate operation information including bit width information, an approximate operation adder, and an approximate operation multiplier; a simulation module for performing a simulation of a plurality of deep neural network models using previously stored training data and test data based on the received approximate operation information; and a result providing module for performing a performance evaluation of each deep neural network model based on the results of each simulation when each simulation is performed.

[0014] The above approximate operation information may include bit width information for a floating-point number for adjusting the bit width of the exponent and mantissa of the floating-point number from the user, an approximate operation adder according to an approximate operation addition algorithm written by the user, and an approximate operation multiplier according to an approximate operation multiplication algorithm.

[0015] The above approximate addition algorithm and the above approximate multiplication algorithm can be written using CUDA (Compute Unified Device Architecture).

[0016] The simulation module may further include a computation module that performs computations associated with the deep neural network model; and a learning and inference module that performs learning and inference on the plurality of deep neural network models using the computation module.

[0017] The above operation module may further include: a bit width adjustment unit that receives a plurality of input data represented as floating points from the learning and inference module and adjusts the bit width of the exponent and mantissa of each of the input data; and an operation unit that replaces a preset adder and multiplier with the input approximate operation adder and approximate operation multiplier, and performs operations between the input data with adjusted bit widths according to an operation algorithm set in the replaced approximate operation adder and approximate operation multiplier.

[0018] The bit width adjustment unit adjusts the bit width of the exponent of the input data based on the bit width information and the size of the exponent of the input data, and can determine the bit width of the exponent of the input data using the following mathematical formula 1.

[0019] [Mathematical Formula 1]

[0020]

[0021]

[0022] (Here, subscript n is the bit width of the floating-point number to be adjusted, is an n-bit floating-point exponent, is the bias value of the exponent of an n-bit floating-point number, the subscript n is the bit width of the exponent to be adjusted, is the bit width of the exponent of an n-bit floating-point number)

[0023] The bit width adjustment unit can adjust the bit width of the input data by truncation of the lower bits of the exponent of the input data by the difference between the bit width of the mantissa included in the bit width information and the bit width of the mantissa of the input data.

[0024] According to another exemplary embodiment of the present invention, a method for simulating a MAC operator for deep neural network computation is provided, comprising a step of receiving approximate operation information including bit width information, approximate operation adder and approximate operation multiplier, based on the received approximate operation information, using previously stored training data and test data, and, when each simulation is performed, performing a performance evaluation of each deep neural network model based on the results of each simulation. Effects of the invention

[0026] According to embodiments of the present invention, by approximating the Multiplication and Accumulation (MAC) operation, it is possible to design a MAC operator that minimizes area without significantly reducing accuracy.

[0027] In addition, according to embodiments of the present invention, by designing a MAC operator using CUDA, simulations of multiple deep neural network models can be performed through a Python-based framework. Brief explanation of the drawing

[0029] FIG. 1 is a conceptual diagram showing a simulation device of a MAC calculator for deep neural network computation according to an embodiment of the present invention. FIG. 2 is a configuration diagram illustrating a simulation device of a MAC calculator for deep neural network computation according to an embodiment of the present invention. FIG. 3 is a diagram showing a floating-point number represented in 32 bits. FIG. 4 is a drawing for explaining a simulation module of a simulation device of a MAC calculator for deep neural network computation according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a simulation method of a MAC calculator for deep neural network computation according to an embodiment of the present invention. FIG. 6 is a flowchart illustrating step 530 of a simulation method of a MAC calculator for deep neural network computation according to an embodiment of the present invention. FIG. 7 is a block diagram illustrating a computing environment including a computing device suitable for use in exemplary embodiments. Specific details for implementing the invention

[0030] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, apparatuses, and / or systems described herein. However, this is merely illustrative and the present invention is not limited thereto.

[0031] In describing the embodiments of the present invention, detailed descriptions of known technologies related to the present invention are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention. Furthermore, the terms described below are defined in consideration of their functions within the present invention, and these may vary depending on the intentions or practices of the user or operator. Therefore, such definitions should be based on the content throughout this specification. Terms used in the detailed description are intended merely to describe the embodiments of the present invention and should not be limiting in any way. Unless explicitly stated otherwise, expressions in the singular form include the meaning of the plural form. In this description, expressions such as "include" or "comprise" are intended to refer to certain characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof, and should not be interpreted to exclude the existence or possibility of one or more other characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof other than those described.

[0032] In the following description, terms such as "transmission," "communication," "transmission," "reception," and other terms of similar meaning regarding signals or information include not only the direct transfer of signals or information from one component to another but also the transfer through other components. In particular, "transmission" or "transmitting" a signal or information to one component refers to the final destination of the signal or information and does not mean a direct destination. The same applies to the "reception" of signals or information. Furthermore, in this specification, two or more data or information are "related" means that if one data (or information) is obtained, at least a portion of another data (or information) can be obtained based thereon.

[0033] Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0035] FIG. 1 is a conceptual diagram showing a simulation device for a MAC operator for deep neural network computation according to one embodiment of the present invention, and FIG. 2 is a configuration diagram for explaining a simulation device for a MAC operator for deep neural network computation according to one embodiment of the present invention.

[0036] Referring to FIGS. 1 and 2, a simulation device (100) of a MAC computer for deep neural network computation may include an input module (200), a simulation module (300), and a result providing module (400).

[0038] First of all, the present invention is described as being implemented using Python and utilizing various libraries provided by Python. Of course, it is obvious that it may also be implemented through platforms other than Python, and that libraries provided by platforms other than Python may be utilized.

[0039] Meanwhile, deep neural network-related operations are operations performed in relation to deep learning at each node of the hidden layer or output layer of the deep neural network, and may be operations performed according to the learning process, validation process, test process, or inference process of deep learning. That is, deep neural network-related operations may include multiplication operations on weights (W) and inputs (I) and MAC (multiply and accumulation) operations, which are addition operations on the results of such multiplication operations, at each node of the hidden layer or output layer of the deep learning.

[0040] The computation module (300) of the present invention can be used for training and inference of a deep neural network. For example, floating-point operations can be performed when performing training weight operations. That is, the computation module (300) can perform MAC operations on data in a floating-point data format. To this end, the computation module (300) may include a plurality of MAC operators that perform floating-point MAC operations.

[0041] Here, a floating-point number is a concept in which a real number is represented by separating it into a mantissa, which represents the significant digits, and an exponent, which represents the position of the decimal point. Figure 3 illustrates the method of representing floating-point numbers as defined by the IEEE (Institute of Electrical and Electronics Engineers) standard. According to the IEEE standard, a floating-point number can be represented by 32 bits and can be composed of a 1-bit sign (S), an 8-bit exponent, and a 23-bit mantissa. An operation module can perform operations on floating-point numbers represented in bit units, and the operation result can also be represented in bit units.

[0042] That is, the simulation device (100) of a MAC calculator for deep neural network computation according to one embodiment of the present invention receives bit-width information for floating-point numbers, an approximate adder, and an approximate multiplier from a user, thereby allowing the exponent and mantissa bit widths of floating-point numbers to be adjusted during the process of learning and inferring the deep neural network, and by applying approximate operations to the adder and multiplier of floating-point operations and simulating, the time and cost for applying an approximate algorithm to the deep neural network can be reduced.

[0044] The input module (200) can receive training data and test data for training and inferring a deep neural network model. For example, the training data and test data may be the MNIST dataset (Modified National Institute of Standards and Technology), the CIFAR-10 dataset, and the ETH-80 dataset.

[0045] Additionally, the input module (200) may receive from the user bit-width information for a floating-point number, approximate operation information including an approximate adder and an approximate multiplier. For example, the input module (200) may receive from the user bit-width information for a floating-point number to adjust the bit widths of the exponent and mantissa of the floating-point number. Additionally, the input module (200) may receive from the user an approximate adder according to a designed approximate addition algorithm and an approximate multiplier according to an approximate multiplication algorithm.

[0046] At this time, the user can design approximate addition and multiplication algorithms using CUDA (Compute Unified Device Architecture). CUDA is a development environment provided for NVIDIA GPUs, and it is possible to configure specific parts of a program to be executed by an execution unit (e.g., a computation module) within the GPU or to process specific parts of a program in parallel using a programming language similar to C. In this case, the input module (200) can compile the approximate addition and multiplication algorithms written using CUDA with the NVIDIA CUDA compiler. That is, while algorithms written in the existing C / C++ language are difficult to apply to libraries provided by Python (e.g., PyTorch, TensorFlow), approximate addition and multiplication algorithms for performing simulation of a MAC operator can be written similarly to the C language based on CUDA, which has the advantage of making it easier to perform simulation of the MAC operator.

[0048] The simulation module (300) receives training data, test data, bit-width information for floating-point numbers, an approximate adder, and an approximate multiplier from the input module (200), and can perform simulations of multiple deep neural networks based on this.

[0049] Referring to FIG. 4, the simulation module (300) may include a computation module (310) and a learning / inference module (320).

[0050] The computation module (310) can perform operations associated with the deep neural network. For example, the computation module (310) can receive input data from the learning / inference module (320) and perform operations on the input data. The computation module (310) can perform various operations by utilizing the characteristics of the hardware structure of the Multiplier Accumulator (MAC) unit. Additionally, the computation module (310) may include multiple MAC units that perform floating-point MAC operations.

[0051] The operation module (310) may include a bit width adjustment unit (311) and an operation unit (312).

[0052] The bit width adjustment unit (311) can receive multiple input data expressed as floating-point numbers. Here, the input data may be the weight values ​​of the kernel and feature map data (a set of pixel values ​​of an image or numerical data input to a deep neural network).

[0053] Additionally, the bit width adjustment unit (311) can adjust the bit width of the exponent and mantissa of the input data based on bit width information. Here, the bit width information may be the bit width size of the exponent and mantissa of the floating-point number to be adjusted. By setting the size of the floating-point number based on the bit width adjusted by the user, the bit width adjustment unit can reduce the bit width required for multiplication and addition operations between input data represented as floating-point numbers during deep learning operations, thereby reducing computational complexity while minimizing loss of accuracy. Accordingly, the user can simulate the performance of the deep neural network while varying the bit width, thereby enabling the setting of the optimal bit width.

[0054] In an exemplary embodiment, the bit width adjustment unit (311) can adjust the bit width of the exponent of the input data based on bit width information and the size of the exponent of the input data. Meanwhile, the present invention may use a floating-point representation method (32-bit (FP32)) defined in the IEEE standard. Specifically, the bit width adjustment unit (311) can determine the bit width of the exponent using the size of the exponent, the bit width of the exponent, and the bias value of the exponent included in the bit width information, and the size of the exponent of the input data, the bit width of the exponent, and the bias value of the exponent. For example, the bit width adjustment unit (311) can determine the bit width of the exponent using the following mathematical formula 1 and adjust the bit width of the exponent of the input data.

[0055] [Mathematical Formula 1]

[0056]

[0057]

[0058] (Here, subscript n is the bit width of the floating-point number to be adjusted, is an n-bit floating-point exponent, is the bias value of the exponent of an n-bit floating-point number, the subscript n is the bit width of the exponent to be adjusted, is the bit width of the exponent of an n-bit floating-point number)

[0059] In other words, it can resolve overflows or underflows that occur during the process of adjusting to an n-bit floating-point format.

[0060] In another exemplary embodiment, the bit width adjustment unit (311) can adjust the bit width of the mantissa of the input data based on bit width information and the bit width of the mantissa of the input data. Specifically, the bit width adjustment unit (311) can adjust the bit width of the mantissa of the input data by using the difference between the bit width of the mantissa included in the bit width information and the bit width of the mantissa of the input data. For example, the bit width adjustment unit (311) can adjust the bit width of the mantissa of the input data by truncation of the lower bits of the exponent of the input data by the difference between the bit width of the mantissa included in the bit width information and the bit width of the mantissa of the input data. Here, the lower bit may represent a bit of a smaller digit, i.e., a right bit.

[0061] The bit width adjustment unit (311) can output input data with adjusted bit width.

[0062] Meanwhile, the bit width adjustment unit (311) can restore an n-bit format floating-point number (a sequence of bits of a floating-point number calculated by the operation unit) output from the operation unit into a 32-bit format floating-point number. At this time, the bit width adjustment unit (311) can restore the 32-bit format floating-point number by performing the bit width adjustment process described above in reverse. For example, the bit width adjustment unit (311) can restore the bit width of the floating-point number exponent (8 bits) using the following mathematical formula 2.

[0063] [Mathematical Formula 2]

[0064]

[0065] Additionally, the bit width adjustment unit (311) can restore the bit width of the floating-point mantissa (23 bits) by left-shifting the bit sequence of the floating-point mantissa (the shifted bit sequence is converted to 0).

[0067] The operation unit (312) can perform operations on input data with adjusted bit width. The operation unit (312) may be an arithmetic unit capable of performing MAC operations. The operation unit (312) can perform multiplication and addition operations between input data with adjusted bit width. For example, the operation unit (312) can perform multiplication and addition operations between a weight value with adjusted bit width and an input feature map with adjusted bit width.

[0068] In an exemplary embodiment, the operation unit (312) may replace the existing multiplier with an approximate multiplier and perform multiplication operations according to the operation algorithm of the approximate multiplier. Specifically, the operation unit (312) may perform approximate multiplication between the exponents of each bit-width-adjusted input data and approximate multiplication between the mantissas, and then perform operations through normalization.

[0069] The operation algorithm of the approximate multiplier separates the mantissa bit sequence of each input data into upper n bits and lower kq bits, performs addition by operating on the product of the upper n bits of the mantissa bit sequence, the product of the upper n bits of the mantissa bit sequence and the lower k bits of the mantissa bit sequence, and the product of the lower bits of the mantissa bit sequence, and can truncate the lower bits to fit the bit width (since the bit width has doubled due to the multiplication between mantissa bit sequences, the lower bits are truncated by the bit width). Multiplication between the exponents of each input data can be performed using a general floating-point operation method. Here, the upper bit can represent the bit of the larger digit, i.e., the left bit, and the lower bit can represent the bit of the smaller digit, i.e., the right bit.

[0070] Meanwhile, although the present invention describes the approximation multiplier as performing only the multiplication between mantissas using the approximation multiplication method, it is not limited thereto, and the approximation multiplication algorithm can be applied to the multiplication between exponents or the multiplication between mantissas according to the operation algorithm of the approximation multiplier set by the user.

[0071] In another exemplary embodiment, the operation unit (312) may replace the existing adder with an approximate adder and perform an addition operation according to the operation algorithm of the approximate adder. Specifically, the operation unit (312) may perform an approximate addition between the exponents of each bit-width-adjusted input data and an approximate addition between the mantissas, and then perform an operation through normalization.

[0072] The operation algorithm of the approximation adder separates the mantissa bit sequence of each input data into an accurate part and an inaccurate part, and performs addition on the accurate part of the input data mantissa bit sequence, while performing an OR operation on the inaccurate part. In this case, the carry generated by performing an AND operation on the most significant bit of the inaccurate part can be added to the accurate part. The addition between the exponents of each input data can be performed using a general floating-point operation method.

[0073] Meanwhile, although the present invention has been described as an approximation adder that performs only the addition between mantissas using the approximation addition method, it is not limited thereto, and an approximation addition algorithm can be applied to the addition between exponents or the addition between mantissas according to the operation algorithm of the approximation adder set by the user.

[0075] The learning / inference module (320) can perform learning and inference on multiple deep neural networks using the computation module (311).

[0076] In one embodiment, the learning / inference module (320) can input training data into each of the multiple deep neural network models to train each deep neural network model. Here, operations related to the training of the deep neural network models can be performed using the operation module (311). For example, the deep neural network models may include ResNet, VGGNet, DenseNet, GoogleNet, Inception-v3, SDNN (Spiking DNN), DCSNN (Deep Convolution SNN), R-STDP, etc.

[0077] In another embodiment, the learning / inference module (320) may input test data into a plurality of trained deep neural network models, each of which may output an inference result. Here, operations related to the inference of the deep neural network models may be performed using an operation module.

[0078] For example, the learning / inference module (320) can use the PyTorch library to train and infer a deep neural network model through feedforward propagation, backward propagation, and SNN training, thereby generating a deep neural network model with an approximation adder based on an approximation addition algorithm designed by the user and an approximation multiplier based on an approximation multiplication algorithm applied. The training and inference of the deep neural network model can be performed using loss functions and optimization methods provided by the PyTorch library. Additionally, SNN training can be performed using the SNN training function of SpykeTorch (e.g., STDP).

[0080] The result providing module (400) can provide performance evaluation and monitoring information for multiple deep neural network models for the computation module (311). For example, the result providing module (400) can provide information on the learning accuracy, inference accuracy, simulation time, training weights, and error characterization of multiple deep neural network models for the computation module (311) based on the results of the simulation of multiple deep neural network models for the computation module (311) through the simulation module (300). Through this, a user who receives performance evaluation and monitoring information can analyze and evaluate the impact of the approximation algorithm (approximation adder and approximation multiplier) set by the user on the deep neural network model.

[0081] Additionally, the result providing module (400) performs a performance evaluation of multiple deep neural network models for the computation module (311) and can select one or more deep neural network models among the multiple deep neural network models based on the performance evaluation results. The result providing module (400) calculates the learning accuracy, inference accuracy, and simulation time of the multiple deep neural network models for the computation module (311) from the simulation results of the multiple deep neural network models for the computation module (311), and can calculate a performance evaluation score for each deep neural network model based on this. For example, a higher score may be assigned as the learning accuracy and inference accuracy are higher, and a lower score may be assigned as the simulation time is shorter. That is, the result providing module (400) calculates a performance evaluation score for each deep neural network model, and then selects one or more deep neural network models as deep neural network models for the computation module (311) based on the performance evaluation scores.

[0082] According to the disclosed embodiment, by approximating the Multiplication and Accumulation (MAC) operation, it is possible to design a MAC operator that minimizes area without significantly reducing accuracy.

[0083] In addition, according to the disclosed embodiment, by designing a MAC operator using CUDA, simulations of multiple deep neural network models can be performed through a Python-based framework.

[0084] In this specification, the term "module" may refer to a functional and structural combination of hardware for carrying out the technical concept of the present invention and software for driving said hardware. For example, the "module" may refer to a logical unit of a specific code and a hardware resource for executing said code, and does not necessarily refer to physically connected code or a single type of hardware.

[0086] FIG. 5 is a flowchart illustrating a simulation method for a MAC operator for deep neural network computation according to an embodiment of the present invention. The method illustrated in FIG. 5 may be performed, for example, by a simulation device for a MAC operator for deep neural network computation described above. Although the method is described in the illustrated flowchart by dividing it into a plurality of steps, at least some of the steps may be performed in a different order, combined with other steps and performed together, omitted, divided into detailed steps, or performed with one or more steps not illustrated added.

[0087] In step 510, the simulation device (100) of the MAC computer for deep neural network computation can receive training data and test data. For example, the training data and test data may be the MNIST dataset (Modified National Institute of Standards and Technology), the CIFAR-10 dataset and the ETH-80 dataset, etc.

[0088] In step 520, the simulation device (100) of the MAC operator for deep neural network operation can receive bit width information, an approximate operation adder, and an approximate operation multiplier. For example, the simulation device (100) of the MAC operator for deep neural network operation can receive bit width information for floating-point numbers from a user to adjust the bit widths of the exponent and mantissa of the floating-point numbers. Additionally, the simulation device (100) of the MAC operator for deep neural network operation can receive an approximate operation adder according to a designed approximate operation addition algorithm and an approximate operation multiplier according to an approximate operation multiplication algorithm from a user.

[0089] In step 530, the simulation device (100) of the MAC calculator for deep neural network computation can simulate multiple deep neural network models based on bit width information, approximate computation adders, and approximate computation multipliers.

[0090] In step 540, the simulation device (100) of the MAC computer for deep neural network computation can evaluate the performance of multiple deep neural network models. For example, the simulation device (100) of the MAC computer for deep neural network computation can provide information on the learning accuracy, inference accuracy, simulation time, training weights, and error characterization of multiple deep neural network models for the computation module (311) based on the results of the simulation of multiple deep neural network models for the computation module (311) through the simulation module (300).

[0091] According to the disclosed embodiment, by approximating the Multiplication and Accumulation (MAC) operation, it is possible to design a MAC operator that minimizes area without significantly reducing accuracy.

[0092] In addition, according to the disclosed embodiment, by designing a MAC operator using CUDA, simulations of multiple deep neural network models can be performed through a Python-based framework.

[0094] FIG. 6 is a flowchart illustrating step 530 of a simulation method for a MAC calculator for deep neural network computation according to an embodiment of the present invention. Although the method is described in the illustrated flowchart in a plurality of steps, at least some of the steps may be performed in a different order, combined with other steps and performed together, omitted, divided into detailed steps, or performed with one or more steps not illustrated added.

[0095] In step 531, the simulation device (100) of the MAC calculator for deep neural network computation can receive multiple input data expressed as floating points.

[0096] In step 532, the simulation device (100) of the MAC operator for deep neural network computation can adjust the bit widths of the exponents and mantissas of the input data. For example, the simulation device (100) of the MAC operator for deep neural network computation can adjust the bit width of the exponents of the input data based on bit width information and the bit width of the exponents of the input data. Additionally, the simulation device (100) of the MAC operator for deep neural network computation can adjust the bit width of the mantissa of the input data based on bit width information and the bit width of the mantissa of the input data.

[0097] In step 533, the simulation device (100) of the MAC operator for deep neural network operation can replace the adder and multiplier with an approximate operation adder and approximate operation multiplier.

[0098] In step 534, the simulation device (100) of the MAC operator for deep neural network operation can perform operations between bit-width-adjusted input data. For example, the simulation device (100) of the MAC operator for deep neural network operation can perform multiplication operations according to the operation algorithm of the approximation multiplier. Specifically, the simulation device (100) of the MAC operator for deep neural network operation can perform approximation multiplication between the exponents of each bit-width-adjusted input data and approximation multiplication between the mantissas, and then perform operations through normalization. Additionally, the simulation device (100) of the MAC operator for deep neural network operation can perform addition operations according to the operation algorithm of the approximation adder. Specifically, the simulation device (100) of the MAC operator for deep neural network operation can perform approximation addition between the exponents of each bit-width-adjusted input data and approximation addition between the mantissas, and then perform operations through normalization.

[0099] Meanwhile, the simulation device (100) of the MAC calculator for deep neural network computation can restore an n-bit format floating-point number (a sequence of bits of a floating-point number computed by the computation unit) output from the computation unit to a 32-bit format floating-point number.

[0101] FIG. 7 is a block diagram illustrating a computing environment including a computing device suitable for use in exemplary embodiments. In the illustrated embodiments, each component may have different functions and capabilities in addition to those described below, and may include additional components in addition to those described below.

[0102] The illustrated computing environment (10) includes a computing device (12). In one embodiment, the computing device (12) may be a simulation device for a MAC computer for deep neural network computation.

[0103] The computing device (12) includes at least one processor (14), a computer-readable storage medium (16), and a communication bus (18). The processor (14) can cause the computing device (12) to operate according to the exemplary embodiment described above. For example, the processor (14) can execute one or more programs stored in the computer-readable storage medium (16). The one or more programs may include one or more computer-executable instructions, and the computer-executable instructions may be configured to cause the computing device (12) to perform operations according to the exemplary embodiment when executed by the processor (14).

[0104] A computer-readable storage medium (16) is configured to store computer-executable instructions or program code, program data and / or other suitable forms of information. A program (20) stored in the computer-readable storage medium (16) includes a set of instructions executable by a processor (14). In one embodiment, the computer-readable storage medium (16) may be memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other forms of storage media that are accessed by a computing device (12) and capable of storing desired information, or a suitable combination thereof.

[0105] The communication bus (18) interconnects various other components of the computing device (12), including the processor (14) and the computer-readable storage medium (16).

[0106] The computing device (12) may also include one or more input / output interfaces (22) and one or more network communication interfaces (26) that provide interfaces for one or more input / output devices (24). The input / output interfaces (22) and the network communication interfaces (26) are connected to a communication bus (18). The input / output devices (24) may be connected to other components of the computing device (12) through the input / output interfaces (22). An exemplary input / output device (24) may include an input device such as a pointing device (such as a mouse or trackpad), a keyboard, a touch input device (such as a touchpad or touchscreen), a voice or sound input device, various types of sensor devices and / or imaging devices, and / or an output device such as a display device, a printer, a speaker and / or a network card. An exemplary input / output device (24) may be included inside the computing device (12) as a component constituting the computing device (12), or it may be connected to the computing device (12) as a separate device distinct from the computing device (12).

[0108] Although representative embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications can be made to the above-described embodiments without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof. Explanation of the symbols

[0110] 100: Simulation device for a MAC computer for deep neural network computation 200 : Input module 300 : Simulation Module 310: Computation module 311: Bit width adjustment section 312 : Operation unit 320 : Learning / Inference Module 400: Result providing module

Claims

Claim 1 A simulation device for a MAC computer for deep neural network computation, comprising one or more processors and a memory for storing one or more programs executed by said one or more processors, wherein the simulation device comprises: an input module for receiving approximate computation information including bit width information, an approximate computation adder, and an approximate computation multiplier; a simulation module for performing simulations for a plurality of deep neural network models using previously stored training data and test data based on the received approximate computation information; and a result providing module for performing performance evaluations for each deep neural network model based on the results of each simulation when each simulation is performed, wherein the approximate computation information includes bit width information for floating-point numbers for adjusting the bit widths of the exponent and mantissa of a floating-point number from a user, an approximate computation adder according to an approximate computation addition algorithm written by the user, and an approximate computation multiplier according to an approximate computation multiplication algorithm, wherein the simulation module comprises an computation module for performing operations accompanying the deep neural network model. and further includes a learning and inference module that performs learning and inference on the plurality of deep neural network models using the above-described operation module, wherein the operation module includes a bit width adjustment unit that receives a plurality of input data expressed as floating points from the learning and inference module and adjusts the bit width of the exponent and mantissa of each of the input data;A simulation device for a MAC calculator for deep neural network computation, comprising: a computation unit that replaces a previously configured adder and multiplier with an input approximate operation adder and approximate operation multiplier, and performs operations between input data with adjusted bit widths according to a computation algorithm configured in the replaced approximate operation adder and approximate operation multiplier; wherein the bit width adjustment unit adjusts the bit width of the input data by truncation of the lower bits of the exponent of the input data by the difference between the bit width of the mantissa included in the bit width information and the bit width of the mantissa of the input data. Claim 2 delete Claim 3 A simulation device for a MAC computer for deep neural network computation, wherein the approximation addition algorithm and the approximation multiplication algorithm are implemented using CUDA (Compute Unified Device Architecture). Claim 4 delete Claim 5 delete Claim 6 A simulation device for a MAC calculator for deep neural network computation according to claim 1, wherein the bit width adjustment unit adjusts the bit width of the exponent of the input data based on the bit width information and the size of the exponent of the input data, and determines the bit width of the exponent of the input data using the following mathematical formula 1. [Mathematical Formula 1] (Here, subscript n is the bit width of the floating-point number to be adjusted, is an n-bit floating-point exponent, is the bias value of the exponent of an n-bit floating-point number, the subscript n is the bit width of the exponent to be adjusted, is the bit width of the exponent of an n-bit floating-point number) Claim 7 delete Claim 8 A method for simulating a MAC operator for deep neural network computation performed in a computing device having one or more processors and a memory storing one or more programs executed by said one or more processors, comprising: receiving approximate operation information including bit width information, an approximate operation adder, and an approximate operation multiplier; and performing a simulation of a plurality of deep neural network models using previously stored training data and test data based on the received approximate operation information. The method includes the step of performing a performance evaluation of each deep neural network model based on the results of each simulation when each simulation is performed, wherein the approximation information includes bit width information for floating-point numbers for adjusting the bit widths of the exponent and mantissa of floating-point numbers from a user, an approximation adder according to an approximation addition algorithm written by the user, and an approximation multiplier according to an approximation multiplication algorithm, wherein the step of performing the simulation includes: receiving a plurality of input data expressed as floating-point numbers; adjusting the bit widths of the exponent and mantissa of each of the input data; and replacing a pre-set adder and multiplier with the input approximation adder and approximation multiplier. A simulation method for a MAC operator for deep neural network operation, comprising the step of performing an operation between input data with adjusted bit widths according to an operation algorithm set in the replaced approximate operation adder and approximate operation multiplier, wherein the step of adjusting the bit widths adjusts the bit width of the input data by truncation of the lower bits of the exponent of the input data by the difference between the bit width of the mantissa included in the bit width information and the bit width of the mantissa of the input data. Claim 9 delete Claim 10 A simulation method of a MAC computer for deep neural network computation, wherein the approximate addition algorithm and the approximate multiplication algorithm are implemented using CUDA (Compute Unified Device Architecture). Claim 11 delete Claim 12 A simulation method of a MAC calculator for deep neural network computation according to claim 8, wherein the step of adjusting the bit width adjusts the bit width of the exponent of the input data based on the bit width information and the size of the exponent of the input data, and determines the bit width of the exponent of the input data using the following Equation 1. [Equation 1] (Here, subscript n is the bit width of the floating-point number to be adjusted, is an n-bit floating-point exponent, is the bias value of the exponent of an n-bit floating-point number, the subscript n is the bit width of the exponent to be adjusted, is the bit width of the exponent of an n-bit floating-point number) Claim 13 delete

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