Inverting top-tier FET for multi-tier gate-on-gate 3D integration (3DI)

Abstract

An embodiment of the present disclosure provides a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure may include a first semiconductor device tier comprising a first semiconductor device. A first signal wiring structure may be formed on the first semiconductor device tier and electrically connected. An insulator layer may be formed on the first signal wiring structure. A second semiconductor device tier may be formed on the insulator layer, and the second semiconductor device tier includes a second semiconductor device. A second signal wiring structure may be formed on the second semiconductor device tier and electrically connected. An inter-tier via may be formed vertically through the insulator layer and the second signal wiring structure may be electrically connected to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier, and the inter-tier via may be formed monolithically.

Description

Technology Field

[0001] Inclusion by reference

[0002] The present disclosure claims the benefit of U.S. Provisional Application No. 63 / 151,166, filed February 19, 2021, with the title of the invention "Inverted top-tier FET for multi-tier gate-on-gate 3Di", and U.S. Provisional Application No. 17 / 542,024, filed December 3, 2021, with the title of the invention "Inverted top-tier FET for multi-tier gate-on-gate 3Di", the full text of which is incorporated herein by reference.

[0003] The present disclosure generally relates to a microelectronic device comprising a semiconductor device, a transistor, and an integrated circuit, and a microfabrication method. Background Technology

[0004] During the manufacturing of semiconductor devices (particularly on a microscopic scale), various manufacturing processes such as film deposition, etching mask generation, patterning, material etching and removal, and doping are executed. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, transistors were characterized by two-dimensional (2D) circuits or 2D manufacturing because wiring and metallization were formed on a single plane through microfabrication. Scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, making it possible to integrate heterogeneous functional circuits, such as logic circuits and memory circuits, onto the same semiconductor substrate. However, 2D scaling efforts are facing more challenges as miniaturization enters the single-digit nanometer semiconductor device manufacturing node. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked vertically on top of each other as another means of further miniaturizing integrated circuits (ICs). [Patent Document 1] : U.S. Patent Application Publication US2018 / 0108607 means of solving the problem

[0005] An aspect of the present disclosure provides a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure may include a first semiconductor device tier comprising a first semiconductor device. A first signal wiring structure may be formed on the first semiconductor device tier and electrically connected. An insulator layer may be formed on the first signal wiring structure. In an embodiment, the insulator layer may include a silicon-on-insulator (SoI) layer. A second semiconductor device tier may be formed on the insulator layer, and the second semiconductor device tier may include a second semiconductor device. A second signal wiring structure may be formed on the second semiconductor device tier and electrically connected. An inter-tier via may be formed vertically through the insulator layer and the second signal wiring structure may be electrically connected to the first signal wiring structure. In an embodiment, the first semiconductor device tier, the second semiconductor device tier, and the inter-tier via may be formed monolithically.

[0006] For example, a tier-to-tier via may be formed within a diffusion-prevention region that vertically isolates adjacent devices among the second semiconductor devices. As another example, the second semiconductor device tier may include a dummy poly, and the tier-to-tier via may be aligned with the dummy poly.

[0007] In an embodiment, the multi-tier semiconductor structure may further include a substrate, and a first semiconductor device tier may be formed on the substrate. For example, the multi-tier semiconductor structure may further include a first power rail, and such first power rail is embedded within the substrate and electrically connected to the first semiconductor device tier. As another example, the multi-tier semiconductor structure may further include a second power rail, and the second power rail is formed on the second semiconductor device tier and electrically connected to the second semiconductor device tier.

[0008] In an embodiment, the first semiconductor device may be stacked vertically on top of each other and / or the second semiconductor device may be stacked vertically on top of each other. For example, the second semiconductor device may include a field effect transistor (FET).

[0009] In an embodiment, the multi-tier semiconductor structure may further include a vertically formed contact to electrically connect the second semiconductor device tier to the second signal wiring structure. In another embodiment, the multi-tier semiconductor structure may further include a vertically formed contact through an insulator layer to electrically connect the second semiconductor device tier to the first signal wiring structure. For example, the contact may include a gate contact that electrically connects the gate region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure. As another example, the contact may include a source / drain contact that electrically connects the source / drain region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure.

[0010] Aspects of the present disclosure further provide a method for manufacturing a multi-tier semiconductor structure. For example, the method may include the step of forming a first semiconductor device tier, wherein the first semiconductor device tier comprises a first semiconductor device. The method may further include the step of forming a first signal wiring structure on the first semiconductor device tier and electrically connecting the first signal wiring structure to the first semiconductor device tier, and forming an insulator layer on the first signal wiring structure. In an embodiment, the insulator layer may comprise an SoI layer. The method may further include the step of forming a second semiconductor device tier on the insulator layer, wherein the second semiconductor device tier comprises a second semiconductor device. The method may further include the step of forming a second signal wiring structure on the second semiconductor device tier and electrically connecting the second signal wiring structure to the second semiconductor device tier, and forming a tier-to-tier via vertically through the insulator layer to electrically connect the second signal wiring structure to the first signal wiring structure. In an embodiment, a first semiconductor device tier, a second semiconductor device tier, and tier-to-tier vias are formed monolithically.

[0011] In an embodiment, the step of forming a tier-to-tier via may include forming the tier-to-tier via within a diffusion prevention region that vertically isolates adjacent devices among the second semiconductor devices. For example, the second semiconductor device tier may include a dummy poly, and the tier-to-tier via is aligned with the dummy poly.

[0012] In an embodiment, the method may further include the step of forming a contact vertically through an insulating layer to electrically connect a second semiconductor device tier to a first signal wiring structure.

[0013] It should be noted that the “Description of the Invention” section does not specify all embodiments and / or progressively new aspects of the present disclosure or the claimed disclosure. Instead, the “Description of the Invention” section provides only a preliminary discussion of embodiments that differ from the prior art and corresponding points of novelty. For further details and / or possible aspects of the present disclosure and embodiments, the reader refers to the “Description of the Invention for Practice” of the present disclosure and the corresponding drawings as further described below. Brief explanation of the drawing

[0014] Various embodiments of the present disclosure presented as examples will be described in detail below with reference to the drawings, in which the same reference numerals indicate the same components. Figure 1 illustrates a simplified cross-sectional view of a semiconductor segment. FIG. 2 illustrates a semiconductor structure comprising two semiconductor segments manufactured by face-to-face 3D integration (3Di). FIG. 3 illustrates a semiconductor structure comprising two semiconductor segments manufactured by face-to-face 3Di. FIG. 4 illustrates a semiconductor structure comprising two semiconductor segments manufactured by a sequential 3Di process. FIG. 5 illustrates a semiconductor structure comprising two semiconductor segments manufactured by a sequential 3Di process. FIG. 6(a) illustrates a cross-sectional view of an exemplary multi-tier semiconductor structure of FIG. 6(b) according to some embodiments of the present disclosure. FIG. 6(b) illustrates a perspective view of a semiconductor structure according to some embodiments of the present disclosure. FIGS. 7(a) and FIGS. 7(b) respectively show a top view and a bottom view (or layout drawing) of an exemplary multi-tier semiconductor structure of FIGS. 7(c) according to some embodiments of the present disclosure. FIG. 7(c) illustrates a perspective view of a semiconductor structure according to some embodiments of the present disclosure. FIGS. 8a to 8d each illustrate cross-sectional views of the semiconductor structures shown in FIGS. 7(a) to 7(c) along lines 8a-8a', 8b-8b', 8c-8c', and 8d-8d' of FIGS. 7(a) and FIGS. 7(b), according to some embodiments of the present disclosure. FIG. 9 is a flowchart illustrating an exemplary method for manufacturing a multi-tier semiconductor structure according to some embodiments of the present disclosure. Specific details for implementing the invention

[0015] As used herein, the word "exemplary" is used to mean "functions as an example, illustration, or description." Any embodiment of a configuration, process, design, technology, etc., indicated herein as exemplary is not to be interpreted as being more desirable or advantageous than other embodiments. No specific quality or fitness of the examples indicated herein as exemplary is intended or to be inferred.

[0016] Additionally, spatially relative terms such as “bottom,” “below,” “lower,” “top,” and “upper” may be used herein to facilitate the description of the relationship between one element or feature and another element(s) or feature(s) depicted in the drawings. Spatially relative terms are intended to include not only the orientation depicted in the drawings but also other orientations of the device (or apparatus) in use or operation. The device (or apparatus) may be oriented differently (it may be rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may likewise be interpreted accordingly.

[0017] The order of description for the different steps as described herein is provided for clarity. In general, these steps may be performed in any suitable order. Additionally, while each of the different features, techniques, configurations, etc. of this disclosure may be discussed in different places within this disclosure, each concept is intended to be practiced independently or in combination with one another. Accordingly, this disclosure may be embodied and illustrated in various different ways.

[0018] As described in the 'Background Technology,' semiconductor device manufacturers have expressed the need for three-dimensional (3D) semiconductor devices, in which transistors are stacked vertically, as an alternative means of miniaturizing ICs in addition to conventional 2D miniaturization. 3D integration (3Di), or the vertical stacking of semiconductor devices, aims to overcome these 2D scaling limitations by increasing transistor density within volume rather than area. While device stacking has been successfully demonstrated and implemented with the introduction of 3D NAND in the flash memory industry, applying it to random logic designs is significantly more challenging. 3D integration for logic chips such as central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), and systems-on-chips (SoCs) is being driven primarily by two approaches. One approach is heterogeneous stacking, while the other is more homogeneous.

[0019] Heterogeneous stacking utilizes wafer / chip stacking and through-silicon via (TSV) technologies, as disclosed in "Process Integration Modes Enabling 3D Sequential Stacking Planar and FinFET Technologies" (Anne VanDooren, IMEC PTW Spring 2018). For example, in this 3D integration approach, two chips can be optimized in design and fabrication for different specific tasks (e.g., one task includes chemical and biological sensors and the other includes nano-devices and micro-electrochemical systems (MEMS)), and TSVs can be used to integrate these two different functional chips to build a stacked SoC. Detailed information on the heterogeneous integration approach is provided in "Heterogeneous Integration Roadmap, 2019 edition published October 2019" (http: / / eps.ieee.org / hir).

[0020] Homogeneous stacking utilizes a wafer bonding process to overcome the density loss associated with micron-sized TSVs used in heterogeneous stacking. For example, a base wafer can be processed to form devices such as n-type metal-oxide semiconductors (nMOS) and p-type MOS (pMOS), and several layers of metallization / wiring, and then a thinned silicon-on-insulator (SOI) layer can be placed on top of the base wafer and bonded by oxide-oxide bonding to form a finished structure.

[0021] FIG. 1 illustrates a simplified cross-sectional view of a semiconductor segment (100). A substrate (or wafer) (110), for example, a silicon or SiGe substrate, may be provided. A tier of semiconductor devices (or semiconductor device tiers) (150) may be disposed on the front side (110a) of the substrate (110). For example, the tier of semiconductor devices (150) may include one or more semiconductor devices, such as field-effect transistors (FETs), which form a functional circuit such as a logic circuit or a memory circuit. Additionally, these FETs may be n-type or p-type FETs arranged along the front side (110a) or stacked vertically up and down along the thickness direction of the substrate (110).

[0022] One or more power rails (120) may be embedded within the substrate (110) and the tier (150) of the semiconductor device may be electrically connected to a power delivery network (PDN) (130) via a TSV (e.g., nano-scale) (140) to provide, for example, low voltage (Vss) and high voltage (VDD) power delivery from the PDN (130) to the tier (150) of the semiconductor device. The PDN (130) may be formed on the rear side (110b) of the substrate (110).

[0023] A signal wiring structure (or wiring tier) (160) may be placed on a tier (150) of a semiconductor device and may be used to electrically connect the tier (150) of the semiconductor device to, for example, a tier (not shown) of another semiconductor device placed on the wiring tier (160). The wiring tier (160) may include one or more wiring layers (or wiring levels), and each wiring layer includes one or more wiring tracks extending in a direction along the front side (110a) of the substrate (110). Generally, a wiring track within one wiring layer will extend in a direction perpendicular to the direction of a wiring track within an adjacent wiring layer. For example, the wiring tier (160) may include three wiring layers (1601, 1602 and 1603), and the wiring layer (1601) may include seven wiring tracks (1601a to 1601g) extending in a direction perpendicular to the direction of the wiring track within the wiring layer (1602) along the front side (110a) of the substrate (110) (e.g., perpendicular to the plane of the drawing floor).

[0024] FIG. 2 illustrates a semiconductor structure (200), which comprises two semiconductor segments manufactured by face-to-face 3D integration (3Di), namely a multi-tier stack of semiconductor devices with high density of inter-tier wiring for efficient logic-to-memory or logic-to-logic connections. FIG. 2 illustrates the end result targeted by the present disclosure. These two semiconductor segments may be constructed separately, and each semiconductor segment may include power distribution, semiconductor devices (e.g., FETs), and signal wiring structures. For example, a semiconductor structure (200) may include two of the semiconductor segments (100) shown in FIG. 1 that are vertically stacked one on top of the other by flipping one over, and each of the semiconductor segments (100) may include a power distribution (e.g., a power rail (120), a PDN (130), and a TSV (140)), a semiconductor device (e.g., a tier (150) of the semiconductor device), and a signal wiring structure (e.g., a signal wiring structure (160)). In face-to-face 3Di manufacturing, these two separately constructed semiconductor segments (100) are carefully aligned with each other and face-to-face bonded together at a bonding site (not shown) with a face-to-face bond. Generally, one of the semiconductor segments (100) may include a TSV leading to a bump (not shown) placed on the top of the semiconductor segment (100), which is used to connect a semiconductor structure (200) to the package as specifically described in “https: / / spectrum.ieee.org / tech-talk / semiconductors / processors / globalfoundries-arm-close-in-on-3d-chip-integration”.

[0025] FIG. 3 illustrates a semiconductor structure (300) comprising two semiconductor segments manufactured by face-to-face 3Di. It can be seen that face-to-face bonding may require a relatively high (or thick) wire stack (i.e., a large number of wiring layers) (12 wiring layers to extend to a pitch of 1 μm) in order to progressively extend the wiring pitch to a large value required to satisfy the overlay requirements of face-to-face bonding. In the process, this progressive extension leads to a significant increase in the area used, which prevents the achievement of the initial objective of density improvement sought in face-to-face 3Di. Therefore, this face-to-face 3Di approach is not a true monolithic integration, as wafers or wafer segments processed independently are stacked vertically on top of each other and cannot provide a true miniaturization solution for semiconductor manufacturing.

[0026] To achieve overlay tolerances compatible with dense inter-tier wiring, sequential 3Di (also referred to as monolithic 3Di in some places) is required.

[0027] FIG. 4 illustrates a semiconductor structure (400) comprising two semiconductor segments manufactured by a sequential 3Di process. In a sequential 3Di process, a complete bottom tier (410) (which may be similar to the semiconductor segment (100)) may be built at the introduction, and then a silicon-on-insulator (SoI) layer (490) may be bonded to the top of the bottom tier (410), and a top tier (420), which may be a power distribution, semiconductor device (e.g., FET), and signal wiring structure, may be finally built on top of the SoI layer (490). For example, the CoolCube, which is a sequential 3Di pioneered by CEA-Leti (more information can be found at https: / / en.wikipedia.org / wiki / Three-dimensional_integrated_circuit).TM In this case, the complete bottom tier (410) can be constructed in a thermal budget of up to 1,000°C, and then the SoI layer (490) can be bonded to the top of the bottom tier (410), and finally, the top tier (420) can be constructed on the SoI layer (490) in a different thermal budget of less than 600°C, for example, 500°C, which is much lower than 1,000°C. This low thermal budget can ensure that the performance of the bottom tier (410) is not degraded while the top tier (420) is being manufactured, and that the intrinsic performance of the top tier (420) is not reduced. The main advantage of this sequential 3Di process is the near-perfect alignment of the top tier (420) to the existing bottom tier (410). This can be achieved by lithographic alignment through the thin SoI layer (490).

[0028] FIG. 5 illustrates a semiconductor structure (500) comprising two semiconductor segments manufactured in a sequential 3Di process, e.g., a bottom tier (410) and a top tier (420) as illustrated in FIG. 4. As illustrated, the challenge in the sequential 3Di process is the connection between the top tier (420) and the bottom tier (410) (e.g., 510 and 520). For example, extending the top-tier signal laterally through inter-tier vias can block space and reduce the achievable device density in the top tier (420). Thus, the connection density competes directly with the device density of the top tier (420).

[0029] The present disclosure relates to a dense 3Di, in particular a gate-on-gate (GoG) 3Di, more specifically a sequential 3Di (known as monolithic) implemented with a dense nanoscale connection (distinguished from micro-scale connections achievable by face-to-face bonding). Embodiments of the present invention may also be applied to inverting transistor architectures configured to utilize dense connections in sequential 3Di. This is advantageous as the semiconductor industry is moving toward 3Di, and the term is becoming more commonplace.

[0030] The technology of the present invention includes an upper semiconductor device tier and a standard cell architecture, which can densely connect tier-to-tier connections while maintaining a dense upper semiconductor device tier layout by using a combination of a lower contact extending through a diffusion-prevention region and a monolithic inter-tier via (MIV) to route all pin connections to a wiring tier below the upper semiconductor device tier.

[0031] FIG. 6(a) illustrates a cross-sectional view of an exemplary multi-tier semiconductor structure (600) according to some embodiments of the present disclosure, and FIG. 6(b) is a perspective view illustrating only the top tier of the semiconductor structure (600). In an embodiment, the semiconductor structure (600) may include a substrate (610) (or wafer) (not shown in FIG. 6(b)). For example, the substrate (610) may be a silicon or SiGe substrate. A tier (651) of a first semiconductor device may be disposed on the front side (610a) of the substrate (610). For example, the tier (651) of the first semiconductor device may include one or more semiconductor devices, such as a field-effect transistor (FET), which forms a functional circuit such as a logic circuit or a memory circuit. Additionally, these FETs may be n-type or p-type FETs (e.g., NMOS and PMOS) arranged along the front side (610a) or stacked vertically up and down along the thickness direction of the substrate (610).

[0032] One or more first power rails (621) may be embedded within the substrate (610) and the tier (651) of the first semiconductor device may be electrically connected to the first PDN (631) via a first TSV (e.g., nano-scale) (641) to provide, for example, low voltage (Vss) and high voltage (VDD) power transfer from the first PDN (631) to the tier (651) of the first semiconductor device. The first PDN (631) may be formed on the rear side (610b) of the substrate (610).

[0033] A first signal wiring structure (or first wiring tier) (661) may be placed on a first semiconductor device tier (651) and may be used to electrically connect the first semiconductor device tier (651) to another semiconductor device tier (e.g., second semiconductor device tier (652)) placed on, for example, the first wiring tier (661) or another signal wiring structure (e.g., second signal wiring structure (or second wiring tier) (662)). Similar to the wiring tier (160) shown in FIG. 1, the first wiring tier (661) may also include one or more wiring layers (or wiring levels), each wiring layer including one or more wiring tracks extending in a direction along the front side (610a) of the substrate (610). For example, the first wiring tier (661) may comprise five wiring layers, and the top, middle, and bottom wiring layers may comprise seven, six, and seven wiring tracks, respectively. Generally, a wiring track within one wiring layer will extend in a direction perpendicular to the direction of a wiring track within an adjacent wiring layer. For example, a wiring track within the top wiring layer may extend along the front side (610a) of the substrate (610) in a direction perpendicular to the direction of a wiring track within a wiring layer immediately below the top wiring layer (e.g., perpendicular to the plane of the drawing surface).

[0034] An insulating layer (or SoI layer) (690) (not shown in the diagram for brevity and indicated by an arrow) can be formed on the first wiring tier (661) and bonded to the top thereof. For example, the insulating layer (690) may include a thermal silicon oxide (SiO2) layer.

[0035] A second semiconductor device tier (652) may be formed by depositing on the front side (690a) of an insulator layer (or SoI layer) (690). For example, the second semiconductor device tier (652) may include one or more semiconductor devices, such as FETs, that form a functional circuit, such as a logic circuit or a memory circuit. Additionally, these FETs may be n-type or p-type FETs arranged along the front side (690a) of the insulator layer (690) or stacked vertically above and below each other along the thickness direction of the insulator layer (690). For example, these FETs may form a standard cell, e.g., an XOR or NAND logic cell, and include a plurality of lower p-type FETs and a plurality of upper n-type FETs stacked vertically above the lower p-type FETs to form a complementary FET (CFET). Adjacent CFETs may be isolated by a diffusion-prevention region (653) (not shown for brevity but indicated by an arrow) that can provide space for a monolithic tier-to-tier via (MIV) (670) (described later) to pass through. For example, the diffusion-prevention region (653) may include a double diffusion prevention region (DDB) or a single diffusion prevention region (SDB). As another example, such a FET may be a gate-all-around (GAA) or GAA nano-sheet (GAA NS) FET having a source / drain region (S / D), a gate region (G), and a channel (or nano-channel) region (CH) that is entirely surrounded by the gate region (G). Although the description herein focuses on CFET and GAA devices for convenience, it will be understood that the technology of the present invention may be applied to other 3D device architectures.

[0036] A second signal wiring structure (or second wiring tier) (662) may be placed on a second semiconductor device tier (652) and may be used to electrically connect the second semiconductor device tier (651) to, for example, another semiconductor device tier (e.g., the first semiconductor device tier (651)) and another signal wiring structure (e.g., the first signal wiring structure (661)). Similar to the wiring tier (160) shown in FIG. 1, the second wiring tier (662) may include one or more wiring layers (or wiring levels), and each wiring layer includes one or more wiring tracks extending in a direction along the front side (690a) of the insulator layer (690). For example, the second wiring tier (662) may include one wiring layer, and the wiring layer may include two wiring tracks (662a and 662b).

[0037] One or more second power rails (622) may be formed on the second semiconductor device tier (652) and the second semiconductor device tier (652) may be electrically connected to the second PDN (632) via a second TSV (e.g., nano-scale) (642) to provide, for example, low voltage (Vss) and high voltage (VDD) power delivery from the second PDN (632) to the second semiconductor device tier (652). Thus, the second semiconductor device tier (652) may include an inverted top-tier FET of an exemplary multi-tier semiconductor structure (600).

[0038] One or more monolithic inter-tier vias (MIV) (670) may be formed to electrically connect the second wiring tier (662) to the first wiring tier (661). For example, the MIV (670) may be aligned with a dummy poly and formed vertically through a diffusion-prevention region (653) and an insulator layer (690) so as to electrically connect the second wiring tier (662) to the first wiring tier (661) without extending the top-tier signal laterally to the inter-tier vias.

[0039] Additionally, one or more connections may be formed to electrically connect the second semiconductor device tier (652) to the first wiring tier (661). For example, the connection may include one or more bottom gate contacts (680) formed vertically through an insulator layer (690) to electrically connect the gate region (G) of the lower FET of the second semiconductor device tier (652) to the outside (e.g., the first wiring tier (661)).

[0040] As illustrated in the example of FIG. 6(b), the top-tier of the semiconductor structure (600) is illustrated and shows one level of wiring above the device plane (e.g., a second wire tier (662)) and another level of wiring below the device plane (e.g., a first wire tier (661)). The level of wiring (661) represents the top of the bottom tier of the semiconductor structure (600). These two levels are illustrated in FIG. 7(a) and FIG. 7(b) as a top view (or layout drawing) of an exemplary top-tier semiconductor structure (700) of FIG. 7(c), which is a perspective view of the semiconductor structure (700) according to some embodiments of the present disclosure. In an embodiment, the semiconductor structure (700) may include first to third gate-on-gate logic cells (701 to 703), each logic cell including top and bottom semiconductor device tiers (TP and BM). For example, the upper and lower semiconductor device tiers (TP and BM) may each include a plurality of upper n-type FETs and lower p-type FETs of the second semiconductor device tier (652) of the semiconductor structure (600). Each of the upper and lower semiconductor device tiers (TP and BM) may form a plurality of FETs by including a plurality of source / drain (S / D) tracks arranged alternately with a plurality of gate (G) tracks. These FETs may be p-type FETs or n-type FETs. For example, the FETs in the lower semiconductor device tier (BM) may be p-type, and the FETs in the upper semiconductor device tier may be n-type, thereby forming CFETs. Each cell boundary may be formed by the first and second upper power tracks (731 and 732) and the left and right poly gate tracks (741 and 742).

[0041] As shown in FIG. 7 (a) and FIG. 7 (c), which illustrate a top view of the upper semiconductor device tier (TP) of the semiconductor structure (700), the upper power contact (780) can electrically connect the upper semiconductor device tier (TP) of the first logic cell (701) to the second upper power track (732) through a local interconnect (785), the upper gate contact (781) can electrically connect the gate region (G) of the upper semiconductor device tier (TP) of the second logic cell (702) to the first upper wiring track (762a), and the upper source / drain region contact (782) can electrically connect the source / drain region (S / D) of the upper semiconductor device tier (TP) of the third logic cell (703) to the second upper wiring track (762b) through a local interconnect (786). In an embodiment, the upper power contact (780), the upper gate contact (781), and the upper source / drain contact (782) may all be formed vertically along the thickness direction of the semiconductor structure (700), as further described in U.S. provisional application No. 63 / 085,583, filed September 30, 2020, titled “Connections from Buried Interconnects to Device Terminals in Multiple Stacked Devices Structures,” which is incorporated herein by reference.

[0042] As illustrated in FIG. 7(a) and FIG. 7(c), as well as FIG. 7(b), which illustrates a bottom view of a bottom semiconductor device tier (BM) of a semiconductor structure (700), a monolithic tier-to-tier via (MIV) (770) is formed vertically through an insulator layer (790) (not shown in FIG. 7(c) for clarity) to electrically connect a third upper wiring track (762c) to a third lower wiring track (761c), a bottom source / drain contact (783) can electrically connect a source / drain region (S / D) of the bottom semiconductor device tier (BM) of a first logic cell (701) to a first lower wiring track (761a), and a bottom gate contact (784) can electrically connect a gate region (G) of the bottom semiconductor device tier (BM) of a second logic cell (702) to a second lower wiring track (761b). There are. The first to third bottom wiring tracks (761a to 761c) may be referred to together as the bottom wiring tier (or the first wiring tier), and the first to third top wiring tracks (762a to 762c) may be referred to together as the top wiring tier (or the second wiring tier). In an embodiment, the MIV (770), bottom source / drain contact (783), and bottom gate contact (784) may all be formed vertically through an insulator layer (790) along the thickness direction of the semiconductor structure (700). For example, the MIV (770) may be self-aligned with a dummy poly gate, for example, the left poly gate track (741) of the first logic cell (701), and may be formed through a diffusion prevention region (753) that isolates neighboring CFETs.

[0043] FIGS. 8a through 8d are respective cross-sectional views of a semiconductor structure (700) along lines 8a-8a', 8b-8b', 8c-8c', and 8d-8d' of FIGS. 7(a) and FIGS. 7(b), according to some embodiments of the present disclosure. All pins (i.e., pieces of wiring structures to which tier-to-tier signal routing (661) is connected internally) may be terminated at a location below the upper and lower semiconductor device tiers (TP and BM) of the semiconductor structure (700). For example, the upper pin (A0) on the upper semiconductor device tier (TP) can be connected to the upper semiconductor device tier (TP) of the semiconductor structure (700) as shown in FIG. 8a and routed to the corresponding lower pin (A0) under the lower semiconductor device tier (BM) through the MIV (770), and the upper pins (A1 and B0) on the upper semiconductor device tier (TP) can be connected to the upper semiconductor device tier (TP) of the semiconductor structure (700) as shown in FIG. 8d and routed to the corresponding lower pins (A1 and B0) under the lower semiconductor device tier (BM) through each of the MIVs (771 and 772). As another example, the bottom pins (C0 and Y) can be directly connected to the bottom semiconductor device tier (BM) of the semiconductor structure (700) through the bottom source / drain contact (783) and bottom gate contact (784), as illustrated in FIG. 8b and FIG. 8c, respectively. FIG. 8b further illustrates that a gate dielectric material can be deposited on the channel region (CH) of the semiconductor device of the top and bottom semiconductor device tiers (TP and BM) by selective deposition. For example, an intermediate layer (IL) and a high-k layer (HK) can be formed sequentially on the channel region (CH). FIG. 8b further illustrates that a metal layer (ML) can be deposited on the high-k layer (HK). For example, the metal layer (ML) may comprise TiN, TaN, or TiAl.

[0044] FIG. 9 is a flowchart illustrating an exemplary method (900) for manufacturing a multi-tier semiconductor structure according to some embodiments of the present disclosure. In an embodiment, some of the steps of the illustrated exemplary method (900) may be performed simultaneously or in a different order than illustrated, replaced by other method steps, or omitted. Additional method steps may also be performed as desired. In other embodiments, the exemplary method (900) may correspond to the multi-tier semiconductor structures (600 and 700) illustrated in FIG. 6 (a), FIG. 6 (b), FIG. 7 (a) through FIG. 7 (c), and FIG. 8a through FIG. 8d.

[0045] In step (S910), a first semiconductor device tier including a first semiconductor device may be provided. For example, the first semiconductor device tier may include a first semiconductor device tier (651) of a semiconductor structure (600) illustrated in FIG. 6 (a). In an embodiment, the first semiconductor device tier may be formed on the front side of a substrate and may receive power provided by a PDN disposed on the rear side of the substrate through a power rail embedded in the substrate. For example, as illustrated in FIG. 6 (a), the first semiconductor device tier (651) may be formed on the front side (610a) of the substrate (610) and may receive power provided by a first PDN (631) disposed on the rear side (610b) of the substrate (610) through a first power rail (621) embedded in the substrate (610). The first semiconductor device may include a FET, and the FET may be an n-type or p-type FET, and may be arranged along the front side (610a) of the substrate (610) or may be stacked vertically up and down along the thickness direction of the substrate (110).

[0046] In step (S920), a first signal wiring structure (or a first wiring tier) may be formed on a first semiconductor device tier and electrically connected. For example, as shown in FIG. 6 (a), a first wiring tier (661) may be formed on a first semiconductor device tier (651) and electrically connected.

[0047] In step (S930), an insulating layer (or SoI layer) may be formed on the first signal wiring structure. For example, as shown in FIG. 6 (a), an insulating layer (690) may be formed on the first signal wiring structure (661). As another example, as shown in FIG. 7 (c), an insulating layer (790) may be formed on the first to third bottom wiring tracks (761a to 761c).

[0048] In step (S940), a second semiconductor device tier including a second semiconductor device may be formed on an insulator layer. For example, as illustrated in FIG. 6(a) and FIG. 6(b), the second semiconductor device tier may include a second semiconductor device tier (652) of a semiconductor structure (600) formed on an insulator layer (690). As another example, as illustrated in FIG. 7(c), the second semiconductor device tier may include upper and lower semiconductor device tiers (TP and BM) of a semiconductor structure (700) formed on an insulator layer (790). The second semiconductor device tier may be processed and constructed only after a second wafer of new Si is bonded to the first semiconductor device tier. In an embodiment, a second power rail may be formed on the second semiconductor device tier and may provide power from a PDN to the semiconductor device tier. For example, as illustrated in FIG. 6(a), a second power rail (622) may be formed over a second semiconductor device tier (652) and the second semiconductor device tier (652) may be electrically connected to a second PDN (632) via a second TSV (e.g., nano-scale) (642) to provide, for example, low voltage (Vss) and high voltage (VDD) power transfer from the second PDN (632) to the second semiconductor device tier (652). The second semiconductor device may include a FET, which may be an n-type or p-type FET, and may be arranged along the front side (690a) of the insulator layer (690) or stacked vertically up and down along the thickness direction of the insulator layer (690).

[0049] In step (S950), a second signal wiring structure (or a second wiring tier) may be formed on a second semiconductor device tier and electrically connected. For example, as shown in FIG. 6(a), a second wiring tier (662) may be formed on a second semiconductor device tier (652) of a second semiconductor structure (600) and electrically connected. As another example, as shown in FIG. 7(c), first to third upper wiring tracks (762a to 762c) may be formed on upper and lower semiconductor device tiers (TP and BM) of a semiconductor structure (700) and electrically connected.

[0050] In step (S960), a tier-to-tier via can be formed vertically through an insulator layer and electrically connected to a second signal wiring structure. For example, as shown in FIG. 6(a) and FIG. 6(b), a monolithic tier-to-tier via (MIV) (670) can be formed vertically through an insulator layer (690) to electrically connect a second wiring tier (662) to a first wiring tier (661). As another example, as shown in FIG. 7(a) through FIG. 7(c) and FIG. 8a, a monolithic tier-to-tier via (MIV) (770) can be formed vertically through an insulator layer (790) to electrically connect a third upper wiring track (762c) to a third lower wiring track (761c). In an embodiment, the tier-to-tier via may be formed within a diffusion prevention region that vertically isolates adjacent devices among the second semiconductor devices. For example, as shown in FIG. 6(b), the MIV (670) may be formed within a diffusion prevention region (653) that isolates adjacent semiconductor devices (e.g., CFETs) of the semiconductor structure (600). As another example, as shown in FIG. 7(c), the MIV (770) may be formed within a diffusion prevention region (753) that vertically isolates adjacent semiconductor devices (e.g., CFETs) of the upper and lower semiconductor device tiers (TP and BM) of the semiconductor structure (700). In another embodiment, the second semiconductor device tier may include a dummy poly, and the tier-to-tier via may be aligned with the dummy poly. For example, as shown in FIG. 7(a), the top semiconductor device tier (TP) may include a left poly gate track (741), and the MIV (770) may be aligned with the left poly gate track (741).In an embodiment, a lower source / drain contact (e.g., lower source / drain contact (783)) and a lower gate contact (e.g., lower gate contact (784)) are formed so that the source / drain region and the gate region of the lower semiconductor device tier of the second semiconductor device tier can be electrically connected to the lower wiring track (e.g., first and second lower wiring tracks (761a and 761b)), respectively. For example, the lower source / drain contact and the lower gate contact may be formed vertically through an insulator layer (790).

[0051] In the foregoing description, specific details have been described, such as the specific structure of the processing system and the description of the various components and processes used in that structure. However, it should be understood that the technology described herein may be implemented in other embodiments that deviate from these specific details, and that these details are for illustrative purposes only and are not intended to limit such implementation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Likewise, for illustrative purposes and to provide a complete understanding, specific numbers, materials, and configurations have been presented. Nevertheless, the embodiments may be implemented without such specific details. Components having substantially the same functional configuration have been given the same reference numerals, and any redundant descriptions may be omitted.

[0052] To aid in understanding various embodiments, various techniques have been described as multiple individual operations. The order of description should not be interpreted to mean that these operations must necessarily depend on the order. In practice, these operations do not need to be performed in the order presented. The described operations may be carried out in a different order than that of the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0053] As used herein, “substrate” or “target substrate” generally refers to an object processed according to some embodiments of the present disclosure. A substrate may comprise any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer or reticle, or a layer that is on or over a base substrate structure such as a thin film. Accordingly, a substrate is not limited to any specific base structure, a lower layer or a top layer, patterned or unpatterned, but rather is considered to include any such layer or base structure, and any combination of layers and / or base structures. Specific types of substrates may be mentioned in the description, but are for illustrative purposes only.

[0054] Furthermore, those skilled in the art will understand that many modifications can be made to the work of the technology described above while still achieving the same objective of the present invention. Such modifications are intended to be included within the scope of this disclosure. Accordingly, the foregoing description of the embodiments of the present invention is not intended to be limiting. Rather, any limitations on the embodiments of the present invention are set forth in the following claims.

Claims

Claim 1 A multi-tier semiconductor structure comprising: a first semiconductor device tier including a first semiconductor device; a first signal wiring structure formed on and electrically connected to the first semiconductor device tier; an insulator layer formed on the first signal wiring structure; a second semiconductor device tier formed on the insulator layer and including a second semiconductor device; a second signal wiring structure formed on and electrically connected to the second semiconductor device tier; and a second power rail formed on and electrically connected to the second semiconductor device tier. A multi-tier semiconductor structure comprising a tier-to-tier via formed vertically through the insulating layer and electrically connecting the second signal wiring structure to the first signal wiring structure, wherein the tier-to-tier via has two ends located opposite each other, the two ends each in direct contact with the second signal wiring structure and the first signal wiring structure, and the tier-to-tier via is electrically connected to the lower surface of the second signal wiring structure within an area above the second semiconductor device tier, and the second power rail does not horizontally overlap with said area. Claim 2 In claim 1, the tier-to-tier via is a multi-tier semiconductor structure formed within a diffusion prevention region that vertically isolates adjacent devices among the second semiconductor devices. Claim 3 A multi-tier semiconductor structure according to paragraph 2, wherein the second semiconductor device tier includes a dummy poly, and the tier-to-tier vias are aligned with the dummy poly. Claim 4 A multi-tier semiconductor structure according to claim 1, further comprising a substrate, wherein the first semiconductor device tier is formed on the substrate. Claim 5 A multi-tier semiconductor structure according to claim 4, further comprising a first power rail embedded within the substrate and electrically connected to the first semiconductor device tier. Claim 6 delete Claim 7 A multi-tier semiconductor structure according to claim 1, wherein the first semiconductor devices are stacked vertically up and down relative to each other and / or the second semiconductor devices are stacked vertically up and down relative to each other. Claim 8 In claim 7, the multi-tier semiconductor structure wherein the second semiconductor device comprises a field effect transistor (FET). Claim 9 A multi-tier semiconductor structure according to claim 1, wherein the first semiconductor device tier, the second semiconductor device tier, and the tier-to-tier vias are formed monolithically. Claim 10 A multi-tier semiconductor structure according to claim 1, further comprising a contact formed vertically to electrically connect the second semiconductor device tier to the second signal wiring structure. Claim 11 A multi-tier semiconductor structure according to claim 1, further comprising a contact formed vertically through the insulating layer to electrically connect the second semiconductor device tier to the first signal wiring structure. Claim 12 In claim 11, the contact comprises a gate contact that electrically connects a gate region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure, in a multi-tier semiconductor structure. Claim 13 In claim 11, the contact comprises a source / drain contact that electrically connects a source / drain region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure, in a multi-tier semiconductor structure. Claim 14 A multi-tier semiconductor structure according to claim 1, wherein the insulator layer comprises a silicon-on-insulator (SoI) layer. Claim 15 A method for manufacturing a multi-tier semiconductor structure, comprising: forming a first semiconductor device tier including a first semiconductor device; forming a first signal wiring structure on the first semiconductor device tier and electrically connecting the first signal wiring structure to the first semiconductor device tier; forming an insulating layer on the first signal wiring structure; forming a second semiconductor device tier on the insulating layer, wherein the second semiconductor device tier includes a second semiconductor device; forming a second signal wiring structure on the second semiconductor device tier and electrically connecting the second signal wiring structure to the second semiconductor device tier; A method comprising the steps of: forming a tier-to-tier via vertically through the insulating layer to electrically connect the second signal wiring structure to the first signal wiring structure, wherein the tier-to-tier via has two ends located opposite each other that are in direct contact with the second signal wiring structure and the first signal wiring structure, respectively, and the tier-to-tier via is electrically connected to the lower surface of the second signal wiring structure within an area above the second semiconductor device tier; and forming a second power rail above the second semiconductor device tier and electrically connecting the second power rail to the second semiconductor device tier, wherein the second power rail does not horizontally overlap with the area. Claim 16 A method according to claim 15, wherein the step of forming the tier-to-tier via comprises forming the tier-to-tier via within a diffusion prevention region that vertically isolates adjacent devices among the second semiconductor devices. Claim 17 In claim 16, the second semiconductor device tier comprises a dummy poly, and the tier-to-tier vias are aligned with the dummy poly, a method. Claim 18 A method according to claim 15, wherein the first semiconductor device tier, the second semiconductor device tier, and the tier-to-tier vias are formed monolithically. Claim 19 delete Claim 20 A method according to claim 15, further comprising the step of forming a contact vertically through the insulating layer to electrically connect the second semiconductor device tier to the first signal wiring structure.

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