One-time programmable Anti-Fuse physical cloning protection

Abstract

The method comprises the steps of: performing a first read operation on a memory cell of a programmed first OTP (one-time programmable) anti-fuse to determine the state of the memory cell based on a first parameter level; performing a second read operation on a memory cell of a programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level; identifying the memory cell of the programmed first OTP anti-fuse as an uncertain bit when the state determined during the first read operation and the state determined during the second read operation are different; and programming one or more memory cells of a second OTP anti-fuse based on the bit position of the identified uncertain bit of the first OTP anti-fuse.

Description

Technology Field

[0001] The present disclosure generally relates to a one-time programmable (OTP) system. In particular, the present disclosure relates to an OTP anti-fuse physical copy protection function. Background Technology

[0002] A Physical Unclonable Function (PUF) is a physically defined keyword that serves as a unique identifier for semiconductor devices, such as microprocessors. A PUF is a physical entity implemented within a physical structure. PUFs are based on unique physical variations that occur naturally during semiconductor manufacturing or post-processing. PUFs are typically implemented in integrated circuits and are used in applications with high security requirements, more specifically in cryptography. Prior art literature

[65535] U.S. Patent Application Publication No. US2010 / 0202183 (August 12, 2010)

[0003] In one embodiment, the method comprises: performing a first read operation on a memory cell of a programmed first OTP (one-time programmable) anti-fuse to determine the state of the memory cell based on a first parameter level; performing a second read operation on a memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level; identifying the memory cell of the programmed first OTP anti-fuse as an uncertain bit if the state determined during the first read operation and the state determined during the second read operation are different; and programming one or more memory cells of the second OTP anti-fuse based on the bit position of the identified uncertain bit of the programmed first OTP anti-fuse.

[0004] In one embodiment, the method comprises the steps of: performing a first read operation on memory cells of a first OTP (one-time programmable) anti-fuse; performing a second read operation on memory cells of a second OTP anti-fuse to determine the programmed / unprogrammed state of memory cells of a second OTP anti-fuse; and masking a portion of memory cells of the first OTP anti-fuse based on the second read operation, wherein the masked memory cells correspond to uncertain bits of the first OTP anti-fuse.

[0005] In one embodiment, the system includes a memory for storing instructions and a processor coupled to the memory for executing instructions. When the instructions are executed, the processor performs operations including: performing a first read operation on a memory cell of a programmed first OTP anti-fuse to determine the state of the memory cell based on a first parameter level; performing a second read operation on a memory cell of a programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level; identifying the memory cell of a programmed first OTP anti-fuse as an uncertain bit if the state determined during the first read operation and the state determined during the second read operation are different; and programming one or more memory cells of a second OTP anti-fuse based on the bit position of the identified uncertain bit of the first OTP anti-fuse.

[0006] The structure and operation of various embodiments, as well as additional features of the present disclosure, are described below in detail with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Brief explanation of the drawing

[0007] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of embodiments of the disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Additionally, the drawings are not necessarily drawn in proportion. FIG. 1 illustrates a physical copy protection function (PUF) key according to an embodiment of the present disclosure. FIG. 2 illustrates an exemplary graph of a normalized programmed cell current distribution function according to an embodiment of the present disclosure. FIG. 3 illustrates a flowchart of a process for generating a PUF key according to an embodiment of the present disclosure. FIG. 4 illustrates examples of normalized programmed cell currents of one-time programmable (OTP) PUF keywords according to an embodiment of the present disclosure. FIG. 5 illustrates the reading of an OTP PUF keyword during programming according to an embodiment of the present disclosure. FIG. 6 illustrates the reading of an OTP PUF pairing word during programming according to an embodiment of the present disclosure. FIG. 7 illustrates a flowchart of a process for reading a PUF key according to an embodiment of the present disclosure. FIG. 8 illustrates the reading of an OTP PUF keyword and an OTP PUF pairing word during application reading according to an embodiment of the present disclosure. FIG. 9 illustrates the reading of a PUF key during application reading according to an embodiment of the present disclosure. FIG. 10 illustrates an abstract diagram of an exemplary computer system in which embodiments of the present disclosure can operate. Specific details for implementing the invention

[0008] Aspects of the present disclosure relate to a one-time programmable (OTP) anti-fuse physical copy protection function (PUF).

[0009] To prevent physical duplication, PUF keys include the following attributes: the key is physically available when the chip is powered on, and physical inspection of the silicon die (e.g., imaging and reverse engineering) does not expose key information. By using other protection techniques while the chip is powered on, an adversary may not be able to retrieve the key.

[0010] PUF keys can be implemented as once-programmable (OTP) antifuses. An OTP antifuse is a type of non-volatile memory (NVM). Typically, a relatively high programming voltage (e.g., from about 5 V to about 10 V) is applied to the OTP antifuse to destroy the gate oxide of the antifuse cell transistor in order to create a conductive channel between the gate and the channel for data writing. This type of gate oxide destruction is permanent and irreversible physical damage. OTP antifuses have the advantages of small area, low power, high reliability, and fast readout.

[0011] OTP anti-fuse memory products can generate programmed cells having breakdown transistor gate oxides that exhibit stable and sufficiently high conductivity, which can be used to distinguish programmed cells from unprogrammed cells. The conductivity of well-programmed OTP cells can typically be represented by programmed cell currents that exhibit a normal distribution. Due to the nature of silicon and silicon manufacturing, relatively low or high conductivity of the breakdown transistor gate oxides occurs randomly at each cell location. Additionally, since the low or high conductivity of the breakdown transistor gate cannot be detected by physical inspection, PUF keywords can be generated to have programmed OTP cells. In the PUF keywords, low-conductivity cells can represent binary 0 (or low state) and high-conductivity cells can represent binary 1 (or high state), or vice versa.

[0012] The conductivity of programmed OTP anti-fuse cells undergoes fluctuations such as die-to-die processing, power supplies, temperature, and aging. These fluctuations can affect the stability of OTP PUF words. Therefore, improvement of OTP PUF stability is required. The OTP anti-fuse PUF method described herein provides high stability performance.

[0013] The approaches described herein provide a method for generating a PUF key having an all-cell-programmed OTP PUF keyword (OTP anti-fuse) and a partial-cell-programmed OTP PUF pairing word by using multiple read operations with different read conditions to define a PUF having binary 0s and 1s as well as masking all uncertain bits on the OTP PUF keyword. By using well-developed designs and program / read methodologies for the OTP words, desired conductivity levels are defined to increase the margins of application reads of the PUF key, as further described below. By using these increased margins, the OTP anti-fuse PUF method described herein can achieve improved stability of the PUF key for all silicon and for operational variations such as inter-die variation, supply power variation, and temperature variation, as understood by a person skilled in the art.

[0014] In one embodiment, by applying a relatively high programming voltage to the gates of the cell transistors of the OTP word and a relatively low voltage to the transistor channels to destroy the gate oxide, all cells or bits of the OTP anti-fuse or word are first programmed to generate a PUF keyword. After programming, each cell on the OTP word exhibits a certain degree of conductivity. Thus, with a desired read voltage for the cell gates and a desired read time length, all programmed cells read as high or binary 1 compared to a relatively low conductivity level L0. For example, the desired read time length may range from about 10 ns to about 1000 ns. Unprogrammed cells read as low or binary 0 compared to a low conductivity level L0. As discussed above, due to the characteristics of silicon and silicon manufacturing, each programmed cell with destroyed gate oxide exhibits randomly different conductivity levels at different cell locations on the OTP word.

[0015] Additionally, two read operations are performed on the programmed OTP word. During the first read operation, all programmed cells are compared with a high conductivity level L1 selected to be higher than L0. As a result, programmed cells with relatively low conductivity are read as a low state or binary 0, and cells with relatively high conductivity are read as a high state or binary 1. Cells read as binary 0 during the first read are considered as the 0s of the PUF keyword. During the second read operation, all programmed cells are compared with another high conductivity level L3 selected to be greater than L1. As a result, programmed cells with relatively high conductivity are read as a high state or binary 1, and cells with relatively low conductivity are read as a low state or binary 0. Cells read as binary 1 during the second read operation are considered as the 1s of the PUF keyword. All cells read as 1 during the first read and read as 0 during the second read are considered as uncertain bits that need to be masked during the application read of the PUF keyword. Thus, after two read operations, all programmed cells on the OTP word can be divided into three groups: one group with low conductivity, one group with medium conductivity, and one group with high conductivity. To generate the PUF keyword, cells with low conductivity are assigned to the 0s of the PUF keyword, and cells with high conductivity are assigned to the 1s of the PUF keyword. Meanwhile, cells with medium conductivity are assigned to uncertain bits, and the respective cell locations on the OTP word are recorded and used for masking the PUF keyword application read. The programmed OTP word is referred to as the OTP PUF keyword.

[0016] To enable masking of the uncertain bits of the OTP PUF keyword, a second OTP word is programmed as a pairing word of the OTP PUF keyword programmed in the first step. In the pairing word, all cells at the same cell locations as the uncertain bits of the OTP PUF keyword are programmed, while all other cells are not programmed. In one embodiment, all cells at the same cell locations as the uncertain bits of the OTP PUF keyword are not programmed, while all other cells are programmed. As introduced above, compared to a low conductivity level L0, all programmed cells on the pairing OTP word are read as a high state or binary 1, and all unprogrammed cells are read as a low state or binary 0. Therefore, during the PUF keyword application read, the bit locations of all uncertain bits of the OTP PUF keyword can be identified by reading the pairing OTP word having conductivity level L0. As a result, all uncertain bits of the OTP PUF keyword can be masked. Accordingly, one PUF key includes two OTP words (OTP anti-fuse), the first OTP word represents an OTP PUF keyword, and the second OTP word represents an OTP PUF pairing word.

[0017] During the application read of the PUF word, two read operations are performed to read the PUF keyword. During the first read operation, all cells on the OTP PUF keyword are compared with a predetermined high conductivity level L2 selected to be higher than conductivity level L1 but lower than conductivity level L3. If there are good margins between L1 and L2 as well as between L2 and L3, all 0s of the PUF key on the OTP PUF keyword are read as binary 0s, and all 1s of the PUF key on the OTP PUF keyword are read as binary 1s. For example, the read margin improvement can be about 10% to about 30%. Meanwhile, uncertain bits of the OTP PUF keyword are read as binary 0s or 1s. All these uncertain bits are masked based on performing a second read operation for the OTP PUF pairing word. During the second read operation, all cells of the OTP PUF pairing word are compared with a low conductivity level L0 selected to be lower than conductivity level L1. After the second read operation, bit position information of all 1s on the OTP PUF pairing word is used to mask all uncertain bits of the OTP PUF keyword. In one embodiment, the OTP PUF pairing word is read prior to the OTP PUF keyword.

[0018] FIG. 1 illustrates a physical anti-cloning function key according to an embodiment of the present disclosure. In one embodiment, a PUF key (100) may be generated by two OTP words. The first word may be referred to as an OTP PUF keyword (102) containing all the 0s and 1s of the PUF key, and the second word is referred to as an OTP PUF pairing word (104) used to mask uncertain bits on the OTP PUF keyword. All cells of the OTP PUF keyword (102) are programmed. Programmed cells having relatively low conductivity on the OTP PUF keyword (102) are designated as the 0s of the PUF key, whereas programmed cells having relatively high conductivity on the OTP PUF keyword (102) are designated as the 1s of the PUF key as previously described herein. Programmed cells having medium conductivity are designated as uncertain bits, and the cell locations of the uncertain bits on the OTP PUF keyword (102) are written on the OTP PUF pairing word (104) by programming. To program the OTP PUF pairing word (104), all cells having cell locations identical to the uncertain bits of the OTP PUF keyword (102) are programmed. During application reading of the PUF key (100), PUF key information can be read from the OTP PUF keyword (102), and the uncertain bits of the OTP PUF keyword (102) are masked by cell location information read from the bits programmed on the OTP PUF pairing word (104). In the OTP PUF method described herein, the stability of the OTP PUF key is improved by introducing the OTP PUF pairing word (104) to mask programmed cells having medium conductivity on the OTP PUF keyword (102).

[0019] In the following description, the normalized programmed cell current I cella is used as an example to represent the conductivity of OTP-programmed cells as well as the threshold of the OTP reading operation. A person skilled in the art will understand that other OTP reading parameters, such as the reading voltage level or the reading pulse time length or any combination thereof, may also be utilized in the reading operation of OTP PUF words.

[0020] FIG. 2 illustrates an exemplary graph (200) of a normalized programmed cell current distribution function (NDF) according to an embodiment of the present disclosure. An OTP anti-fuse memory product can generate programmed cells with stable and relatively high cell currents. The cell currents of properly programmed OTP cells typically have a normal distribution as indicated by the waveform (202). Programmed cell current levels occur randomly across cell locations on the OTP word or within the OTP memory array.

[0021] FIG. 3 illustrates a flowchart of a process (300) for generating a PUF key according to an embodiment of the present disclosure.

[0022] In 302, the PUF keyword is generated based on programming all cells (memory cells) or bits of an OTP word (first OTP anti-fuse) by applying a relatively low voltage to the transistor channels to destroy the gate oxide and a relatively high programming voltage on the gates of the cell transistors of the OTP word. In one embodiment, one or more programmed cells of the OTP word may be read as unprogrammed if the cell current of the programmed cell is less than L0.

[0023] FIG. 4 illustrates an example of normalized programmed cell currents of an OTP PUF keyword according to an embodiment of the present disclosure. Cell current levels occur randomly at each cell location due to the characteristics of silicon and silicon manufacturing. Table 400 shows OTP PUF keyword current levels (402) and corresponding cell locations (404).

[0024] In 304, all programmed cells of the PUF keyword are read. The system performs a first comparison of the parameter values ​​of each programmed cell against a first parameter level. The parameter value may be a parameter associated with the conductivity of the memory cell. The first parameter level may include a first conductivity level or a representative current level of the first conductivity level. For example, the current level of each programmed cell is the first current level (I cell_1 It is compared with ).

[0025] In 306, all programmed cells of the PUF keyword are read again. The system performs a second comparison of the parameter values ​​of each programmed cell for a second parameter level. For example, the current level is the second current level (I cell_3 It is compared with ). In this example, I cell_1 is 0.55, and I cell_3 is 0.75. Both are normalized current figures. I cell_1 and I cell_3 It is as shown in Fig. 2.

[0026] In 308, the state is associated with each cell of the PUF key based on the first comparison and the second comparison. For example, the first current level (I cell_1 Programmed cells having a cell current lower than ) are designated as binary 0 of the PUF key, and the second current level (I cell_3 Programmed cells with a cell current higher than ) are designated as binary 1 of the PUF key. The first current level (I cell_1 ) and the second current level (Icell_3 Cells having cell currents between ) are designated as uncertain bits or 0 / 1. FIG. 5 illustrates the reading of an OTP PUF keyword during programming according to an embodiment of the present disclosure. Table 500 shows the OTP PUF keyword status (502) and cell location (504).

[0027] In 310, the second OTP anti-fuse (i.e., OTP PUF pairing word) is programmed with an OTP PUF keyword programmed as the OTP PUF pairing word. All cells of the OTP PUF pairing word having the same cell positions designated by uncertain bits on the OTP PUF keyword are programmed.

[0028] FIG. 6 illustrates the reading of an OTP PUF pairing word during programming according to an embodiment of the present disclosure. Table 600 shows the OTP PUF pairing word (602) and cell location (604). Cells having cell locations identical to the uncertain bits of the OTP PUF keyword are programmed, as indicated by "P" in FIG. 6. All other cells are not programmed, as indicated by "U" in FIG. 6. As illustrated in FIG. 2, the programmed cells and unprogrammed cells on the OTP PUF pairing word are I cell_1 Each cell current having a lower third current level can be distinguished and read by comparing them. In one embodiment, the third current level is I cell_0 am.

[0029] During the application, the reading of the PUF key is performed as described below. The PUF key contains two programmed OTP words, one of which is an OTP PUF keyword and the other is an OTP PUF pairing word.

[0030] FIG. 7 illustrates a flowchart of a process (700) for reading a PUF key according to an embodiment of the present disclosure.

[0031] In 702, all cells on the OTP PUF keyword (i.e., the first OTP anti-fuse) are read and the fourth current level (I cell_2 It is compared with the fourth current level (I cell_2 ) may be as shown in FIG. 2, where I cell_2 is 0.65 in this example.

[0032] In 704, all cells on the OTP PUF pairing word (i.e., the second OTP anti-fuse) are read, and a third current level (I) as shown in FIG. 2 cell_0 (Compared to ). FIG. 8 illustrates the reading of an OTP PUF keyword and an OTP PUF pairing word during an application read according to an embodiment of the present disclosure. Table 800 shows the reading for an OTP PUF keyword (802) and the reading for an OTP PUF pairing word (804). For the OTP PUF keyword (802), all cell locations having an OTP PUF keyword state (502) of binary 0 are read as binary 0, cells having an OTP PUF keyword state (502) of binary 1 are read as binary 1, and cells having an OTP PUF keyword state (502) of binary 0 / 1 are read as binary 0 or 1. For the OTP PUF pairing word (804), as expected from FIG. 6, all unprogrammed cells are read as binary 0 and all programmed cells are read as binary 1.

[0033] In 706, uncertain bits on the OTP PUF keyword are masked based on the reading of the OTP PUF pairing word. FIG. 9 illustrates the reading of a PUF key during an application read according to an embodiment of the present disclosure. Table 900 shows the OTP PUF keyword (902) and the cell location (904). Table 900 is derived from Table 800. For example, in the case of cell location cell0, the OTP PUF keyword is read as binary 1 and the corresponding OTP PUF pairing word is read as binary 0 (from Table 800). Thus, the binary 0 for the OTP PUF pairing word indicates that the OTP PUF keyword is not masked in cell location cell0. In the case of cell location cell3, the OTP PUF keyword is read as binary 1 and the corresponding OTP PUF pairing word is read as binary 1. A binary 1 for the OTP PUF pairing word indicates that cell location cell3 is masked as shown in Fig. 9.

[0034] As discussed above, the cell current of programmed OTP anti-fuse cells can vary over the user's lifetime and may differ depending on changes in power supplies and ambient temperature. Reference current (I cell ) may also have variations in die-in processing, power supplies, temperature, aging, etc., as understood by a person skilled in the art. However, I cell_3 and I cell_2 Not only the margin between, but also I cell_1 and I cell_2 Due to the margin between them, the overall stability of this OTP PUF keyword is improved.

[0035] In one embodiment, the PUF key may require a balance of zeros and ones as understood by a person skilled in the art. In one embodiment, the balance can be easily achieved by generating more PUF bits on a single OTP PUF keyword than required, and then masking the unbalanced bits (unwanted cells) using the OTP pairing word associated with the OTP PUF keyword. Unbalanced bits or unwanted cells correspond to memory cells that exceed the balance of zeros and ones. If necessary, multiple OTP PUF keywords and their OTP pairing words may be used to generate a single PUF key. For example, to generate a 256-bit PUF key, all cells on multiple OTP PUF keywords are programmed to obtain at least 128 PUF zeros and at least 128 PUF ones. On these multiple OTP PUF keywords' OTP pairing words, only 256 cells having cell locations identical to any 128 PUF 0s and any 128 PUF 1s are not programmed, while all other cells are programmed. Thus, the programmed cells on the OTP pairing words represent not only the uncertain bits of the OTP PUF keywords but also the unnecessary PUF key bits. Therefore, the number of 0s and 1s of a single PUF key can be generated in a balanced manner.

[0036] In one embodiment, two or more OTP pairing words are assigned to a single OTP PUF keyword to improve the readability of the OTP PUF pairing words. For example, a third OTP anti-fuse may be programmed in step 310. While reading the PUF key, two or more OTP PUF pairing words may be used together to identify uncertain bits of the OTP PUF keyword.

[0037] In one embodiment, the memory cell may have a data storage element configured around an ultrathin dielectric, such as a gate oxide, and is used to store information by applying stress to the ultrathin dielectric to break it down in order to set the leakage current level of the memory cell. The memory cell is read by detecting the current drawn from the cell.

[0038] The OTP anti-fuses described in this specification may be part of a memory integrated circuit comprising a number of other well-known elements such as sense amplifiers, pull-up circuits, word line amplifiers, decoders, voltage amplifiers, etc.

[0039] A memory including an OTP anti-fuse is preferably manufactured using any advanced process for making n-type gate devices, p-type gate devices, or both types of devices.

[0040] FIG. 10 illustrates an exemplary machine of a computer system (1000) on which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines within a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate as a server or client machine with capacity in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0041] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal information terminal (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or not) specifying the actions that the machine is to take. Additionally, although exemplified by a single machine, the term “machine” should be construed to include any set of machines that execute a set (or multiple sets) of instructions individually or jointly to perform any one or more of the methodologies discussed herein.

[0042] An exemplary computer system (1000) includes a processing device (1002), a main memory (1004) (e.g., dynamic random access memory (DRAM), such as read-only memory (ROM), flash memory, synchronous DRAM (SDRAM)), static memory (1006) (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device (1018) that communicate with each other via a bus (1030).

[0043] The processing device (1002) represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device (1002) may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal device (DSP), a network processor, etc. The processing device (1002) may be configured to execute instructions (1026) for performing the operations and steps described herein.

[0044] The computer system (1000) may additionally include a network interface device (1008) for communicating through a network (1020). The computer system (1000) may also include a video display unit (1010) (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device (1012) (e.g., a keyboard), a cursor control device (1014) (e.g., a mouse), a graphics processing unit (1022), a signal generation device (1016) (e.g., a speaker), a graphics processing unit (1022), a video processing unit (1028), and an audio processing unit (1032).

[0045] The data storage device (1018) may include a machine-readable storage medium (1024) (also referred to as a non-transient computer-readable medium) in which software is stored that implements one or more sets of instructions (1026) or any one or more of the methodologies or functions described herein. The instructions (1026) may also reside in the main memory (1004) and / or the processing device (1002) in whole or at least partially while being executed by the computer system (1000), and the main memory (1004) and the processing device (1002) also constitute a machine-readable storage medium.

[0046] In some implementations, the instructions (1026) include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium (1024) is shown as a single medium in exemplary implementations, the term “machine-readable storage medium” should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and associated caches and servers) that store a set of one or more instructions. The term “machine-readable storage medium” is also understood to include any medium capable of enabling a machine and processing device (1002) to perform one or more methodologies of the present disclosure and to store or encode a set of instructions for machine execution. Accordingly, the term “machine-readable storage medium” should be understood to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0047] Parts of the previous detailed descriptions were presented in terms of algorithms and symbolic representations of data bits within computer memory. These algorithmic descriptions and representations are methods used by technicians in the field of data processing technology to most effectively convey the essence of their work to other technicians in the same field. An algorithm can be a series of operations leading to a desired result. Operations are those that require the physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. These signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0048] However, it should be kept in mind that all such terms and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to such quantities. As is evident from this disclosure, unless otherwise specifically stated, throughout the description, certain terms are understood to refer to operations and processes of a computer system or similar electronic computing device that convert and manipulate data represented by physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented by physical quantities within the computer system memories or registers or other such information storage devices.

[0049] The present disclosure also relates to an apparatus for performing the operations of the present specification. The apparatus may include a computer that is specifically configured for intended purposes or is selectively activated or reconfigured by a computer program stored in the computer. Such computer program may be stored on any type of disk, including but not limited to floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0050] The algorithms and displays presented in this specification are not essentially related to any specific computer or other device. Various other systems may be used with programs according to the teachings of this specification, or it may be found convenient to configure a more specialized device to perform the method. Furthermore, this disclosure is not described by reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of the disclosure as described in this specification.

[0051] The present disclosure may be provided as a computer program product or software comprising a machine-readable medium storing instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium comprises any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0052] In the foregoing disclosure, embodiments of the disclosure have been described by reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made without exceeding the scope of the embodiments of the disclosure, as set forth in the claims below. Where the disclosure refers to certain elements in the singular tense, one or more elements may be depicted in the drawings, and similar elements are labeled with similar numbers. Accordingly, the disclosure and the drawings should be considered in an exemplary sense rather than a restrictive sense.

Claims

Claim 1 A method comprising: performing a first read operation on a memory cell of a programmed first OTP (one-time programmable) anti-fuse by one or more computer devices to determine a first state of the memory cell based on a first parameter level; performing a second read operation on a memory cell of the programmed first OTP anti-fuse by one or more computer devices to determine a second state of the memory cell based on a second parameter level; identifying the memory cell of the programmed first OTP anti-fuse as an uncertain bit by one or more computer devices if the first state determined during the first read operation and the second state determined during the second read operation are different; and programming one or more memory cells of a second OTP anti-fuse by one or more computer devices based on the bit position of the identified uncertain bit of the first OTP anti-fuse. A method comprising the step of programming a plurality of memory cells of the second OTP anti-fuse corresponding to unwanted memory cells, wherein the unwanted memory cells correspond to memory cells that exceed the balance between the high-state memory cells and the low-state memory cells of the first OTP anti-fuse based on the number of bits required in a physical replication prevention (PUF) key. Claim 2 A method according to claim 1, wherein the parameter value of the memory cell identified as the uncertain bit is between the first parameter level and the second parameter level. Claim 3 A method according to paragraph 2, wherein the parameter value corresponds to the conductivity of the memory cell, the first parameter level includes a first conductivity level, and the second parameter level includes a second conductivity level. Claim 4 A method according to paragraph 2, wherein the first parameter level includes a first voltage level and the second parameter level includes a second voltage level. Claim 5 A method according to paragraph 2, wherein the first parameter level and the second parameter level are threshold current levels selected based on the normalized memory cell current distribution of the memory cells of the programmed first OTP anti-fuse. Claim 6 A method according to claim 1, wherein the programmed memory cell of the second OTP anti-fuse has the same bit position as the uncertain bit in the first OTP anti-fuse within the second OTP anti-fuse. Claim 7 A method according to claim 1, wherein the number of programmed memory cells of the programmed first OTP anti-fuse is greater than the number of bits required in a physical replication prevention (PUF) key. Claim 8 A method according to claim 1, further comprising the step of programming one or more cells of a third OTP anti-fuse based on the bit position of the identified uncertain bit of the first OTP anti-fuse. Claim 9 A method comprising: performing a first read operation on memory cells of a first OTP (one-time programmable) anti-fuse by one or more computer devices; performing a second read operation on memory cells of a second OTP anti-fuse by one or more computer devices to determine the programming state of memory cells of a second OTP anti-fuse; and masking some of the memory cells of the first OTP anti-fuse by one or more computer devices based on the second read operation, wherein the masked memory cells are based on the programming state of memory cells within the second OTP anti-fuse. Claim 10 In claim 9, the step of performing the first read operation comprises the step of associating a low state with the memory cell of the first OTP anti-fuse when the parameter value is lower than the first parameter level. Claim 11 A method according to claim 10, wherein the parameter value corresponds to the conductivity of the memory cell, and the first parameter level includes the first conductivity level. Claim 12 A method according to claim 11, wherein the first conductivity level is greater than the second conductivity level but lower than the third conductivity level, and the second conductivity level and the third conductivity level are based on the normalized memory cell current distribution of the first OTP anti-fuse. Claim 13 A method according to claim 12, wherein the step of performing the second read operation comprises: associating a high state with the memory cell of the second OTP anti-fuse when the conductivity of the memory cell of the second OTP anti-fuse is greater than the second conductivity level; and identifying the uncertain bits of the first OTP anti-fuse as memory cells having the same location as the memory cells having the high states of the second OTP anti-fuse within the first OTP anti-fuse. Claim 14 A method according to claim 9, further comprising the step of performing a third read operation on the memory cells of the third OTP anti-fuse, wherein the step of masking some of the memory cells of the first OTP anti-fuse is also based on the third read operation. Claim 15 In the system, memory for storing instructions; a first OTP (one-time programmable) anti-fuse; a second OTP anti-fuse; and includes a processor coupled to the memory and configured to execute the instructions, wherein, when executed, the instructions cause the processor to perform operations including: programming a memory cell of the first OTP anti-fuse to provide a programmed first OTP anti-fuse; performing a first read operation on the memory cell of the programmed first OTP anti-fuse to determine a first state of the memory cell based on a first parameter level; performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine a second state of the memory cell based on a second parameter level; identifying the memory cell of the programmed first OTP anti-fuse as an uncertain bit if the first state determined during the first read operation and the second state determined during the second read operation are different; and programming one or more memory cells of the second OTP anti-fuse based on the bit position of the identified uncertain bit of the programmed first OTP anti-fuse, and the processor also includes a plurality of memory cells of the second OTP anti-fuse corresponding to unnecessary memory cells A system configured to perform operations including programming, wherein the unnecessary memory cells correspond to memory cells that exceed the balance between the high-state memory cells and the low-state memory cells of the first OTP anti-fuse. Claim 16 A system according to claim 15, wherein the parameter value of the memory cell identified as the uncertain bit is between the first parameter level and the second parameter level. Claim 17 A system according to claim 15, wherein the programmed memory cell of the second OTP anti-fuse has the same bit position as the uncertain bit in the first OTP anti-fuse within the second OTP anti-fuse. Claim 18 A system according to claim 15, wherein the processor is also configured to perform operations including programming one or more cells of a third OTP anti-fuse based on the bit position of the identified uncertain bit of the first OTP anti-fuse. Claim 19 delete Claim 20 delete

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