Integrated circuit packages and methods of forming the same

Abstract

One embodiment is a device, the device comprising a substrate including a conductive pad, a package component bonded to the conductive pad of the substrate using a solder connector — the package component includes an integrated circuit die, the integrated circuit die includes a die connector, and one of the solder connectors is coupled to each of the die connectors and a corresponding conductive pad of the substrate — a first dielectric layer transversely surrounding each of the die connectors and a portion of the solder connector, and a second dielectric layer between the first dielectric layer and the substrate and transversely surrounding each of the conductive pads of the substrate.

Description

Technology Field

[0001] This application claims priority to U.S. provisional application No. 63 / 483,817 filed February 8, 2023, which is incorporated herein by reference. Background Technology

[0002] The semiconductor industry is experiencing rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integration density have resulted from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturization of electronic devices increases, the need for smaller and more creative packaging technologies for semiconductor dies has emerged. Brief explanation of the drawing

[0003] The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not depicted to scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. Figure 1 is a cross-sectional view of an integrated circuit die. FIGS. 2 to 20 are drawings of intermediate stages during the manufacture of an integrated circuit package according to some embodiments. FIGS. 21 to 23 are drawings of intermediate stages during the manufacture of an integrated circuit package according to some embodiments. FIGS. 24 and 25 are drawings of intermediate stages during the manufacture of an integrated circuit package according to some embodiments. Specific details for implementing the invention

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the present invention. To simplify the content of the disclosure, specific exemplary components and arrangements are described below. These are, of course, merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0005] Additionally, spatial terms such as “immediately below,” “below,” “lower,” “above,” and “upper” may be used herein for convenience of description to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings. These spatial terms are intended to include various orientations of the device in use or operation, in addition to the orientations illustrated in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other directions), and accordingly, the spatial descriptors used herein may be interpreted in the same manner.

[0006] According to various embodiments, an integrated circuit die (sometimes referred to as a chip) is bonded to a wafer in a chip-to-wafer structure. In some embodiments, the chip is bonded to another chip in a chip-to-chip structure (sometimes referred to as a chip stack structure). In some embodiments, the chip is attached to the wafer using microbumps (e.g., conductive posts with solder). In some embodiments, the pitch of the microbumps is less than 10 μm. In the present disclosure, the microbumps may be formed within a multilayer structure comprising a first layer and a second layer. Solder planarization is performed on the first layer existing before the second layer is formed to improve solder coplanarity. Additionally, the second layer may have lower fluidity than the solder at high temperatures to prevent solder collapse and bridging. By improving solder coplanarity after bump reflow and preventing solder collapse and bridging, the yield and reliability of the package are improved.

[0007] FIG. 1 illustrates a cross-sectional view of an integrated circuit die (50) according to some embodiments. The integrated circuit die (50) will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die (50) may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), etc., or a combination thereof.

[0008] An integrated circuit die (50) may be formed within a wafer, which may include different device regions that are singulated in a subsequent step to form a plurality of integrated circuit dies. The integrated circuit die (50) may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die (50) may include a semiconductor substrate (52), such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate (52) may include other semiconductor materials, for example, germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate (52) has an active surface (e.g., the surface facing upward in FIG. 1), which is sometimes referred to as the front side, and an inactive surface (e.g., the surface facing downward in FIG. 1), which is sometimes referred to as the back side.

[0009] A device (54) (indicated as a transistor) may be formed on the front surface of a semiconductor substrate (52). The device (54) may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. An interlayer dielectric (ILD) (56) is on the front surface of the semiconductor substrate (52). The ILD (56) may surround and cover the device (54). The ILD (56) may include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0010] A conductive plug (58) extends through the ILD (56) to electrically and physically connect with the device (54). For example, if the device (54) is a transistor, the conductive plug (58) may be connected to the gate and source / drain regions of the transistor. Source / drain(s) may refer to the source or drain individually or collectively depending on the context. The conductive plug (58) may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. An interconnect structure (60) is positioned over the ILD (56) and the conductive plug (58). The interconnect structure (60) interconnects the devices (54) to form an integrated circuit. The interconnect structure (60) may be formed, for example, by a metallization pattern within a dielectric layer on the ILD (56). The metallization pattern includes metal lines and vias formed within one or more low-k dielectric layers. The metallization pattern of the interconnect structure (60) is electrically connected to the device (54) by a conductive plug (58).

[0011] The integrated circuit die (50) further comprises a pad (62) to which an external connection is made, for example, an aluminum pad. The pad (62) is located on the active side (sometimes referred to as the front side (50F)) of the integrated circuit die (50), such as inside and / or on top of the interconnection structure (60). One or more passivation films (64) are located on the integrated circuit die (50), for example, on a portion of the interconnection structure (60) and the pad (62). An opening extends through the passivation film (64) to the pad (62). A die connector (66), such as a conductive pillar (formed, for example, of a metal such as copper), extends through the opening in the passivation film (64) and is physically and electrically connected to each of the pads (62). The die connector (66) may be formed, for example, by plating, etc. The die connector (66) electrically connects each integrated circuit of the integrated circuit die (50).

[0012] In some embodiments, the integrated circuit die (50) is a stacked device comprising a plurality of semiconductor substrates (52). For example, the integrated circuit die (50) may be a memory device comprising a plurality of memory dies, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, etc. In these embodiments, the integrated circuit die (50) comprises a plurality of semiconductor substrates (52) interconnected by through-substrate vias (TSVs). Each semiconductor substrate (52) may have an interconnection structure (60) (or may not).

[0013] In FIG. 2, a solder region (68) (e.g., a solder layer or a solder bump) is formed on a die connector (66). The solder region (68) may be formed from a reflowable conductive material, e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the solder region (68) is formed by initially forming a solder layer on the die connector (66) through methods such as evaporation, electroplating, printing, solder transfer, or ball placement. The solder region (68) is used to electrically connect the integrated circuit die (50) to another structure. The die connector (66) and the solder region (68) may be referred to as microbumps. The solder region (68) may also be used to perform chip probe (CP) testing on the integrated circuit die (50). CP testing can be performed on the integrated circuit die (50) to determine whether the integrated circuit die (50) is a known good die (KGD). Therefore, only the integrated circuit die (50) that is a KGD is subsequently processed and packaged, and dies that fail CP testing are not packaged. After testing, the solder area can be removed in the subsequent processing step.

[0014] In FIG. 3, a dielectric layer (70) is formed on the active side of an integrated circuit die (50) and, for example, on a passivation film (64), a die connector (66), and a solder area (68). The dielectric layer (70) encapsulates the die connector (66) and the solder area (68), and the dielectric layer (70) is coterminous with the integrated circuit die (50). In some embodiments, the dielectric layer (70) encapsulates the die connector (66) and the solder area (68) such that the uppermost surface of the dielectric layer (70) is on the uppermost surface of the solder area (68).

[0015] The dielectric layer (70) may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), molding compound, etc. The dielectric layer (70) may comprise a base material such as a polymer and filler particles within the polymer. The filler particles may include dielectric particles such as silicon oxide, aluminum oxide, silica, etc., and may have a spherical shape. Additionally, the spherical filler particles may have the same or different diameters. In some embodiments, the diameter of the filler particles is less than 1 μm. The dielectric layer (70) may be formed, for example, by spin coating, lamination, liquid molding, chemical vapor deposition (CVD), etc. In some embodiments, the dielectric layer (70) may be cured after being applied in a liquid or semi-liquid form.

[0016] In FIG. 4, the dielectric layer (70) is flattened to expose the solder region (68). The flattening process may be a grinding process, chemical mechanical polishing (CMP), etch-back, or a combination thereof. After the flattening process, the solder region (68) and the top surface of the dielectric layer (70) are coplanar (within process variation) so that they are at the same height as each other. Flattening is performed until a desired amount of the solder region (68) and / or dielectric layer (70) is removed. In an embodiment where the solder region (68) is not embedded within the dielectric layer (70), the flattening process may be omitted.

[0017] In FIG. 5, the solder region (68) is formed into a solder bump (68). In some embodiments, a reflow process may be performed to form the solder region (68) into a desired bump shape.

[0018] In FIG. 6, a coating (72) is formed on the active side of an integrated circuit die (50), for example, on a dielectric layer (70) and a solder area (68). The coating (72) covers and re-embeds the solder area (68) and may have a lateral boundary with the integrated circuit die (50). In some embodiments, the dielectric layer (70) embeds the solder area (68) and the dielectric layer (70) such that the top surface of the coating (72) is over the top surface of the solder area (68) and the dielectric layer (70). In some embodiments, the coating (72) may be an adhesive, flux, a non-conductive film, or a combination thereof. In some embodiments, the coating (72) may be thinner than the dielectric layer (70). In some embodiments, the coating (72) may have a thickness in the range of about 3 μm to about 10 μm.

[0019] The coating (72) may include a base material and filler particles within the base material. The filler particles may include dielectric particles such as silicon oxide, aluminum oxide, and silica, and may have a spherical shape. Additionally, the spherical filler particles may have the same or different diameters. In some embodiments, the diameter of the filler particles is less than 1 μm. In some embodiments, the Young's modulus of the coating (72) is smaller than the Young's modulus of the dielectric layer (70). In some embodiments, the Young's modulus of the coating (72) and the dielectric layer (70) respectively is greater than the Young's modulus of a typical underfill material. Additionally, in some embodiments, the coefficient of thermal expansion of the coating (72) and the dielectric layer (70) respectively is smaller than the coefficient of thermal expansion of a typical underfill material. The fluidity of the coating (72) and the dielectric layer (70) respectively may also be slower than the fluidity of solder during high-temperature conditions such as reflow and bonding processes.

[0020] FIGS. 7 through 20 are drawings of intermediate stages during the manufacture of an integrated circuit package (200) according to some embodiments. FIGS. 7 through 19 are cross-sectional and plan views of a process for forming a package component (210) including an interposer such as a package component for a chip-on-wafer-on-substrate (CoWoS®) device (200). The package component (210) may be a chip-on-wafer (CoW) package component.

[0021] FIGS. 7 through 20 describe a chip-on-wafer-on-substrate device or a chip-on-wafer device, but the wafer in these configurations may be replaced with a chip or die for a chip-on-chip device. In these embodiments, the chip or die may be formed in a manner similar to an integrated circuit die (50). Accordingly, the present disclosure is not limited to wafer-type structures but also includes embodiments having a chip-on-chip structure.

[0022] An integrated circuit package (200) (see FIG. 19) will be formed by initially packaging an integrated circuit die (50) to form a package component (210) within a wafer (100). One package area (100A) of the wafer (100) is illustrated, and the integrated circuit die (50) is packaged to form a package component (210) within each package area (100A) of the wafer (100). It should be recognized that any number of package areas may be processed simultaneously to form any number of package components. The package areas (100A) of the wafer (100) will be individualized to form the package component (210). The package component (210) will be attached to a package substrate (220) (e.g., see FIG. 20).

[0023] In FIG. 7, a wafer (110) is obtained or formed. The wafer (110) contains devices in a package area (100A), and these devices will be individualized in a subsequent process to be included in a package component (210). The devices within the wafer (110) may be an interposer, an integrated circuit die, etc. In some embodiments, an interposer (102) comprising a substrate (112), an interconnect structure (114), and a conductive via (120) is formed within the wafer (110). As discussed above, in some embodiments, the wafer (110) is a chip or a die (110).

[0024] The substrate (112) may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, etc. The substrate (112) may include semiconductor materials, for example, silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate (112) may be doped or may not be doped. In an embodiment where the interposer is formed within the wafer (110), the substrate (112) generally does not contain an active device, but the interposer may include a passive device formed within and / or on the front surface of the substrate (112) (e.g., the upward-facing surface in FIG. 7). In an embodiment where an integrated circuit device is formed within the wafer (110), active devices such as transistors, capacitors, resistors, diodes, etc., may be formed within and / or on the front surface of the substrate (112).

[0025] An interconnect structure (114) is positioned on the front surface of a substrate (112) and is used to electrically connect devices (if present) on the substrate (112). The interconnect structure (114) may comprise one or more dielectric layer(s) and respective metallization layer(s) within the dielectric layer(s). Dielectric materials permitted for the dielectric layer include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc.; or combinations thereof, for example, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, silicon oxycarbide nitride, etc. Other dielectric materials, for example, polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc., may also be used. The metallization layer(s) may comprise conductive vias and / or conductive lines for interconnecting any devices together and / or interconnecting to an external device. The metallization layer(s) can be formed from a conductive material such as a metal, e.g., copper, cobalt, aluminum, gold, or a combination thereof. The interconnect structure (114) can be formed by a damascene process such as a single damascene process, a double damascene process, etc.

[0026] In some embodiments, the die connector (116) and the dielectric layer (118) are on the front side of the wafer (110). Specifically, the wafer (110) may include a die connector (116) (sometimes referred to as a conductive pad (116)) and a dielectric layer (118) similar to those of the integrated circuit die (50) described for FIG. 1. For example, the die connector (116) and the dielectric layer (118) may be part of the upper metallization layer of the interconnect structure (114).

[0027] A conductive via (120) extends into an interconnect structure (114) and / or a substrate (112). The conductive via (120) is electrically connected to a metallized layer(s) of the interconnect structure (114). The conductive via (120) is sometimes referred to as a through-substrate via (TSV). As an example for forming the conductive via (120), a recess may be formed within the interconnect structure (114) and / or the substrate (112) by, for example, etching, milling, laser technology, a combination thereof, etc. A thin dielectric material may be formed within the recess using oxidation technology, etc. A thin barrier layer may be conformally deposited within the opening by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, etc. The barrier layer may be formed of an oxide, a nitride, a carbide, a combination thereof, etc. A conductive material may be deposited on the barrier layer and within the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, or a combination thereof. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, and combinations thereof. Excess conductive material and barrier layers are removed from the surface of the interconnect structure (114) or substrate (112), for example, by CMP. The remaining portions of the barrier layer and conductive material form conductive vias (120).

[0028] In FIG. 8, an integrated circuit die (50) (e.g., a first integrated circuit die (50A) and a plurality of second integrated circuit dies (50B)) is attached to a wafer (110). In the illustrated embodiment, a plurality of integrated circuit dies (50), including a first integrated circuit die (50A) and a second integrated circuit die (50B), are arranged adjacent to each other, wherein the first integrated circuit die (50A) is located between the second integrated circuit dies (50B). In some embodiments, the first integrated circuit die (50A) is a logic device such as a CPU, GPU, etc., and the second integrated circuit die (50B) is a memory device such as a DRAM die, HMC module, HBM module, etc. In some embodiments, the first integrated circuit die (50A) is a device of the same type as the second integrated circuit die (50B) (e.g., SoC).

[0029] In the illustrated embodiment, the integrated circuit die (50) is attached to the wafer (110) by a solder bond (e.g., from the solder region (68)) to form a conductive connector (132). The integrated circuit die (50) may be placed on the interconnect structure (114) using, for example, a pick and place tool. The conductive connector (132) may be formed from the conductive material of the solder region (68) of the integrated circuit die (50) (e.g., see FIG. 6). Attaching the integrated circuit die (50) to the wafer (110) may include placing the integrated circuit die (50) on the wafer (110) and performing a thermal compression bonding process to form the conductive connector (132). For example, the integrated circuit die (50) is placed on the wafer (100) and then, for example, is compressed into the wafer (110) as part of a thermal compression bonding process. The coating (72) covers the solder area (68) at the start of the thermal compression bonding process, but after this process, the solder area (68) comes into physical contact with the connector (116) and extends through the coating (72). The conductive connector (132) forms a joint between the corresponding die connector (116) of the wafer (110) and the die connector (66) of the integrated circuit die (50), thereby electrically connecting the interposer (102) to the integrated circuit die (50).

[0030] After the bonding process, the coating (72) and the dielectric layer (70) surround the conductive connector (132). The coating (72) fills the area between the integrated circuit die (50) and the wafer (110). In some embodiments, the coating (72) extends to the sidewall of the integrated circuit die (50) and protrudes outward from the area between the integrated circuit die (50) and the wafer (110). In some embodiments, the coating (72) has a curved sidewall (72S) that protrudes outward from the side of the integrated circuit die (50). In some embodiments, the curved sidewall (72S) has a convex shape.

[0031] FIGS. 9a and 9b illustrate a detailed view of the bonding process of a single conductive connector (132). In FIG. 9a, the die connector (66) and solder area (68) of the integrated circuit die (50) are aligned with the connector (116) of the wafer (110). In FIG. 9b, the die connector (66) and solder area (68) of the integrated circuit die (50) are placed on the connector (116) of the wafer (110). During placement, the coating (72) comes into physical contact with the connector (116) and dielectric layer (118) of the wafer (110). In an embodiment having a thermal compression bonding process, the integrated circuit die (50) is compressed into the wafer (110) so that the solder area (68) of the integrated circuit die (50) comes into physical contact with the connector (116) of the wafer (110) to form a conductive connector (132). In some embodiments, the solder area (68) is in physical contact with the connector (116) before crimping, and in other embodiments, the solder area (68) comes into contact with the connector (116) due to crimping. In some embodiments, after the bonding process, the coating (72) separates the dielectric layers (70 and 118).

[0032] FIGS. 10a and 10b illustrate intermediate processing steps similar to FIGS. 9a and 9b, but excluded in this embodiment is that the wafer (110) does not contain a dielectric (118) (or the connector (116) may extend over the dielectric layer (118) so that the coating (72) does not physically contact the dielectric layer (118). In this embodiment, the coating (72) surrounds the connector (116), and in some embodiments, surrounds a portion of the conductive connector (132). Other details of FIGS. 10a and 10b may be similar to those described above in FIGS. 9a and 9b and are therefore not repeated here.

[0033] Various configurations of the dielectric layer (70), coating (72), die connector (66), conductive connector (132), connector (116), and dielectric layer (118) are within the scope of the present disclosure. Some of these configurations are described below with reference to FIGS. 11 through 16.

[0034] FIG. 11 illustrates a detailed view of a single conductive connector (132) according to some embodiments. In FIG. 11, the top surface (72A) of the coating (72) extends over the top surface (116A) of the connector (116). In some embodiments, the conductive connector (132) has a protrusion (132A) that extends into the coating (72). The protrusion (132A) of the conductive connector (132) may cover a portion of the side wall of the connector (116).

[0035] FIG. 12 illustrates a detailed view of a single conductive connector (132) according to some embodiments. In FIG. 12, the top surface (72A) of the coating (72) is substantially coplanar with the top surface (116A) of the connector (116). In some embodiments, the conductive connector (132) has a substantially vertical sidewall defined by a dielectric layer (70). In some embodiments, the sidewall of the conductive connector (132) is completely covered by the dielectric layer (70).

[0036] FIG. 13a illustrates a detailed view of a single conductive connector (132) according to some embodiments. FIG. 13b, FIG. 13c, and FIG. 13d illustrate detailed views of a portion of FIG. 13a. In FIG. 13a through FIG. 13d, the top surface (72A) of the coating (72) is below the top surface (116A) of the connector (116) so that the connector (116) is inserted into the dielectric layer (70).

[0037] In FIG. 13b, the sidewalls of the conductive connector (132) are completely covered by the dielectric layer (70). In this embodiment, the conductive connector (132) may also have substantially vertical sidewalls defined by the dielectric layer (70).

[0038] In FIG. 13c, the coating (72) is in physical contact with the sidewall of the conductive connector (132) and is in physical contact with and covers the inner sidewall of the dielectric layer (70) (the sidewall facing the conductive connector (132)). In some embodiments, the coating (72) covers a portion of the sidewall of the conductive connector (132).

[0039] In FIG. 13c and FIG. 13d, the conductive connector (132) extends into the coating (72) and covers part of the sidewall of the connector (116).

[0040] Although FIGS. 13a to 13d are illustrated as different embodiments, the present disclosure encompasses embodiments that combine the features of FIGS. 13a to 13d in various configurations.

[0041] FIG. 14 illustrates a detailed view of a single conductive connector (132) according to some embodiment. FIG. 14 illustrates the top surface (72A) of a coating (72) on the top surface (116A) of the connector (116). The embodiment of FIG. 14 is similar to the embodiment of FIG. 11 having the embodiment of FIG. 14 that does not include a dielectric layer (118) (e.g., see FIG. 10a and FIG. 10b). FIG. 11 has been described above, and similar features of FIG. 14 are not repeated here. In this embodiment, the coating (72) can completely cover the sidewall of the connector (116) as the dielectric layer (118) is omitted.

[0042] FIG. 15 illustrates a detailed view of a single conductive connector (132) according to some embodiments. FIG. 14 illustrates the top surface (116A) of the connector (116) and the top surface (72A) of the coating (72) that is substantially in the same plane. The embodiment of FIG. 15 is similar to the embodiment of FIG. 12 having the embodiment of FIG. 14 that does not include a dielectric layer (118) (e.g., see FIG. 10a and FIG. 10b). FIG. 12 has been described above, and similar features of FIG. 15 are not repeated here. In this embodiment, the coating (72) can completely cover the sidewall of the connector (116) as the dielectric layer (118) is omitted.

[0043] FIG. 16 illustrates a detailed view of a single conductive connector (132) according to some embodiments. FIG. 16 illustrates the top surface (72A) of a coating (72) on the top surface (116A) of the connector (116). The embodiment of FIG. 16 is similar to the embodiments of FIG. 13a through 13d having the embodiment of FIG. 16 that does not include a dielectric layer (118) (e.g., see FIG. 10a and FIG. 10b). FIG. 13a through 13d have been described above, and similar features of FIG. 16 are not repeated here. In this embodiment, the coating (72) can completely cover the sidewall of the connector (116) as the dielectric layer (118) is omitted.

[0044] In FIG. 17, an encapsulant (136) is formed on and around an integrated circuit die (50). After formation, the encapsulant (136) encapsulates the integrated circuit die (50), the dielectric layer (70), and the coating (72). The encapsulant (136) may be a molding compound, epoxy, etc. The encapsulant (136) may be applied by compression molding, transfer molding, etc., and formed on a wafer (110) so that the integrated circuit die (50) is embedded or covered. The encapsulant (136) may be applied in a liquid or semi-liquid form and then cured. The encapsulant (136) may be thinned to expose the integrated circuit die (50). The thinning process may be a grinding process, chemical mechanical polishing (CMP), etch-back, or a combination thereof. After the thinning process, the top surfaces of the integrated circuit die (50) and the encapsulant (136) are on the same plane (within process variation) so that they are at the same height as each other. Thinning is performed until a desired amount of the integrated circuit die (50) and / or encapsulant (136) is removed.

[0045] As illustrated in FIG. 17, the encapsulating material (136) separates the coatings (72) of adjacent integrated circuit dies (50) from each other. In some embodiments, the coatings (72) of adjacent integrated circuit dies (50) may be merged together between adjacent integrated circuit dies (50) so that the encapsulating material (136) does not separate them (e.g., see FIG. 21 to FIG. 23). In these embodiments, the encapsulating material (136) may have a curved interface with the merged coatings (72) between adjacent integrated circuit dies (50). In some embodiments, the curved interface may include a coating (72) having a convex upward interface (e.g., see FIG. 21 or FIG. 23) or a concave upward interface (e.g., see FIG. 22).

[0046] In FIG. 18, the substrate (112) is thinned to expose a conductive via (130). The exposure of the conductive via (130) can be achieved by a thinning process which may be a grinding process, chemical mechanical polishing (CMP), etch-back, or a combination thereof. In some embodiments (not separately illustrated), the thinning process for exposing the conductive via (130) includes CMP, and the conductive via (130) protrudes from the back side of the wafer (110) as a result of dishing occurring during CMP. In these embodiments, an insulating layer (not separately illustrated) may be optionally formed on the back surface of the substrate (112) to surround the protruding portion of the conductive via (130). The insulating layer can be formed from silicon-containing insulators such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by a suitable deposition method such as spin coating, CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD). After the substrate (112) is thinned, the conductive vias (130) and the insulating layer (if present) or the exposed surfaces of the substrate (112) are on the same plane (within process variation) so as to be at the same height from each other and are exposed on the back side of the wafer (110).

[0047] In FIG. 19, the UBM (146) is formed on the exposed surface of the conductive via (130) and the substrate (112). As an example for forming the UBM (146) in this embodiment, a seed layer (not separately shown) is formed on the exposed surface of the conductive via (130) and the substrate (112). In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer on top of the titanium layer. The seed layer may be formed, for example, using PVD, etc. Then, a photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc. and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM (146). The patterning forms an opening that penetrates the photoresist to expose the seed layer. Afterward, a conductive material is formed within the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, for example, by electroplating or electroless plating. The conductive material may include a metal, for example, copper, titanium, tungsten, aluminum, etc. Afterward, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, for example, using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, using an acceptable etching process. The remaining portion of the seed layer and the conductive material forms the UBM (146).

[0048] Additionally, a conductive connector (148) is formed on the UBM (146). The conductive connector (148) may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connector (148) may include a conductive material, for example, solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector (148) is formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be performed to form the material into a desired bump shape. In other embodiments, the conductive connector (148) includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solder-free and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillar. The metal cap layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0049] Additionally, the singulation process is performed, for example, by sawing along the scribe line area around the package area (100A). The singulation process may include sawing, dicing, etc. For example, the singulation process may include sawing the encapsulant (136), the interconnect structure (114), and the substrate (112). The singulation process singulates the package area (100A) from the adjacent package area. Consequently, the singulated package component (210) is derived from the package area (100A). The singulation process forms an interposer (102) from the singulated portion of the wafer (110). As a result of the singulation process, the outer sidewalls of the interposer (102) and the encapsulant (136) share a lateral boundary (within process variation).

[0050] In some embodiments, the package component (210) may be attached to the package substrate. In FIG. 20, the package component (210) is attached to the package substrate (220) using a conductive connector (148). The package substrate (220) includes a substrate core (222) that may be formed from a semiconductor material, for example, silicon, germanium, diamond, etc. Alternatively, compound materials, for example, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. may also be used. Additionally, the substrate core (222) may be an SOI substrate. Generally, the SOI substrate comprises a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In other embodiments, the substrate core (222) is an insulating core, such as a glass fiber reinforced resin core. One example of a core material is a glass fiber resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively include other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminates may be used for the substrate core (222).

[0051] The substrate core (222) may include active and / or passive devices (not separately shown). Devices such as transistors, capacitors, resistors, combinations thereof, etc., may be used to create structural and functional requirements for the design of the system. The devices may be formed using any suitable method.

[0052] The substrate core (222) may also include a metallization layer and vias, and bond pads (224) on the metallization layer and vias. The metallization layer may be formed on active and passive devices and is designed to connect various devices to form a functional circuit. The metallization layer may be formed as alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) together with vias interconnecting layers of conductive material, and may be formed through any suitable process (e.g., deposition, damascene, etc.). In some embodiments, active and passive devices are substantially absent from the substrate core (222).

[0053] The conductive connector (148) is reflowed to attach the UBM (146) to the bond pad (224). The conductive connector (148) connects the package component (210), which includes the metallization layer (144) of the redistribution structure (140), to the package substrate (220), which includes the metallization layer of the substrate core (222). Thus, the package substrate (220) is electrically connected to the integrated circuit die (50). In some embodiments, a passive device (e.g., a surface-mount device (SMD), not separately shown) may also be attached to the package component (210) before being mounted on the package substrate (220) (e.g., bonded to the UBM (146)). In such embodiments, the passive device may be bonded to the surface of the package component (210) that is the same as the conductive connector (148). In some embodiments, a passive device (226) (e.g., SMD) may be attached to a package substrate (220), e.g., a bond pad (224).

[0054] In some embodiments, an underfill (228) surrounding a conductive connector (148) is formed between the package component (210) and the package substrate (220). The underfill (228) may be formed by a capillary flow process after the package component (210) is attached, or by any suitable deposition method before the package component (210) is attached. The underfill (228) may be a continuous material extending from the package substrate (220) to the substrate (112).

[0055] Although not illustrated, the package substrate (220) may have a conductive connector formed on a bond pad on the opposite side of the package substrate (220) from the package component (210) (the bottom side in FIG. 20). Additionally, although not illustrated, the package substrate (220) may have a cover / heat dissipation structure attached to the package component (210) and / or the package substrate (220).

[0056] FIGS. 21, FIGS. 22, and FIGS. 23 illustrate various configurations of the coating (72) and the encapsulating material (136). In FIG. 21, the coating (72) of adjacent integrated circuit dies (50) is merged together between adjacent integrated circuit dies (50) so that the encapsulating material (136) does not separate the coating (72). Merging may occur due to a thicker coating (72) applied over the dielectric layer (70) and the solder area (68).

[0057] In FIG. 21, the interface between the merged coatings (72) is a curved interface, and the merged coatings (72) have an upwardly convex interface. In FIG. 22, the interface between the merged coatings (72) is a curved interface, and the merged coatings (72) have a concave upward interface. The concave upward interface of the coatings (72) may be caused by the difference in Young's modulus between the coatings (72) and the encapsulant (136) and / or by pressure applied during the encapsulant process. For example, if the coating (72) has a lower Young's modulus than the encapsulant (136), the coatings (72) may have a concave upward interface with the encapsulant (136).

[0058] In FIG. 23, the coating (72) is within the scribe line area of ​​the package area (100A). In this embodiment, the individualization process may include sawing the encapsulant (136), the coating (72), the interconnect structure (114), and the substrate (112). This embodiment is illustrated with a combined coating (72) having a convex upward interface, but this embodiment is not limited thereto, and, for example, the combined coating (72) may have a concave upward interface.

[0059] FIGS. 24 and 25 are drawings of intermediate stages during the manufacture of an integrated circuit package according to some embodiments. Specifically, this embodiment includes an integrated circuit die (50) bonded to a rewiring structure (400). Details of this embodiment, which is similar to the previously described embodiment, are not repeated herein.

[0060] Referring to FIG. 24, a redistribution structure (400) can be formed on an emission layer (304) on a carrier substrate (302). The carrier substrate (302) may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate (302) may be a wafer, so that a plurality of packages can be formed simultaneously on the carrier substrate (302).

[0061] The emission layer (304) may be formed from a polymer-based material and may be removed along with the carrier substrate (302) from the upper structure to be formed in a subsequent step. In some embodiments, the emission layer (304) is an epoxy-based heat-emitting material that loses adhesive properties upon heating, e.g., a light-to-heat-conversion (LTHC) emission coating. In other embodiments, the emission layer (304) may be a UV glue that loses adhesive properties upon exposure to ultraviolet (UV) light. The emission layer (304) may be sprayed as a liquid and cured, or may be a laminate film laminated on the carrier substrate (302). The top surface of the emission layer (304) may be flat and may have a high degree of planarity.

[0062] Additionally, in FIG. 24, a redistribution structure (400) is formed on the emission layer (304) and the carrier substrate (302). The redistribution structure (400) includes dielectric layers (402, 406, and 408); and metallization patterns (404 and 410). The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure (400) is illustrated as an example having three layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed within the redistribution structure (400). If fewer dielectric layers and metallization patterns are formed, the steps and processes described below may be omitted. If more dielectric layers and metallization patterns are formed, the steps and processes described below may be repeated.

[0063] A dielectric layer (402) is deposited on the emission layer (304). In some embodiments, the dielectric layer (402) is formed from a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a lithography mask. The dielectric layer (402) can be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0064] Next, a metallization pattern (404) is formed. The metallization pattern (404) includes a conductive element extending along the main surface of the dielectric layer (402). As an example for forming the metallization pattern (404), a seed layer is formed on the dielectric layer (402). In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer on top of the titanium layer. The seed layer may be formed, for example, using PVD, etc. Then, a photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc. and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern (404). The patterning forms an opening penetrating the photoresist to expose the seed layer. Subsequently, a conductive material is formed within the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, for example, by electroplating or electroless plating, etc. The conductive material may include a metal, for example, copper, titanium, tungsten, or aluminum, etc. The combination of the conductive material and the portion of the underlying seed layer forms a metallized pattern (404). The portion of the seed layer where the conductive material is not formed and the photoresist are removed. The photoresist may be removed by an acceptable ashing or stripping process, for example, using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed by an acceptable etching process, for example, by wet or dry etching.

[0065] A dielectric layer (406) is deposited on the metallization pattern (404) and the dielectric layer (402). The dielectric layer (406) may be formed in a manner similar to the dielectric layer (402) and may be formed from a material similar to the dielectric layer (402). Subsequently, the dielectric layer (406) is patterned. The patterning forms an opening that exposes a portion of the dielectric layer (402). The patterning may be formed by an acceptable process, for example, by developing the dielectric layer (406) by exposing it to light when the dielectric layer (406) is a photosensitive material, or for example, by etching using anisotropic etching.

[0066] Next, a metallization pattern (410) is formed. The metallization pattern (410) includes a portion that extends along the main surface of the dielectric layer (406) on the main surface of the dielectric layer (406). The metallization pattern (410) further includes a portion that extends through the dielectric layer (406) to be physically and electrically connected to the metallization pattern (404). The metallization pattern (410) may be formed in a manner similar to that of the metallization pattern (404) and with a similar material. In some embodiments, the metallization pattern (410) has a different size from the metallization pattern (404). For example, the conductive lines and / or vias of the metallization pattern (410) may be wider or thicker than the conductive lines and / or vias of the metallization pattern (404). Additionally, the metallization pattern (410) may be formed with a larger pitch than the metallization pattern (404).

[0067] The dielectric layer (408) is deposited on the metallization pattern (410) and the dielectric layer (406). The dielectric layer (408) can be formed in a manner similar to the dielectric layer (402) and can be formed from the same material as the dielectric layer (402). The dielectric layer (408) is the uppermost dielectric layer of the redistribution structure (400).

[0068] Next, a metallization pattern (412) is formed. The metallization pattern (412) (sometimes referred to as underbump metallization (UBM)) includes a portion extending along the main surface of the dielectric layer (408) on the main surface of the dielectric layer (408). The metallization pattern (412) further includes a portion extending through the dielectric layer (408) to be physically and electrically connected to the metallization pattern (410). The metallization pattern (412) may be formed in a manner similar to and with a similar material to the metallization patterns (404 and 410). The metallization pattern (412) is the uppermost metallization pattern of the redistribution structure (400). In some embodiments, the metallization pattern (412) has a different size from the metallization patterns (410 and 404). For example, the conductive lines and / or vias of the metallization pattern (412) may be wider or thicker than the conductive lines and / or vias of the metallization patterns (410 and 404). Additionally, the metallization pattern (412) may be formed with a larger pitch than the metallization pattern (410). In some embodiments, the metallization pattern (412) may provide UBM for the redistribution structure (400).

[0069] In FIG. 25, the integrated circuit die (50) is attached to the redistribution structure (400) with a solder bond, such as a conductive connector. The integrated circuit die (50) has been described above and is not repeated here. The integrated circuit die (50) can be placed on the redistribution structure (400), for example, using a pick-and-place tool, and bonded in a manner similar to that described above (see FIG. 8 through 16). Similar to the previous embodiment, the encapsulant (420) can be formed around the integrated circuit die, the dielectric layer (70), and the coating (72) and on the redistribution structure (400). Similar to the previous embodiment, the package regions (100A and 100B) can be individualized into the package structure (300). As a result of the individualization process, the outer sidewalls of the redistribution structure (600) and the encapsulant (420) are laterally bound together (within process variation).

[0070] Although not illustrated, the carrier substrate (302) may be debonded to separate (or "debonded") the carrier substrate (302) from the rewiring structure (400), e.g., the dielectric layer (402). According to some embodiments, debonding involves projecting light, such as laser light or UV light, onto the emission layer (304) so ​​that the emission layer (304) decomposes under the heat of the light and the carrier substrate (302) can be removed. After the debonding process, the conductive connector and UBM may be formed to extend through the dielectric layer (402) to contact the metallization pattern (404).

[0071] Other features and processes may also be included. For example, a testing structure to support verification testing of a 3D package or 3DIC device may be included. The testing structure may include, for example, test pads formed within a rewiring layer or on a substrate, enabling testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with a testing method that includes intermediate verification of known good dies to increase yield and reduce costs.

[0072] The embodiments can achieve advantages. In some embodiments, an integrated circuit die (sometimes referred to as a chip) is bonded to a wafer in a chip-to-wafer structure. In some embodiments, the chip is attached to the wafer using microbumps (e.g., conductive posts with solder). In some embodiments, the pitch of the microbumps is less than 10 μm. In the present disclosure, the microbumps may be formed within a multilayer structure comprising a first layer and a second layer. Solder planarization is performed on the first layer existing before the second layer is formed to improve solder coplanarity. Additionally, the second layer may have lower fluidity than the solder at high temperatures to prevent solder collapse and bridging. By improving solder coplanarity after bump reflow and preventing solder collapse and bridging, the yield and reliability of the package are improved.

[0073] One embodiment is a device, the device comprising a substrate including a conductive pad, a package component bonded to the conductive pad of the substrate using a solder connector — the package component includes an integrated circuit die, the integrated circuit die includes a die connector, and one of the solder connectors is coupled to each of the die connectors and a corresponding conductive pad of the substrate — a first dielectric layer transversely surrounding each of the die connectors and a portion of the solder connector, and a second dielectric layer between the first dielectric layer and the substrate and transversely surrounding each of the conductive pads of the substrate.

[0074] In some embodiments, the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof, and the second dielectric layer transversely surrounds a portion of each solder connector, one of the solder connectors protrudes outward into the second dielectric layer, the top surface of the second dielectric layer is coplanar with the top surface of one of the conductive pads, the top surface of the second dielectric layer is below the top surface of one of the conductive pads, the top surface of the second dielectric layer is above the top surface of one of the conductive pads, the second dielectric layer extends to the sidewall of the integrated circuit die, the sidewall of the second dielectric layer is curved and protrudes outward from the integrated circuit die, and / or the substrate is the second integrated circuit die.

[0075] One embodiment is a method, the method comprising the steps of: forming microbumps on a first side of an integrated circuit die—each of which includes a conductive post, and a solder region is present on the conductive post—forming a first dielectric layer that surrounds the microbumps at least laterally on the first side of the integrated circuit die; flattening the microbumps and the first dielectric layer; reflowing the solder region of the flattened microbumps—the reflowing step is to form solder bumps on the conductive post—forming a second dielectric layer on the first dielectric layer and the solder bumps of the microbumps; and bonding the first side of the integrated circuit die to a conductive pad of a wafer using the microbumps—the solder bumps of the microbumps are in physical contact with the conductive pad of the wafer.

[0076] In some embodiments, after bonding a first side of an integrated circuit die to a conductive pad on a wafer using microbumps, a second dielectric layer laterally surrounds each of the conductive pads on the wafer. In some embodiments, after bonding a first side of an integrated circuit die to a conductive pad on a wafer using microbumps, a second dielectric layer laterally surrounds each of the solder bumps of the microbumps. In some embodiments, after bonding a first side of an integrated circuit die to a conductive pad on a wafer using microbumps, the solder bumps of the microbumps cover the sidewall portions of the conductive pads on the wafer. In some embodiments, after bonding a first side of an integrated circuit die to a conductive pad on a wafer using microbumps, the solder bumps of the microbumps extend laterally into the second dielectric layer. In some embodiments, the step of bonding a first side of an integrated circuit die to a conductive pad on a wafer using microbumps includes the step of performing a thermal compression bonding process. In some embodiments, the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof. In some embodiments, the conductive pad of the wafer extends into the first dielectric layer.

[0077] One embodiment is a method, the method comprising the steps of: forming microbumps on a first side of an integrated circuit die—each of which includes a conductive post, and a solder region is present on the conductive post—; depositing a first dielectric layer on the first side of the integrated circuit die—the first dielectric layer fills the solder region of the microbumps—; grinding the first dielectric layer to expose the solder region of the microbumps; reflowing the solder region of the microbumps—the reflowing step is to form a solder bump on the conductive post—; forming a second dielectric layer on the first dielectric layer and the solder bump of the microbumps; and performing a thermal compression bonding process to bond the microbumps of the integrated circuit die to a conductive pad of a wafer—the solder bump of the microbumps is in physical contact with the conductive pad of the wafer, and the second dielectric layer is formed at the start of the thermal compression bonding process Includes covering solder bumps.

[0078] In some embodiments, the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof. In some embodiments, the conductive pad of the wafer extends into the first dielectric layer.

[0079] The foregoing describes the features of various embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures that perform the same purpose and / or achieve the same effect as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and variations may be made herein without departing from the spirit and scope of the present disclosure.

[0080] Examples

[0081] Example 1. As a device,

[0082] A substrate including a conductive pad;

[0083] A package component bonded to a conductive pad of the substrate using a solder connector — the package component includes an integrated circuit die, the integrated circuit die includes a die connector, and one of the solder connectors is coupled to each of the die connectors and to a corresponding conductive pad of the substrate —;

[0084] A first dielectric layer that transversely surrounds each of the above-mentioned die connectors and a portion of the above-mentioned solder connector; and

[0085] A second dielectric layer located between the first dielectric layer and the substrate, and laterally surrounding each of the conductive pads of the substrate.

[0086] A device including

[0087] Example 2. In Example 1,

[0088] A device in which the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof.

[0089] Example 3. In Example 1,

[0090] A device in which the second dielectric layer laterally surrounds a portion of each of the solder connectors.

[0091] Example 4. In Example 3,

[0092] A device in which one of the above solder connectors protrudes outwardly into the second dielectric layer.

[0093] Example 5. In Example 1,

[0094] A device in which the top surface of the second dielectric layer is coplanar with the top surface of one of the conductive pads.

[0095] Example 6. In Example 1,

[0096] A device in which the top surface of the second dielectric layer is located below the top surface of one of the conductive pads.

[0097] Example 7. In Example 1,

[0098] A device in which the top surface of the second dielectric layer is located on the top surface of one of the conductive pads.

[0099] Example 8. In Example 1,

[0100] A device wherein the second dielectric layer extends to the sidewall of the integrated circuit die, and the sidewall of the second dielectric layer is curved and protrudes outwardly from the integrated circuit die.

[0101] Example 9. In Example 1,

[0102] The above substrate is a device that is a second integrated circuit die.

[0103] Example 10. As a method,

[0104] A step of forming microbumps on a first side of an integrated circuit die — each of the microbumps includes a conductive post, and a solder region exists on the conductive post —;

[0105] A step of forming a first dielectric layer on a first side of the integrated circuit die and surrounding the microbump at least laterally;

[0106] A step of flattening the microbumps and the first dielectric layer;

[0107] A step of reflowing the solder region of the flattened microbump — the reflowing step forms a solder bump on the conductive post —;

[0108] A step of forming a second dielectric layer on the first dielectric layer and the solder bumps of the microbumps; and

[0109] A step of bonding a first side of the integrated circuit die to a conductive pad of a wafer using the microbump — the solder bump of the microbump physically contacts the conductive pad of the wafer —

[0110] A method including

[0111] Example 11. In Example 10,

[0112] A method in which, after the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbump, the second dielectric layer surrounds each of the conductive pads of the wafer laterally.

[0113] Example 12. In Example 11,

[0114] A method in which, after the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbump, the second dielectric layer laterally surrounds each of the solder bumps of the microbump.

[0115] Example 13. In Example 10,

[0116] A method in which, after the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbump, the solder bump of the microbump covers a sidewall portion of the conductive pad of the wafer.

[0117] Example 14. In Example 10,

[0118] A method in which, after the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbump, the solder bump of the microbump extends laterally into the second dielectric layer.

[0119] Example 15. In Example 10,

[0120] A method in which the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbumps comprises the step of performing a thermal compression bonding process.

[0121] Example 16. In Example 10,

[0122] A method in which the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof.

[0123] Example 17. In Example 10,

[0124] A method in which the conductive pad of the wafer extends into the first dielectric layer.

[0125] Example 18. As a method,

[0126] A step of forming microbumps on a first side of an integrated circuit die — each of the microbumps includes a conductive post, and a solder region exists on the conductive post —;

[0127] A step of depositing a first dielectric layer on a first side of the integrated circuit die — the first dielectric layer fills the solder region of the microbump —;

[0128] A step of grinding the first dielectric layer to expose the solder region of the microbump;

[0129] A step of reflowing the solder region of the microbump — the reflowing step forms a solder bump on the conductive post —;

[0130] A step of forming a second dielectric layer on the first dielectric layer and the solder bumps of the microbumps; and

[0131] A step of performing a thermal compression bonding process to bond microbumps of the integrated circuit die to a conductive pad of a wafer — a solder bump of the microbump physically contacts the conductive pad of the wafer, and the second dielectric layer covers the solder bump at the start of the thermal compression bonding process —

[0132] A method including

[0133] Example 19. In Example 18,

[0134] A method in which the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof.

[0135] Example 20. In Example 18,

[0136] A method in which the conductive pad of the wafer extends into the first dielectric layer.

Claims

Claim 1 A device comprising: a substrate including a conductive pad; a package component bonded to the conductive pad of the substrate using a solder connector — the package component includes an integrated circuit die, the integrated circuit die includes a die connector, and one of the solder connectors is coupled to each of the die connectors and a corresponding conductive pad of the substrate —; a first dielectric layer transversely surrounding each of the die connectors and a portion of the solder connector; and a second dielectric layer located between the first dielectric layer and the substrate and transversely surrounding each of the conductive pads of the substrate, wherein the second dielectric layer extends to a sidewall of the integrated circuit die, the sidewall of the second dielectric layer has a convex shape protruding outward from the integrated circuit die, and the second dielectric layer covers the sidewall of the first dielectric layer. Claim 2 A device according to claim 1, wherein the second dielectric layer is an adhesive, flux, a non-conductive film, or a combination thereof. Claim 3 A device according to claim 1, wherein the second dielectric layer laterally surrounds a portion of each of the solder connectors. Claim 4 A device according to claim 1, wherein the top surface of the second dielectric layer is coplanar with the top surface of one of the conductive pads. Claim 5 A device according to claim 1, wherein the upper surface of the second dielectric layer is located below the upper surface of one of the conductive pads. Claim 6 A device according to claim 1, wherein the upper surface of the second dielectric layer is on the upper surface of one of the conductive pads. Claim 7 A device according to claim 1, wherein the substrate is a second integrated circuit die. Claim 8 As a method, the method comprises the steps of: forming microbumps on a first side of an integrated circuit die — each of the microbumps comprises a conductive post, and a solder region exists on the conductive post —; forming a first dielectric layer on the first side of the integrated circuit die and surrounding the microbumps at least laterally; flattening the microbumps and the first dielectric layer; reflowing the solder region of the flattened microbumps — the reflowing step forms solder bumps on the conductive post —; and forming a second dielectric layer on the first dielectric layer and the solder bumps of the microbumps. A method comprising the step of bonding a first side of an integrated circuit die to a conductive pad of a wafer using the microbumps, wherein the solder bumps of the microbumps physically contact the conductive pad of the wafer, wherein the second dielectric layer extends to a sidewall of the integrated circuit die, the sidewall of the second dielectric layer has a convex shape protruding outward from the integrated circuit die, and the second dielectric layer covers the sidewall of the first dielectric layer. Claim 9 A method according to claim 8, wherein the step of bonding a first side of the integrated circuit die to a conductive pad of the wafer using the microbump comprises the step of performing a thermal compression bonding process. Claim 10 As a method, the method comprises the steps of: forming microbumps on a first side of an integrated circuit die — each of the microbumps comprises a conductive post, and a solder region exists on the conductive post —; depositing a first dielectric layer on the first side of the integrated circuit die — the first dielectric layer fills the solder region of the microbumps —; grinding the first dielectric layer to expose the solder region of the microbumps; reflowing the solder region of the microbumps — the reflowing step forms a solder bump on the conductive post —; and forming a second dielectric layer on the first dielectric layer and the solder bump of the microbumps. A method comprising the step of performing a thermal compression bonding process to bond a microbump of the integrated circuit die to a conductive pad of a wafer, wherein the solder bump of the microbump physically contacts the conductive pad of the wafer and the second dielectric layer covers the solder bump at the start of the thermal compression bonding process, wherein the second dielectric layer extends to a sidewall of the integrated circuit die and the sidewall of the second dielectric layer has a convex shape protruding outward from the integrated circuit die.

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