Semiconductor device including air spacer and method of manufacture

Abstract

Semiconductor devices comprising air gaps between source / drain regions and a semiconductor substrate and methods for forming the same are disclosed. In an embodiment, the semiconductor device comprises: a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source / drain region adjacent to the gate structure and the first channel region; a first internal spacer layer between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate; and a first air gap between the first source / drain region and the first internal spacer layer in a first direction.

Description

Technology Field

[0001] Related applications

[0002] This application claims priority to U.S. provisional application No. 63 / 268,178 filed February 17, 2022, which is incorporated herein by reference. Background Technology

[0003] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and by patterning various material layers using lithography to form circuit components and elements on the substrate.

[0004] The semiconductor industry has continuously improved the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated within a given area. However, as minimum feature sizes decrease, additional problems arise that need to be addressed. The technology forming the background of the present invention is described in U.S. Patent Application Publication US 2020 / 0365692 A1 (Publication date: Nov. 19, 2020). Brief explanation of the drawing

[0005] Aspects of this disclosure are best understood from the detailed description below when read together with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to actual scale. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIG. 1 illustrates an example of a nanostructured field-effect transistor (FET) in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6a, Fig. 6b, Fig. 7a, Fig. 7b, Fig. 8a, Fig. 8b, Fig. 9a, Fig. 9b, Fig. 10a, Fig. 10b, Fig. 11a, Fig. 11b, Fig. 11c, Fig. 12a, Fig. 12b, Fig. 12c, Fig. 12d, Fig. 12e, Fig. 12f, Fig. 13a, Fig. 13b, Fig. 13c, Fig. 13d, Fig. 13e, Fig. 13f, Fig. 13g, Fig. 13h, Fig. 13i, Fig. 14a, Fig. 14b, Fig. 14c, Fig. 15a, Fig. 15b, Fig. 16a, Fig. 16b, Fig. 17a, Fig. 17b, Fig. 18a, Fig. 18b, Fig. FIGS. 19a, FIGS. 19b, FIGS. 19c, FIGS. 20a, FIGS. 20b, FIGS. 20c, FIGS. 21a, FIGS. 21b, FIGS. 21c, FIGS. 22a, FIGS. 22b, and FIGS. 22c are cross-sectional views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Specific details for implementing the invention

[0006] The disclosure below provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on or above the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat drawing numbers and / or letters in different examples. Such repetition is for simplification and clarification and does not, in itself, explain the relationship between the various embodiments and / or configurations disclosed.

[0007] Additionally, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for ease of explanation to describe the relationship of one element or feature to other element(s) or feature(s) illustrated in the drawings. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other orientations), and spatially relative descriptors used herein may be interpreted similarly accordingly.

[0008] Various embodiments provide methods for forming sealed air gaps (e.g., gas spacers) adjacent to source / drain regions of semiconductor devices and semiconductor devices formed thereby. The method comprises the steps of: depositing a multilayer stack on a semiconductor substrate — the multilayer stack comprises alternating layers of a first semiconductor material and a second semiconductor material —; etching the multilayer stack and the semiconductor substrate to form a plurality of nanostructures from the multilayer stack and first recesses adjacent to the nanostructures and extending into the semiconductor substrate; etching the side surfaces of the nanostructures to the first recesses to form sidewall recesses adjacent to the first recesses; depositing two or more internal spacer layers in the first recesses and filling the sidewall recesses — the internal spacer layers extend along the side surfaces of the nanostructures and along the semiconductor substrate —; and etching the internal spacer layers to form internal spacers adjacent to the nanostructures and the semiconductor substrate. The method includes the step of forming source / drain regions adjacent to internal spacers and nanostructures. The source / drain regions may be formed by epitaxial film deposition processes and may seal bottom air gaps vertically positioned between the spacers on the semiconductor substrate and the source / drain regions. In some embodiments, the source / drain regions may also seal side air gaps horizontally positioned between the source / drain regions and the spacers positioned on the nanostructures. The side air gaps may be positioned vertically between adjacent nanostructures formed of the same semiconductor material or vertically between the nanostructures and the semiconductor substrate. Providing bottom air gaps and side air gaps helps reduce the parasitic capacitance of devices containing air gaps and helps improve bottom isolation between the source / drain regions and the semiconductor substrate. This improves device performance, such as AC performance.

[0009] The embodiments are described below in relation to a specific context, namely, a die containing nanostructured FETs. However, various embodiments may be applied to dies containing other types of transistors (e.g., FinFETs, planar transistors, etc.) instead of or in combination with nanostructured FETs.

[0010] FIG. 1 illustrates, in a three-dimensional view, examples of nanostructure FETs (e.g., nanowire FETs, nanosheet FETs (Nano-FETs), multi-bridge-channel FETs (MBCFETs), gate-all-around FETs (GAA FETs), nanoribbon FETs, etc.) according to some embodiments. The nanostructure FETs comprise nanostructures (55) (e.g., nanosheets, nanowires, nanoribbons, etc.) on pins (66) on a substrate (50) (e.g., a semiconductor substrate). The nanostructures (55) serve as channel regions for the nanostructure FETs. The nanostructures (55) may comprise materials suitable for forming channel regions in p-type transistors, n-type transistors, etc. Isolation regions (68) are placed between adjacent pins (66) that can protrude upward between adjacent isolation regions (68). Although the isolation regions (68) have been described / exemplified as being separated from the substrate (50), as used herein, the term “substrate” may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and isolation regions. Additionally, although the lower portions of the pins (66) have been exemplified as being a single continuous material together with the substrate (50), the lower portions of the pins (66) and / or the substrate (50) may comprise a single material or multiple materials. In this context, the pins (66) refer to a portion extending between adjacent isolation regions (68).

[0011] The gate dielectric layers (104) are located on the upper surfaces of the pins (66) and along the upper surfaces, sidewalls, and lower surfaces of the nanostructures (55). The gate electrodes (106) are located on the gate dielectric layers (104). Epitaxial source / drain regions (92) are placed on the pins (55) on both sides of the gate dielectric layers (104) and the gate electrodes (106).

[0012] FIG. 1 further illustrates reference cross-sectional views used in subsequent drawings. Cross-section A-A' is along the longitudinal axis of the gate electrode (102), for example, perpendicular to the direction of current flow between the epitaxial source / drain regions (92) of the nanostructure FET. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fin (66) of the nanostructure FET, for example, in the direction of current flow between the epitaxial source / drain regions (92) of the nanostructure FET. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions (92) of the nanostructure FET. Subsequent drawings refer to these reference cross-sections for clarity.

[0013] Some embodiments discussed herein are discussed in the context of nanostructured FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments consider aspects used in planar devices, such as planar FETs, or in FinFETs.

[0014] FIGS. 2 to 22c are cross-sectional views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. FIGS. 2 to 5, FIG. 6a, FIG. 14a, FIG. 15a, FIG. 16a, FIG. 17a, FIG. 18a, FIG. 19a, FIG. 20a, FIG. 21a, and FIG. 22a illustrate the reference cross-section A-A' illustrated in FIG. 1. FIGS. 6b, FIGS. 7b, FIGS. 8b, FIGS. 9b, FIGS. 10b, FIGS. 11b, FIGS. 12b, FIGS. 13b, FIGS. 13c, FIGS. 13e, FIGS. 13f, FIGS. 13g, FIGS. 13h, FIGS. 13i, FIGS. 14b, FIGS. 15b, FIGS. 16b, FIGS. 17b, FIGS. 18b, FIGS. 19b, FIGS. 20b, FIGS. 21b, and FIGS. 22B illustrate the reference section B-B' exemplified in FIGS. 1. FIGS. 7a, FIGS. 8a, FIGS. 9a, FIGS. 10a, FIGS. 11a, FIGS. 12a, FIGS. 13a, FIGS. 13c, FIGS. 14c, FIGS. 19c, FIGS. 20c, FIGS. 21c, and FIGS. 22c illustrate the reference section C-C' exemplified in FIGS. 1.

[0015] In FIG. 2, a substrate (50) is provided. The substrate (50) may be a bulk semiconductor, semiconductor-on-insulator (SOI) substrate that may be doped (e.g., with a p-type or n-type dopant) or may not be doped. The substrate (50) may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate that is generally a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate (50) is silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; An alloy semiconductor comprising silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium arsenide, and / or gallium indium arsenide phosphide; or a combination thereof may be included.

[0016] The substrate (50) has an n-type region (50N) and a p-type region (50P). The n-type region (50N) may be for forming n-type devices such as NMOS transistors, for example, n-type nanostructure FETs, and the p-type region (50P) may be for forming p-type devices such as PMOS transistors, for example, p-type nanostructure FETs. The n-type region (50N) may be physically separated from the p-type region (50P) (as exemplified by the divider (20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be placed between the n-type region (50N) and the p-type region (50P). Although one n-type region (50N) and one p-type region (50P) are exemplified, any number of n-type regions (50N) and p-type regions (50P) may be provided.

[0017] Additionally, in FIG. 2, a multilayer stack (64) is formed on the substrate (50). The multilayer stack (64) comprises alternating layers of first semiconductor layers (51A-C) (collectively referred to as the first semiconductor layers (51)) and second semiconductor layers (53A-C) (collectively referred to as the second semiconductor layers (53)). For example, and as discussed in more detail below, the second semiconductor layers (53) will be removed and the first semiconductor layers (51) will be patterned to form channel regions of nanostructure FETs in a p-type region (50P). The first semiconductor layers (51) will be removed and the second semiconductor layers (53) will be patterned to form channel regions of nanostructure FETs in an n-type region (50N). In some embodiments, the first semiconductor layers (51) may be removed and the second semiconductor layers (53) may be patterned to form channel regions of nanostructure FETs in the n-type region (50N), and the second semiconductor layers (53) may be removed and the first semiconductor layers (51) may be patterned to form channel regions of nanostructure FETs in the p-type region (50P).

[0018] In some embodiments, the first semiconductor layers (51) will be removed and the second semiconductor layer (53) will be patterned to form channel regions of the nanostructure FETs in both the n-type region (50N) and the p-type region (50P). In some embodiments, the second semiconductor layers (53) will be removed and the first semiconductor layer (51) will be patterned to form channel regions of the nanostructure FETs in both the n-type region (50N) and the p-type region (50P). In these embodiments, the channel regions of both the n-type region (50N) and the p-type region (50P) may have the same material composition (e.g., silicon or other semiconductor material) and may be formed simultaneously. FIGS. 22a, 22b, and 22c illustrate structures produced from embodiments in which the channel regions of both the p-type region (50P) and the n-type region (50N) comprise silicon, for example.

[0019] The multilayer stack (64) is illustrated for illustrative purposes as comprising three layers each of the first semiconductor layers (51) and the second semiconductor layers (53). In some embodiments, the multilayer stack (64) may comprise any number of first semiconductor layers (51) and second semiconductor layers (53). Each of the layers of the multilayer stack (64) may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the first semiconductor layers (51) may be formed from a first semiconductor material suitable for p-type nanostructure FETs such as silicon germanium, and the second semiconductor layers (53) may be formed from a second semiconductor material suitable for n-type nanostructure FETs such as silicon, silicon carbon, etc. The multilayer stack (64) is illustrated for example as having a bottom semiconductor layer suitable for p-type nanostructure FETs. In some embodiments, the multilayer stack (64) may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanostructure FETs.

[0020] The first semiconductor materials and the second semiconductor materials may be materials having high etching selectivity toward each other. In this way, the first semiconductor layers (51) of the first semiconductor material can be removed without significantly removing the second semiconductor layers (53) of the second semiconductor material in the n-type region (50N), thereby allowing the second semiconductor layers (53) to be patterned to form channel regions of n-type nanostructure FETs. Similarly, the second semiconductor layers (53) of the second semiconductor material can be removed without significantly removing the first semiconductor layers (51) of the first semiconductor material in the p-type region (50P), thereby allowing the first semiconductor layers (51) to be patterned to form channel regions of p-type nanostructure FETs.

[0021] In FIG. 3, pins (66) are formed on the substrate (50) and nanostructures (55) are formed on the multilayer stack (64). In some embodiments, the nanostructures (55) and pins (66) may be formed on the multilayer stack (64) and the substrate (50), respectively, by etching trenches in the multilayer stack (64) and the substrate (50). The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), or a combination thereof. The etching may be anisotropic. Forming nanostructures (55) by etching the multilayer stack (64) may further define first nanostructures (52A-C) (collectively referred to as first nanostructures (52)) from the first semiconductor layers (51) and second nanostructures (54A-C) (collectively referred to as second nanostructures (54)) from the second semiconductor layers (53). The first nanostructures (52) and the second nanostructures (54) may also be collectively referred to as nanostructures (55).

[0022] The pins (66) and nanostructures (55) can be patterned by any suitable method. For example, the pins (66) and nanostructures (55) can be patterned using one or more photolithography processes including double patterning or multiple patterning processes. Generally, a double patterning or multiple patterning process combines photolithography and a self-aligning process to allow patterns with smaller pitches to be produced than can be obtained, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed together with the sacrificial layer patterned using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the pins (66).

[0023] FIG. 3 illustrates pins (66) in an n-type region (50N) and a p-type region (50P) having substantially the same widths for illustrative purposes. In some embodiments, the widths of the pins (66) in the n-type region (50N) may be larger or thinner than the pins (66) in the p-type region (50P). Additionally, while the pins (66) and nanostructures (55) are each illustrated as having a constant width throughout, in some embodiments the pins (66) and / or nanostructures (55) may have tapered sidewalls so that the width of each pin (66) and / or nanostructure (55) increases continuously in the direction toward the substrate (50). In such embodiments, each nanostructure (55) may have a different width and may be trapezoidal in shape.

[0024] In FIG. 4, shallow trench isolation (STI) regions (68) are formed adjacent to the pins (66). The STI regions (68) can be formed by depositing an insulating material on the substrate (50), the pins (66), and the nanostructures (55), and between the adjacent pins (66) and the nanostructures (55). The insulating material (62) may be an oxide such as silicon oxide; a nitride such as silicon nitride; etc.; or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the nanostructures (55). The insulating material is exemplified as a single layer, but some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately exemplified) may be formed along the surfaces of the substrate (50), pins (66), and nanostructures (55). A filling material such as those discussed above may be formed on the liner.

[0025] A removal process is applied to the insulating material to remove excess insulating material on the nanostructures (55). In some embodiments, a flattening process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof may be used. After the flattening process is completed, the nanostructures (55) are exposed so that the upper surfaces of the nanostructures (55) and the insulating material are level.

[0026] The insulating material is recessed to form STI regions (68). The insulating material is recessed so that the upper portions of the pins (66) of the n-type region (50N) and the nanostructures (55) of the p-type region (50P) protrude from between the adjacent STI regions (68). The upper surfaces of the STI regions (68) may have flat surfaces, convex surfaces, concave surfaces (such as dishing), or a combination thereof as illustrated. The upper surfaces of the STI regions (68) may be formed flat, convex, and / or concave by appropriate etching. The STI regions (68) may be recessed using an acceptable etching process such as one that is optional for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the pins (66) and nanostructures (55). For example, oxide removal using dilute hydrofluoric acid (dHF) can be used.

[0027] The process described in connection with FIGS. 2 through 4 is merely an example of how the pins (66) and nanostructures (55) may be formed. In some embodiments, the pins (66) and / or nanostructures (55) may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed on the upper surface of the substrate (50), and trenches may be etched through the dielectric layer to expose the substrate (50) placed underneath. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed so that the epitaxial structures protrude from the dielectric layer to form the pins (66) and / or nanostructures (55). The epitaxial structures may include the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be doped in situ during growth, which may exclude prior and / or subsequent injection. In situ and injection doping may be used together.

[0028] Additionally, the first semiconductor layers (51) (and the first nanostructures (52)) and the second semiconductor layers (53) (and the second nanostructures (54)) are illustrated and discussed herein for example as comprising the same materials in the p-type region (50P) and the n-type region (50N). In some embodiments, one or both of the first semiconductor layers (51) and the second semiconductor layers (53) may be formed with different materials or in a different order in the p-type region (50P) and the n-type region (50N).

[0029] Additionally, in FIG. 4, suitable wells (not separately illustrated) may be formed on the pins (66), nanostructures (55), and / or STI regions (68). In embodiments having different well types, different injection steps for the n-type region (50N) and the p-type region (50P) may be achieved using photoresist or other masks (not separately illustrated). For example, photoresist may be formed on the pins (66), nanostructures (55), and STI regions (68) in the n-type region (50N) and the p-type region (50P). The photoresist is patterned to expose the p-type region (50P). The photoresist may be formed by using a spin-on technique and may be patterned using acceptable photolithography techniques. When the photoresist is patterned, n-type impurity implantation is performed in the p-type region (50P), and the photoresist can act as a mask to prevent n-type impurities from being implanted in the n-type region (50N). The n-type impurities are about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 It may be phosphorus, arsenic, antimony, etc. injected into the area at a concentration within a range. After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0030] After or before the injection of the p-type region (50P), a photoresist or other masks (not otherwise exemplified) are formed over the pins (66), nanostructures (55), and STI regions (68) of the p-type region (50P) and the n-type region (50N). The photoresist is patterned to expose the n-type region (50N). The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity injection into the n-type region (50N) can be performed, and the photoresist can act as a mask to prevent p-type impurities from being injected into the p-type region (50P). The p-type impurities are about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 It may be boron, boron fluoride, indium, etc. injected into the area at a concentration within a range. After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After injection of the n-type region (50N) and the p-type region (50P), annealing may be performed to repair injection damage and activate the injected p-type and / or n-type impurities. In some embodiments, the grown materials of the epitaxial pins may be doped in situ during growth, which may exclude injection, but in situ and injection doping may be used together.

[0032] In FIG. 5, a dummy dielectric layer (70) is formed on the pins (66) and nanostructures (55). The dummy dielectric layer (70) may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer (72) is formed on the dummy dielectric layer (70), and a mask layer (74) is formed on the dummy gate layer (72). The dummy gate layer (72) is deposited on the dummy dielectric layer (70) and then planarized, for example, by CMP. The mask layer (74) may be deposited on the dummy gate layer (72). The dummy gate layer (72) may be a conductive or non-conductive material and may be selected from the group comprising amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer (72) may be formed by physical vapor deposition (PVD), CVD, sputtering, or other techniques for forming selected materials. The dummy gate layer (72) may be made of other materials having high etch selectivity from the etching of isolation regions. The mask layer (74) may include, for example, silicon nitride, silicon oxynitride, etc. In the embodiment illustrated in FIG. 5, a single dummy gate layer (72) and a single mask layer (74) are formed across the n-type region (50N) and the p-type region (50P). The dummy dielectric layer (70) is illustrated as covering only the pins (66) and nanostructures (55) for illustrative purposes only. In some embodiments, the dummy dielectric layer (70) may be formed so that the dummy dielectric layer (70) covers the STI regions (68) so that the dummy dielectric layer (70) extends between the dummy gate layer (72) and the STI regions (68).

[0033] FIGS. 6a through 21c illustrate various additional steps in the fabrication of the exemplary devices. FIGS. 7a, FIGS. 8a, FIGS. 9a, FIGS. 10a, FIGS. 11a, FIGS. 12a, FIGS. 13a, FIGS. 13c, FIGS. 14a, FIGS. 14c, FIGS. 15a, FIGS. 16a, FIGS. 19c, FIGS. 20c, and FIGS. 21c illustrate features of an n-type region (50N) or a p-type region (50). In FIGS. 6a and 6b, the mask layer (74) (see FIG. 5) may be patterned using acceptable photolithography and etching techniques to form masks (78). The pattern of the masks (78) is transferred to a dummy gate layer (72) and a dummy dielectric layer (70) to form dummy gates (76) and dummy gate dielectrics (71), respectively. Dummy gates (76) cover each channel region of the nanostructures (55). The pattern of the masks (78) can be used to physically separate each dummy gate (76) from adjacent dummy gates (76). The dummy gates (76) may also have a longitudinal direction substantially perpendicular to the longitudinal direction of each pin (66) and the nanostructures (55).

[0034] In FIGS. 7A and 7B, the first spacer layer (80) and the second spacer layer (82) are formed on the structures illustrated in FIGS. 6A and 6B, respectively. The first spacer layer (80) and the second spacer layer (82) will subsequently be patterned to serve as spacers for forming self-aligned source / drain regions. In FIGS. 7A and 7B, the first spacer layer (80) is formed on the top surfaces of the STI regions (68); the surfaces and sides of the nanostructures (55) and masks (78); and the side surfaces of the pins (66), dummy gates (76), and dummy gate dielectrics (71). The second spacer layer (82) is formed on the first spacer layer (80). The first spacer layer (80) may be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., by using techniques such as thermal oxidation or by CVD, ALD, etc. The second spacer layer (82) may be formed from a material having an etching rate different from that of the first spacer layer (80), such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be formed by CVD, ALD, etc.

[0035] After the first spacer layer (80) is formed and before the second spacer layer (82) is formed, injections may be performed on low-concentration doped source / drain (LDD) regions (not separately illustrated). In embodiments having different device types similar to the injections previously discussed in FIG. 4, a mask such as photoresist may be formed over an n-type region (50N) while exposing a p-type region (50P). Appropriate type (e.g., p-type) impurities may be injected into the exposed pins (66) and nanostructures (55) of the p-type region (50P). The mask may be removed. Subsequently, a mask such as photoresist may be formed over a p-type region (50P) while exposing an n-type region (50N). Appropriate types of impurities (e.g., n-type) can be injected into the exposed pins (66) and nanostructures (55) of the n-type region (50N). The mask can be removed. The n-type impurities can be any of the previously discussed n-type impurities, and the p-type impurities can be any of the previously discussed p-type impurities. Low-concentration doped source / drain regions are approximately 1 x 10⁻⁶ 15 atoms / cm 3 to about 1x10 19 atoms / cm 3 It can have a range of impurity concentrations. Annealing can be used to repair injection damage and activate injected impurities.

[0036] In FIGS. 8a and 8b, the first spacer layer (80) and the second spacer layer (82) are etched to form the first spacers (81) and the second spacers (83), respectively. As discussed in more detail below, the first spacers (81) and the second spacers (83) serve to self-align the subsequently formed source / drain regions, control the growth of the subsequently formed source / drain regions, and protect the pins (66) and / or nanostructures (55) during subsequent processing. The first spacer layer (80) and the second spacer layer (82) may be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), an anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer (82) has a different etching rate than the material of the first spacer layer (80), so that the first spacer layer (80) can act as an etching stop layer during patterning of the second spacer layer (82). The second spacer layer (82) can act as a mask during patterning of the first spacer layer (80). For example, the second spacer layer (82) can be etched using an anisotropic etching process in which the first spacer layer (80) acts as an etching stop layer. The remaining portions of the second spacer layer (82) form the second spacers (83) as illustrated in FIG. 8a. The second spacers (83) act as a mask while etching the exposed portions of the first spacer layer (80) to form the first spacers (81) as illustrated in FIG. 8a.

[0037] As illustrated in FIG. 8a, the first spacers (81) and the second spacers (83) are placed on the sidewalls of the pins (66) and nanostructures (55). As illustrated in FIG. 8b, in some embodiments, the second spacer layer (82) may be removed from the first spacer layer (80) adjacent to the masks (78), dummy gates (76), and dummy gate dielectrics (71), and the first spacers (81) are placed on the sidewalls of the masks (78), dummy gates (76), and dummy gate dielectrics (71). In some embodiments, a portion of the second spacer layer (82) may remain on the first spacer layer (80) adjacent to the masks (78), dummy gates (76), and dummy gate dielectrics (71) (for example, the second spacers (83) may be formed on the first spacers (81) adjacent to the masks (78), dummy gates (76), and dummy gate dielectrics (71).

[0038] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, steps in a different order may be used (e.g., the first spacers (81) may be patterned prior to the formation of the second spacers (82)), and additional spacers may be formed and removed. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0039] In FIGS. 9a through 9c, first recesses (86) are formed in the pins (66), nanostructures (55), and substrate (50). Epitaxial source / drain regions will subsequently be formed in the first recesses (86). The first recesses (86) may extend into the substrate (50) through the first nanostructures (52) and the second nanostructures (54). As illustrated in FIG. 9a, the upper surfaces of the STI regions (58) may be on the lower surfaces of the first recesses (86) (e.g., the upper surfaces of the pins (66)). As illustrated in FIG. 9b, the first recesses (86) extend into the substrate (50) through the nanostructures (55). The portions of the first recesses (86) extending into the substrate (50) may be V-shaped (as illustrated in FIG. 9b), U-shaped, etc. In some embodiments, the pins (66) may be etched so that the lower surfaces of the first recesses (86) are positioned at the same height as or above the upper surfaces of the STI regions (68). The first recesses (86) may be formed by etching the pins (66), nanostructures (55), and substrate (50) using an anisotropic etching process such as RIE, NBE, etc. The first spacers (81), second spacers (83), masks (78), and STI regions (68) mask portions of the pins (66), nanostructures (55), and substrate (50) during the etching processes used to form the first recesses (86). Single etching processes or multiple etching processes may be used to etch each layer of the nanostructures (55) and / or pins (66). Timed etching processes may be used to stop the etching of the first recesses (86) after the first recesses (86) have reached a desired height. The first recesses (86) may have depths (D1) below the upper surfaces of the STI regions (68) in the range of about 30 nm to about 70 nm and depths (D2) below the upper surfaces of the pins (66) in the range of about 5 nm to about 40 nm.Forming the first recesses (86) with depths (D1 and D2) does not extend into the substrate (50) to the extent that the substrate (50) is damaged, and provides sufficient space so that air gaps can be sealed under the subsequently formed source / drain regions.

[0040] In FIG. 10a and FIG. 10b, portions of the sidewalls of nanostructures (55) formed from first semiconductor materials (e.g., first nanostructures (52)) exposed by the first recesses (86) are etched to form sidewall recesses (88) in an n-type region (50N), and portions of the sidewalls of nanostructures (55) formed from second semiconductor materials (e.g., second nanostructures (54)) exposed by the first recesses (86) are etched to form sidewall recesses (88) in a p-type region (50P). Although the sidewalls of the first nanostructures (52) and the second nanostructures (54) within the sidewall recesses (88) are illustrated as straight in FIG. 10b, the sidewalls may be concave or convex. The sidewalls can be etched using isotropic etching processes such as wet etching. While etchants selective to the first semiconductor materials are used to etch the first nanostructures (52), the p-type region (50P) can be protected using a mask (not separately illustrated) so that the second nanostructures (54) and the substrate (50) remain relatively unetched in the n-type region (50N) compared to the first nanostructures (52). Similarly, while etchants selective to the second semiconductor materials are used to etch the second nanostructures (54), the n-type region (50N) can be protected using a mask (not separately illustrated) so that the first nanostructures (52) and the substrate (50) remain relatively unetched in the p-type region (50P) compared to the second nanostructures (54).In embodiments where the first nanostructures (52) comprise, for example, SiGe and the second nanostructures (54) comprise, for example, Si or SiC, the sidewalls of the first nanostructures (52) in the n-type region (50N) can be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and a wet or dry etching process using hydrofluoric acid, other fluorine-based etchants, etc. can be used to etch the sidewalls of the second nanostructures (54) in the p-type region (50P).

[0041] As illustrated in FIG. 10b, the sidewalls of the first nanostructures (52) can be recessed from the sidewalls of the second nanostructures (54) in the n-type region (50N) by a distance (D3) ranging from about 3 nm to about 15 nm. The sidewalls of the second nanostructures (54) can be recessed from the sidewalls of the first nanostructures (52) in the p-type region (50P) by a distance (D4) ranging from about 3 nm to about 15 nm. Recessing the first nanostructures (52) in the n-type region (50N) and the second nanostructures (54) in the p-type region (50P) by the defined distances provides sufficient isolation between the subsequently formed source / drain regions and the gate structures without excessively reducing the volume of the subsequently formed gate structures.

[0042] In FIGS. 11a through 11c, a multilayer spacer film (90) is formed over the structures of FIGS. 10a and 10b. FIG. 11c illustrates detailed views of the regions (97a and 97b) of FIG. 11b. As illustrated in FIGS. 11b and 11c, the multilayer spacer film (90) can fill the sidewall recesses (88) (illustrated in FIG. 10b). The multilayer spacer film (90) is subsequently patterned to form internal spacers that act as isolation features between the subsequently formed source / drain regions and the gate structures. As discussed in more detail below, source / drain regions will be formed in the first recesses (86), while the first nanostructures (52) of the n-type region (50N) and the second nanostructures (54) of the p-type region (50P) will be replaced with corresponding gate structures.

[0043] FIGS. 11a and 11b illustrate an embodiment in which a multilayer spacer film (90) comprises a first internal spacer layer (90A) and a second internal spacer layer (90B). FIG. 11c illustrates an embodiment in which a multilayer spacer film (90) comprises a first internal spacer layer (90A), a second internal spacer layer (90B), a third internal spacer layer (90C), and a fourth internal spacer layer (90D). The multilayer spacer film (90) may comprise any number of internal spacer layers, and the number of internal spacer layers, the thicknesses of the internal spacer layers, and the materials selected for the internal spacer layers may be selected to control the shape and effective dielectric constant of the subsequently formed internal spacer.

[0044] The internal spacer layers of the multilayer spacer film (90) can be formed from dielectric materials such as silicon carbon nitride (SiCN), silicon nitride (SiN), silicon carbon oxynitride (SiCON), silicon oxycarbide (SiOC), silicon oxynitride (SiON), etc. The internal spacer layers of the multilayer spacer film (90) can be formed by conformal film formation processes such as ALD, CVD, etc.

[0045] In the embodiments illustrated in FIGS. 11a and 11b, the first internal spacer layer (90A) may be formed with a thickness (T1) in the range of about 1 nm to about 15 nm, and the second internal spacer layer (90B) may be formed with a thickness (T2) in the range of about 3 nm to about 8 nm. The ratio of the thickness (T2) of the second internal spacer layer (90B) to the thickness (T1) of the first internal spacer layer (90A) may be about 0.5 to about 3. The first internal spacer layer (90A) and the second internal spacer layer (90B) fill the sidewall recesses (88). The first internal spacer layer (90A) may be formed of a material having a relatively high etching resistance and a relatively high dielectric constant, and the second internal spacer layer (90B) may be formed of a material having a relatively low etching resistance and a relatively low dielectric constant. The material of the second inner spacer layer (90B) may also have a higher etching selectivity compared to the material of the first inner spacer layer (90A). In this way, the second inner spacer layer (90B) can be removed without significantly removing the first inner spacer layer (90A). In some embodiments, the ratio of the etching rate of the material of the second inner spacer layer (90B) to the etching rate of the material of the first inner spacer layer (90A) during a subsequent etching process (e.g., the etching selectivity of the second inner spacer layer (90B) relative to the first inner spacer layer (90B)) may be greater than about 5. The material of the first inner spacer layer (90A) may also have a higher etching selectivity compared to the material of the second inner spacer layer (90B), so that the first inner spacer layer (90A) can be removed without significantly removing the second inner spacer layer (90B).

[0046] The first inner spacer layer (90A) may have a dielectric constant in the range of about 4 to about 7, and the second inner spacer layer (90B) may have a dielectric constant in the range of about 3 to about 6. In some embodiments, the etching selectivity and dielectric constants of the first inner spacer layer (90A) and the second inner spacer layer (90B) may be determined based on the oxygen, carbon, and nitrogen concentrations of the first inner spacer layer (90A) and the second inner spacer layer (90B). The first inner spacer layer (90A) may be formed of a material having a higher carbon and / or nitrogen concentration, and the second inner spacer layer (90B) may be formed of a material having a higher oxygen concentration. The first inner spacer layer (90A) may have an oxygen concentration in the range of about 0 at.% to about 40 at.%, a nitrogen concentration in the range of about 5 at.% to about 50 at.%, and an oxygen concentration in the range of about 2 at.% to about 40 at.%. The second inner spacer layer (90B) may have an oxygen concentration in the range of about 10 at.% to about 60 at.%, a nitrogen concentration in the range of about 10 at.% to about 60 at.%, and an oxygen concentration in the range of about 0 at.% to about 20 at.%.

[0047] Forming the first internal spacer layer (90A) with the aforementioned materials and the aforementioned thicknesses ensures that desired portions of the first internal spacer layer (90A) remain undamaged after subsequent etching processes (e.g., etching processes used to remove the second internal spacer layer (90B), the first nanostructures (52) of the n-type region (50N), and the second nanostructures (54) of the p-type region (50P), which protects the subsequently formed source / drain regions from damage. This improves device performance and reduces device defects. Forming the second internal spacer layer (90B) with the aforementioned materials and the aforementioned thickness reduces the effective dielectric constant of subsequently formed internal spacers including the remaining portions of the second internal spacer layer (90B) and helps the second internal spacer layer (90B) to be easily removed, which helps reduce the effective dielectric constant of subsequently formed internal spacers. This improves device performance.

[0048] In some embodiments, the first inner spacer layer (90A) and the second inner spacer layer (90B) may have thicknesses on the bottom portions of the first recess (86), the top portions of the first recess (86), and the surfaces of the first spacers (81), the second spacers (83), the STI regions (68), and the masks (78) that are greater than the thicknesses of the first inner spacer layer (90A) and the second inner spacer layer (90B) in the sidewall recesses (88). For example, the first inner spacer layer (90A) may have a thickness (T3) in the range of about 1 nm to about 10 nm in the bottom portions of the first recesses (86), and the second inner spacer layer (90B) may have a thickness (T4) in the range of about 5 nm to about 30 nm in the bottom portions of the first recesses (86). The ratio of the thickness (T3) of the first internal spacer layer (90A) of the bottom portions of the first recesses (86) to the thickness (T1) of the first internal spacer layer (90A) along the side surfaces of the nanostructures (55) may be in the range of about 0.2 to about 1. The ratio of the thickness (T4) of the second internal spacer layer (90B) of the bottom portions of the first recesses (86) to the thickness (T2) of the second internal spacer layer (90B) along the side surfaces of the nanostructures (55) may be in the range of about 0.2 to about 1. Providing a first internal spacer layer (90A) and a second internal spacer layer (90B) having greater thicknesses at the lower portions of the first recesses (86) ensures that portions of the pins (66) adjacent to the substrate (50) and the first recesses (86) remain covered by the first internal spacer layer (90A) and the second internal spacer layer (90B) even after the multilayer spacer film (90) is etched to form internal spacers. This prevents epitaxial growth of source / drain regions subsequently formed from the substrate (50) and pins (66) so that air spacers are formed between the source / drain regions and the substrate (50) and pins (66).Air spacers reduce capacitance and improve the isolation of finished devices, thereby enhancing device performance (e.g., AC performance) and reducing device defects.

[0049] In the embodiment illustrated in FIG. 11c, the multilayer spacer film (90) comprises four internal spacer layers (e.g., a first internal spacer layer (90A), a second internal spacer layer (90B), a third internal spacer layer (90C), and a fourth internal spacer layer (90D)). The first internal spacer layer (90A) may be formed with a thickness ranging from about 0.5 nm to about 2 nm, and the second internal spacer layer (90B), the third internal spacer layer (90C), and the fourth internal spacer layer (90D) may each be formed with a thickness ranging from about 0.5 nm to about 2 nm. The first internal spacer layer (90A), the second internal spacer layer (90B), the third internal spacer layer (90C), and the fourth internal spacer layer (90D) fill the sidewall recesses (88).

[0050] The first internal spacer layer (90A) may comprise the materials previously described for the first internal spacer layer (90A), and the second internal spacer layer (90B), the third internal spacer layer (90C), and the fourth internal spacer layer (90D) may each comprise the materials previously described for the second internal spacer layer (90B). In some embodiments, the first internal spacer layer (90A), the second internal spacer layer (90B), the third internal spacer layer (90C), and the fourth internal spacer layer (90D) may have reduced etching resistances and reduced dielectric constants. Each of the first internal spacer layer (90A), the second internal spacer layer (90B), the third internal spacer layer (90C), and the fourth internal spacer layer (90D) can be formed of materials having excellent etching selectivity for adjacent internal spacer layers, so that each layer of the multilayer spacer film (90) can be selectively etched. Providing a multilayer spacer film (90) having a greater number of internal spacer layers can be used to provide greater control over the shape and effective dielectric constant of subsequently formed internal spacers formed by patterning the multilayer spacer film (90). In the embodiment of FIG. 11c in which the multilayer spacer film (90) comprises four internal spacer layers, the first internal spacer layer (90A) may be formed with a smaller thickness than in embodiments provided with a smaller number of internal spacer layers, which can be used to reduce the effective dielectric constant of subsequently formed internal spacers.

[0051] In FIGS. 12a through 12f, the multilayer spacer film (90) is etched to form internal spacers (91). The processes used to etch the multilayer spacer film (90) may be trimming processes and may be referred to as internal spacer trimming processes. FIG. 12e illustrates detailed views of the regions (97a and 97b) of FIG. 12b. In the various embodiments illustrated in FIGS. 12a through 12f, the remainder of the first internal spacer layer (90A) forms the first internal spacer portions (91A), the remainder of the second internal spacer layer (90B) forms the second internal spacer portions (91B), the remainder of the third internal spacer layer (90C) forms the third internal spacer portions (91C), and the remainder of the fourth internal spacer layer (90D) forms the fourth internal spacer portions (91D). The multilayer spacer film (90) may be etched by one or more etching processes, such as dry etching processes, wet etching processes, combinations thereof, etc. The etching processes used to etch the multilayer spacer film (90) may be isotropic. In embodiments where a wet etching process is used, the multilayer spacer film (90) may be etched using sulfuric acid (H2SO4), phosphoric acid (H3PO4), dilute hydrofluoric acid (dHF), or combinations thereof. In embodiments where a dry etching process is used, the multilayer spacer film (90) may be etched using a gas source comprising a mixture of trifluoromethane (CHF3) and oxygen (O2), a mixture of carbon tetrafluoride (CF4) and oxygen, a mixture of nitrogen trifluoride (NF3) and fluoromethane (CH3F) and trifluoromethane, or combinations thereof; oxygen ashing or oxygen plasma; etc.

[0052] As previously discussed, the etching processes used to etch the multilayer spacer film (90) can etch the second inner spacer layer (90B), the third inner spacer layer (90C), and the fourth inner spacer layer (90D) at a faster rate than the first inner spacer layer (90A), for example, at a rate at least five times the rate at which the first inner spacer layer (90A) is etched. In this way, the second inner spacer layer (90B), the third inner spacer layer (90C), and the fourth inner spacer layer (90D) can be etched without significantly removing the material of the first inner spacer layer (90A). Afterward, the first inner spacer layer (90A) can be etched by a selective etching process without significantly removing the material of the second inner spacer layer (90B), the third inner spacer layer (90C), and the fourth inner spacer layer (90D). This provides excellent control over the final shapes of the inner spacers (91).

[0053] In the embodiment illustrated in FIGS. 12a and 12b, the first internal spacer portions (91A) remain in the sidewall recesses (88) (see FIGS. 10a and 10b) and in the lower portions of the first recesses (86). The first internal spacer portions (91A) cover portions of the sidewall recesses (88) adjacent to the nanostructures (55), specifically covering portions of the sidewall recesses (88) adjacent to the first nanostructures (52) in the n-type region (50N) and portions of the sidewall recesses (88) adjacent to the second nanostructures (54) in the p-type region (50P). The first internal spacer portions (91A) extend continuously from the sidewall recesses (88) adjacent to the first nanostructures (52A) to the lower portions of the first recesses (86) in the n-type region (50N). The first internal spacer portions (91A) and the second internal spacer portions (91B) may be at least partially recessed from the side surfaces of the second nanostructures (54) of the n-type region (50N) and the side surfaces of the first nanostructures (52) of the p-type region (50P). The second internal spacer portions (91B) remain in the sidewall recesses (88) and in the bottom portions of the first recesses (86). The first internal spacer portions (91A) and the second internal spacer portions (91B) are the side surfaces of the second nanostructures (54) of the n-type region (50N) and the side surfaces of the first nanostructures (52) of the p-type region (50P); the side surfaces and top surfaces of the first spacers (81), the second spacers (83), and the STI regions (68); and is removed from the upper surfaces of the masks (78).

[0054] Providing first internal spacer portions (91A) in the sidewall recesses (88) prevents subsequent etching processes, such as etching processes used to remove first nanostructures (52) from the n-type region (50N) and etching processes used to remove second nanostructures (54) from the p-type region (50P), from damaging source / drain regions subsequently formed in the first recesses (86). This reduces device defects and improves device performance. The second internal spacer portions (91B) remaining in the sidewall recesses (88) have lower dielectric constants than the first internal spacer portions (91A), which reduces the effective dielectric constant of the internal spacers (91). Recessing the second internal spacer portions (91B) and the first internal spacer portions (91A) with respect to the sidewalls of the second nanostructures (54) of the n-type region (50N) and the first nanostructures (52) of the p-type region (50P) allows air gaps to be sealed adjacent to the internal spacers (91), which further reduces the effective dielectric constants of the internal spacers (91). This improves isolation between subsequently formed source / drain regions and subsequently formed gate structures, reduces capacitance, and improves device performance. Removing the first internal spacer portions (91A) and the second internal spacer portions (91B) from the side surfaces of the first nanostructures (52) and the second nanostructures (54) allows the source / drain regions to subsequently be epitaxially grown from the first nanostructures (52) and the second nanostructures (54). The first internal spacer portions (91A) and the second internal spacer portions (91B) remaining in the lower portions of the first recesses (86) cover the pins (66) and the substrate (50), which block the epitaxial growth of source / drain regions from the pins (66) and the substrate (50).This allows air gaps to be sealed between the source / drain regions and the internal spacers (91) in the lower portions of the first recesses (86). The air gaps remaining in the lower portions of the first recesses (86) and the second internal spacer portions (91B) provide improved isolation between the source / drain regions and the pins (66) and the substrate (50) placed underneath, provide reduced capacitance, and improve device performance.

[0055] In the embodiment illustrated in FIG. 12c, the multilayer spacer film (90) is etched such that the first inner spacer portions (91A) of the n-type region (50N) are discontinuous between the bottom portions of the first recesses (86) and the sidewall recesses (88) adjacent to the first nanostructures (52A). The portions of the substrate (50) and the pins (66) may be exposed by the first inner spacer portions (91A) and the second inner spacer portions (91B) in both the n-type region (50N) and the p-type region (50P). The first internal spacer portions (91A) and the second internal spacer portions (91B) remaining in the lower portions of the first recesses (86) cover portions of the pins (66) and the substrate (50), which block epitaxial growth of source / drain regions from the pins (66) and the substrate (50). This allows air gaps to be sealed between the source / drain regions and the internal spacers (91) in the lower portions of the first recesses (86). The air gaps remaining in the lower portions of the first recesses (86) and the second internal spacer portions (91B) provide improved isolation between the source / drain regions and the underlying pins (66) and the substrate (50), provide reduced capacitance, and improve device performance. Exposing portions of the pins (66) and the substrate (50) allows larger source / drain regions to be formed, which provides improved device performance.

[0056] In the embodiment illustrated in FIG. 12d, the side surfaces of the first internal spacer portions (91A) and the second internal spacer portions (91B) are aligned with the side surfaces of the second nanostructures (54) of the n-type region (50N) and the first nanostructures (52) of the p-type region (50P). The side profiles of the internal spacers (91) can be changed by adjusting the etching processes used to form the internal spacers (91) (e.g., by performing the etching processes for a smaller amount of time). In embodiments where the side surfaces of the first internal spacer portion (91A) and the second internal spacer portion (91B) are aligned with the side surfaces of the second nanostructures (54) and the first nanostructures (52), the first internal spacer portion (91A) and the second internal spacer portion (91B) can come into contact with subsequently formed source / drain regions without air gaps formed horizontally between the internal spacers (91) and the source / drain regions.

[0057] In the embodiment illustrated in FIG. 12e, the internal spacers (91) are formed from four internal spacer layers (e.g., the first internal spacer portions (91A) are formed from the first internal spacer layer (90A) (illustrated in FIG. 11c), the second internal spacer portions (91B) are formed from the second internal spacer layer (90B), the third internal spacer portions (91C) are formed from the third internal spacer layer (90C), and the fourth internal spacer portions (91D) are formed from the fourth internal spacer layer (90D)). Forming the internal spacers (91) from a larger number of internal spacer layers allows layers formed with larger etching resistances (such as the first internal spacer layer (90A)) to be formed with smaller thicknesses, which can be used to reduce the effective dielectric constant of the internal spacers, reduce capacitance, and improve device performance. Providing a larger number of internal spacer layers provides greater flexibility in the shape and effective dielectric constant of the internal spacers (91).

[0058] The side surfaces of the first internal spacer portions (91A), the second internal spacer portions (91B), the third internal spacer portions (91C), and the fourth internal spacer portions (91D) may be at least partially recessed from the side surfaces of the second nanostructures (54) of the n-type region (50N) and the side surfaces of the first nanostructures (52) of the p-type region (50P), and may be aligned with the side surfaces of the second nanostructures (54) and the first nanostructures (52), similar to the embodiments illustrated and discussed in relation to FIGS. 12a through 12d. The first inner spacer portions (91A), the second inner spacer portions (91B), the third inner spacer portions (91C), and the fourth inner spacer portions (91D) may be continuous or discontinuous between the bottom portions of the first recesses (86) and the bottom portions of the bottom sidewall recesses (88), similar to the embodiments discussed above in relation to FIGS. 12a through 12c.

[0059] In the embodiment illustrated in FIG. 12f, the second internal spacer layer (90B) is completely removed, and the internal spacers (91) include the first internal spacer portions (91A). Removing the second internal spacer layer (90B) leaves additional space for air gaps to be sealed horizontally in the sidewall recesses (88) between the internal spacers (91) and the subsequently formed source / drain regions, and vertically in the bottom portion of the first recesses (86) between the internal spacers (91) and the source / drain regions. The air gaps have dielectric constants lower than those of the second internal spacer layer (90B). Thus, removing the second internal spacer layer (90B) lowers the effective dielectric constant of the internal spacers (91), reduces capacitance, and improves device performance.

[0060] In FIGS. 13a through 13i, epitaxial source / drain regions (92) are formed within the first recesses (86). The epitaxial source / drain regions (92) seal the side air gaps (94) (also referred to as side air spacers) of the sidewall recesses (88) (see FIG. 10b) horizontally between the epitaxial source / drain regions (92) and the internal spacers (91) adjacent to the first nanostructures (52) of the n-type region (50N) and the second nanostructures (54) of the p-type region (50P). Epitaxial source / drain regions (92) seal the bottom air gaps (96) (also referred to as bottom air spacers) vertically between the epitaxial source / drain regions (92) and the internal spacers (91) on the substrate (50) and pins (66) at the bottom portion of the first recesses (86) (see FIG. 10b). In some embodiments, the epitaxial source / drain regions (92) can improve performance by applying stress to the second nanostructures (54) of the n-type region (50N) and to the first nanostructures (52) of the p-type region (50P). As illustrated in FIG. 13b, the epitaxial source / drain regions (92) are formed in the first recesses (86) such that each dummy gate (76) is placed between each adjacent pair of epitaxial source / drain regions (92). In some embodiments, the first spacers (81) are used to separate the epitaxial source / drain regions (92) from the dummy gates (76), and the internal spacers (91) and lateral air gaps (94) are used to separate the epitaxial source / drain regions (92) from the nanostructures (55) by an appropriate lateral distance so that the epitaxial source / drain regions (92) do not short-circuit the subsequently formed gates of the resulting nanostructure FETs.Internal spacers (91) and bottom air gaps (96) are used to separate the epitaxial source / drain regions (92) from the substrate (50) and pins (66) by an appropriate vertical distance, thereby reducing leakage to the substrate (50) and pins (66), reducing capacitance, and improving device performance.

[0061] Epitaxial source / drain regions (92) of an n-type region (50N), e.g., an NMOS region, can be formed by masking a p-type region (50P), e.g., a PMOS region. Then, the epitaxial source / drain regions (92) are epitaxially grown in the first recesses (86) of the n-type region (50N). The epitaxial source / drain regions (92) may comprise any acceptable material suitable for forming the source / drain regions of n-type nanostructure FETs. For example, if the second nanostructures (54) are silicon, the epitaxial source / drain regions (92) may comprise materials that apply tensile strain to the second nanostructures (54), such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions (92) may have surfaces raised from each upper surface of the nanostructures (55) and may have facets.

[0062] Epitaxial source / drain regions (92) of a p-type region (50P), e.g., a PMOS region, can be formed by masking an n-type region (50N), e.g., an NMOS region. Then, the epitaxial source / drain regions (92) are epitaxially grown in the first recesses (86) of the p-type region (50P). The epitaxial source / drain regions (92) may comprise any acceptable material suitable for forming the source / drain regions of the p-type nanostructure FETs. For example, if the first nanostructures (52) are silicon germanium, the epitaxial source / drain regions (92) may comprise materials that apply compressive strain to the first nanostructures (52), such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions (92) may also have surfaces raised from each surface of the multilayer stacks (56) and may have facets.

[0063] The epitaxial source / drain regions (92), first nanostructures (52), second nanostructures (54) and / or the substrate (50) may be doped with dopants to form source / drain regions, which is followed by annealing similar to the process previously discussed to form low-concentration doped source / drain regions. The source / drain regions are approximately 1 x 10⁻⁶ 19 atoms / cm 3 to about 1x10 21 atoms / cm 3 The impurity concentration may be such that n-type and / or p-type impurities for the source / drain regions may be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions (92) may be in situ doped during growth.

[0064] As a result of the epitaxial source / drain regions (92) used to form the epitaxial source / drain regions (92) in the n-type region (50N) and the p-type region (50P), the upper surfaces of the epitaxial source / drain regions (92) have facets that extend laterally outward beyond the sidewalls of the nanostructures (55). In some embodiments, these facets allow adjacent epitaxial source / drain regions (92) of the same nanostructure FET to merge, as illustrated in FIG. 13a. In some embodiments, adjacent epitaxial source / drain regions (92) remain separated even after the epitaxial process is completed, as illustrated in FIG. 13c. In the embodiments illustrated in FIG. 13a and FIG. 13c, first spacers (81) are formed on the upper surface of the STI regions (68) to block epitaxial growth. In some embodiments, the first spacers (81) may cover portions of the sidewalls of the nanostructures (55) that further block epitaxial growth. In some embodiments, the spacer etching used to form the first spacers (81) may be adjusted to remove the spacer material so that the epitaxially grown region may extend to the surfaces of the STI region (68).

[0065] The epitaxial source / drain regions (92) may include one or more semiconductor material layers. For example, the epitaxial source / drain regions (92) may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers may be used in the epitaxial source / drain regions (92). Each of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer may be formed of different semiconductor materials and doped with different dopant concentrations. In some embodiments, the first semiconductor material layer may have a dopant concentration lower than that of the second semiconductor material layer and higher than that of the third semiconductor material layer. In embodiments where the epitaxial source / drain regions (92) include three semiconductor material layers, the first semiconductor material layer may be deposited, the second semiconductor material layer may be deposited on the first semiconductor material layer, and the third semiconductor material layer may be deposited on the second semiconductor material layer.

[0066] Epitaxial source / drain regions (92) are epitaxially grown from any exposed portions of the second nanostructure (54) of the n-type region (50N), the first nanostructures (52) of the p-type region (50P), and the substrate (50) and pins (66) of the n-type region (50N) and the p-type region (50P). The internal spacers (91) of the sidewall recesses (88) prevent the epitaxial source / drain regions (92) from being epitaxially grown from the first nanostructures (52) of the n-type region (50N) and the second nanostructures (54) of the p-type region (50P), so that side air gaps (94) are horizontally formed and sealed between the internal spacers (91) of the sidewall recesses (88) and the epitaxial source / drain regions (92). Side air gaps (94) are formed vertically between adjacent second nanostructures (54) in the n-type region (50N) and between the second nanostructures (54A) and the substrate (50) and pins (66), and vertically between adjacent first nanostructures (52) in the p-type region (50P). The first internal spacer portions (91A) of the sidewall recesses (88) protect the epitaxial source / drain regions (92) from subsequent etching processes, such as etching processes used to remove the first nanostructures (52) in the n-type region (50N) and the second nanostructures (54) in the p-type region (50P). This reduces device defects and improves device performance. The internal spacers (91) in the lower portions of the first recesses (86) prevent the epitaxial source / drain regions (92) from growing epitaxially from the pins (66) and the substrate (50) in the lower portions of the first recesses (86), so that the lower air gaps (96) are formed vertically between the internal spacers (91) and the epitaxial source / drain regions (92) in the lower portions of the first recesses (86) and are sealed. The dielectric constant of air is about 1, which is smaller than the dielectric constant of the materials typically used for internal spacers.In this way, including side air gaps (94) reduces the effective dielectric constant between the epitaxial source / drain regions (92) and the subsequently formed gate structures, reduces capacitance, and improves device performance. Additionally, the internal spacers (91) and bottom air gaps (96) have a low dielectric constant and provide isolation between the epitaxial source / drain regions (92) and the substrate (50) and pins (66), which reduces leakage to the substrate (50) and pins (66), reduces capacitance, and improves device performance (e.g., AC performance).

[0067] FIGS. 13a to 13c illustrate embodiments of FIGS. 12a and 12b, wherein first internal spacer portions (91A), second internal spacer portions (91B), and side air gaps (94) are formed in side wall recesses (88); first internal spacer portions (91A), second internal spacer portions (91B), and bottom air gaps (96) are formed in bottom portions of the first recesses (86); and the first internal spacer portions (91A) are continuous between the bottom portions of the first recesses (86) and the side wall recesses (88) in an n-type region (50N). As illustrated in FIG. 13b, the epitaxial source / drain regions (92) can be separated from the first internal spacer portions (91A) and the second internal spacer portions (91B) at the bottom portions of the first recesses (86), so that the side air gaps (94) are continuous with the bottom air gaps (96). FIG. 13d illustrates an embodiment of FIG. 12a and FIG. 12b, wherein the epitaxial source / drain regions (92) are formed to a greater depth and contact the first internal spacer portions (91A) at the bottom portions of the first recesses (86). The epitaxial source / drain regions (92) can be formed for a longer period than in the embodiment illustrated in FIG. 13a through FIG. 13c. Forming epitaxial source / drain regions (92) in contact with the first internal spacer portions (91A) at the lower portions of the first recesses (86) separates the side air gaps (94) from the lower air gaps (96).

[0068] FIG. 13e illustrates an embodiment of FIG. 12c, wherein first internal spacer portions (91A), second internal spacer portions (91B), and side air gaps (94) are formed in side wall recesses (88); first internal spacer portions (91A), second internal spacer portions (91B), and bottom air gaps (96) are formed in bottom portions of the first recesses (86); and the first internal spacer portions (91A) are discontinuous between the bottom portions of the first recesses (86) and the side wall recesses (88) in an n-type region (50N). As illustrated in FIG. 13e, the epitaxial source / drain regions (92) may be separated from the first internal spacer portions (91A) and the second internal spacer portions (91B) at the bottom portions of the first recesses (86), so that the side air gaps (94) are continuous with the bottom air gaps (96). FIG. 13f illustrates an embodiment of FIG. 12c, wherein the epitaxial source / drain regions (92) are formed to a greater depth and contact the first internal spacer portions (91A) and / or the second internal spacer portions (91B) at the bottom portions of the first recesses (86). The epitaxial source / drain regions (92) may be formed for a longer period than in the embodiment illustrated in FIG. 13e. Forming epitaxial source / drain regions (92) in contact with the first internal spacer portions (91A) and / or the second internal spacer portions (91B) at the lower portions of the first recesses (86) separates the side air gaps (94) from the lower air gaps (96).

[0069] FIG. 13g illustrates an embodiment of FIG. 12d, wherein the first internal spacer portions (91A) and the second internal spacer portions (91B) have side surfaces aligned with the nanostructures (55), and the first internal spacer portions (91A), the second internal spacer portions (91B), and the bottom air gaps (96) are formed in the bottom portions of the first recesses (86). As illustrated in FIG. 13g, the bottom air gaps (96) may extend adjacently to the portions of the internal spacers (91) adjacent to the first nanostructures (52A) in the n-type region (50N). In some embodiments, the epitaxial source / drain regions (92) may be formed to a greater depth so that the epitaxial source / drain regions (92) are in physical contact with the internal spacers (91) adjacent to the first nanostructures (52A) in the n-type region (50N). In the embodiment of FIG. 13g, the side air gaps (94) are omitted and only the bottom air gaps (96) are included.

[0070] FIG. 13h illustrates an embodiment of FIG. 12e, wherein the internal spacers (91) include first internal spacer portions (91A), second internal spacer portions (91B), third internal spacer portions (91C), and fourth internal spacer portions (91D). As illustrated in FIG. 13h, the first internal spacer portions (91A) may be in physical contact with the epitaxial source / drain regions (92), and the second internal spacer portions (91B), third internal spacer portions (91C), and fourth internal spacer portions (91D) may be separated from the epitaxial source / drain regions (92) by lateral air gaps (94). However, in some embodiments, any of the first inner spacer portions (91A), the second inner spacer portions (91B), the third inner spacer portions (91C), and the fourth inner spacer portions (91D) may be physically in contact with or separated from the epitaxial source / drain regions (92).

[0071] FIG. 13i illustrates an embodiment of FIG. 12f, wherein the second internal spacer layer (90B) is removed; the first internal spacer portions (91A) and side air gaps (94) are formed in the side wall recesses (88); the first internal spacer portions (91A) and bottom air gaps (96) are formed in the bottom portions of the first recesses (86); and the first internal spacer portions (91A) are continuous between the bottom portions of the first recesses (86) and the side wall recesses (88) in the n-type region (50N). As illustrated in FIG. 13i, epitaxial source / drain regions (92) may be separated from the first internal spacer regions (91A) and the second internal spacer regions (91B) at the bottom portions of the first recesses (86), so that the side air gaps (94) are continuous with the bottom air gaps (96). In some embodiments, the epitaxial source / drain regions (92) are formed to a deeper depth and contact the first internal spacer regions (91A) at the bottom portions of the first recesses (86). Forming the epitaxial source / drain regions (92) that contact the first internal spacer regions (91A) at the bottom portions of the first recesses (86) separates the side air gaps (94) from the bottom air gaps (96). Removing the second internal spacer layer (90B) expands the side air gaps (94) and bottom air gaps (96), further reducing the effective dielectric constants, reducing the capacitance, and improving the device performance.

[0072] In FIGS. 14a through 14c, a first interlayer dielectric (ILD) (102) is deposited on the structures illustrated in FIGS. 6a, FIG. 13b, and FIG. 13a, respectively (the processes of FIGS. 7a through 13i do not alter the cross-section illustrated in FIG. 6a). The first ILD (102) may be formed from a dielectric material and may be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) (100) is disposed between the first ILD (102) and the epitaxial source / drain regions (92), masks (78), and first spacers (81). The CESL (100) may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etching rate different from that of the material of the first ILD (102) placed above it.

[0073] In FIG. 15a and FIG. 15b, a flattening process such as CMP may be performed to level the upper surfaces of the first ILD (102) and CESL (100) with the upper surfaces of the dummy gates (76) or masks (78). The flattening process may also remove portions of the first spacers (81) along the sidewalls of the masks (78) and the masks (78) on the dummy gates (76). After the flattening process, the upper surfaces of the dummy gates (76), the first spacers (81), the ILDs (102), and the CESL (100) are at the same height as each other within the process variations. Thus, the upper surfaces of the dummy gates (76) are exposed through the first ILD (102) and CESL (100). In some embodiments, the masks (78) may remain, in which case the flattening process makes the upper surfaces of the masks (78) and the first spacers (81) and the upper surfaces of the first ILD (102) and CESL (100) the same height.

[0074] In FIG. 16a and FIG. 16b, dummy gates (76) and, if present, masks (78) are removed in one or more etching steps to form recesses (98). Parts of the dummy gate dielectrics (71) within the recesses (98) are also removed. In some embodiments, the dummy gates (76) and the dummy gate dielectrics (71) are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas(s) that selectively etches the dummy gates (76) at a faster rate than the first ILD (102), CESL (100), or first spacers (81). Each of the recesses (98) subsequently exposes and / or places over parts of the nanostructures (55) that serve as channel regions of the completed nanostructure FETs. Parts of the nanostructures (55) serving as channel regions are placed between neighboring pairs of epitaxial source / drain regions (92). During removal, when the dummy gates (76) are etched, the dummy gate dielectrics (71) can be used as etch stop layers. Then, the dummy gate dielectrics (71) can be removed after the removal of the dummy gates (76).

[0075] In FIG. 17a and FIG. 17b, the first nanostructures (52) of the n-type region (50N) and the second nanostructures (54) of the p-type region (50P) are removed to expand the recesses (98). The first nanostructures (52) can be removed by the steps of forming a mask (not otherwise illustrated) over the p-type region (50P) and performing an isotropic etching process, such as wet etching, using selective etchants on the materials of the first nanostructures (52), while the first internal spacer portions (91A), the second nanostructures (54), the substrate (50), the pins (66), the STI regions (68), the first ILD (102), the CESL (100), and the first spacers (81) remain relatively unetched compared to the first nanostructures (52). In embodiments where the first nanostructures (52) comprise, for example, SiGe and the second nanostructures (54A-54C) comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructures (52) in the n-type region (50N).

[0076] The second nanostructures (54) of the p-type region (50P) can be removed by the steps of forming a mask (not otherwise illustrated) over the n-type region (50N) and performing an isotropic etching process, such as wet etching, using selective etchants on the materials of the second nanostructures (54), while the first internal spacer portions (91A), the second nanostructures (52), the substrate (50), the pins (66), the STI regions (68), the first ILD (102), the CESL (100), and the first spacers (81) remain relatively unetched compared to the second nanostructures (54). In embodiments where the second nanostructures (54) include, for example, SiGe and the first nanostructures (52) include, for example, Si or SiC, hydrogen fluoride, other fluorine-based etchants, etc. may be used to remove the second nanostructures (54) from the p-type region (50P).

[0077] In other embodiments, the channel regions of the n-type region (50N) and the p-type region (50P) may be formed simultaneously, for example, by removing the first nanostructures (52) in both the n-type region (50N) and the p-type region (50P), or by removing the second nanostructures (54) in both the n-type region (50N) and the p-type region (50P). In such embodiments, the channel regions of the n-type nanostructure FETs and the p-type nanostructure FETs may have the same material composition, such as silicon, silicon germanium, etc. FIGS. 22a through 22c illustrate a structure produced from such embodiments in which the channel regions of both the p-type region (50P) and the n-type region (50N) are provided by the second nanostructures (54) and comprise silicon.

[0078] In FIG. 18a and FIG. 18b, gate dielectric layers (104) and gate electrodes (106) are formed for alternate gates. The gate dielectric layers (104) are conformally deposited in the recesses (98). In the n-type region (50N), the gate dielectric layers (104) may be formed on the upper surfaces of the STI regions (68); the upper surfaces and side surfaces of the pins (66); the upper surfaces, side surfaces, and lower surfaces of the second nanostructures (54); and the side surfaces of the internal spacers (91) and the first spacers (81). In the p-type region (50P), the gate dielectric layers (104) may be formed on the upper surfaces of the STI regions (68); the side surfaces of the pins (66); the upper surfaces, side surfaces, and lower surfaces of the first nanostructures (52); And it can be formed on the side surfaces of the inner spacers (91) and the first spacers (81). The gate dielectric layers (104) can be formed on the upper surfaces of the upper inner spacers (91) and may have a stepped structure. The gate dielectric layers (104) can also be formed on the upper surfaces of the first ILD (102), CESL (100), and the first spacers (81).

[0079] In some embodiments, the gate dielectric layers (104) comprise one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, the gate dielectric layers (104) may comprise a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layers (104) comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers (104) may have a k value greater than about 7.0 and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers (104) may be the same or different in the n-type region (50N) and the p-type region (50P). Methods for forming the gate dielectric layers (104) may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0080] Gate electrodes (106) are deposited on the gate dielectric layers (104) and fill the remaining portions of the recesses (98). The gate electrodes (106) may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, while single-layer gate electrodes (106) are illustrated in FIGS. 18a and 18b, the gate electrodes (106) may comprise any number of liner layers, any number of work function tuning layers, and a filling material. Any combination of layers constituting the gate electrodes (106) can be formed in the n-type region (50N) between adjacent second nanostructures (54) and between the second nanostructures (54A) and the pins (66), and can be formed in the p-type region (50P) between adjacent first nanostructures (52).

[0081] The formation of the gate dielectric layer (104) in the n-type region (50N) and the p-type region (50P) may occur simultaneously so that the gate dielectric layers (104) of each region are formed of the same materials, and the formation of the gate electrodes (106) may occur simultaneously so that the gate electrodes (106) of each region are formed of the same materials. In some embodiments, the gate dielectric layers (104) of each region may be formed by separate processes so that the gate dielectric layers (104) are made of different materials and / or have a different number of layers, and / or the gate electrodes (106) of each region may be formed by separate processes so that the gate electrodes (106) are made of different materials and / or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using separate processes.

[0082] After filling the recesses (98), a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer (104) and the material of the gate electrodes (106), the excess portions being on the upper surfaces of the first ILD (102), CESL (100), and the first spacers (81). Thus, the remaining portions of the material of the gate electrodes (106) and the gate dielectric layers (104) form alternative gate structures of the resulting nanostructure FETs. The gate electrodes (106) and the gate dielectric layers (104) may be collectively referred to as "gate structures".

[0083] In FIGS. 19a through 19c, gate structures (including gate dielectric layers (104) and corresponding gate electrodes (106) placed on top) are recessed so that recesses are formed immediately above each of the gate structures and between opposing portions of the first spacers (81). Gate caps (108) comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, etc. are filled into the recesses, and then a planarization process is performed to remove excess portions of dielectric material extending over the first ILD (102), CESL (100), and the first spacers (81). Subsequently formed gate contacts (e.g., gate contacts (118) discussed below in relation to FIGS. 21a and 21b) penetrate the gate caps (108) and contact the upper surfaces of the recessed gate electrodes (106).

[0084] Also, in FIGS. 19a to 19c, the second ILD (110) is formed on the first ILD (102), CESL (100), first spacers (81), and gate caps (108). In some embodiments, the second ILD (110) is a fluid film formed by FCVD. In some embodiments, the second ILD (110) is formed from a dielectric material such as PSG, BSG, BPSG, USG, etc. and can be formed by any suitable method such as CVD, PECVD, etc.

[0085] In FIG. 20a through 20c, the second ILD (110), the first ILD (102), the CESL (100), and the gate caps (108) are etched to form recesses (112) that expose the surfaces of the epitaxial source / drain regions (92) and / or the gate electrodes (106). The recesses (112) may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the recesses (112) may be etched through the second ILD (110) and the first ILD (102) using a first etching process; etched through the gate caps (108) using a second etching process; and etched through the CESL (100) using a third etching process. A mask, such as a photoresist, may be formed and patterned on the second ILD (110) to mask portions of the second ILD (110) from the first etching process and the second etching process. In some embodiments, the etching process may be over-etched, and thus the recesses (112) extend into the epitaxial source / drain regions (92) and / or gate electrodes (106). The lower surfaces of the recesses (112) may be equal to (e.g., at the same level or at the same distance from the substrate (50)) or lower than (e.g., closer to the substrate (50)) the upper surfaces of the epitaxial source / drain regions (92) and / or gate electrodes (106). Fig. 20b illustrates recesses (112) by exposing epitaxial source / drain regions (92) and gate electrodes (106) in the same cross section, but in some embodiments, the epitaxial source / drain regions (92) and gate electrodes (106) may be exposed in different cross sections, thus reducing the risk of subsequently formed contacts being short-circuited.

[0086] After the recesses (112) are formed, silicide regions (114) are formed on the epitaxial source / drain regions (92). In some embodiments, the silicide regions (114) are formed by a step of depositing a metal (not otherwise illustrated) capable of reacting with the semiconductor materials (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions (92) placed underneath to form the silicide or germanide regions. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal is deposited on the exposed portions of the epitaxial source / drain regions (92), and then a thermal annealing process is performed to form the silicide regions (114). Unreacted portions of the deposited metal are removed, for example, by an etching process. The silicide regions (114) are referred to as silicide regions, but the silicide regions (114) may also be germanide regions, or silicon germanide regions (e.g., regions containing silicide and germanide). In some embodiments, the silicide regions (114) comprise titanium silicide (TiSi) having a thickness in the range of about 2 nm to about 10 nm.

[0087] In FIGS. 21a through 21c, source / drain contacts (116) and gate contacts (118) (each of which may also be referred to as a contact plug) are formed in recesses (112). The source / drain contacts (116) and gate contacts (118) may each include one or more layers, such as barrier layers, diffusion layers, and filling materials. For example, in some embodiments, the source / drain contacts (116) and gate contacts (118) each include a barrier layer and a conductive material. The source / drain contacts (116) and gate contacts (118) are electrically coupled to underlying conductive features (e.g., gate electrodes (106) and silicide regions (114) in the illustrated embodiment). The gate contacts (118) are electrically coupled to the gate electrodes (106). Source / drain contacts (116) are electrically coupled to epitaxial source / drain regions (92) through a silicide region (114). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may include copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material of the source / drain contacts (116) and gate contacts (118) from the surfaces of the second ILD (110).

[0088] FIGS. 22a through 22c illustrate cross-sectional views of a device according to several alternative embodiments. In FIGS. 22a through 22c, the same reference numerals indicate similar elements formed by processes similar to those of the structures in FIGS. 21a through 21c. In the embodiments of FIGS. 22a through 22c, the channel regions of the n-type region (50N) and the p-type region (50P) comprise the same material. For example, second nanostructures (54) comprising silicon provide channel regions for p-type nanostructure FETs in the p-type region (50P) and n-type nanostructure FETs in the n-type region (50N). The structures of FIGS. 22a through 22c include, for example, the step of simultaneously removing the first nanostructures (52) in both the p-type region (50P) and the n-type region (50N);

[0089] It can be formed by the step of depositing gate dielectric layers (104) and gate electrodes (106P) (e.g., gate electrodes suitable for p-type nanostructure FETs) around the second nanostructures (54) of the p-type region (50P); and the step of depositing gate dielectric layers (104) and gate electrodes (106N) (e.g., gate electrodes suitable for n-type nanostructure FETs) around the second nanostructures (54) of the n-type region (50N). The materials of the epitaxial source / drain regions (92) may be different in the n-type region (50N) and the p-type region (50P) as described above.

[0090] The embodiments can obtain advantages. For example, including side air gaps (94) reduces the effective dielectric constant between the epitaxial source / drain regions (92) and the gate structures (including gate dielectric layers (104) and gate electrodes (106)), reduces capacitance, and improves device performance. Including bottom air gaps (96) and internal spacers (91) between the epitaxial source / drain regions and the substrate (50) improves the isolation of the epitaxial source / drain regions (92), reduces leakage, reduces capacitance, and improves device performance. Both the bottom air gaps (96) and the side air gaps (94) can contribute to improved AC performance.

[0091] According to an embodiment, the semiconductor device comprises: a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source / drain region adjacent to the gate structure and the first channel region; a first internal spacer layer between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate; and a first air gap between the first source / drain region and the first internal spacer layer in the first direction. In an embodiment, the semiconductor device further comprises a second internal spacer layer between the gate structure and the first source / drain region in a second direction parallel to the main surface of the semiconductor substrate; and a second air gap between the first source / drain region and the second internal spacer layer in the second direction. In an embodiment, the first air gap comprises air that is in physical contact with the surfaces of the first internal spacer layer and the first source / drain region. In an embodiment, the semiconductor device further comprises a second internal spacer layer between a first internal spacer layer and a first air gap in a first direction, wherein the first internal spacer layer comprises a first material, and the second internal spacer layer comprises a second material different from the first material. In an embodiment, the first source / drain region is in physical contact with the semiconductor substrate. In an embodiment, the first internal spacer layer is in physical contact with the gate structure. In an embodiment, the first air gap is between the first source / drain region and the gate structure in a second direction parallel to the main surface of the semiconductor substrate.

[0092] According to another embodiment, the semiconductor device comprises: a semiconductor substrate; a plurality of channel regions on the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate; a gate structure on the plurality of channel regions; a source / drain region adjacent to the gate structure; and a first spacer structure between the source / drain region and the semiconductor substrate, wherein the first spacer structure comprises: a first spacer layer comprising a first material; a second spacer layer on the first spacer layer comprising a second material different from the first material; and a bottom air gap between the second spacer layer and the source / drain region. In an embodiment, the semiconductor device further comprises an internal spacer structure between the source / drain region and the gate structure, wherein the internal spacer structure comprises: a first internal spacer layer comprising a first material; a second internal spacer layer on the first internal spacer layer comprising a second material; and a lateral air gap between the second internal spacer layer and the source / drain region. In an embodiment, the first spacer layer and the first internal spacer layer comprise a continuous material. In an embodiment, the semiconductor device further comprises an internal spacer structure between a source / drain region and a gate structure, wherein the internal spacer structure comprises: a first internal spacer layer comprising a first material; and a second internal spacer layer on the first internal spacer layer comprising a second material, and the side surfaces of the first internal spacer layer and the second internal spacer layer are aligned with the side surfaces of a plurality of channel regions. In an embodiment, the source / drain region is in physical contact with the first spacer layer. In an embodiment, the source / drain region is in physical contact with a semiconductor substrate. In an embodiment, the bottom air gap is in physical contact with the semiconductor substrate.

[0093] According to another embodiment, the method comprises the steps of: forming a gate structure on a first channel region; forming a first recess in a substrate adjacent to the gate structure; depositing a first spacer layer within the first recess; depositing a second spacer layer on the first spacer layer within the first recess; etching the first spacer layer and the second spacer layer using a first etching process to form a first internal spacer portion and a second internal spacer portion, respectively, within the first recess; and forming a source / drain region in the first recess — a bottom air gap surrounded by the source / drain region and the first internal spacer portion. In an embodiment, the first etching process etches the second spacer layer at a rate at least five times greater than the rate at which the first etching process etches the first spacer layer. In an embodiment, the first spacer layer comprises a first material, and the second spacer layer comprises a second material different from the first material. In an embodiment, the method further comprises the step of forming a multilayer stack on a substrate — the multilayer stack comprises alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material, a gate structure is formed on the multilayer stack, a first recess is formed through the multilayer stack and a plurality of nanostructures are formed from the multilayer stack — and the step of etching the sidewalls of the first semiconductor material to form sidewall recesses — the first spacer layer and the second spacer layer are deposited in the sidewall recesses and fill the sidewall recesses, and the step of etching the first spacer layer and the second spacer layer using a first etching process forms a third internal spacer portion and a fourth internal spacer portion, respectively, within the sidewall recesses —. In an embodiment, the first internal spacer portion and the third internal spacer portion are continuous. In an embodiment, the step of forming a source / drain region forms a side air gap within a sidewall recess that is surrounded by the source / drain region and a third internal spacer portion.

[0094] The foregoing describes the features of some embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should recognize that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present disclosure.

[0095] Examples

[0096] Example 1. In a semiconductor device,

[0097] semiconductor substrate;

[0098] A first channel region on the semiconductor substrate;

[0099] Gate structure on the first channel region above;

[0100] A first source / drain region adjacent to the gate structure and the first channel region;

[0101] A first internal spacer layer between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate; and

[0102] A first air gap between the first source / drain region and the first internal spacer layer in the first direction.

[0103] A semiconductor device including

[0104] Example 2. In Example 1,

[0105] A second internal spacer layer between the gate structure and the first source / drain region in a second direction parallel to the main surface of the semiconductor substrate; and

[0106] A second air gap between the first source / drain region and the second internal spacer layer in the second direction.

[0107] A semiconductor device further comprising

[0108] Example 3. In Example 1,

[0109] A semiconductor device wherein the first air gap comprises air that is in physical contact with the surfaces of the first internal spacer layer and the first source / drain region.

[0110] Example 4. In Example 1,

[0111] It further includes a second inner spacer layer between the first inner spacer layer and the first air gap in the first direction,

[0112] A semiconductor device wherein the first internal spacer layer comprises a first material, and the second internal spacer layer comprises a second material different from the first material.

[0113] Example 5. In Example 1,

[0114] A semiconductor device in which the first source / drain region is in physical contact with the semiconductor substrate.

[0115] Example 6. In Example 1,

[0116] A semiconductor device in which the first internal spacer layer is in physical contact with the gate structure.

[0117] Example 7. In Example 1,

[0118] A semiconductor device in which the first air gap is located between the first source / drain region and the gate structure in a second direction parallel to the main surface of the semiconductor substrate.

[0119] Example 8. In a semiconductor device,

[0120] semiconductor substrate;

[0121] A plurality of channel regions on the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate;

[0122] Gate structure on the plurality of channel regions above;

[0123] Source / drain regions adjacent to the gate structure; and

[0124] A first spacer structure between the source / drain region and the semiconductor substrate

[0125] Includes, and the first spacer structure is:

[0126] A first spacer layer comprising a first material;

[0127] A second spacer layer on the first spacer layer comprising a second material different from the first material; and

[0128] The lower air gap between the second spacer layer and the source / drain region

[0129] A semiconductor device comprising

[0130] Example 9. In Example 8,

[0131] The structure further includes an internal spacer structure between the source / drain region and the gate structure, wherein the internal spacer structure is:

[0132] A first internal spacer layer comprising the above-mentioned first material;

[0133] A second inner spacer layer on the first inner spacer layer comprising the second material; and

[0134] Side air gap between the second inner spacer layer and the source / drain region

[0135] A semiconductor device comprising

[0136] Example 10. In Example 9,

[0137] A semiconductor device wherein the first spacer layer and the first internal spacer layer comprise a continuous material.

[0138] Example 11. In Example 8,

[0139] The structure further includes an internal spacer structure between the source / drain region and the gate structure, wherein the internal spacer structure is:

[0140] A first internal spacer layer comprising the above-mentioned first material; and

[0141] A second inner spacer layer on the first inner spacer layer comprising the second material.

[0142] A semiconductor device comprising, wherein the side surfaces of the first internal spacer layer and the second internal spacer layer are aligned with the side surfaces of the plurality of channel regions.

[0143] Example 12. In Example 8,

[0144] A semiconductor device in which the source / drain region is in physical contact with the first spacer layer.

[0145] Example 13. In Example 8,

[0146] A semiconductor device in which the source / drain region is in physical contact with the semiconductor substrate.

[0147] Example 14. In Example 8,

[0148] A semiconductor device in which the lower air gap above is in physical contact with the semiconductor substrate.

[0149] Example 15. In the method,

[0150] A step of forming a gate structure on a first channel region;

[0151] A step of forming a first recess on a substrate adjacent to the gate structure;

[0152] A step of forming a first spacer layer within the first recess;

[0153] A step of forming a second spacer layer on the first spacer layer within the first recess;

[0154] A step of etching the first spacer layer and the second spacer layer using a first etching process to form a first internal spacer portion and a second internal spacer portion, respectively, within the first recess; and

[0155] Step of forming a source / drain region in the first recess — a lower air gap is surrounded by the source / drain region and the first internal spacer portion —

[0156] A method including

[0157] Example 16. In Example 15,

[0158] A method wherein the first etching process etches the second spacer layer at a rate at least five times greater than the rate at which the first etching process etches the first spacer layer.

[0159] Example 17. In Example 15,

[0160] A method in which the first spacer layer comprises a first material, and the second spacer layer comprises a second material different from the first material.

[0161] Example 18. In Example 15,

[0162] Step of forming a multilayer stack on a substrate ― said multilayer stack comprises alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material, said gate structure is formed on said multilayer stack, said first recess is formed penetrating said multilayer stack and forming a plurality of nanostructures from said multilayer stack ―; and

[0163] A step of etching the sidewalls of the first semiconductor material to form sidewall recesses — the first spacer layer and the second spacer layer are deposited in the sidewall recesses and fill the sidewall recesses, and the step of etching the first spacer layer and the second spacer layer using the first etching process forms a third internal spacer portion and a fourth internal spacer portion, respectively, within the sidewall recesses —

[0164] A method that further includes.

[0165] Example 19. In Example 18,

[0166] A method in which the first internal spacer portion and the third internal spacer portion are continuous.

[0167] Example 20. In Example 18,

[0168] A method in which the step of forming the source / drain region is to form a lateral air gap within the sidewall recess that is surrounded by the source / drain region and the third internal spacer portion.

Claims

Claim 1 A semiconductor device comprising: a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source / drain region adjacent to the gate structure and the first channel region; a first internal spacer layer between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate; a second internal spacer layer on the first internal spacer layer - wherein the first internal spacer layer comprises a first material and the second internal spacer layer comprises a second material different from the first material -; and a first air gap between the first source / drain region and the second internal spacer layer in the first direction, wherein the first air gap is between the first source / drain region and the gate structure in a second direction parallel to the main surface of the semiconductor substrate. Claim 2 A semiconductor device according to claim 1, further comprising: a third internal spacer layer between the gate structure and the first source / drain region in the second direction; and a second air gap between the first source / drain region and the third internal spacer layer in the second direction. Claim 3 A semiconductor device according to claim 1, wherein the first air gap comprises air that is in physical contact with the surfaces of the first internal spacer layer and the first source / drain region. Claim 4 delete Claim 5 A semiconductor device according to claim 1, wherein the first source / drain region is in physical contact with the semiconductor substrate. Claim 6 A semiconductor device according to claim 1, wherein the first internal spacer layer is in physical contact with the gate structure. Claim 7 delete Claim 8 A semiconductor device comprising: a semiconductor substrate; a plurality of channel regions on the semiconductor substrate in a first direction perpendicular to a main surface of the semiconductor substrate; a gate structure on the plurality of channel regions; a source / drain region adjacent to the gate structure; and a first spacer structure between the source / drain region and the semiconductor substrate, wherein the first spacer structure comprises: a first spacer layer comprising a first material; a second spacer layer on the first spacer layer comprising a second material different from the first material; and a bottom air gap between the second spacer layer and the source / drain region. Claim 9 A semiconductor device according to claim 8, further comprising an internal spacer structure between the source / drain region and the gate structure, wherein the internal spacer structure comprises: a first internal spacer layer comprising the first material; a second internal spacer layer on the first internal spacer layer comprising the second material; and a lateral air gap between the second internal spacer layer and the source / drain region. Claim 10 A method comprising: forming a gate structure on a first channel region; forming a first recess in a substrate adjacent to the gate structure; depositing a first spacer layer within the first recess; depositing a second spacer layer on the first spacer layer within the first recess; etching the first spacer layer and the second spacer layer using a first etching process to form a first internal spacer portion and a second internal spacer portion, respectively, within the first recess; and forming a source / drain region in the first recess, wherein a bottom air gap is surrounded by the source / drain region and the first internal spacer portion.

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