Transistor gate structures and methods of forming thereof

Abstract

The device comprises a semiconductor substrate; a set of nanostructures vertically stacked on the semiconductor substrate; a first source / drain region; and a second source / drain region, wherein the set of nanostructures vertically stacked extends between the first source / drain region and the second source / drain region along a first cross-section. The device further comprises a gate structure surrounding the set of nanostructures vertically stacked along a second cross-section. The second cross-section is along the longitudinal axis of the gate structure. The gate structure comprises a gate dielectric surrounding each nanostructure of the set of nanostructures vertically stacked; a first metal carbide layer on the gate dielectric; and a gate filler material on the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo.

Description

Technology Field

[0001] Priority and Cross-reference

[0002] This application claims the benefit of U.S. provisional application No. 63 / 362,053 filed on March 29, 2022, which is incorporated herein by reference. Background Technology

[0003] Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and by patterning the various material layers using lithography to form circuit components and elements thereon.

[0004] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by enabling more components to be integrated into a given area through the continuous reduction of the minimum feature size. However, as the minimum feature size decreases, additional problems arise that need to be solved. [Patent Document 1] : U.S. Patent Application Publication US2021 / 0183707 Brief explanation of the drawing

[0005] The embodiments of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to a constant scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of discussion. FIG. 1 illustrates an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6a, Fig. 6b, Fig. 7a, Fig. 7b, Fig. 8a, Fig. 8b, Fig. 9a, Fig. 9b, Fig. 10a, Fig. 10b, Fig. 11a, Fig. 11b, Fig. 11c, Fig. 12a, Fig. 12b, Fig. 12c, Fig. 12d, Fig. 13a, Fig. 13b, Fig. 13c, Fig. 14a, Fig. 14b, Fig. 15a, Fig. 15b, Fig. 16a, Fig. 16b, Fig. 17a, Fig. 17b, Fig. 17c, Fig. 18a, Fig. 18b, Fig. 19a, Fig. 19b, Fig. 19c, Fig. 19d, Fig. 20a, Fig. 20b, Fig. 20c, Fig. 20d, Fig. FIGS. 21a, FIGS. 21b, FIGS. 21c, FIGS. 21d, FIGS. 22a, FIGS. 22b, FIGS. 22c, FIGS. 23a, FIGS. 23b, FIGS. 23c, FIGS. 24a, FIGS. 24b, and FIGS. 24c are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. FIGS. 25a, FIGS. 25b, and FIGS. 25c are cross-sectional views of a nano-FET according to some embodiments. FIGS. 26a, FIGS. 26b, and FIGS. 26c are cross-sectional views of a nano-FET according to some embodiments. FIGS. 27a, FIGS. 27b, and FIG. 27c are cross-sectional views of a nano-FET according to some embodiments. FIGS. 28a, FIG. 28b, and FIG. 28c are cross-sectional views of a nano-FET according to some embodiments. FIG. 29 is a cross-sectional view of a nano-FET according to some embodiments. Specific details for implementing the invention

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not affect the relationships between the various embodiments and / or configurations discussed in themselves.

[0007] Furthermore, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this specification for convenience of explanation to describe the relationship between one element or feature and another element(s) or feature(s), as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientations depicted in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other orientations), and spatially relative terms used in this specification may likewise be interpreted accordingly.

[0008] Various embodiments in this specification include a gate structure having a work function metal layer comprising a metal carbide. For example, the metal carbide is Ce 1-y C y , Hf 1-y C y , V 1-y C y, Nb 1-y C y , Sc 1-y C y , Y 1-y C y , Hf 1-y C y , or Mo 1-y C y It may include, where y is a number satisfying 0 < y < 1. In some embodiments, the metal carbide layer may be used only as the work function metal in the gate structure. In some embodiments, the metal carbide layer may be used in combination with one or more other work function metals (e.g., one or more metal nitride layers and / or metal carbide layers) to provide multiple work function metal layers in the gate structure. As a result of using different metal carbides as work function metals, work function tuning can be achieved more precisely.

[0009] The embodiments are described below in a specific context of a die containing nano-FETs. However, various embodiments may be applied to dies containing other types of transistors (e.g., FinFETs, planar transistors, etc.) instead of or in combination with nano-FETs.

[0010] FIG. 1 illustrates, in a three-dimensional view, examples of nano-FETs (e.g., nanowire FETs, nanosheet FETs (nano-FETs) etc.) according to some embodiments. The nano-FETs comprise nanostructures (55) (e.g., nanosheets, nanowires, etc.) on fins (66) on a substrate (50) (e.g., a semiconductor substrate), wherein the nanostructures (55) act as channel regions for the nano-FETs. The nanostructures (55) may comprise p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions (68) are disposed between adjacent fins (66), and these fins (66) may protrude upward from between adjacent isolation regions (68). Although the isolation regions (68) are described / exemplified as being separated from the substrate (50), as used herein, the term “substrate” may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and isolation regions. Additionally, although the bottom portion of the pins (66) is exemplified as being a single continuous material with the substrate (50), the bottom portion of the pins (66) and / or the substrate (50) may comprise a single material or multiple materials. In this context, the pins (66) refer to a portion extending between adjacent isolation regions (68).

[0011] Gate dielectric layers (100) are located on the upper surfaces of the pins (66) and along the upper surfaces, sidewalls, and lower surfaces of the nanostructures (55). Gate electrodes (102) are located on the gate dielectric layers (100). Epitaxial source / drain regions (92) are placed on the pins (66) on both sides of the gate dielectric layers (100) and the gate electrodes (102).

[0012] FIG. 1 further illustrates reference cross-sections used in subsequent drawings. Cross-section (A-A') follows the longitudinal axis of the gate electrode (102) in a direction perpendicular to the direction of current flow between the epitaxial source / drain regions (92) of the nano-FET, for example. Cross-section (B-B') is perpendicular to cross-section (A-A') and parallel to the longitudinal axis of the fin (66) of the nano-FET in the direction of current flow between the epitaxial source / drain regions (92) of the nano-FET, for example. Cross-section (C-C') is parallel to cross-section (A-A') and extends through the epitaxial source / drain regions of the nano-FETs. Subsequent drawings refer to these reference cross-sections for clarity.

[0013] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments consider aspects used in planar devices, such as planar FETs, or in FinFETs.

[0014] FIGS. 2 to 24c are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. FIGS. 2 to 5, FIG. 6a, FIG. 13a, FIG. 14a, FIG. 15a, FIG. 16a, FIG. 17a, FIG. 18a, FIG. 19a, FIG. 19c, FIG. 19d, FIG. 20a, FIG. 21a, FIG. 21c, FIG. 21d, FIG. 22a, FIG. 23a, and FIG. 24a illustrate the reference cross-section (A-A') illustrated in FIG. 1. FIGS. 6b, FIGS. 7b, FIGS. 8b, FIGS. 9b, FIGS. 10b, FIGS. 11b, FIGS. 11c, FIGS. 12b, FIGS. 12d, FIGS. 13b, FIGS. 14b, FIGS. 15b, FIGS. 16b, FIGS. 17b, FIGS. 17c, FIGS. 18b, FIGS. 19b, FIGS. 20b, FIGS. 21b, FIGS. 22b, FIGS. 23b, and FIGS. 24b illustrate the reference cross section (B-B') illustrated in FIGS. 1. FIGS. 7a, FIGS. 8a, FIGS. 9a, FIGS. 10a, FIGS. 11a, FIGS. 12a, FIGS. 12c, FIGS. 13c, FIGS. 22c, FIGS. 23c, and FIGS. 24c illustrate the reference cross section (C-C') illustrated in FIGS. 1.

[0015] In FIG. 2, a substrate (50) is provided. The substrate (50) may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or may not be doped. The substrate (50) may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate (50) is silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; It may include silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or a combination thereof.

[0016] The substrate (50) has an n-type region (50N) and a p-type region (50P). The n-type region (50N) may be for forming n-type devices, such as NMOS transistors, for example, n-type nano-FETs, and the p-type region (50P) may be for forming p-type devices, such as PMOS transistors, for example, p-type nano-FETs. The n-type region (50N) may be physically separated from the p-type region (50P) (as exemplified by the divider (20)), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be placed between the n-type region (50N) and the p-type region (50P). Although one n-type region (50N) and one p-type region (50P) are exemplified, any number of n-type regions (50N) and p-type regions (50P) may be provided.

[0017] In addition, in FIG. 2, a multilayer stack (64) is formed on the substrate (50). The multilayer stack (64) comprises alternating layers of first semiconductor layers (51A to 51C) (collectively referred to as the first semiconductor layers (51)) and second semiconductor layers (53A to 53C) (collectively referred to as the second semiconductor layers (53)). For example, and as discussed in more detail below, the second semiconductor layers (53) will be removed and the first semiconductor layers (51) will be patterned to form channel regions of nano-FETs in the p-type region (50P). Also, the first semiconductor layers (51) will be removed and the second semiconductor layers (53) will be patterned to form channel regions of nano-FETs in the n-type region (50N). Nevertheless, in some embodiments, the first semiconductor layers (51) may be removed and the second semiconductor layers (53) may be patterned to form channel regions of nano-FETs in the p-type region (50P), and the second semiconductor layers (53) may be removed and the first semiconductor layers (51) may be patterned to form channel regions of nano-FETs in the n-type region (50N).

[0018] In other embodiments, the first semiconductor layers (51) may be removed, and the second semiconductor layers (53) may be patterned to form channel regions of nano-FETs in both the n-type region (50N) and the p-type region (50P). In other embodiments, the second semiconductor layers (53) may be removed, and the first semiconductor layers (51) may be patterned to form channel regions of nano-FETs in both the n-type region (50N) and the p-type region (50P). In such embodiments, the channel regions in both the n-type region (50N) and the p-type region (50P) may have the same material composition (e.g., silicon or other semiconductor material) and may be formed simultaneously. FIGS. 25a, 25b, and 25c illustrate a structure resulting from such embodiments in which, for example, the channel regions in both the p-type region (50P) and the n-type region (50N) comprise silicon.

[0019] The multilayer stack (64) is illustrated for illustrative purposes as comprising three layers each of the first semiconductor layers (51) and the second semiconductor layers (53). In some embodiments, the multilayer stack (64) may comprise any number of first semiconductor layers (51) and second semiconductor layers (53). Each of the layers of the multilayer stack (64) may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layers (51) may be formed from a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, etc., and the second semiconductor layers (53) may be formed from a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, etc. The multilayer stack (64) is illustrated for illustrative purposes as having a bottom semiconductor layer suitable for p-type nano-FETs. In some embodiments, the multilayer stack (64) may be formed such that the bottom layer is a semiconductor layer suitable for n-type nano-FETs.

[0020] The first semiconductor materials and the second semiconductor materials may be materials having high etching selectivity toward each other. Accordingly, the first semiconductor layers (51) of the first semiconductor material can be removed without significantly removing the second semiconductor layers (53) of the second semiconductor material in the n-type region (50N), thereby allowing the second semiconductor layers (53) to be patterned to form channel regions of n-type nano-FETs. Similarly, the second semiconductor layers (53) of the second semiconductor material can be removed without significantly removing the first semiconductor layers (51) of the first semiconductor material in the p-type region (50P), thereby allowing the first semiconductor layers (51) to be patterned to form channel regions of p-type nano-FETs.

[0021] Now, referring to FIG. 3, according to some embodiments, pins (66) are formed on the substrate (50) and nanostructures (55) are formed on the multilayer stack (64). In some embodiments, the nanostructures (55) and pins (66) may be formed on the multilayer stack (64) and the substrate (50), respectively, by etching trenches in the multilayer stack (64) and the substrate (50). The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etch (NBE), etc., or a combination thereof. The etching may be anisotropic. Forming nanostructures (55) by etching the multilayer stack (64) may additionally define first nanostructures (52A to 52C) (collectively referred to as first nanostructures (52)) from the first semiconductor layers (51) and second nanostructures (54A to 54C) (collectively referred to as second nanostructures (54)) from the second semiconductor layers (53). The first nanostructures (52) and the second nanostructures (54) may additionally be collectively referred to as nanostructures (55).

[0022] The pins (66) and nanostructures (55) can be patterned by any suitable method. For example, the pins (66) and nanostructures (55) can be patterned using one or more photolithography processes, including a double-patterning process or a multi-patterning process. Generally, a double-patterning process or a multi-patterning process combines a photolithography process and a self-aligning process to enable the creation of patterns having smaller pitches than can be obtained, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Using a self-aligning process, spacers are formed alongside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the pins (66).

[0023] FIG. 3 illustrates, for illustrative purposes, that the pins (66) in the n-type region (50N) and the p-type region (50P) have substantially the same width. In some embodiments, the widths of the pins (66) in the n-type region (50N) may be larger or thinner than those of the pins (66) in the p-type region (50P). Furthermore, although the pins (66) and the nanostructures (55) are each illustrated as having a consistent width throughout, in other embodiments, the pins (66) and / or nanostructures (55) may have tapered sidewalls so that the width of each pin (66) and / or nanostructure (55) increases continuously in the direction toward the substrate (50). In such embodiments, each nanostructure (55) may have a different width and may be trapezoidal in shape.

[0024] In FIG. 4, shallow trench isolation (STI) regions (68) are formed adjacent to the pins (66). The STI regions (68) can be formed by depositing an insulating material on the substrate (50), the pins (66), and the nanostructures (55) and between the adjacent pins (66). The insulating material may be an oxide, such as silicon oxide, a nitride, etc., or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by the FCVD process. Once the insulating material is formed, an annealing process may be performed. In the embodiment, the insulating material is formed such that the excess insulating material covers the nanostructures (55). Although the insulating material is exemplified as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately exemplified) may first be formed along the surface of the substrate (50), pins (66), and nanostructures (55). Then, a filling material, as discussed above, may be formed on the liner.

[0025] A removal process is subsequently applied to the insulating material to remove excess insulating material on the nanostructures (55). In some embodiments, a flattening process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof may be utilized. After the flattening process is completed, the flattening process exposes the nanostructures (55) so that the upper surfaces of the nanostructures (55) and the insulating material are level.

[0026] The insulating material is subsequently recessed to form STI regions (68). The insulating material is recessed so that the upper portions of the pins (66) in the n-type region (50N) and the p-type region (50P) protrude from between the adjacent STI regions (68). Furthermore, the upper surfaces of the STI regions (68) may have a flat surface, a convex surface, a concave surface (such as dishing), or a combination thereof as illustrated. The upper surfaces of the STI regions (68) may be formed flat, convex, and / or concave by appropriate etching. The STI regions (68) may be recessed using an acceptable etching process, such as an etching process that is selective with respect to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the pins (66) and nanostructures (55). For example, oxide removal using dilute hydrogen fluoride (dHF) acid can be used.

[0027] The process described above in relation to FIGS. 2 through 4 is merely one example of how the pins (66) and nanostructures (55) can be formed. In some embodiments, the pins (66) and / or nanostructures (55) may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed on the upper surface of the substrate (50), and trenches may be etched through the dielectric layer to expose the substrate (50) placed underneath. Epitaxial structures may be grown epitaxially within the trenches, and the dielectric layer may be recessed so that the epitaxial structures protrude from the dielectric layer to form the pins (66) and / or nanostructures (55). The epitaxial structures may include the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth, which may eliminate prior injection and / or subsequent injection, but in situ doping and injection doping may be used together.

[0028] Additionally, the first semiconductor layers (51) (and resulting nanostructures (52)) and the second semiconductor layers (53) (and resulting nanostructures (54)) are illustrated and discussed herein only for illustrative purposes as comprising the same materials in the p-type region (50P) and the n-type region (50N). Accordingly, in some embodiments, one or both of the first semiconductor layers (51) and the second semiconductor layers (53) may be different materials or formed in a different order in the p-type region (50P) and the n-type region (50N).

[0029] In addition, in FIG. 4, suitable wells (not separately illustrated) may be formed on the pins (66), nanostructures (55), and / or STI regions (68). In embodiments having different well types, different injection steps for the n-type region (50N) and p-type region (50P) may be achieved using photoresist or other masks (not separately illustrated). For example, photoresist may be formed on the pins (66) and STI regions (68) in the n-type region (50N) and p-type region (50P). The photoresist is patterned to expose the p-type region (50P). The photoresist may be formed using spin-on technology and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region (50P), and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region (50N). The n-type impurities are about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 It may be phosphorus, arsenic, antimony, etc. injected into the area at a concentration within the range. After injection, the photoresist is removed, for example, by an acceptable ashing process.

[0030] After or before the injection of the p-type region (50P), a photoresist or other masks (not separately illustrated) are formed over the pins (66), nanostructures (55), and STI regions (68) in the p-type region (50P) and the n-type region (50N). The photoresist is patterned to expose the n-type region (50N). The photoresist can be formed using spin-on technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity injection can be performed in the n-type region (50N), and the photoresist can act as a mask to substantially prevent p-type impurities from being injected into the p-type region (50P). The p-type impurities are about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 It may be boron, boron fluoride, indium, etc. injected into the area at a concentration within the range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0031] After the injection of the n-type region (50N) and the p-type region (50P), annealing may be performed to repair implant damage and to activate the injected p-type impurities and / or n-type impurities. In some embodiments, the grown materials of the epitaxial pins may be doped in-situ during growth, which may remove the implant, but in-situ doping and implant doping may be used together.

[0032] In FIG. 5, a dummy dielectric layer (70) is formed on the pins (66) and nanostructures (55). The dummy dielectric layer (70) may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer (72) is formed on the dummy dielectric layer (70), and a mask layer (74) is formed on the dummy gate layer (72). The dummy gate layer (72) may be deposited on the dummy dielectric layer (70) and then flattened, for example, by CMP. The mask layer (74) may be deposited on the dummy gate layer (72). The dummy gate layer (72) may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer (72) may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer (72) may be made of other materials having high etch selectivity from the etching of isolation regions. The mask layer (74) may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer (72) and a single mask layer (74) are formed across the n-type region (50N) and the p-type region (50P). Note that the dummy dielectric layer (70) is shown covering only the pins (66) and nanostructures (55) for illustrative purposes only. In some embodiments, the dummy dielectric layer (70) may be deposited so that the dummy dielectric layer (70) extends between the dummy gate layer (72) and the STI regions (68), and the dummy dielectric layer (70) covers the STI regions (68).

[0033] FIGS. 6a through 24c illustrate various additional steps in the fabrication of the embodiment devices. FIGS. 6a, FIGS. 7a, FIGS. 8a, FIGS. 9a, FIGS. 10a, FIGS. 11a, FIGS. 12a, FIGS. 12c, FIGS. 13a, FIGS. 13c, FIGS. 14a, FIGS. 15a, FIGS. 22c, FIGS. 23c, and FIGS. 24c illustrate features in any one of the regions (50N) or regions (50P). In FIGS. 6a and 6b, the mask layer (74) (see FIG. 5) may be patterned using photolithography and etching techniques that allow to form masks (78). The pattern of the masks (78) may then be transferred to a dummy gate layer (72) and a dummy dielectric layer (70) to form dummy gates (76) and dummy gate dielectrics (71), respectively. Dummy gates (76) cover the respective channel regions of the pins (66). The pattern of the masks (78) can be used to physically separate each dummy gate (76) from adjacent dummy gates (76). The dummy gates (76) may also have a lengthwise direction substantially perpendicular to the lengthwise direction of each pin (66).

[0034] In FIGS. 7a and 7b, the first spacer layer (80) and the second spacer layer (82) are formed respectively on the structures illustrated in FIGS. 6a and 6b. The first spacer layer (80) and the second spacer layer (82) will subsequently be patterned to act as spacers for forming self-aligned source / drain regions. In FIGS. 7a and 7b, the first spacer layer (80) is formed on the upper surfaces of the STI regions (68); the upper surfaces and sidewalls of the pins (66), nanostructures (55), and masks (78); and the sidewalls of the dummy gates (76) and dummy gate dielectrics (71). The second spacer layer (82) is deposited on the first spacer layer (80). The first spacer layer (80) can be formed using techniques such as thermal oxidation, silicon oxide, silicon nitride, silicon oxynitride, etc., or can be deposited by CVD, ALD, etc. The second spacer layer (82) can be formed from a material having an etching rate different from that of the first spacer layer (80), such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0035] After the first spacer layer (80) is formed and before the second spacer layer (82) is formed, injections may be performed on low-concentration doped source / drain (LDD) regions (not otherwise exemplified). In embodiments having different device types, similar to the injections discussed above in FIG. 4, a mask, such as a photoresist, may be formed over an n-type region (50N) while exposing a p-type region (50P), and appropriate types of (e.g., p-type) impurities may be injected into the exposed pins (66) and nanostructures (55) in the p-type region (50P). The mask may then be removed. Subsequently, a mask, such as a photoresist, can be formed over a p-type region (50P) while exposing an n-type region (50N), and appropriate types of impurities (e.g., n-type) can be injected into the exposed pins (66) and nanostructures (55) in the n-type region (50N). The mask can then be removed. The n-type impurities may be any of the previously discussed n-type impurities, and the p-type impurities may be any of the previously discussed p-type impurities. Low-concentration doped source / drain regions are approximately 1 x 10⁻⁶ 15 atoms / cm 3 to about 1x10 19 atoms / cm 3 It can have an impurity concentration in the range of. Annealing can be used to repair injection damage and to activate injected impurities.

[0036] In FIG. 8a and FIG. 8b, the first spacer layer (80) and the second spacer layer (82) are etched to form the first spacers (81) and the second spacers (83). As will be discussed in more detail below, the first spacers (81) and the second spacers (83) serve to self-align the source-drain regions subsequently formed, as well as to protect the sidewalls of the pins (66) and / or nanostructures (55) during subsequent processing. The first spacer layer (80) and the second spacer layer (82) may be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), an anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer (82) has a different etching rate from the material of the first spacer layer (80) so that the first spacer layer (80) can act as an etching stop layer when patterning the second spacer layer (82) and the second spacer layer (82) can act as a mask when patterning the first spacer layer (80). For example, the second spacer layer (82) can be etched using an anisotropic etching process, wherein the first spacer layer (80) acts as an etching stop layer, and the remaining portion of the second spacer layer (82) forms the second spacers (83) as illustrated in FIG. 8a. After that, the second spacers (83) act as a mask while etching the exposed portions of the first spacer layer (80), thereby forming the first spacers (81) as illustrated in FIG. 8a.

[0037] As illustrated in FIG. 8a, the first spacers (81) and the second spacers (83) are disposed on the sidewalls of the pins (66) and / or nanostructures (55). As illustrated in FIG. 8b, in some embodiments, the second spacer layer (82) may be removed from the first spacer layer (80) adjacent to the masks (78), dummy gates (76), and dummy gate dielectrics (71), and the first spacers (81) are disposed on the sidewalls of the masks (78), dummy gates (76), and dummy gate dielectrics (71). In other embodiments, a portion of the second spacer layer (82) may remain on the first spacer layer (80) adjacent to the masks (78), dummy gates (76), and dummy gate dielectrics (71).

[0038] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different step sequences may be utilized (e.g., the first spacers (81) may be patterned before depositing the second spacer layer (82)), additional spacers may be formed and removed, etc. Furthermore, n-type devices and p-type devices may be formed using different structures and steps.

[0039] In FIG. 9a and 9b, according to some embodiments, first recesses (86) are formed in pins (66), nanostructures (55), and substrates (50). Epitaxial source / drain regions will subsequently be formed in the first recesses (86). The first recesses (86) may extend into the substrate (50) through the first nanostructures (52) and the second nanostructures (54). As illustrated in FIG. 9a, the upper surfaces of the STI regions (68) may be at the same height as the lower surfaces of the first recesses (86). In various embodiments, the pins (66) may be etched so that the lower surfaces of the first recesses (86) are positioned below the upper surfaces of the STI regions (68). The first recesses (86) can be formed by etching the pins (55), nanostructures (55), and substrate (50) using anisotropic etching processes such as RIE, NBE, etc. The first spacers (81), second spacers (83), and masks (78) mask portions of the pins (55), nanostructures (55), and substrate (50) during the etching processes used to form the first recesses (86). A single etching process or multiple etching processes may be used to etch each layer of the nanostructures (55) and / or pins (66). Timed etching processes may be used to stop the etching of the first recesses (86) after the first recesses (86) have reached a desired depth.

[0040] In FIG. 10a and FIG. 10b, portions of the sidewalls of the layers of a multilayer stack (64) formed of first semiconductor materials (e.g., first nanostructures (52)) exposed by the first recesses (86) are etched to form sidewall recesses (88) in an n-type region (50N), and portions of the sidewalls of the layers of a multilayer stack (64) formed of second semiconductor materials (e.g., second nanostructures (54)) exposed by the first recesses (86) are etched to form sidewall recesses (88) in a p-type region (50P). Although the sidewalls of the first nanostructures (52) and the second nanostructures (54) in the sidewall recesses (88) are illustrated as straight in FIG. 10b, the sidewalls may be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching. While etchants selectively applied to the first semiconductor materials are used to etch the first nanostructures (52) so that the second nanostructures (54) and the substrate (50) remain relatively unetched compared to the first nanostructures (52) in the n-type region (50N), the p-type region (50P) can be protected using a mask (not shown). Similarly, while etchants selectively applied to the second semiconductor materials are used to etch the second nanostructures (54) so ​​that the first nanostructures (52) and the substrate (50) remain relatively unetched compared to the second nanostructures (54) in the p-type region (50P), the n-type region (50N) can be protected using a mask (not shown).In an embodiment where the first nanostructures (52) comprise, for example, SiGe and the second nanostructures (54) comprise, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewalls of the first nanostructures (52) in the n-type region (50N), and a wet or dry etching process using hydrogen fluoride, other fluorine-based etchants, etc., can be used to etch the sidewalls of the second nanostructures (54) in the p-type region (50P).

[0041] In FIGS. 11a through 11c, the first internal spacers (90) are formed in the sidewall recesses (88). The first internal spacers (90) may be formed by depositing an internal spacer layer (not separately illustrated) on the structures illustrated in FIGS. 10a and 10b. The first internal spacers (90) serve as isolation features between the source / drain regions and the gate structure that are subsequently formed. As will be discussed in more detail below, the source / drain regions will be formed in the recesses (86), while the first nanostructures (52) in the n-type region (50N) and the second nanostructures (54) in the p-type region (50P) will be replaced by the corresponding gate structures.

[0042] The internal spacer layer can be deposited by a conformal deposition process such as CVD, ALD, etc. The internal spacer layer may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as low dielectric constant (low-k) materials having a k value of less than about 3.5. The internal spacer layer can then be anisotropically etched to form first internal spacers (90). However, although the outer sidewalls of the first inner spacers (90) are illustrated as being flush with the sidewalls of the second nanostructures (54) in the n-type region (50N) and flush with the sidewalls of the first nanostructures (52) in the p-type region (50P), the outer sidewalls of the first inner spacers (90) may each extend beyond or be recessed from the sidewalls of the second nanostructures (54) and / or the first nanostructures (52).

[0043] Furthermore, although the outer sidewalls of the first inner spacers (90) are illustrated as straight in FIG. 11b, the outer sidewalls of the first inner spacers (90) may be concave or convex. For example, FIG. 11c illustrates an embodiment in which the sidewalls of the first nanostructures (52) are concave, the outer sidewalls of the first inner spacers (90) are concave, and the first inner spacers (90) are recessed from the sidewalls of the second nanostructures (54) in the n-type region (50N). Also illustrated are embodiments in which the sidewalls of the second nanostructures (54) are concave, the outer sidewalls of the first inner spacers (90) are concave, and the first inner spacers (90) are recessed from the sidewalls of the first nanostructures (52) in the p-type region (50P). The internal spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first internal spacers (90) can be used to prevent damage to source / drain regions (e.g., epitaxial source / drain regions (92) discussed below in relation to FIGS. 12a to 12c) subsequently formed by subsequent etching processes, such as etching processes used to form gate structures.

[0044] In FIGS. 12a through 12c, epitaxial source / drain regions (92) are formed in the first recesses (86). In some embodiments, the source / drain regions (92) can apply stress to the second nanostructures (54) in the n-type region (50N) and to the first nanostructures (52) in the p-type region (50P), thereby improving performance. As illustrated in FIG. 12b, the epitaxial source / drain regions (92) are formed in the first recesses (86) such that each dummy gate (76) is positioned between their respective adjacent pairs of epitaxial source / drain regions (92). In some embodiments, so that the epitaxial source / drain regions (92) do not short out with the subsequently formed gates of the resulting nano-FETs, the first spacers (81) are used to separate the epitaxial source / drain regions (92) from the dummy gates (76), and the first internal spacers (90) are used to separate the epitaxial source / drain regions (92) from the nanostructures (55) by an appropriate lateral distance.

[0045] Epitaxial source / drain regions (92) in an n-type region (50N), for example, an NMOS region, can be formed by masking a p-type region (50P), for example, a PMOS region. Subsequently, the epitaxial source / drain regions (92) are grown epitaxially in the first recesses (86) in the n-type region (50N). The epitaxial source / drain regions (92) may comprise any acceptable material suitable for n-type nano-FETs. For example, if the second nanostructures (54) are silicon, the epitaxial source / drain regions (92) may comprise materials that apply tensile strain to the second nanostructures (54), such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions (92) may have raised surfaces from their respective upper surfaces of the nanostructures (55) and may have facets.

[0046] Epitaxial source / drain regions (92) in a p-type region (50P), for example, a PMOS region, can be formed by masking an n-type region (50N), for example, an NMOS region. Subsequently, epitaxial source / drain regions (92) are grown epitaxially in the first recesses (86) in the p-type region (50P). The epitaxial source / drain regions (92) may comprise any acceptable material suitable for p-type nano-FETs. For example, if the first nanostructures (52) are silicon germanium, the epitaxial source / drain regions (92) may comprise materials that apply compressive strain to the first nanostructures (52), such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions (92) may also have raised surfaces and facets from their respective surfaces of the multilayer stack (64).

[0047] The epitaxial source / drain regions (92), first nanostructures (52), second nanostructures (54), and / or the substrate (50) may be injected with dopants to form source / drain regions, similar to the previously discussed process for forming low-concentration doped source / drain regions, and annealing may follow. The source / drain regions are approximately 1 x 10⁻⁶ 19 atoms / cm 3 to about 1x10 21 atoms / cm 3 The impurity concentration may be such that n-type and / or p-type impurities for the source / drain regions may be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions (92) may be doped in-situ during growth.

[0048] As a result of epitaxy processes used to form epitaxial source / drain regions (92) in the n-type region (50N) and p-type region (50P), the upper surfaces of the epitaxial source / drain regions (92) have facets that extend laterally outward beyond the sidewalls of the nanostructures (55). In some embodiments, these facets merge adjacent epitaxial source / drain regions (92) of the same nano-FET, as illustrated by FIG. 12a. In other embodiments, adjacent epitaxial source / drain regions (92) remain separated after the epitaxy process is completed, as illustrated by FIG. 12c. In the embodiments illustrated in FIG. 12a and FIG. 12c, first spacers (81) are formed on the upper surface of the STI regions (68), thereby blocking epitaxial growth. In some other embodiments, the first spacers (81) may cover portions of the sidewalls of the nanostructures (55) to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacers (81) may be adjusted to remove the spacer material so that the epitaxially grown region can extend to the surface of the STI region (68).

[0049] The epitaxial source / drain regions (92) may include one or more semiconductor material layers. For example, the epitaxial source / drain regions (92) may include a first semiconductor material layer (92A), a second semiconductor material layer (92B), and a third semiconductor material layer (92C). Each of the semiconductor material layers (92A, 92B, and / or 92C) may have curved surfaces as a result of the epitaxial process(s) used. Any number of semiconductor material layers may be used for the epitaxial source / drain regions (92). Each of the first semiconductor material layer (92A), the second semiconductor material layer (92B), and the third semiconductor material layer (92C) may be formed of different semiconductor materials and doped with different dopant concentrations. In some embodiments, the first semiconductor material layer (92A) may have a dopant concentration smaller than that of the second semiconductor material layer (92B) and larger than that of the third semiconductor material layer (92C). In embodiments where the epitaxial source / drain regions (92) comprise three semiconductor material layers, the first semiconductor material layer (92A) may be deposited, the second semiconductor material layer (92B) may be deposited on the first semiconductor material layer (92A), and the third semiconductor material layer (92C) may be deposited on the second semiconductor material layer (92B).

[0050] FIG. 12d illustrates an embodiment in which the sidewalls of the first nanostructures (52) in the n-type region (50N) and the sidewalls of the second nanostructures (54) in the p-type region (50P) are concave, the outer sidewalls of the first inner spacers (90) are concave, and the first inner spacers (90) are each recessed from the sidewalls of the second nanostructures (54) and the first nanostructures (52). As illustrated in FIG. 12d, epitaxial source / drain regions (92) may be formed to be in contact with the first inner spacers (90) and may extend beyond the sidewalls of the second nanostructures (54) in the n-type region (50N) and beyond the sidewalls of the first nanostructures (52) in the p-type region (50P).

[0051] In FIGS. 13a through 13c, the first interlayer dielectric (ILD) (96) is deposited, respectively, on the structure illustrated in FIGS. 6a, FIG. 12b, and FIG. 12a (the processes of FIGS. 7a through 12d do not alter the cross-section illustrated in FIG. 6a). The first ILD (96) may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etching stop layer (CESL) (94) is disposed between the first ILD (96) and the epitaxial source / drain regions (92), masks (78), and first spacers (81). The CESL (94) may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etching rate different from that of the material of the first ILD (96) placed above it.

[0052] In FIG. 14a and FIG. 14b, a flattening process, such as CMP, may be performed to make the upper surface of the first ILD (96) equal in height to the upper surfaces of the dummy gates (76) or masks (78). The flattening process may also remove portions of the masks (78) on the dummy gates (76) and the first spacers (81) along the sidewalls of the masks (78). After the flattening process, the dummy gates (76), the first spacers (81), and the upper surfaces of the first ILD (96) become equal in height within the process variation. Accordingly, the upper surfaces of the dummy gates (76) are exposed through the first ILD (96). In some embodiments, the masks (78) may be retained, in which case the flattening process makes the upper surface of the first ILD (96) the same height as the upper surface of the masks (78) and the first spacers (81).

[0053] In FIG. 15a and FIG. 15b, dummy gates (76) and, if present, masks (78) are removed in one or more etching steps so that second recesses (98) are formed. Parts of the dummy dielectric layers (70) within the second recesses (98) may also be removed. In some embodiments, the dummy gates (76) and the dummy dielectric layers (70) are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas(s) that selectively etches the dummy gates (76) at a faster rate than the first ILD (96) or the first spacers (81). Each second recess (98) subsequently exposes and / or places over parts of the nanostructures (55) that act as channel regions in the completed nano-FETs. Parts of the nanostructures (55) acting as channel regions are placed between adjacent pairs of epitaxial source / drain regions (92). During removal, when the dummy gates (76) are etched, the dummy dielectric layers (70) can be used as etching stop layers. After the removal of the dummy gates (76), the dummy dielectric layers (70) can be subsequently removed.

[0054] In FIG. 16a and FIG. 16b, the first nanostructures (52) in the n-type region (50N) and the second nanostructures (54) in the p-type region (50P) are removed to extend the second recesses (98). The first nanostructures (52) can be removed by forming a mask (not shown) over the p-type region (50P) and performing an isotropic etching process, such as wet etching using selective etchants for the materials of the first nanostructures (52), while the second nanostructures (54), the substrate (50), and the STI regions (68) remain relatively unetched compared to the first nanostructures (52). In embodiments where the first nanostructures (52) comprise, for example, SiGe and the second nanostructures (54A to 54C) comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., may be used to remove the first nanostructures (52) in the n-type region (50N).

[0055] The second nanostructures (54) in the p-type region (50P) can be removed by forming a mask (not shown) over the n-type region (50N) and performing an isotropic etching process, such as wet etching using selective etchants for the materials of the second nanostructures (54), while the first nanostructures (52), the substrate (50), and the STI regions (68) remain relatively unetched compared to the second nanostructures (54). In embodiments where the second nanostructures (54) comprise, for example, SiGe, and the first nanostructures (52) comprise, for example, Si or SiC, hydrogen fluoride, other fluorine-based etchants, etc., can be used to remove the second nanostructures (54) in the p-type region (50P).

[0056] In other embodiments, channel regions in the n-type region (50N) and the p-type region (50P) may be formed simultaneously, for example, by removing the first nanostructures (52) in both the n-type region (50N) and the p-type region (50P) or by removing the second nanostructures (54) in both the n-type region (50N) and the p-type region (50P). In such embodiments, the channel regions of the n-type nano-FETs and the p-type nano-FETs may have the same material composition, such as silicon, silicon germanium, etc. FIGS. 25a, 25b, and 25c illustrate a structure resulting from such embodiments in which the channel regions in both the p-type region (50P) and the n-type region (50N) are provided by the second nanostructures (54) and, for example, include silicon.

[0057] In FIG. 17a and FIG. 17b, gate dielectric layers (100) are formed for alternate gates. The gate dielectric layers (100) are conformally deposited in the second recesses (98). In the n-type region (50N), the gate dielectric layers (100) may be formed on the upper surfaces and sidewalls of the substrate (50) and on the upper surfaces, sidewalls, and lower surfaces of the second nanostructures (54), and in the p-type region (50P), the gate dielectric layers (100) may be formed on the upper surfaces and sidewalls of the substrate (50) and on the upper surfaces, sidewalls, and lower surfaces of the first nanostructures (52). The gate dielectric layers (100) may also be deposited on the upper surfaces of the first ILD (96), CESL (94), first spacers (81), and STI regions (68).

[0058] According to some embodiments, the gate dielectric layers (100) comprise one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric layers (100) may comprise an interface layer (101) (e.g., a silicon oxide layer, etc.) and a high-k gate dielectric layer (103) (e.g., a metal oxide layer) on the interface layer (101). In some embodiments, the high-k gate dielectric layer (103) has a k value greater than about 7.0 and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers (100) may be the same or different in the n-type region (50N) and the p-type region (50P). Methods for forming the gate dielectric layers (100) may include molecular beam deposition (MBD), ALD, PECVD, etc. In some embodiments, the thickness (T1) of the interface layer (101) may be in the range of about 7 Å to about 25 Å, and the thickness (T2) of the high-k gate dielectric layer (103) may be in the range of about 7 Å to about 35 Å. In other embodiments, the interface layer (101) and / or the high-k gate dielectric layer (103) may have different thicknesses. In the illustrated embodiment, the interface layer (101) may be deposited using a conformal deposition process. In other embodiments, the interface layer (101) may be formed by a selective growth process so as to be placed only on the surfaces of nanostructures (e.g., nanostructures (52 / 54)) using, for example, a thermal oxidation process. FIG. 17c illustrates an alternative embodiment in which the interface layer (101) is thermally grown, which may be applied to all subsequent embodiments of gate electrode formation.

[0059] The formation of gate dielectric layers (100) in the n-type region (50N) and the p-type region (50P) may occur simultaneously so that the gate dielectric layers (100) in each region are formed from the same materials. In some embodiments, the gate dielectric layers (100) in each region may be formed by separate processes so that the gate dielectric layers (100) may be made of different materials and / or have a different number of layers. When using separate processes, various masking steps may be used to mask and expose appropriate regions.

[0060] In FIGS. 18a through 21d, gate electrodes (102P and 102N) (see FIGS. 20a, 20b, 21a, and 21b) are formed on the gate dielectric layers (100) in the p-type region (50P) and n-type region (50N), respectively, to fill the remaining portions of the second recesses (98). The formation of the gate electrodes (102) in the n-type region (50N) and the p-type region (50P) may occur simultaneously so that the gate electrodes (102) in each region are formed from the same materials. In some embodiments, the gate electrodes (102) in each region may be formed by separate processes so that the gate electrodes (102) may be made of different materials and / or have a different number of layers. When using separate processes, various masking steps may be used to mask and expose appropriate regions. FIGS. 18a to 20b illustrate cross-sectional views of forming various layers of gate electrodes (102) in a p-type region (50P), and FIGS. 21a to 21d illustrate cross-sectional views of completed gate electrodes (102) in an n-type region (50N).

[0061] The gate electrodes (102) may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Additionally, the gate electrodes (102) may comprise one or more layers of metal carbides, such as transition metal carbides, which enable increased work function control flexibility.

[0062] Referring to FIGS. 18a and 18b, an optional work function metal layer (105) is deposited on the gate dielectric layers (100) (e.g., on the high-k gate dielectric layer (103)). The work function metal layer (105) may be deposited to surround each of the nanostructures (e.g., nanostructures (52)), and the work function metal layer (105) may be additionally deposited in the inner sheet region (50I) between adjacent nanostructures among the stacked nanostructures (e.g., between nanostructures (52A / 52B) and / or nanostructures (52B / 52C)). In some embodiments, the work function metal layer (105) is a metal nitride layer, such as a titanium nitride (TiN) layer. Methods for forming the work function metal layer (105) may include CVD, ALD, PVD, etc. In embodiments where the work function metal layer (105) is a titanium nitride layer deposited by ALD, a titanium-containing precursor (e.g., TiCl4, etc.) and a nitrogen-containing precursor (e.g., NH3) may be used to form multiple monolayers of titanium nitride. The work function metal layer (105) may have a thickness (T3) in the range of about 5 Å to about 15 Å. Advantages can be achieved by including a work function metal layer (105) comprising a metal nitride (e.g., titanium nitride) directly above the high-k gate dielectric layer (103). For example, the metal nitride material of the work function metal layer (105) may provide a more stable interface with the high-k gate dielectric layer (103) with fewer dangling bonds, particularly when the work function metal layer (105) has a thickness in the aforementioned thickness range. In other embodiments, the work function metal layer (105) may be omitted in exchange for reduced stability (e.g., more dangling bonds, see FIG. 26a to 26c).

[0063] In FIGS. 19a to 19d, a work function metal layer (107) is deposited on a work function metal layer (105) (if present) or on a high-k gate dielectric layer (103) if the work function metal layer (105) is omitted (see FIGS. 26a to 26c). The work function metal layer (107) may be deposited to surround each of the nanostructures (e.g., nanostructures (52)), and the work function metal layer (107) may be additionally deposited in an inner sheet region (50I) between adjacent nanostructures among the stacked nanostructures (e.g., between nanostructures (52A / 52B) and / or nanostructures (52B / 52C). In some embodiments, a combination of gate dielectric layers (100), a work function metal layer (105), and a work function metal layer (107) can completely fill an internal sheet region (50I) extending from a first nanostructure (52) to a second nanostructure (52). In some embodiments (e.g., when the work function metal layer (105) is omitted), a combination of gate dielectric layers (100) and a work function metal layer (107) can completely fill an internal sheet region (50I) extending from a first nanostructure (52) to a second nanostructure (52) (see FIG. 26a through 26c). Other configurations are also possible.

[0064] In some embodiments, the work function metal layer (107) is a metal carbide layer comprising carbon and Ce, Hf, V, Nb, Sc, Y, or Mo. By using a metal carbide layer having said metals, improved flexibility in threshold voltage regulation in the resulting device can be achieved. FIGS. 19c and 19d illustrate detailed views of the work function metal layer (107) (e.g., region (111) in FIG. 19a). In some embodiments, as illustrated by FIG. 19c, the work function metal layer (107) is a single layer entirely formed of a metal carbide comprising Ce, Hf, V, Nb, Sc, Y, or Mo. In other embodiments, as illustrated by FIG. 19d, the work function metal layer (107) is a multilayer structure comprising each metal carbide. For example, the work function metal layer (107) comprises a lower layer (107A) comprising titanium carbide (TiC) or tantalum carbide (TaC), and an upper layer (107B) comprising Ce, Hf, V, Nb, Sc, Y, or Mo. The lower layer (107A) may be formed on the work function metal layer (105) (if present) or the gate dielectric layers (100), and the upper layer (107B) may be formed on the lower layer (107A). The lower layer (107A) comprising titanium or tantalum may facilitate the deposition process of the upper layer (107B) placed on top comprising Ce, Hf, V, Nb, Sc, Y, or Mo.

[0065] Methods for forming the work function metal layer (107) may include CVD, ALD, PVD, etc. In some embodiments, the deposition process may be performed at a temperature in the range of about 125°C to about 600°C. Performing the deposition process within this temperature range may provide advantages. For example, performing the deposition process at a temperature below 125°C may result in the deposition precursors not reacting properly to form the work function metal layer (107). Furthermore, performing the deposition process at a temperature above 600°C may result in poor film quality due to an excessive deposition rate, which may result in unacceptable roughness of the work function metal layer (107). For example, the deposition process may be further performed at a pressure in the range of 0.1 Torr to 70 Torr. The work function metal layer (107) may be deposited in-situ with the work function metal layer (105) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (107) may be deposited ex-situ with the work function metal layer (105) (e.g., in different chambers and / or in a vacuum environment with interruption in between). In embodiments where the work function metal layer (107) is a multilayer structure, each of the layers (e.g., layers (107A and 107B)) may be formed according to the processes.

[0066] In some embodiments, the deposition process of the work function metal layer (107) involves flowing suitable precursors to form a work function metal layer (107) containing the desired metal carbide(s). The precursors may include carbon-containing precursors (e.g., trimethylaluminum (TMA), Al(CH3)3, etc.). The precursors may further include metal-containing precursors, which may vary depending on the type of metal carbide being deposited. Exemplary metal-containing precursors for depositing a work function metal layer (107) containing Ce, Hf, V, Nb, Sc, Y, or Mo are, respectively, CeCl4, HfCl4, VCl3, NbCl5, ScCl4, and YCl4. x , or MoCl x It includes, where 'x' represents a positive integer. In addition, exemplary metal-containing precursors for depositing a work function metal layer (107) containing titanium or tantalum each include TiCl4 or TaCl5. In other embodiments, other suitable precursors may be used.

[0067] Next, in FIG. 20a and FIG. 20b, a charge metal (109) is formed on the work function metal layer (107). The charge metal (109) may be a metal-containing material such as Co, Ru, Al, W, combinations thereof, or multiple layers thereof. The formation of the charge metal (109) may include one or more deposition steps using CVD, ALD, PVD, etc. The charge metal (109) may be a multilayer structure or a single layer. For example, in embodiments where the charge metal (109) comprises W, the charge metal (109) may comprise a fluorine-free tungsten (FFW) layer and a low fluorine tungsten (LFW) layer on top of the FFW layer. The combination of the charge metal (109), the work function metal layer (107), and the work function metal layer (105) (if present) provides a gate electrode (102P) in a p-type region (50P). In some embodiments, the gate electrode (102P) may have an internal sheet thickness (T4) in the range of about 7 Å to about 25 Å (e.g., a spanning region between adjacent nanostructures (52)).

[0068] After filling the second recesses (98), a planarization process, such as CMP, may be performed to remove excess material of the gate dielectric layers (100) and gate electrodes (102P), which is located on the upper surface of the first ILD (96). The material of the gate electrodes (102P) and the remaining portions of the gate dielectric layers (100) thus form alternative gate structures of the resulting nano-FETs. The gate electrodes (102P) and the gate dielectric layers (100) may be collectively referred to as "gate structures." FIG. 20c illustrates a plan view of a gate structure along line XX of FIG. 20b. FIG. 20d illustrates a plan view of a gate structure along line YY of FIG. 20b.

[0069] FIGS. 21a through 21d illustrate cross-sectional views of gate structures (e.g., including gate electrodes (102N) and gate dielectric layers (100)) in n-type regions (50N). FIGS. 21c and 21d illustrate detailed views of the region (119) of FIG. 21a. The gate electrodes (102N) may include an optional work function metal layer (113), a work function metal layer (115), and a filler material (117). In some embodiments, the gate electrode (102N) may have a thickness in the range of about 7 Å to about 25 Å.

[0070] An optional work function metal layer (113) is deposited on the gate dielectric layers (100). The optional work function metal layer (113) may be a metal nitride layer manufactured from a similar material using a process similar to that described above in relation to the work function metal layer (105). The work function metal layer (113) may have the same or different material composition as the work function metal layer (105). The work function metal layer (113) may have a thickness (T4) in the range of about 5 Å to about 15 Å. Advantages can be achieved by including a work function metal layer (113) comprising a metal nitride (e.g., titanium nitride) immediately above the high-k gate dielectric layer (103). For example, the metal nitride material of the work function metal layer (113) can provide a more stable interface with the high-k gate dielectric layer (103) with fewer dangling bonds, particularly when the work function metal layer (113) has a thickness within the above range. In other embodiments, the work function metal layer (113) may be omitted in exchange for reduced stability (e.g., more dangling bonds, FIG. 26a to FIG. 26c).

[0071] A work function metal layer (115) is deposited on the work function metal layer (113) (if present) and the gate dielectric layer (100). The work function metal layer (115) may be one or more metal carbide layer(s) that are manufactured from a similar process and include a material similar to that described above in relation to the work function metal layer (107). For example, the work function metal layer (115) may include Ce, Hf, V, Nb, Sc, Y, or Mo. The work function layer (115) may be a single layer (e.g., illustrated by FIG. 21c) or a multilayer structure including a bottom layer (115A) and a top layer (115B). The bottom layer (115A) may be a metal carbide layer including Ti or Ta, and the top layer (115B) may be a metal carbide layer including Ce, Hf, V, Nb, Sc, Y, or Mo. The lower layer (115A) can facilitate the growth of the upper layer (115B). At least one of the work function metal layers (113 or 115) may further provide an n-type work function metal layer comprising an n-type metal (e.g., aluminum, etc.). For example, the work function metal layer (115) may comprise a metal carbide layer comprising carbon, aluminum, and an alloy of Ti, Ta, Ce, Hf, V, Nb, Sc, Y, or Mo.

[0072] The filler material (117) may be formed from a material similar to that described above in relation to the filler metal (109) and may be formed using a similar process. The filler material (117) may have the same or different material composition as the filler metal (109).

[0073] In FIGS. 22a through 22c, a gate structure (including gate dielectric layers (100) and corresponding gate electrodes (102N / 102P) placed on top) is recessed so that a recess is formed directly above the gate structure between opposing portions of the first spacers (81). A gate mask (104) comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., is filled into the recess, and a flattening process follows to remove excess portions of dielectric material extending over the first ILD (96). Subsequently formed gate contacts (e.g., gate contacts (114) discussed below in relation to FIGS. 24a and 24b) penetrate the gate mask (104) to contact the upper surface of the recessed gate electrodes (102).

[0074] As further illustrated by FIGS. 22a through 22c, the second ILD (106) is deposited on the first ILD (96) and on the gate mask (104). In some embodiments, the second ILD (106) is a fluid film formed by FCVD. In some embodiments, the second ILD (106) is formed from a dielectric material such as PSG, BSG, BPSG, USG, etc. and can be deposited by any suitable method such as CVD, PECVD, etc.

[0075] In FIGS. 23a through 23c, the second ILD (106), the first ILD (96), the CESL (94), and the gate masks (104) are etched to form third recesses (108) that expose the epitaxial source / drain regions (92) and / or surfaces of the gate structure. The third recesses (108) may be formed by etching using an anisotropic etching process, such as RIE, NBE, etc. In some embodiments, the third recesses (108) may be etched through the second ILD (106) and the first ILD (96) using a first etching process; etched through the gate masks (104) using a second etching process; and then etched through the CESL (94) using a third etching process. A mask, such as a photoresist, may be formed and patterned on the second ILD (106) to mask portions of the second ILD (106) from the first etching process and the second etching process. In some embodiments, the etching process may be over-etched, so that the third recesses (108) extend into the epitaxial source / drain regions (92) and / or the gate structure, and the bottom of the third recesses (108) may be at the same height as the epitaxial source / drain regions (92) and / or the gate structure (e.g., at the same level or at the same distance from the substrate), or may be lower than the epitaxial source / drain regions (92) and / or the gate structure (e.g., closer to the substrate). Although FIG. 23b illustrates third recesses (108) by exposing the epitaxial source / drain regions (92) and the gate structure in the same cross section, in various embodiments, the epitaxial source / drain regions (92) and the gate structure may be exposed in different cross sections, thereby reducing the risk of short-circuiting subsequently formed contacts.After the third recesses (108) are formed, silicide regions (110) are formed over the epitaxial source / drain regions (92). In some embodiments, the silicide regions (110) are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the epitaxial source / drain regions (92) (e.g., silicon, silicon germanium, germanium) placed underneath to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portions of the epitaxial source / drain regions (92), and then performing a thermal annealing process to form the silicide regions (110). The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide regions (110) are referred to as silicide regions, the silicide regions (110) may also be germanide regions, or silicon germanide regions (e.g., regions containing silicide and germanide). In one embodiment, the silicide region (110) contains TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0076] Next, in FIGS. 24a through 24c, contacts (112 and 114) (which may also be referred to as contact plugs) are formed in the third recesses (108). Each of the contacts (112 and 114) may comprise one or more layers, such as barrier layers, diffusion layers, and filling materials. For example, in some embodiments, each of the contacts (112 and 114) comprises a barrier layer and a conductive material and is electrically coupled to an underlying conductive feature (e.g., in the illustrated embodiment, a gate structure (102) and / or a silicide region (110)). The contacts (112) may be electrically coupled to the gate structure (102) and may be referred to as gate contacts, and the contacts (114) may be electrically coupled to the silicide regions (110) and may be referred to as source / drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. To remove excess material from the surface of the second ILD (106), a planarization process, such as CMP, may be performed.

[0077] Accordingly, various transistor structures having metal carbide work function metal layers can be formed to provide enhanced flexibility in threshold voltage control. Although FIGS. 2 through 24c illustrate transistors having specific configurations, other configurations are also possible. For example, the shape of each of the nanostructures (52 and / or 54) may differ, such as being round in other embodiments. A round shape can be achieved by adjusting the etching process(s) used to form the nanostructures (52 / 54). FIG. 29 illustrates a cross-sectional view along cross-section AA of FIG. 1 in which the nanostructures (52 / 54) have a round cross section. Furthermore, additional or fewer work function metal layers may be included in each of the gate electrodes (102N / 102P) as described below.

[0078] FIGS. 25a through 25c illustrate cross-sectional views of a device according to some alternative embodiments. FIG. 25a illustrates the reference cross-section (A-A') illustrated in FIG. 1. FIG. 25b illustrates the reference cross-section (B-B') illustrated in FIG. 1. FIG. 25c illustrates the reference cross-section (C-C') illustrated in FIG. 1. In FIGS. 25a through 25c, similar reference numbers indicate similar elements formed by processes similar to those of the structures in FIGS. 24a through 24c. However, in FIGS. 25a through 25c, the channel regions in the n-type region (50N) and the p-type region (50P) comprise the same material. For example, second nanostructures (54) comprising silicon provide channel regions for p-type nano-FETs in the p-type region (50P) and n-type nano-FETs in the n-type region (50N). The structures of FIGS. 25a through 25c may be formed, for example, by simultaneously removing the first nanostructures (52) from both the p-type region (50P) and the n-type region (50N); depositing gate dielectrics (100) and gate electrodes (102P) (e.g., gate electrodes suitable for a p-type nano-FET) around the second nanostructures (54) in the p-type region (50P); and depositing gate dielectrics (100) and gate electrodes (102N) (e.g., gate electrodes suitable for an n-type nano-FET) around the second nanostructures (54) in the n-type region (50N). In such embodiments, the materials of the epitaxial source / drain regions (92) may differ in the n-type region (50N) compared to the p-type region (50P) as described above.

[0079] FIGS. 26a through 26c illustrate cross-sectional views of a device according to some alternative embodiments. FIG. 26a illustrates the reference cross-section (A-A') illustrated in FIG. 1. FIG. 26b illustrates the reference cross-section (B-B') illustrated in FIG. 1. FIG. 26c illustrates the reference cross-section (C-C') illustrated in FIG. 1. In FIGS. 26a through 26c, similar reference numbers indicate similar elements formed by processes similar to those of the structures in FIGS. 24a through 24c. However, in FIGS. 26a through 26c, work function metal layers (105 and 113) (e.g., metal nitride layers) may be omitted, and channel regions in the n-type region (50N) and p-type region (50P) comprise the same material. For example, the work function metal layer (107) and the gate dielectric layers (100) together can fill the entire area between adjacent nanostructures (54) in the p-type region (50P), and the work function metal layer (115) and the gate dielectric layers (100) together can fill the entire area between adjacent nanostructures (54) in the n-type region (50N).

[0080] FIGS. 27a through 27c illustrate cross-sectional views of a device according to some alternative embodiments. FIG. 27a illustrates the reference cross section (A-A') illustrated in FIG. 1. FIG. 27b illustrates the reference cross section (B-B') illustrated in FIG. 1. FIG. 27c illustrates the reference cross section (C-C') illustrated in FIG. 1. In FIGS. 27a through 27c, similar reference numerals indicate similar elements formed by processes similar to those of the structures in FIGS. 24a through 24c. However, in FIGS. 27a through 27c, work function metal layers (105 and 113) (e.g., metal nitride layers) may be omitted; Additional work function metal layers (121, 123, 125, and 127) may be included in the gate structures, and channel regions in the n-type region (50N) and p-type region (50P) may include the same material. For example, the gate electrode (102P) in the p-type region (50P) may include an additional work function metal layer (121) on the work function metal layer (107) and a work function metal layer (123) on the work function metal layer (121). The work function metal layer (121) may be a metal nitride layer (e.g., including titanium nitride, etc.) that includes a material similar to the work function metal layer (105) described above (see FIG. 18a and FIG. 18b) and is formed in a similar manner. The work function metal layer (121) may be deposited in-situ with the work function metal layer (107) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (121) may be deposited ex-situ with the work function metal layer (107) (e.g., in a different chamber and / or vacuum environment with interruption in between). The work function metal layer (123) may be a metal carbide layer (e.g., including Ti, Ta, Ce, Hf, V, Nb, Sc, Y, Mo, etc.) that includes a material similar to the work function metal layer (107) and is formed in a similar manner.The work function metal layer (123) may be deposited in-situ with the work function metal layer (121) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (123) may be deposited ex-situ with the work function metal layer (121) (e.g., in a different chamber and / or vacuum environment with interruption in between). Furthermore, the gate electrode (102N) in the n-type region (50N) may include an additional work function metal layer (125) on the work function metal layer (115) and a work function metal layer (127) on the work function metal layer (125). The work function metal layer (125) may be a metal nitride layer (e.g., titanium nitride, etc.) that includes a material similar to the work function metal layer (113) described above (see FIG. 21a and FIG. 21b) and is formed in a similar manner. The work function metal layer (125) may be deposited in-situ with the work function metal layer (115) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (125) may be deposited ex-situ with the work function metal layer (115) (e.g., in a different chamber and / or vacuum environment with interruption in between). The work function metal layer (127) may be a metal carbide layer (e.g., including Ti, Ta, Ce, Hf, V, Nb, Sc, Y, Mo, etc.) that contains a material similar to the work function metal layer (115) and is formed in a similar manner. The work function metal layer (127) can be deposited in-situ with the work function metal layer (125) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (127) can be deposited ex-situ with the work function metal layer (125) (e.g., in a different chamber and / or vacuum environment with interruption in between).

[0081] FIGS. 28a through 28c illustrate cross-sectional views of a device according to some alternative embodiments. FIG. 28a illustrates the reference cross-section (A-A') illustrated in FIG. 1. FIG. 28b illustrates the reference cross-section (B-B') illustrated in FIG. 1. FIG. 28c illustrates the reference cross-section (C-C') illustrated in FIG. 1. In FIGS. 28a through 28c, similar reference numbers indicate similar elements formed by processes similar to those of the structures in FIGS. 24a through 24c. However, in FIGS. 28a through 28c, additional work function metal layers (131 and 133) may be included in the gate structures, and the channel regions in the n-type region (50N) and p-type region (50P) comprise the same material. For example, in the p-type region (50P), an additional work function metal layer (131) may be formed on the work function metal layer (107). The work function metal layer (131) may be a metal nitride layer (e.g., titanium nitride, etc.) that includes a material similar to the work function metal layer (105) and is formed in a similar manner. The work function metal layer (131) may be deposited in-situ with the work function metal layer (107) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (131) may be deposited ex-situ with the work function metal layer (107) (e.g., in a different chamber and / or vacuum environment with interruption in between). In the n-type region (50N), an additional work function metal layer (133) may be formed on the work function metal layer (115). The work function metal layer (133) can be deposited in-situ with the work function metal layer (115) (e.g., in the same chamber and without interruption in a vacuum environment), or the work function metal layer (133) can be deposited ex-situ with the work function metal layer (115) (e.g., in a different chamber and / or vacuum environment with interruption in between).The work function metal layer (133) may be a metal nitride layer (e.g., titanium nitride, etc.) formed in a similar manner and containing a material similar to the work function metal layer (113).

[0082] Various embodiments in this specification include a gate structure having a work function metal layer comprising a metal carbide. For example, the metal carbide may include Ce, Hf, V, Nb, Sc, YC, Hf, or Mo. In some embodiments, the metal carbide layer may be used only as the work function metal in the gate structure. In some embodiments, the metal carbide layer may be used in combination with one or more other work function metals (e.g., one or more TiN layers) to provide a plurality of work function metal layers in the gate structure. As a result of using different metal carbides as work function metals, work function control can be achieved more precisely.

[0083] In some embodiments, the device comprises a semiconductor substrate; a set of nanostructures stacked vertically on the semiconductor substrate; a first source / drain region; and a second source / drain region. The set of nanostructures stacked vertically extends between the first source / drain region and the second source / drain region along a first cross-section. The device further comprises a gate structure surrounding the set of nanostructures stacked vertically along a second cross-section, wherein the second cross-section is along the longitudinal axis of the gate structure. The gate structure comprises a gate dielectric surrounding each nanostructure of the set of nanostructures stacked vertically; a first metal carbide layer on the gate dielectric—the first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo—; and a gate filler material on the first metal carbide layer. Optionally, in one embodiment, the device further comprises a first metal nitride layer between the first metal carbide layer and the gate dielectric. Optionally, in one embodiment, the first metal nitride layer comprises titanium nitride. Optionally, in one embodiment, the device further comprises a second metal nitride layer on a first metal carbide layer. Optionally, in one embodiment, the device further comprises a second metal carbide layer between the first metal carbide layer and the gate dielectric, wherein the second metal carbide layer comprises a metal element different from that of the first metal carbide layer. Optionally, in one embodiment, the second metal carbide layer comprises titanium carbide or tantalum carbide. Optionally, in one embodiment, the device further comprises a third metal nitride layer on the first metal carbide layer; and a third metal carbide layer on the third metal nitride layer, wherein the gate filler material is disposed on the third metal carbide layer. Optionally, in one embodiment, the third metal carbide layer comprises Ti, Ta, Ce, Hf, V, Nb, Sc, Y, or Mo.

[0084] In some embodiments, the semiconductor device comprises a plurality of channel regions; a first source / drain region comprising a first semiconductor material layer and a second semiconductor material on the first semiconductor material layer, wherein the surface of the first semiconductor material layer is curved; a second source / drain region, wherein the plurality of channel regions extend between the first source / drain region and the second source / drain region; and a gate structure surrounding each of the plurality of channel regions. The gate structure comprises a gate dielectric; a first metal nitride layer on the gate dielectric; a first metal carbide layer on the first metal nitride layer, wherein the metal element of the first metal carbide layer is Ce, Hf, V, Nb, Sc, Y, or Mo; and a gate filler material on the first metal carbide layer. Optionally, in one embodiment, the device further comprises a second metal carbide layer between the first metal carbide layer and the first metal nitride layer, wherein the metal element of the first metal carbide layer is different from the metal element of the second metal carbide layer. Optionally, in one embodiment, the device further comprises a second metal nitride layer on a first metal carbide layer. Optionally, in one embodiment, the first metal nitride layer has a thickness in the range of 5 Å to 15 Å. Optionally, in one embodiment, the gate dielectric, the first metal nitride layer, and the first metal carbide layer completely fill a first region, and the first region extends from a first channel region among a plurality of channel regions to a second channel region among a plurality of channel regions. Optionally, in one embodiment, the gate dielectric comprises an interface layer; and a high-k dielectric on the interface layer.

[0085] In some embodiments, the method comprises the steps of: depositing a high-k gate dielectric layer on and along the sidewalls of a semiconductor fin; depositing a first work function metal on the high-k gate dielectric layer, wherein the step of depositing the first work function metal comprises flowing a first carbon-containing precursor and a first metal-containing precursor, and the first metal-containing precursor comprises Ce, Hf, V, Nb, Sc, Y, or Mo; and depositing a filler metal on the first work function metal. Optionally, in one embodiment, the method further comprises the step of depositing a second work function metal on the high-k gate dielectric layer before depositing the first work function metal, wherein the step of depositing the second work function metal comprises flowing a second carbon-containing precursor and a second metal-containing precursor, wherein the second metal-containing precursor comprises titanium or tantalum. Optionally, in one embodiment, the method further comprises the step of depositing a third work function metal on a high-k gate dielectric layer before depositing a first work function metal, wherein the step of depositing the third work function metal comprises the step of flowing a nitrogen-containing precursor and a third metal-containing precursor. Optionally, in one embodiment, the third metal-containing precursor comprises titanium. Optionally, in one embodiment, the first metal-containing precursor comprises TaCl5, CeCl4, HfCl4, VCl3, NbCl5, ScCl4, YCl x , or MoCl x It includes. Optionally, in one embodiment, the method further includes the step of depositing a fourth work function metal on a first work function metal, wherein the step of depositing the fourth work function metal includes the step of flowing a nitrogen-containing precursor and a fourth metal-containing precursor.

[0086] The foregoing describes an overview of the features of various embodiments to enable a person skilled in the art to better understand the aspects of the present disclosure. A person skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments introduced herein. A person skilled in the art will also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

[0087] [bookkeeping]

[0088] 1. As a device,

[0089] semiconductor substrate;

[0090] A set of nanostructures stacked vertically on the semiconductor substrate;

[0091] First source / drain area;

[0092] Second source / drain region - the vertically stacked set of nanostructures extends along the first cross-section between the first source / drain region and the second source / drain region -; and

[0093] A gate structure surrounding the set of vertically stacked nanostructures along the second cross-section

[0094] It includes, wherein the second cross-section follows the longitudinal axis of the gate structure, and the gate structure,

[0095] A gate dielectric surrounding each nanostructure of the vertically stacked set of nanostructures above;

[0096] A first metal carbide layer on the gate dielectric above - the first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo -; and

[0097] A device comprising a gate filling material on the first metal carbide layer.

[0098] 2. The device according to claim 1, further comprising a first metal nitride layer between the first metal carbide layer and the gate dielectric.

[0099] 3. In paragraph 2, the device wherein the first metal nitride layer comprises titanium nitride.

[0100] 4. A device according to paragraph 2, further comprising a second metal nitride layer on the first metal carbide layer.

[0101] 5. The device according to claim 1, further comprising a second metal carbide layer between the first metal carbide layer and the gate dielectric, wherein the second metal carbide layer comprises a metal element different from that of the first metal carbide layer.

[0102] 6. A device according to claim 5, wherein the second metal carbide layer comprises titanium carbide or tantalum carbide.

[0103] 7. In Paragraph 1,

[0104] A third metal nitride layer on the first metal carbide layer; and

[0105] Third metal carbide layer on the third metal nitride layer above

[0106] A device further comprising, wherein the gate filling material is disposed on the third metal carbide layer.

[0107] 8. The device according to claim 7, wherein the third metal carbide layer comprises Ti, Ta, Ce, Hf, V, Nb, Sc, Y, or Mo.

[0108] 9. As a semiconductor device,

[0109] Multiple channel regions;

[0110] A first source / drain region comprising a first semiconductor material layer and a second semiconductor material on the first semiconductor material layer - the surface of the first semiconductor material layer is curved -;

[0111] A second source / drain region - the plurality of channel regions extend between the first source / drain region and the second source / drain region -; and

[0112] A gate structure surrounding each of the above plurality of channel regions

[0113] Includes, and the gate structure,

[0114] Gate dielectric;

[0115] A first metal nitride layer on the gate dielectric above;

[0116] A first metal carbide layer on the first metal nitride layer above - the metal element of the first metal carbide layer is Ce, Hf, V, Nb, Sc, Y, or Mo -; and

[0117] A semiconductor device comprising a gate filling material on the first metal carbide layer.

[0118] 10. A semiconductor device according to claim 9, further comprising a second metal carbide layer between the first metal carbide layer and the first metal nitride layer, wherein the metal element of the first metal carbide layer is different from the metal element of the second metal carbide layer.

[0119] 11. A semiconductor device according to claim 9, further comprising a second metal nitride layer on the first metal carbide layer.

[0120] 12. A semiconductor device according to claim 9, wherein the first metal nitride layer has a thickness in the range of 5 Å to 15 Å.

[0121] 13. A semiconductor device according to claim 9, wherein the gate dielectric, the first metal nitride layer, and the first metal carbide layer completely fill a first region, and the first region extends from a first channel region among the plurality of channel regions to a second channel region among the plurality of channel regions.

[0122] 14. In claim 9, the gate dielectric is,

[0123] Interfacial layer; and

[0124] A semiconductor device comprising a high-k dielectric on the above interface layer.

[0125] 15. A method for manufacturing a semiconductor device,

[0126] A step of depositing a high-k gate dielectric layer on the sidewalls of a semiconductor fin and along the sidewalls of the semiconductor fin;

[0127] A step of depositing a first work function metal on the high-k gate dielectric layer, comprising a step of flowing a first carbon-containing precursor and a first metal-containing precursor, wherein the first metal-containing precursor comprises Ce, Hf, V, Nb, Sc, Y, or Mo; and

[0128] Step of depositing a filler metal on the first work function metal above

[0129] A method including

[0130] 16. In claim 15, the method further comprises the step of depositing a second work function metal on the high-k gate dielectric layer before depositing the first work function metal, and

[0131] The step of depositing the second work function metal comprises the step of flowing a second carbon-containing precursor and a second metal-containing precursor, wherein the second metal-containing precursor comprises titanium or tantalum.

[0132] 17. In claim 15, the method further comprises the step of depositing a third work function metal on the high-k gate dielectric layer before depositing the first work function metal, and

[0133] A method comprising the step of depositing the third work function metal, wherein the step of flowing a nitrogen-containing precursor and a third metal-containing precursor.

[0134] 18. In paragraph 17, the method wherein the third metal-containing precursor comprises titanium.

[0135] 19. In paragraph 15, the first metal-containing precursor is TaCl5, CeCl4, HfCl4, VCl3, NbCl5, ScCl4, YCl x , or MoCl x A method including

[0136] 20. In paragraph 15, the method further comprises the step of depositing a fourth work function metal on the first work function metal, and

[0137] A method comprising the step of depositing the fourth work function metal, wherein the step of flowing a nitrogen-containing precursor and a fourth metal-containing precursor.

Claims

Claim 1 A device comprising: a semiconductor substrate; a set of nanostructures vertically stacked on the semiconductor substrate; a first source / drain region; a second source / drain region - the set of nanostructures vertically stacked extends between the first source / drain region and the second source / drain region along a first cross-section -; and a gate structure surrounding the set of nanostructures vertically stacked along a second cross-section, wherein the second cross-section follows the longitudinal axis of the gate structure, and the gate structure comprises a gate dielectric surrounding each nanostructure of the set of nanostructures vertically stacked; a first metal carbide layer on the gate dielectric - the first metal carbide layer comprises Ce, V, Sc, or Y -; a second metal carbide layer between the first metal carbide layer and the gate dielectric - the second metal carbide layer comprises tantalum carbide -; and a gate filler material on the first metal carbide layer. Claim 2 A device according to claim 1, further comprising a first metal nitride layer between the first metal carbide layer and the gate dielectric. Claim 3 In paragraph 2, the device, wherein the first metal nitride layer comprises titanium nitride. Claim 4 A device according to paragraph 2, further comprising a second metal nitride layer on the first metal carbide layer. Claim 5 delete Claim 6 delete Claim 7 A device according to claim 1, further comprising: a third metal nitride layer on the first metal carbide layer; and a third metal carbide layer on the third metal nitride layer, wherein the gate filler material is disposed on the third metal carbide layer. Claim 8 In claim 7, the device wherein the third metal carbide layer comprises Ti, Ta, Ce, Hf, V, Nb, Sc, Y, or Mo. Claim 9 A semiconductor device comprising: a plurality of channel regions; a first source / drain region comprising a first semiconductor material layer and a second semiconductor material on the first semiconductor material layer, wherein the surface of the first semiconductor material layer is curved; a second source / drain region, wherein the plurality of channel regions extend between the first source / drain region and the second source / drain region; and a gate structure surrounding each of the plurality of channel regions, wherein the gate structure comprises: a gate dielectric; a first metal nitride layer on the gate dielectric; a first metal carbide layer on the first metal nitride layer, wherein the metal element of the first metal carbide layer is Ce, V, Sc, or Y; a second metal carbide layer between the first metal carbide layer and the gate dielectric, wherein the second metal carbide layer comprises tantalum carbide; and a gate filling material on the first metal carbide layer. Claim 10 A method for manufacturing a semiconductor device, comprising: a step of depositing a high-k gate dielectric layer on and along the sidewalls of a semiconductor fin; a step of depositing a first work function metal on the high-k gate dielectric layer, comprising a step of flowing a first carbon-containing precursor and a first metal-containing precursor, wherein the first metal-containing precursor comprises Ce, V, Sc, or Y; a step of depositing a filler metal on the first work function metal, and further comprising a step of depositing a second work function metal on the high-k gate dielectric layer before depositing the first work function metal, wherein the step of depositing the second work function metal comprises a step of flowing a second carbon-containing precursor and a second metal-containing precursor, wherein the second metal-containing precursor comprises tantalum.

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