Laminate stacking structures

Abstract

For the implementation of semiconductor devices such as transistors, electrical insulating materials and / or structures are disclosed herein. An exemplary electrical insulating layer is a dielectric layer having a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure comprises at least one crystalline boron nitride layer (e.g., a hexagonal boron nitride layer) and at least one amorphous boron nitride layer. In some embodiments, the dielectric layer is implemented in a transistor. For example, the transistor includes a gate spacer and / or an inner spacer, and the dielectric layer is the gate spacer, the inner spacer, or both. In another example, the dielectric layer is a contact etch stop layer that may be formed on the transistor. In another example, the dielectric layer is a gate isolation layer between the gate of the transistor and the gate of another transistor, or forms a part thereof.

Description

Technology Field

[0001] This application is a regular application of U.S. Patent Application No. 63 / 722,158 filed on November 19, 2024, and claims priority thereof, the entire disclosure of which is incorporated herein by reference. Background Technology

[0002] In the electronics industry, there is a growing demand for smaller and faster electronic devices capable of simultaneously supporting multiple functions that are becoming increasingly complex and sophisticated. To meet this demand, the integrated circuit (IC) industry continues to pursue a trend of manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have largely been achieved by reducing IC dimensions (e.g., minimum IC feature size) to improve production efficiency and lower associated costs. For example, reducing the size of a transistor in an IC (and thus reducing its dimensions) can reduce the power supply voltage and / or threshold voltage required to operate the transistor. However, the effectiveness of this improvement is diminished by an increase in leakage current that may occur due to the reduced dimensions of the insulating material in the scaled IC. Improvements are needed. [Patent Document 1]: U.S. Patent Application Publication US2023 / 0369201 Brief explanation of the drawing

[0003] The present disclosure is best understood when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various features are not depicted to actual scale and are used for illustrative purposes only. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. FIG. 1 illustrates a laminated dielectric film that may form part of a semiconductor device according to various embodiments of the present disclosure, either partially or wholly. FIG. 2 is a partial or overall schematic diagram of a laminated dielectric film as in FIG. 1, according to various embodiments of the present disclosure. FIG. 3 provides experimental current-voltage (IV) characteristics for different dielectric structures according to various embodiments of the present disclosure. FIG. 4 illustrates a precursor that can be used to form a laminated dielectric film as in FIG. 1, according to various embodiments of the present disclosure. FIG. 5 is a partial or complete flowchart of a method for forming a laminated dielectric film as in FIG. 1, according to various embodiments of the present disclosure. FIG. 6 is a partial or complete cross-sectional view of a transistor that may include a laminated dielectric film, such as the laminated dielectric film described in FIG. 1 and / or the present specification, according to various embodiments of the present disclosure. FIGS. 7a through 7d are partial or full enlarged views of different configurations of a portion of a transistor that may include a laminated dielectric film, such as a portion of the transistor of FIG. 6, depending on various embodiments of the present specification. FIGS. 8a through 8d are partial or full enlarged views of different configurations of another part of a transistor that may include a laminated dielectric film, such as another part of the transistor of FIG. 6, according to various embodiments of the present disclosure. FIGS. 9a through 9d are partial or full enlarged views of different configurations of a part of an interconnect structure, such as connected to a transistor of FIG. 6 which may include a laminated dielectric film, according to various embodiments of the present disclosure. FIG. 10 is a partial or complete flowchart of a transistor that may include a laminated dielectric film, such as FIG. 1 and / or another laminated dielectric film described herein, according to various embodiments of the present disclosure. FIGS. 11a through 11d are partial or full enlarged views of different configurations of another part of a transistor that may include a laminated dielectric film, such as the part of the transistor in FIG. 10, according to various embodiments of the present disclosure. FIG. 12 is a partial or complete cross-sectional view of a device that may include a laminated dielectric film, such as FIG. 1 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. FIGS. 13a through 13d are partial or full enlarged views of different configurations of a part of a device that may include a laminated dielectric film, such as part of the device of FIG. 12, according to various embodiments of the present disclosure. FIG. 14 is a partial or complete cross-sectional view of a device that may include a laminated dielectric film, such as FIG. 1 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. FIGS. 15 to 15d are partial or full enlarged views of different configurations of a part of a device that may include a laminated dielectric film, such as the part of the device of FIG. 14, according to various embodiments of the present disclosure. FIG. 16 is a partial or complete cross-sectional view of a device that may include a laminated dielectric film, such as FIG. 1 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. FIGS. 17a through 17d are partial or full enlarged views of different configurations of a part of a device that may include a laminated dielectric film, such as the part of the device of FIG. 16, according to various embodiments of the present disclosure. Specific details for implementing the invention

[0004] The present disclosure generally relates to electrical insulating materials (e.g., dielectric materials) and / or structures for reducing leakage current.

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the following detailed description, the formation of a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, or embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, spatially relative terms, e.g., "lower," "upper," "horizontal," "vertical," "top," "upper side," "below," "lower side," "upper," "lower," "top," "bottom," etc., as well as their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.), are used to facilitate the description of the relationship between one feature of the present disclosure and another feature. Spatially relative terms are intended to cover different orientations of the device containing the feature. The present disclosure may also repeat reference numbers and / or letters in various examples. This repetition is for simplification and clarification and does not indicate the relationship between the various embodiments and / or configurations described by itself.

[0006] Furthermore, when a number or range of numbers is described with terms such as “about,” “approximately,” etc., as would be understood by those skilled in the art, these terms are intended to encompass a number within a reasonable range that takes into account the variation inherent in manufacturing. For example, a number or range of numbers encompasses an appropriate range including the number described, such as within + / - 20% of the described number, based on known manufacturing tolerances associated with manufacturing a feature having the characteristics associated with that number. For example, a material layer with a thickness of “about 5 nm” may include a dimensional range of 4.5 nm to 5.5 nm, and the manufacturing tolerance associated with depositing the material layer is known to those skilled in the art to be + / - 10%. Additionally, when a device feature is described as having “substantial” properties and / or characteristics, taking into account the variation inherent in any manufacturing process, these terms are intended to capture properties and / or characteristics within the tolerances of the manufacturing process. For example, "substantially vertical" or "substantially horizontal" features are intended to capture features that are approximately vertical and horizontal within the given tolerances of the manufacturing process used to produce them, not to capture features that are mathematically or perfectly vertical and horizontal.

[0007] As integrated circuit (IC) technology nodes are scaled (i.e., increasing device density (i.e., the number of interconnected devices in a given chip area) and / or decreasing geometric size (e.g., the dimensions and / or size of device features, and / or the spacing between them), leakage current becomes a significant problem. For example, as the thickness of insulating material decreases in scaled IC technology nodes, a significant increase in leakage current has been observed. The present disclosure therefore proposes electrical insulating materials (e.g., dielectric materials) and / or structures for reducing leakage current. In some embodiments, the electrical insulating layer has a laminate structure comprising at least one crystalline boron nitride layer and at least one amorphous boron nitride layer (i.e., the electrical insulating layer has a boron- and nitrogen-containing laminate structure). For example, the electrical insulating layer may have a laminate structure comprising an amorphous boron nitride (aBN) layer and a crystalline boron nitride layer. In some embodiments, the thickness of the crystalline boron nitride layer is greater than the thickness of the amorphous boron nitride layer. In another example, the electrical insulating layer may have a laminate structure comprising an amorphous boron nitride layer disposed between a first crystalline boron nitride layer and a second crystalline boron nitride layer. In some embodiments, the crystalline boron nitride layer(s) are hexagonal boron nitride (hBN) layer(s). The electrical insulating material and / or structure disclosed herein may be implemented as a gate spacer, an inner spacer, an etching stop layer, a gate isolation layer, other layers and / or features of a semiconductor device, or a combination thereof.

[0008] FIG. 1 illustrates a laminated dielectric film (10) partially or wholly according to various embodiments of the present disclosure. FIG. 2 is a partial or wholly schematic diagram of a laminated dielectric film (10) according to some embodiments of the present disclosure. FIG. 3 provides experimental current-voltage characteristics for different laminated dielectric films according to various embodiments of the present disclosure. FIG. 4 illustrates a deposition precursor (60) that may be used to form a laminated dielectric film (10) according to some embodiments of the present disclosure. FIG. 5 illustrates a method for forming a laminated dielectric film such as a laminated dielectric film (10) partially or wholly according to some embodiments of the present disclosure. The laminated dielectric film (10) may be referred to as a laminated dielectric layer, a laminated dielectric structure, a laminated insulating structure, a laminated insulating film (and / or layer), etc. For convenience of explanation and understanding, FIG. 1 to FIG. 5 are described simultaneously in this specification. FIGS. 1 through 5 have been simplified to make it clearer to better understand the concept of the invention of the present disclosure. Additional features may be added to the laminated dielectric film (10), and some of the features described below may be replaced, modified, or removed in other embodiments of the laminated dielectric film (10).

[0009] Referring to FIG. 1, the laminated dielectric film (10) comprises at least two dielectric films having different crystalline properties and / or different crystalline conditions, such as a first dielectric layer and a second dielectric layer having different crystalline properties. For example, the first dielectric layer is formed from a first dielectric material having a crystalline structure (e.g., the first dielectric material is in a crystalline form (i.e., has an aligned atomic structure)), and the second dielectric layer is formed from a second dielectric material having an amorphous structure (e.g., the second dielectric material is in a non-crystalline form (i.e., has an unaligned atomic structure)). In some embodiments, the first dielectric material and the second dielectric material are the same dielectric material formed to have different atomic / particle arrangements to provide the laminated structure. In some embodiments, the first dielectric material and the second dielectric material are different dielectric materials.

[0010] In the illustrated embodiment, the laminated dielectric film (10) comprises crystalline boron nitride layers (15) and amorphous boron nitride layers (20) stacked in an alternating and / or interleaving configuration. For example, in FIG. 1, the laminated dielectric film (10) comprises three crystalline boron nitride layers (15) and three amorphous boron nitride layers (20), the first amorphous boron nitride layer (20) interposed between two separate crystalline boron nitride layers (15), and the second amorphous boron nitride layer (20) interposed between two separate crystalline boron nitride layers (15). In the illustrated embodiment, the third amorphous boron nitride layer (20) is formed on top of the individual crystalline boron nitride layers (15) and forms the top of the laminated dielectric film (10). In some embodiments, individual crystalline boron nitride layers (15) may form the top of the laminated dielectric film (10). In some embodiments, the crystalline boron nitride layers (15) are hexagonal boron nitride (hBN) layers, and amorphous boron nitride layers (20) are interleaved between the crystalline boron nitride layers (15). In these embodiments, referring to FIG. 2, each crystalline boron nitride layer (15) may contain boron (B) atoms and nitrogen (N) atoms arranged in an aligned hexagonal pattern, and each amorphous boron nitride layer (20) may contain boron (B) atoms and nitrogen (N) atoms arranged in an unaligned manner (i.e., not patterned). In some embodiments, the boron atoms and nitrogen atoms of the crystalline boron nitride layers (15) may be covalently bonded. For example, each boron atom may be covalently bonded to three nitrogen atoms in such a way that it provides a crystalline boron nitride layer (15) having a lattice structure including a hexagonal ring. Conversely, in some embodiments, boron atoms and nitrogen atoms of an amorphous boron nitride layer (20) may be aggregated and / or held together by van der Waals forces.In this example, the weaker van der Waals forces between the boron atoms and the nitrogen atoms can provide an amorphous boron nitride layer (20) with an irregular lattice structure.

[0011] The present disclosure includes an amorphous dielectric layer (e.g., an amorphous boron nitride layer (20)) within a laminated dielectric formed from a crystalline dielectric layer (e.g., a laminated dielectric film (10) formed from a crystalline boron nitride layer (15)), thereby reducing leakage current that flows undesirably within the dielectric material and degrades the performance of the semiconductor device. Referring to FIG. 3, plot (50) provides experimental current-voltage (IV) characteristics for different laminated dielectric structures according to various embodiments of the present disclosure. For example, plot (50) is in units of amperes per square centimeter (A / cm²). 2The leakage current density (J) of the laminated boron nitride film is plotted as a function of an electric field in units of megavolts per centimeter (MV / cm) under voltage applied to different laminated boron nitride films. In plot (50), line (52) corresponds to the observed leakage current density of a laminated crystalline boron nitride film of a first thickness (e.g., about 40 nm); line (54) corresponds to the observed leakage current density of a laminated crystalline boron nitride film of a second thickness (e.g., about 16 nm); line (56) corresponds to the leakage current density of a laminated amorphous / crystalline boron nitride film of a first thickness, such as the laminated dielectric film (10); and line (58) corresponds to the observed leakage current density of a laminated amorphous / crystalline boron nitride film of a second thickness, such as the laminated dielectric film (10). In some embodiments, as described herein, the laminated crystalline boron nitride film is an individual stack of hexagonal boron nitride layers (e.g., hBN-1 and hBN-2) each having a first thickness and a second thickness, and the laminated amorphous / crystalline boron nitride film is an individual stack of hexagonal boron nitride layers interleaved by amorphous boron nitride layers (e.g., ahBN-1 and ahBN-2) having a first thickness and a second thickness.

[0012] As the applied electric field increases from 0 MV / cm to E5, the leakage current density for the laminated boron nitride film is about J1 to about J11 (e.g., about 1 × 10⁻⁶). -11 A / cm 2 to about 1 × 10 -1 A / cm 2...is observed. For example, as the applied voltage increases from 0 to E4, the leakage current density for the thicker laminated crystalline boron nitride film (hBN-1) increases from about J3 to about J11; as the applied voltage increases from 0 to E5, the leakage current density for the thinner laminated crystalline boron nitride film (hBN-2) increases from about J2 to beyond J11; as the applied voltage increases from 0 to E4, the leakage current density for the thicker laminated amorphous / crystalline boron nitride film (ahBN-1) increases from about J3 to about J6; and as the applied voltage increases from 0 to E5, the leakage current density for the thinner laminated amorphous / crystalline boron nitride film (ahBN-2) increases from about J3 to beyond J9. From FIG. 3, the leakage current density of the thicker laminated amorphous / crystalline boron nitride film (ahBN-1) is smaller than the leakage current density of the thicker laminated crystalline boron nitride film (hBN-1) (e.g., for an applied voltage greater than about E1), and the leakage current density of the thicker amorphous / crystalline boron nitride film (ahBN-2) is smaller than the leakage current density of the thinner laminated crystalline boron nitride film (hBN-2). Additionally, the leakage current density of the thicker amorphous / crystalline boron nitride film (ahBN-1) appears to plateau for an applied voltage greater than about E2. In other words, preferably, the leakage current density of the thicker laminated amorphous / crystalline boron nitride film (abBN-1) is shown not to increase when the critical applied voltage is reached.

[0013] Based on these experimental results, since the amorphous boron nitride layer (e.g., amorphous boron nitride layer (20)) reduces leakage current, the amorphous boron nitride layer is incorporated into a laminated dielectric film formed of a crystalline dielectric layer (e.g., a laminated dielectric film (10) formed of a crystalline boron nitride layer (15)), so as to offset the higher leakage current of the crystalline boron nitride layer, and thus improve the performance of the semiconductor device. For example, a laminated amorphous / crystalline boron nitride film can provide a semiconductor device (e.g., a transistor) having a chemically stable dielectric layer with a lower dielectric constant (exhibiting a dielectric constant of about 3 and remaining chemically stable when subjected to high process temperatures and / or high operating temperatures) that exhibits a lower leakage current (as provided by a crystalline boron nitride layer that blocks current leakage paths such as vertical leakage paths). In some embodiments, a leakage current reduction of a greater than first order may be provided by the amorphous boron nitride layer. Different embodiments may have different advantages, and the specific advantages of any embodiment are not required.

[0014] Referring again to FIG. 1, the thickness of the crystalline boron nitride layer (15) and the thickness of the amorphous boron nitride layer (20) (interleaving the crystalline boron nitride layer (15)) are configured to provide a laminated dielectric film (10) as an electrically insulating, thermally conductive layer exhibiting reduced leakage current. In FIG. 1, the laminated dielectric film (10) has a thickness (T), the crystalline boron nitride layer (15) has a thickness (t1), and the amorphous boron nitride layer (20) has a thickness (t2). In some embodiments, as illustrated, the thickness (t1) is greater than the thickness (t2) to provide a laminated dielectric film (10) having sufficiently high thermal conductivity to effectively dissipate heat in the laminated dielectric film (10), for example. For example, a crystalline boron nitride layer (15) (e.g., an h-BN layer) may exhibit a thermal conductivity greater than about 390 W / m·K at room temperature, while an amorphous boron nitride layer (20) (e.g., an a-BN layer) may exhibit an in-plane thermal conductivity of about 3 W / m·K, which is not considered a thermally conductive material in the context of the present disclosure. In some embodiments, thicknesses (t1) and (t2) may be configured to provide a laminated dielectric film (10) having a thermal conductivity of at least 10 W / m·K. Thermal conductivity of less than about 10 W / m·K may not effectively dissipate heat. In some embodiments, the thickness (T) is about 15 nm to about 45 nm. In some embodiments, the thickness (t1) is about 0.5 nm to about 2 nm. In some embodiments, the thickness (t2) is about 0.5 nm to about 5 nm. In some embodiments, the sum of the thicknesses of the crystalline boron nitride layers (15) is smaller than the sum of the thicknesses of the amorphous boron nitride layers (20).In the described embodiments, the crystalline boron nitride layer (15) may have substantially the same thickness (e.g., thickness (t1)) and the amorphous boron nitride layer (20) may have substantially the same thickness (e.g., thickness (t2)), but the present disclosure considers embodiments in which the crystalline boron nitride layer (15) may have different thicknesses and / or embodiments in which the amorphous boron nitride layer (20) may have different thicknesses. The present disclosure also considers embodiments in which the thickness (t1) may be smaller than the thickness (t2).

[0015] In some embodiments, the laminated dielectric film (10) has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6). For example, the laminated dielectric film (10) has a dielectric constant of about 3 (k 3) has. The dielectric constant of the crystalline boron nitride layer (15) is greater than the dielectric constant of the amorphous boron nitride layer (20). Therefore, inserting the amorphous boron nitride layer (20) into the laminated dielectric film (10) can reduce the dielectric constant. In some embodiments, the crystalline boron nitride layer (15) has a dielectric constant of about 3.0 to about 5.0 (3.0 ≤ k ≤ 5.0). In some embodiments, the amorphous boron nitride layer (20) has a dielectric constant of about 1.5 to about 3.0 (1.5 ≤ k ≤ 3.0).

[0016] The laminated dielectric film (10) may be formed by a deposition process such as chemical vapor deposition (CVD), wherein various deposition parameters are tuned to provide at least one crystalline boron nitride layer and at least one amorphous boron nitride layer in the laminated dielectric film (10). In some embodiments, the deposition process is tuned to provide a stack of crystalline boron nitride layers interleaved by an amorphous boron nitride layer in the laminated dielectric film (10), as described herein. Various deposition parameters may include deposition precursor(s) (reactive gas(s)), deposition time(s), deposition temperature(s), deposition pressure(s), other deposition parameters, or combinations thereof. In some embodiments, the laminated dielectric film (10) is directly deposited and / or grown during manufacturing on a base layer (25) (e.g., a substrate, a material layer, a device layer, and / or a device feature) of a semiconductor device (e.g., a transistor). In some embodiments, the laminated dielectric film (10) is deposited and / or grown on a carrier substrate (and / or layer) and then transferred to a semiconductor device (e.g., a transistor) during manufacturing.

[0017] Referring to FIG. 5, FIG. 5 illustrates a flowchart of a deposition process (80) that may be implemented to form a laminated dielectric film (10) according to some embodiments. The deposition process (80) may be a plasma-enhanced CVD process, and the deposition process (80) facilitates the deposition and / or growth of the laminated dielectric film (10) directly on a semiconductor device during its manufacture. In block (82), a workpiece upon which the laminated dielectric film (10) is to be deposited / grow is loaded into a process chamber. In some embodiments, the workpiece may include a semiconductor device (e.g., a transistor) or a portion upon which the deposition process (80) is to form the laminated dielectric film thereon and / or thereon.

[0018] The deposition process (80) may include generating a nitrogen-containing plasma in block (84) into a process chamber and flowing a boron- and nitrogen-containing deposition precursor into a process chamber in block (86). The present disclosure considers block (84) being performed before, after, or simultaneously with block (86). In some embodiments, the boron- and nitrogen-containing deposition precursor is borazine (e.g., B3N3H6). In some embodiments, as shown in FIG. 4, the boron- and nitrogen-containing deposition precursor has a hexagonal ring structure. The hexagonal ring structure may be bonded to a terminal group which may be organic or inorganic. In some embodiments, the boron- and nitrogen-containing deposition precursor may be an organic deposition precursor which may include a hexagonal ring structure. In some embodiments, the boron- and nitrogen-containing deposition precursor may be an inorganic deposition precursor and may include a hexagonal ring structure. The nitrogen-containing plasma may be generated from a nitrogen-containing precursor gas, which may include diatomic nitrogen (N2), ammonia (NH3), other suitable nitrogen-containing precursor gases, or a combination thereof. The nitrogen-containing plasma may therefore be an N2 plasma, an NH3 plasma, or an N2 / NH3 plasma, and the nitrogen-containing plasma may be a nitrogen-containing excited neutral molecule (e.g., N2 * It includes ), nitrogen-containing ionized atoms (e.g., N2+), nitrogen-containing atoms (e.g., N) ionized atoms (N+), or combinations thereof (all generally referred to as plasma-excited nitrogen-containing species).

[0019] Various parameters of the deposition process (80) are tuned to provide at least one crystalline boron nitride layer and at least one amorphous boron nitride layer to the laminated dielectric film. The parameters include deposition precursor(s) (including reactive gas(s) and / or carrier gas(s), flow rate of deposition precursor(s), flow rate of reactive gas(s), flow rate of carrier gas(s), deposition time(s), deposition temperature(s), deposition pressure(s), other deposition parameters (e.g., power and / or voltage used to generate a nitrogen-containing plasma), or a combination thereof. In some embodiments, the deposition process (80) implements a deposition temperature of about 200 °C to about 400 °C. For example, the temperature maintained within the process chamber during the deposition process (80) may be about 200 °C to about 400 °C. In another example, during the deposition process (80), the workpiece is heated to a temperature of about 200 °C to about 400 °C. In some embodiments, the deposition process (80) is switched between two sets of deposition parameters to alternately deposit crystalline boron nitride layers and amorphous boron nitride layers. For example, one set of deposition parameters may be implemented to form a crystalline boron nitride layer, and a second set of deposition parameters may be implemented to form an amorphous boron nitride layer. In some embodiments, the deposition process (80) dynamically adjusts the flow rate of a boron- and nitrogen-containing deposition precursor gas and / or a nitrogen-containing precursor gas to alternately deposit crystalline boron nitride layers and amorphous boron nitride layers. In some embodiments, the deposition process (80) alternately deposits crystalline boron nitride layers and amorphous boron nitride layers by dynamically adjusting the deposition temperature, deposition pressure, deposition time, other deposition parameters (e.g., power and / or voltage used to generate nitrogen-containing plasma), or a combination thereof.

[0020] In some embodiments, the deposition process (80) may include determining whether the laminated dielectric film thus deposited in block (88) has a target thickness. If the laminated dielectric film has a target thickness, the deposition process (80) may end in block (90). Otherwise, in some embodiments, blocks (84) and / or blocks (86) are continued or / or repeated until the target thickness is reached. The deposition process (80) is also configured to minimize oxygen exposure (e.g., by depositing the laminated dielectric film in a vacuum), so that the resulting laminated dielectric film, such as the laminated dielectric film (10), exhibits desirable oxidation resistance. For example, the laminated dielectric film thus deposited exhibits a sufficiently low oxygen concentration, and any oxygen present within the laminated dielectric film thus deposited may be from ambient oxygen (e.g., in the air), which may be exposed when the laminated dielectric film thus deposited is transferred during the process, for example, between process chambers. In some embodiments, the laminated dielectric film, such as the laminated dielectric film (10), has an oxygen concentration of less than about 4%. An oxygen concentration greater than about 4% may undesirably increase the dielectric constant of the laminated dielectric film, increase the leakage current of the laminated dielectric film, decrease the thermal conductivity of the laminated dielectric film, decrease the chemical stability of the laminated dielectric film, or a combination thereof may occur. Additional steps may be provided before, during, and after the method (80), and some of the steps described may be moved, replaced, or removed for additional embodiments of the method (80).

[0021] FIG. 6 is a partial or complete cross-sectional view of a transistor (100) that may include a laminated dielectric film such as the laminated dielectric film (10) described with reference to FIG. 1 through 5 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. FIG. 7a through 7d are partial or complete enlarged views of different configurations of a portion (I1) of a transistor (100) that may include a laminated dielectric film, according to various embodiments of the present disclosure. FIG. 8a through 8d are partial or complete enlarged views of different configurations of a portion (I2) of a transistor (100) that may include a laminated dielectric film, according to various embodiments of the present disclosure. FIGS. 9a through 9d are partial or full enlarged views of different configurations of a portion (I3) of an interconnection structure that may be connected to a transistor (100) and may include a laminated dielectric film, according to various embodiments of the present disclosure. FIGS. 6, FIGS. 7a through 7d, FIGS. 8a through 8d, and FIGS. 9a through 9d are described together in this specification for ease of explanation and understanding. FIGS. 6, FIGS. 7a through 7d, FIGS. 8a through 8d, and FIGS. 9a through 9d have been simplified for clarity to better understand the concept of the invention of the present disclosure. Additional features may be added to the transistor (100) and / or the interconnection structure, and some of the features described below may be replaced, modified, or removed in other embodiments of the transistor (100) and / or the interconnection structure.

[0022] Referring to FIG. 6, the transistor (100) may be formed on or / or include the substrate (102). In the illustrated embodiment, the substrate (102) is a silicon substrate. The substrate (102) includes an elemental semiconductor such as silicon and / or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In some embodiments, the substrate (102) is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (102) may include various doping regions, such as a p-type doping region (e.g., p-well), an n-type doping region (e.g., n-well), or a combination thereof. The n-type doping region includes an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type doping region includes a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof.

[0023] The transistor (100) may include an active region, which may include a channel (110) and a source / drain (120), which may be formed on a substrate (102) and / or disposed on the substrate (102). In FIG. 6, the source / drain (120) is disposed on the substrate (102), and the channel (110) is formed in a portion of the substrate (102) disposed between the source / drain (120). The active region may be oriented longitudinally along the x-direction (i.e., the length follows the x-direction, the width follows the y-direction, and the height follows the z-direction). In some embodiments, such as when the transistor (100) is a fin-like field effect transistor (FinFET), the active region of the transistor (100) may include a fin structure (102') extending from the substrate (102), a source / drain (120) may be formed in the fin structure (102'), and a channel (110) may be formed in a portion of the fin structure (102') positioned between the source / drain (120). The fin structure (102') extends along the x-direction and has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, the fin structure (102') is a semiconductor fin comprising silicon, germanium, silicon germanium, other suitable semiconductor materials, or a combination thereof. In some embodiments, the fin structure (102') is formed from a portion of the substrate (102). For example, the substrate (102) may be a silicon substrate, and the fin structure (102') may be a patterned portion and / or extension (i.e., a silicon fin) of the substrate (102). In some embodiments, the fin structure (102') is formed from one or more semiconductor layers deposited and patterned on the substrate (102). For example, the substrate (102) may be a silicon substrate, and the fin structure (102') (i.e., a silicon germanium fin) may be formed from a silicon germanium layer deposited and patterned on the substrate (102).In some embodiments, the composition and / or material of the fin structure (102') is based on the type of transistor (100) (e.g., whether the transistor (100) is a p-type FinFET or an n-type FinFET).

[0024] The source / drain (120) comprises a semiconductor material, and the source / drain (1120) may be doped with an n-type dopant and / or a p-type dopant, and the source / drain (120) may have the same or different composition and / or material. In some embodiments, the semiconductor material(s) of the source / drain (120) are formed by an epitaxial process, and the source / drain (120) is formed from an epitaxially grown / deposited semiconductor material, and the source / drain may be referred to as an epitaxial source / drain. In some embodiments (e.g., when forming a portion of an n-type transistor), the source / drain (120) may comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments (e.g., when forming a portion of a p-type transistor), the source / drain (120) may comprise germanium doped with boron, other p-type dopants, or a combination thereof, or silicon germanium. In some embodiments, doping regions such as a heavily doped source / drain (HDD) region, a lightly doped source / drain (LDD) region, other doping regions, or a combination thereof are disposed in the source / drain (120). In some embodiments, doping regions such as the LDD region may extend into the channel (110). As used in the present specification, a source / drain region, source / drain, source / drain structure, epitaxial source / drain, epitaxial source / drain feature, etc. may refer to the source of the transistor (100), the drain of the transistor (100), or the source and / or drain of a plurality of devices (including the transistor (100)).

[0025] The transistor (100) comprises a gate structure (125) including at least a gate stack (130). The gate stack (130), which is also referred to as a high-k / metal gate in some embodiments, is placed on the channel (110) and engaged with the channel (110), and the gate stack (130) is placed between the source / drains (120). The gate stack (130) may extend in a different longitudinal direction (e.g., perpendicular to the longitudinal direction of the active region) and (e.g., in a direction in which the channel (110) and the source / drain are aligned relative to each other). For example, the gate stack (130) extends longitudinally along the y-direction and has a length along the y-direction, a width along the x-direction, and a height along the z-direction. In a cross-sectional view along the longitudinal direction of the active region (Fig. 6), the gate stack (130) is placed on the top of the channel (110). In a cross-sectional view along the width direction of the active region (e.g., along the y-direction), the gate stack (130) is positioned on top of the channel (110). In some embodiments, such as when the active region of the transistor (100) is provided by a fin structure (i.e., the transistor (100) is a FinFET), the gate stack (130) may be positioned on the sidewall of the channel (110) in a cross-sectional view along the width direction of the active region, and the gate stack (130) may wrap around the channel (110).

[0026] The gate stack (130) may include a gate dielectric (132) and a gate electrode (134). The gate dielectric (132) is disposed on the channel (110). The gate dielectric (132) includes at least one dielectric layer, such as an interface layer and / or a high-k dielectric layer. The interface layer is SiO2, SiGeO2 xDielectric materials include HfSiO, SiON, other dielectric materials, or combinations thereof. High-k dielectric layers generally refer to dielectric materials having a dielectric constant higher than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3(BST), HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric layer comprises a hafnium oxide (e.g., HfO2) layer and / or a zirconium oxide (e.g., ZrO2) layer.

[0027] A gate electrode (134) is disposed on a gate dielectric (132). The electrically conductive layer comprises an electrically conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other electrically conductive materials, or a combination thereof. In some embodiments, the electrically conductive layer comprises a work function layer tuned to have a desired work function (e.g., an n-type work function or a p-type work function). The work function layer comprises a work function metal and / or an alloy thereof such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or a combination thereof. In some embodiments, the electrically conductive layer comprises a bulk layer over the gate dielectric and / or work function layer. The bulk layer may comprise Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metal(s) and / or alloys thereof, or combinations thereof. In some embodiments, the electrically conductive layer comprises a barrier layer over the work function layer and / or gate dielectric. The barrier layer comprises a material capable of preventing the diffusion and / or reaction of components between adjacent layers, such as the work function layer and the bulk layer, and / or promoting adhesion between adjacent layers. In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0028] In some embodiments, the gate stack (130) includes a hard mask (136) (e.g., a self-aligned cap (SAC) structure). The hard mask (136) may be placed on the gate electrode (134), and the hard mask (136) may be placed on the gate dielectric (132). The hard mask (136) comprises a material different from the dielectric layer subsequently formed to achieve etch selectivity. In some embodiments, the hard mask (136) comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, other silicon nitride, other silicon carbide, or a combination thereof. In some embodiments, the hard mask (136) may comprise a metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, zirconium aluminum oxide, other metal oxide, other metal nitride, or a combination thereof.

[0029] The gate structure (125) further includes a gate spacer (140). The gate spacer (140) is positioned adjacent to and along the sidewall of the gate stack (130). In the illustrated embodiment, the sidewall of the gate stack (130) is formed by a gate dielectric (132), a gate electrode (134), and a hard mask (136), and the gate spacer (140) is adjacent to (abut) the gate dielectric (132), the gate electrode (134), and the hard mask (136). In another embodiment, the gate dielectric (132) and the hard mask (136), excluding the gate electrode (134), may form the sidewall of the gate stack (130) such that the gate spacer (140) is adjacent to the gate dielectric (132) and the hard mask (136), excluding the gate electrode (134). According to the present disclosure, various configurations of the gate stack (130) and the gate spacer (140) relative thereto are considered. The gate spacer (140) may comprise a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable components (e.g., boron), or a combination thereof (e.g., silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonide, silicon oxycarbonitride, boron nitride, etc.).

[0030] In some embodiments, the gate spacer (140) has a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (140a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (140b) (see FIG. 7a through 7d). The crystalline boron nitride layer (140a) is similar to the crystalline boron nitride layer described herein, such as the crystalline boron nitride layer (15), and the amorphous boron nitride layer (140b) is similar to the amorphous boron nitride layer described herein, such as the amorphous boron nitride layer (20). In some embodiments, the gate spacer (140) having the boron- and nitrogen-containing laminate structure has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0031] The boron- and nitrogen-containing laminate structure of the gate spacer (140) may have various configurations as described in FIGS. 7a through 7d. For example, referring to FIG. 7a, the boron- and nitrogen-containing laminate structure of the gate spacer (140) may include an amorphous boron nitride layer (140b) disposed between crystalline boron nitride layers (140a). In this example, the crystalline boron nitride layer (140a) is adjacent to the dielectric layer (150) adjacent to the gate spacer (140), such as the gate stack (130) (e.g., its gate dielectric (132) and / or gate electrode (134)), and the contact etch stop layer (CESL) (152) of the dielectric layer (150). In another example, referring to FIG. 7b, the boron-and-nitrogen containing laminate structure of the gate spacer (140) may include a crystalline boron nitride layer (140a) disposed between amorphous boron nitride layers (140b). In this example, the amorphous boron nitride layer (140b) is adjacent to the gate stack (130) and the dielectric layer (150) (e.g., its CESL (152)). In another example, referring to FIG. 7c and FIG. 7d, the boron-and-nitrogen containing laminate structure of the gate spacer (140) may include a single crystalline boron nitride layer (140a) and a single amorphous boron nitride layer (140b). In some embodiments of this example, as shown in FIG. 7c, the amorphous boron nitride layer (140b) may be adjacent to the gate stack (130d), while the crystalline boron nitride layer (140a) may be adjacent to the dielectric layer (150) (e.g., its CESL (152)). In other embodiments of this example, as shown in FIG. 7d, the crystalline boron nitride layer (140a) may be adjacent to the gate stack (130), while the amorphous boron nitride layer (140b) may be adjacent to the dielectric layer (150) (e.g., its CESL (152)).In another example, the boron- and nitrogen-containing laminate structure of the gate spacer (140) may comprise a plurality of crystalline boron nitride layers (140a) interleaved by an amorphous boron nitride layer (140b). For example, the boron- and nitrogen-containing laminate structure may be composed of a laminated dielectric film (10).

[0032] A dielectric layer (150) is placed on a substrate (102), a source / drain (120), and a gate structure (125) (e.g., a gate stack (130) and a gate spacer (140)). The dielectric layer (150) may have a multilayer structure such as a CESL (152) and an interlayer dielectric (ILD) layer (154). The ILD layer (154) is placed on the CESL (152). The ILD layer (154) may comprise a dielectric material comprising, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS (tetraethyl orthosilicate) formed oxide, BSG, PSG, BPSG (borophosphosilicate glass), FSG (fluorosilicate glass), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (benzocyclobutene)-based dielectric material, polyimide, other suitable dielectric material, or a combination thereof. In some embodiments, the ILD layer (154) comprises a dielectric material having a dielectric constant smaller than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the ILD layer (154) comprises a dielectric material having a dielectric constant less than about 2.5, such as porous silicon oxide, silicon carbide, carbon-doped oxide (e.g., SiCOH-based material), or a combination thereof. CESL (152) comprises a material different from the dielectric material of the ILD layer (154). For example, when the ILD layer (154) may comprise silicon and oxygen (e.g., porous silicon oxide), CESL (152) may comprise silicon and nitrogen, and CESL (152) may be a silicon nitride layer, a silicon carbonitride layer, or a silicon oxycarbonitride layer.

[0033] In some embodiments, the dielectric constant of the CESL (152) is greater than the dielectric constant of the ILD layer (154). In some embodiments, the dielectric constant of the CESL (152) is smaller than the dielectric constant of the gate dielectric (132). In some embodiments, the dielectric constant of the ILD layer (154) is smaller than the dielectric constant of the gate dielectric (132). In some embodiments, the dielectric constant of the gate dielectric (132) is at least twice the dielectric constant of the ILD layer (154). In some embodiments, the dielectric constant of the ILD layer (154) is about 3 to about 5. In some embodiments, the dielectric constant of the boron- and nitrogen-containing laminate structure of the gate spacer (140) (and / or other features implementing the disclosed laminate structure) is smaller than the dielectric constant of the ILD layer (154). In some embodiments, the dielectric constant of the boron- and nitrogen-containing laminate structure of the gate spacer (140) (and / or other features implementing the disclosed laminate structure) is smaller than the dielectric constant of the CESL (152). In some embodiments, the dielectric constant of the boron- and nitrogen-containing laminate structure of the gate spacer (140) (and / or other features implementing the disclosed laminate structure) is smaller than the dielectric constant of the gate dielectric (132). In some embodiments, the dielectric constant of the gate dielectric (132) is larger than the dielectric constants of the gate spacer (140), the CESL (152), and the ILD layer (154). In this embodiment, the dielectric constant of the CESL (152) may be greater than the dielectric constant of the gate spacer (140) and / or the dielectric constant of the ILD layer (154), and the dielectric constant of the gate spacer (140) may be greater than, smaller than, or approximately the same as the dielectric constant of the ILD layer (154).

[0034] In some embodiments, the CESL (152) has a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (152a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (152b) (see FIG. 8a through 8d). The crystalline boron nitride layer (152a) is similar to the crystalline boron nitride layer (15) described herein, and the amorphous boron nitride layer (152b) is similar to the amorphous boron nitride layer (20) described herein. In some embodiments, the CESL (152) having the boron- and nitrogen-containing laminate structure has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0035] The boron- and nitrogen-containing laminate structure of the CESL (152) may have various configurations as described in FIGS. 8a through 8d. For example, referring to FIG. 8a, the boron- and nitrogen-containing laminate structure of the CESL (152) may include an amorphous boron nitride layer (152b) disposed between crystalline boron nitride layers (152a). In this example, the crystalline boron nitride layer (152a) may be adjacent to the gate spacer (140) and the ILD layer (154), and the crystalline boron nitride layer (152a) (of a portion of the CESL (152) disposed over the source / drain (120)) may be adjacent to the source / drain (120). In another example, referring to FIG. 8b, the boron- and nitrogen-containing laminate structure of the CESL (152) may include a crystalline boron nitride layer (152a) disposed between amorphous boron nitride layers (152b). In this example, the amorphous boron nitride layer (152b) is adjacent to the gate spacer (140) and the ILD layer (154), and the amorphous boron nitride layer (152b) (e.g., of a portion of the CESL (152) disposed over the source / drain (120)) may be adjacent to the source / drain (120). In another example, referring to FIG. 8c and FIG. 8d, the boron- and nitrogen-containing laminate structure of CESL (152) may comprise a single crystalline boron nitride layer (152a) and a single amorphous boron nitride layer (152b). In some embodiments of this example, as shown in FIG. 8c, the amorphous boron nitride layer (152b) may be adjacent to the gate spacer (140), while the crystalline boron nitride layer (152a) may be adjacent to the ILD layer (154). In another embodiment of this example, as shown in FIG. 8d, the crystalline boron nitride layer (152a) may be adjacent to the gate spacer (140), while the amorphous boron nitride layer (152b) is adjacent to the ILD layer (154).In another example, the boron- and nitrogen-containing laminate structure of the CESL (152) may comprise a plurality of crystalline boron nitride layers (152a) interleaved by an amorphous boron nitride layer (152b). For example, the laminate structure of the CESL (152) may be composed of a laminated dielectric film (10).

[0036] The transistor (100) may further include a multilayer interconnect (MLI) structure on the substrate (102), as shown on the front side thereof. The MLI structure may include a back-end-of-line (BEOL) structure. The MLI structure includes a dielectric layer and an electrically conductive layer (e.g., a patterned metal layer, which may be a group of metal lines, metal vias, metal contacts, or combinations thereof arranged in a desired pattern), which are combined to form an interconnect (routing) structure. In some embodiments, the dielectric layer of the MLI structure comprises a dielectric layer (160) that may have a multilayer structure (e.g., CESL (162) and ILD layer (164)), a dielectric layer (186) that may have a multilayer structure (CESL (182) and ILD layer (184)), a dielectric layer (188) that may have a multilayer structure (e.g., CESL (190) and ILD layer (192)), and a dielectric layer (194) that may have a multilayer structure (e.g., CESL (196) and ILD layer (197)). CESL (162), CESL (182), CESL (190), CESL (196), or a combination thereof may be configured similarly to CESL (152). The ILD layer (164), ILD layer (184), ILD layer (192), ILD layer (197), or a combination thereof may be configured similarly to the ILD layer (154). The interconnection structure may include vertically oriented electrically conductive features, such as metal contacts and / or metal vias, and may include electrically conductive features that connect horizontally oriented electrically conductive features, such as metal lines of different layers / levels (or different planes) of the MLI structure. In some embodiments, the routing structure of the MLI structure routes electrical signals between a device and / or component of the device layer (DL), the MLI structure, an external device and / or component, or a combination thereof.In some embodiments, the MLI structure distributes an electrical signal (e.g., clock signal, voltage signal, ground signal, etc.) to a transistor (100), another device / component of the chip to which the transistor (100) may belong, an external device and / or component, or a combination thereof.

[0037] The MLI structure comprises a device-level contact layer and / or via layer (collectively referred to as a via zero layer (V0 level)) (which may include device-level contacts such as source / drain contacts (170) and / or device-level vias such as source / drain vias (172)), a metal zero layer (M0 level), a via source layer (V1 level), a metal source layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), and further comprising a via (X-1) layer (V(X-1) level), a metal (X-1) layer (M(X-1) level), a via X layer (VX level), and a metal X layer (MX level), wherein X is an integer (e.g., from 2 to 10). Each level of the MLI structure may include an electrically conductive feature disposed in each dielectric layer (e.g., dielectric layer (186), dielectric layer (188), and / or dielectric layer (194)), such as a metal line (199) or a metal via (198). The metal lines (199) of the M0 level, M1 level, M2 level, ..., M(X-1) level, and MX level may be referred to as the M0 line, M1 line, M2 line, ..., M(X-1) line, and MX line, respectively. The metal vias (198) of the V0 level, V1 level, V2 level, ..., V(X-1) level, and VX level may be referred to as the V0 via, V1 via, V2 via, ..., V(X-1) via, and VX via, respectively. Each metal via (198) can physically and / or electrically connect a metal line (199) placed below (e.g., an individual M1 line) and a metal line (199) placed above (e.g., an individual M2 line), a device-level contact below (e.g., a source / drain contact) and a metal line (199) above (e.g., an individual M0 line), or a device feature below (e.g., a gate and / or source / drain) and a metal line (199) above (e.g., an individual M0 line).

[0038] In some embodiments, one or more CESLs of MLI structures such as CESL (190) have a boron- and nitrogen-containing laminate structure. The boron-and-nitrogen containing laminate structure comprises at least one crystalline boron nitride layer, such as a hexagonal boron nitride layer (e.g., crystalline boron nitride layer (190a)), and at least one amorphous boron nitride layer (e.g., amorphous boron nitride layer (190b)) (see FIG. 9a through 9d). The crystalline boron nitride layer (190a) is similar to the crystalline boron nitride layer described herein, such as the crystalline boron nitride layer (15), and the amorphous boron nitride layer (190b) is similar to the amorphous boron nitride layer described herein, such as the amorphous boron nitride layer (20). In some embodiments, a CESL having a boron-and-nitrogen containing laminate structure, such as CESL (190), has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0039] The boron-and-nitrogen-containing laminate structure of the CESL (190) may have various configurations as described in FIGS. 9a through 9d. For example, referring to FIG. 9a, the boron-and-nitrogen-containing laminate structure of the CESL (190) may include an amorphous boron nitride layer (190b) disposed between crystalline boron nitride layers (190a). In this example, the crystalline boron nitride layer (190a) may be adjacent to an ILD layer (e.g., ILD layer (184) and ILD layer (192)). In another example, referring to FIG. 9b, the boron-and-nitrogen-containing laminate structure of the CESL (190) may include a crystalline boron nitride layer (190a) disposed between amorphous boron nitride layers (190b). In this example, the amorphous boron nitride layer (190b) may be adjacent to the ILD layer (e.g., ILD layer (184) and ILD layer (192)). In another example, referring to FIG. 9c and FIG. 9d, the boron- and nitrogen-containing laminate structure of CESL (190) may comprise a single crystalline boron nitride layer (190a) and a single amorphous boron nitride layer (190b). In some embodiments of this example, as shown in FIG. 9c, the amorphous boron nitride layer (190b) may be adjacent to the ILD layer (184), while the crystalline boron nitride layer (190a) may be adjacent to the ILD layer (192). In another embodiment of this example, as illustrated in FIG. 9d, a crystalline boron nitride layer (190a) may be adjacent to an ILD layer (184), while an amorphous boron nitride layer (190b) is adjacent to an ILD layer (192). In another example, the boron-and-nitrogen containing laminate structure of the CESL (190) may comprise a plurality of crystalline boron nitride layers (190a) interleaved by an amorphous boron nitride layer (190b). In this example, the boron-and-nitrogen containing laminate structure of the CESL (190) may be composed of the laminated dielectric film (10) described herein.

[0040] FIG. 10 is a partial or complete cross-sectional view of a transistor (200) that may include a laminated dielectric film such as the laminated dielectric film (10) described with reference to FIG. 1 through 5 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. The transistor (200) is similar to the transistor (100) in many respects. Accordingly, similar features of the transistor (200) and the transistor (100) are identified by the same reference numerals for clarity and brevity, such as a substrate (102), a fin structure (102'), a channel (110), a source / drain (120), a gate structure (125), a gate stack (130) (including a gate dielectric (132), a gate electrode (134), and a hard mask (136)), a gate spacer (140), a dielectric layer (150) (including a CESL (152) and an ILD layer (154)), an MLI structure connected to the transistor (200), etc. FIGS. 11a through 11d are partial or full enlarged views of different configurations of a portion (I4) of the transistor (200) that may include a laminated dielectric film according to various embodiments of the present disclosure. FIGS. 10 and FIGS. 11a through 1e are discussed together in this specification for convenience of explanation and understanding. FIGS. 10 and FIGS. 11a through 11d have been simplified for clarity to better understand the concept of the invention of the present disclosure. Additional features may be added to the transistor (200), and some of the following features may be replaced, modified, or removed in other embodiments of the transistor (200).

[0041] In FIG. 10, the transistor (200) is a gate-all-around (GAA) transistor. For example, the channel (110) includes a channel layer (110A) and a channel layer (110B), each of which is suspended and / or disposed on the substrate (102). The channel layer (110A) and the channel layer (110B) extend between the source / drain (120), and the channel layer (110A) and the channel layer (110B) may comprise a semiconductor material such as that described herein (and thus may be referred to as a semiconductor layer). The channel layer (110A) and the channel layer (110B) may be disposed on a fin structure (102') and / or a protrusion of the substrate (102). The channel layer (110A) and the channel layer (1110B) may have a cylindrical profile (e.g., nanowire), a rectangular profile (e.g., nanobar), a sheet-shaped profile (e.g., nanosheet), or any other suitable profile shape. In some embodiments, the channel layer (110A) and the channel layer (110B) may have nanometer-sized dimensions and may be referred to as "nanostructures". In some embodiments, the channel layer (110A) and the channel layer (110B) may have dimensions smaller than nanometers and / or other suitable dimensions.

[0042] Additionally, in the transistor (200), the gate stack (130) comprises an upper portion disposed over the channel layer (110A), a middle portion disposed between the channel layer (110A) and the channel layer (110B), and a lower portion disposed between the channel layer (110B) and the substrate (102) (e.g., protrusions thereof). The upper portion of the gate stack (130) is disposed between the gate spacers (140), the middle portion of the gate stack (130) is disposed between each inner spacer (240), and the lower portion of the gate stack (130) is disposed between each inner spacer (240). In some embodiments, the gate stack (130) may be disposed on the upper, lower, and sidewalls of the channel layer (110A) and the channel layer (110B) in a cross-sectional view along the width direction of the active region (e.g., along the width direction of the gate stack (130)). In some embodiments, the gate stack (130) may surround and interlock with the channel layer (110A) and the channel layer (110B). In some embodiments, the gate stack (130) may completely surround and / or partially surround the channel layer (110A) and the channel layer 110B (i.e., may be positioned on at least two sides).

[0043] In the illustrated embodiment, the transistor (200) further includes an inner spacer (240). In some embodiments, the inner spacer (240) includes a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (240a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (240b) (see FIG. 11a through 11d). The crystalline boron nitride layer (240a) is similar to the crystalline boron nitride layer described herein, such as the crystalline boron nitride layer (15), and the amorphous boron nitride layer (240b) is similar to the amorphous boron nitride layer described herein, such as the amorphous boron nitride layer (20). In some embodiments, the inner spacer (240) having a boron- and nitrogen-containing laminate structure has a dielectric constant of about 3 (k As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0044] The boron- and nitrogen-containing laminate structure of the inner spacer (240) may have various configurations as described in FIGS. 11a through 11d. For example, referring to FIG. 11a, the boron- and nitrogen-containing laminate structure of the inner spacer (240) may include an amorphous boron nitride layer (240b) disposed between crystalline boron nitride layers (240a). In this example, the crystalline boron nitride layer (240a) is adjacent to the gate stack (130) (e.g., its gate dielectric (132) and / or gate electrode (134)) and the source / drain. In another example, referring to FIG. 11b, the boron-and-nitrogen containing laminate structure of the inner spacer (240) may include a crystalline boron nitride layer (240a) disposed between amorphous boron nitride layers (240b). In this example, the amorphous boron nitride layer (240b) is adjacent to the gate stack (130) and the source / drain (120). In another example, referring to FIG. 11c and FIG. 11d, the boron-and-nitrogen containing laminate structure of the inner spacer (240) may include a single crystalline boron nitride layer (240a) and a single amorphous boron nitride layer (240b). In some embodiments of these examples, as shown in FIG. 11c, the amorphous boron nitride layer (240b) may be adjacent to the gate stack (130), while the crystalline boron nitride layer (240a) may be adjacent to the source / drain (120). In another embodiment of these examples, as shown in FIG. 11d, the crystalline boron nitride layer (240a) may be adjacent to the gate stack (130), while the amorphous boron nitride layer (240b) is adjacent to the source / drain (120). In another example, the boron- and nitrogen-containing laminate structure of the inner spacer (240) may comprise a plurality of crystalline boron nitride layers (240a) interleaved by the amorphous boron nitride layer (240b).For example, the boron- and nitrogen-containing laminate structure of the inner spacer (240) may be composed of the laminated dielectric film (10) described herein.

[0045] FIG. 12 is a partial or complete cross-sectional view of a device (300) that may include a laminated dielectric film such as the laminated dielectric film (10) described with reference to FIG. 1 through 5 and / or other laminated dielectric films described herein, depending on various aspects of the present disclosure. The device (300) is similar in many respects to the transistor (100) and / or the transistor (200). Accordingly, similar features of the device (300), the transistor (200), and the transistor (100) are identified by the same reference numeral for clarity and simplicity. For example, the device (300) includes transistors (T1) and transistors (T2), each of which includes a portion of each substrate (102), a pin structure (102'), a channel (110) (including a channel layer (110A) and a channel layer (110B)), a source / drain (120) (viewable along the x-direction), a gate structure (125), a gate stack (130) (including a gate dielectric (132), a gate charge (134), and a hard mask (136), a gate spacer (140) (viewable along the x-direction), a dielectric layer (150) (including a CESL (152) and an ILD layer (154)) (viewable along the x-direction), etc. FIGS. 13a through 13d are partial or full enlarged views of different configurations of a portion (I5) of a transistor (300) that may include a laminated dielectric film, according to various embodiments of the present disclosure. FIGS. 12 and FIGS. 13a through 13d are discussed together in this specification for convenience of explanation and understanding. FIGS. 12 and FIGS. 13a through 13d are simplified for clarity to better understand the concept of the invention of the present disclosure. Additional features may be added to the device (300), and some of the features described below may be replaced, modified, or removed in other embodiments of the device (300).

[0046] The device (300) further includes a substrate isolation structure (325) that electrically isolates an active region from an adjacent active region. For example, the substrate isolation structure (325) can separate and electrically isolate the active region of the transistor (T1) from the active region of the transistor (T2) (e.g., its fin structure (102'). The substrate isolation structure (325) comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.), or a combination thereof. The substrate isolation structure (325) may have a multilayer structure. For example, the substrate isolation structure (325) may include a bulk dielectric (e.g., an oxide layer) on a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof). In another example, the substrate isolation structure (325) may include a dielectric layer on a doped liner such as a boron silicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner. The dimensions and / or characteristics of the substrate isolation structure (325) are shallow It is configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof. In the illustrated embodiment, the substrate isolation structure (325) may be an STI placed on the substrate (102).

[0047] The device (300) further comprises a gate isolation structure (350) comprising a gate isolation liner (352) and a gate isolation bulk layer (354). The gate bulk isolation layer (354) comprises any suitable dielectric material (e.g., a low-k dielectric material) as described herein. In some embodiments, the gate isolation liner (352) has a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (352a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (352b) (see FIG. 13a through 13d). The crystalline boron nitride layer (352a) is similar to the crystalline boron nitride layer (15) as described herein, and the amorphous boron nitride layer (352b) is similar to the amorphous boron nitride layer (20) as described herein. In some embodiments, the gate isolation liner (352) having a boron- and nitrogen-containing laminate structure has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0048] The boron- and nitrogen-containing laminate structure of the gate isolation liner (352) may have various configurations as described in FIGS. 13a through 13d. For example, referring to FIG. 13a, the boron- and nitrogen-containing laminate structure of the gate isolation liner (352) may include an amorphous boron nitride layer (352b) disposed between crystalline boron nitride layers (352a). In this example, the crystalline boron nitride layer (352a) includes a gate stack (130) (e.g., its gate dielectric (132) and / or gate electrode (134)), a gate isolation bulk layer (354), and a substrate isolation structure (325). In another example, referring to FIG. 13b, the boron-and-nitrogen containing laminate structure of the gate spacer (352) may include a crystalline boron nitride layer (352a) disposed between amorphous boron nitride layers (352b). In this example, the amorphous boron nitride layer (352b) is adjacent to the gate stack (130), the gate isolation bulk layer (35), and the substrate isolation structure (325). In another example, referring to FIG. 13c and FIG. 13d, the boron-and-nitrogen containing laminate structure of the gate isolation liner (352) may include a single crystalline boron nitride layer (352a) and a single amorphous boron nitride layer (352b). In an embodiment of this example, as shown in FIG. 13c, the amorphous boron nitride layer (352b) may be adjacent to the gate stack (130) and the substrate isolation structure (325), while the crystalline boron nitride layer (352a) may be adjacent to the gate isolation bulk layer (354). In another embodiment of this example, as shown in FIG. 13d, the crystalline boron nitride layer (352a) may be adjacent to the gate stack (130) and the substrate isolation structure (325), while the amorphous boron nitride layer (352b) may be adjacent to the gate isolation bulk layer (354).In another example, the boron- and nitrogen-containing laminate structure of the gate isolation liner (352) may comprise a plurality of crystalline boron nitride layers (352a) interleaved by an amorphous boron nitride layer (352b). For example, as described herein, the boron- and nitrogen-containing laminate structure may be composed of a laminated dielectric film (10).

[0049] FIG. 14 is a partial or complete cross-sectional view of a device (400) that may include a laminated dielectric film such as the laminated dielectric film (10) described with reference to FIG. 1 through 5 and / or other laminated dielectric films described herein, depending on various aspects of the present disclosure. The device (40) is similar to the device (300) in many respects. Accordingly, similar features of the device (400) and the device (300) are identified by the same reference numeral for clarity and simplicity. For example, the device (400) includes transistors (T1) and transistors (T2), each of which includes a portion of each substrate (102), a pin structure (102'), a channel (110) (including a channel layer (110A) and a channel layer (110B)), a source / drain (120) (viewable along the x-direction), a gate structure (125), a gate stack (130) (including a gate dielectric (132), a gate electrode (134), and a hard mask (136), a gate spacer (140) (viewable along the x-direction), a dielectric layer (150) (including a CESL (152) and an ILD layer (154)) (viewable along the x-direction), a substrate isolation structure (325), etc. FIGS. 15a through 15d are partial or full enlarged views of different configurations of a portion (I6) of a device (400) that may include a laminated dielectric film, according to various embodiments of the present disclosure. FIGS. 14 and FIGS. 15a through 15d are discussed together in this specification for convenience of explanation and understanding. FIGS. 14 and FIGS. 15a through 15d are simplified for clarity to better understand the concept of the invention of the present disclosure. Additional features may be added to the device (400), and some of the following features may be replaced, modified, or removed in other embodiments of the device (400).

[0050] The device (400) further includes a gate isolation structure (450). The gate isolation structure (450) is placed over the substrate isolation structure (325). In some embodiments, the gate isolation structure (450) extends into the substrate isolation structure (325) as illustrated. In some embodiments, the gate isolation structure (450) extends into the substrate (102) as illustrated. In some embodiments, a dielectric layer (452) may be placed between the gate isolation structure (450) and the gate stack (130) (e.g., its sidewall). In some embodiments, the dielectric layer (452) extends into the substrate isolation structure (325) as illustrated. The dielectric layer (452) comprises any suitable dielectric material (e.g., a low-k dielectric material) as described herein.

[0051] In some embodiments, the gate isolation structure (450) has a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (450a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (450b) (see FIG. 15a through 15d). The crystalline boron nitride layer (450a) is similar to the crystalline boron nitride layer (15) as described herein, and the amorphous boron nitride layer (450b) is similar to the amorphous boron nitride layer (20) as described herein. In some embodiments, as in (450), a CESL having a boron- and nitrogen-containing laminate structure has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0052] The boron-and-nitrogen containing laminate structure of the gate isolation structure (352) may have various configurations as described in FIGS. 15a through 15d. For example, referring to FIG. 15a, the boron-and-nitrogen containing laminate structure of the gate spacer (450) may include an amorphous boron nitride layer (450b) disposed between crystalline boron nitride layers (450a). In this example, the crystalline boron nitride layer (450a) may be adjacent to the dielectric layer (452) and the substrate isolation structure (325). In some embodiments, the dielectric layer (452) is omitted, and the crystalline boron nitride layer (450a) is a gate stack (130) (e.g., its gate dielectric (132) and / or gate electrode (134)). In another example, referring to FIG. 15b, the boron-and-nitrogen containing laminate structure of the gate spacer (450) may include a crystalline boron nitride layer (450a) disposed between amorphous boron nitride layers (450b). In this example, the amorphous boron nitride layer (450b) is adjacent to the dielectric layer (452) and the substrate isolation structure (325). In some embodiments, if the dielectric layer (452) is omitted, the amorphous boron nitride layer (450) may be adjacent to the gate stack (130). In another example, referring to FIG. 15c and FIG. 15d, the boron-and-nitrogen containing laminate structure of the gate spacer (450) may include a single crystalline boron nitride layer (450a) and a single amorphous boron nitride layer (450b). In some embodiments of these examples, as shown in FIG. 15c, the amorphous boron nitride layer (450b) may be adjacent to the dielectric layer (452) (or the gate stack (130) with the dielectric layer (452) omitted) and the substrate isolation structure (325). In other embodiments of these examples, as shown in FIG. 15d, the crystalline boron nitride layer (450a) may be adjacent to the dielectric layer (452) (or the gate stack (130) with the dielectric layer (452) omitted) and the substrate isolation structure (325).In another example, the boron- and nitrogen-containing laminate structure of the gate isolation structure (450) may comprise a plurality of crystalline boron nitride layers (450a) interleaved by an amorphous boron nitride layer (450b). For example, as described herein, the boron- and nitrogen-containing laminate structure may be composed of a laminated dielectric film (10).

[0053] FIG. 16 is a partial or complete cross-sectional view of a device (500) that may include a laminated dielectric film such as the laminated dielectric film (10) described with reference to FIG. 1 through 5 and / or other laminated dielectric films described herein, according to various embodiments of the present disclosure. FIG. 17a through 17d are partial or complete enlarged views of different configurations of a portion (I7) of a transistor (500) that may include a laminated dielectric film, according to various embodiments of the present disclosure. FIG. 16 and FIG. 17a through 17d are discussed together in this specification for convenience of explanation and understanding. FIG. 16 and FIG. 17a through 17d are simplified for clarity to better understand the concept of the invention of the present disclosure. Additional features may be added to the stacked device structure (500), and some of the features described below may be replaced, modified, or removed in other embodiments of the stacked device structure (500).

[0054] The device (500) may include a device stack, such as a transistor stack, in which an upper device, such as an upper transistor (TU), is vertically stacked on top of a lower device, such as a lower transistor (TL). The upper transistor (TU) and the lower transistor (TL) may be separated from each other and / or electrically isolated by an isolation structure (502) as described below. In some embodiments, the lower transistor (TL) and the upper transistor (TU) are transistors of opposite electrical conductivity types. For example, the lower transistor (TL) is a p-type transistor and the upper transistor (TU) is an n-type transistor, or vice versa. In these embodiments, the lower transistor (TL) and the upper transistor (TU) may form a CFET. In some embodiments, the lower transistor (TL) and the upper transistor (TU) are transistors of the same electrical conductivity type. For example, both the lower transistor (TL) and the upper transistor (TU) are n-type transistors or p-type transistors.

[0055] The upper transistor (TU) includes various features and / or components such as a semiconductor layer (526U), a semiconductor layer (526M), a gate spacer (544), an inner spacer (554), a source / drain (562U), a contact etching stop layer (CESL) (570U), an interlayer dielectric (ILD) structure (572U) (collectively forming a gate stack (590U)), a gate dielectric (578U), a gate electrode (580U), and a hard mask (592). The lower transistor (TL) also includes a protrusion (520') (which may be an extension of the substrate (520)), a semiconductor layer (526L), a semiconductor layer (526M), a substrate isolation structure, an inner spacer (554), a source / drain (562L), a CESL (570L), an ILD layer (572L), and a gate dielectric (578L) and a gate electrode (580L) (collectively forming a gate stack (590L)). The source / drain (562U) and the source / drain (562L) may be collectively referred to as the source / drain (562). The individual gate stack (590U) and the individual gate stack (590L) may be collectively referred to as the gate (590) of the transistor stack. As described, there may be an isolation structure (502) between the upper transistor (TU) and the lower transistor (TL). In the illustrated embodiment, the isolation structure (502) comprises an isolation structure (502A) positioned therebetween to isolate the gate stack (590U) from the gate stack (590L), and an isolation structure (502B) positioned therebetween to isolate the source / drain (562U) from the source / drain (562L) (formed by the CESL (570L) and the ILD layer (572L)). The isolation structure (502A) can thus function as a channel isolation structure and / or a gate isolation structure, and the isolation structure (502B) can thus function as a source / drain isolation structure.

[0056] In some embodiments, the isolation structure (502A) has a boron- and nitrogen-containing laminate structure. The boron- and nitrogen-containing laminate structure has at least one crystalline boron nitride layer (502a), such as a hexagonal boron nitride layer, and at least one amorphous boron nitride layer (502b) (see FIG. 17a through 17d). The crystalline boron nitride layer (502a) is similar to the crystalline boron nitride layer described herein, such as the crystalline boron nitride layer (15), and the amorphous boron nitride layer (502b) is similar to the amorphous boron nitride layer described herein, such as the amorphous boron nitride layer (20). In some embodiments, the isolation structure (502A) having the boron- and nitrogen-containing laminate structure has a dielectric constant (k) of about 3. As in 3), it has a dielectric constant of about 1.8 to about 8.6 (1.8 ≤ k ≤ 8.6).

[0057] The boron-and-nitrogen containing laminate structure (502A) of the isolation structure (502A) may have various configurations as described in FIGS. 17a to 17b. For example, referring to FIG. 17a, the boron-and-nitrogen containing laminate structure of the isolation structure (502A) may include an amorphous boron nitride layer (502b) disposed between crystalline boron nitride layers (502a). In this example, the crystalline boron nitride layer (502a) may be adjacent to the semiconductor layer (526M) and CESL (570L). In another example, referring to FIG. 17b, the boron-and-nitrogen containing laminate structure of the isolation structure (502A) may include a crystalline boron nitride layer (502a) disposed between amorphous boron nitride layers (502b). In this example, the amorphous boron nitride layer (502b) is adjacent to the semiconductor layer (526M) and CESL (570L). In another example, referring to FIGS. 17c and 17d, the boron- and nitrogen-containing laminate structure (502A) of the gate spacer (140) may include a single crystalline boron nitride layer (502a) and a single amorphous boron nitride layer (502b). For example, the amorphous boron nitride layer (502b) and the crystalline boron nitride layer (502a) may be adjacent to the semiconductor layer (526M) and CESL (570L). In another example, the boron- and nitrogen-containing laminate structure of the isolation structure (502A) may comprise a plurality of crystalline boron nitride layers (502a) interleaved by an amorphous boron nitride layer (502b). For example, the boron- and nitrogen-containing laminate structure may be composed of a laminated dielectric film (10).

[0058] In the illustrated embodiment, the lower transistor (TL) is a GAA transistor. For example, the lower transistor (TL) has two channels (also referred to as channel layers or channels) provided by a semiconductor layer (526L), which are suspended on a substrate (520) and extend between each source / drain (e.g., source / drain (562L)). In some embodiments, the lower transistor (TL) includes more or fewer channels (and thus more or fewer semiconductor layers (526L)). The lower transistor (TL) also has a gate stack (590L) placed on and engaged with the semiconductor layer (526L). The gate stack (590L) is placed between the source / drains (562L), and an inner spacer (554) is placed between the gate stack (590L) and the source / drain (562L). Along the gate width direction (e.g., in the YZ plane), the gate stack (590L) is positioned on the upper semiconductor layer (526L), between the semiconductor layers (526L), and between the lower semiconductor layer (526L) and the substrate (520). Along the gate length direction (e.g., in the XZ plane), the gate stack (590L) wraps around the semiconductor layer (526L). During the operation of the GAA transistor, current can flow through the semiconductor layer (526L) and the source / drain (562L). The semiconductor layer (526M) (also referred to as a dummy channel layer or dummy channel) is suspended on the substrate (520), extends between each isolation structure (502B) and isolation structure (502A), and is positioned on the semiconductor layer (526M) between the lower transistor (TL) and the upper transistor (TU).

[0059] In the illustrated embodiment, the upper transistor (TU) is also a GAA transistor. For example, the upper transistor (TU) has two channels provided by a semiconductor layer (526U) (also referred to as a channel layer or channel), which are suspended on a substrate (520) and extend between each source / drain (e.g., source / drain (562U)). In some embodiments, the upper transistor (TU) includes more or fewer channels / semiconductor layers (526U). The upper transistor (TU) also has a gate stack (590U) disposed on and engaged with the semiconductor layer (526U). A gate stack (590U) is positioned between source / drain (562U), a gate stack (590U) is positioned between each gate spacer (544), an inner spacer (554) is positioned between the gate stack (590U) and the source / drain (562U), and a hard mask (592) is positioned on the gate stack (590U). Along the gate width direction, the gate stack (590U) is positioned on the upper semiconductor layer (526U), between the semiconductor layers (526U), and between the lower semiconductor layer (526U) and the semiconductor layer (526M). Along the gate length direction, the gate stack (590U) wraps around the semiconductor layer (526U). During the operation of the GAA transistor, current can flow through the semiconductor layer (526U) and the source / drain (562U).

[0060] The substrate (520) may be configured similarly to the substrate (102) described herein, and the protrusion (520') may be configured similarly to the protrusion and / or pin structure (102') described herein. The semiconductor layer (526U), semiconductor layer (526M), and semiconductor layer (526L) (collectively referred to as semiconductor layer (526)) may include elemental semiconductors such as silicon and / or germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors such as SiGe, GaAsP, ALInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the illustrated embodiment, the substrate (520), semiconductor layer (526U), semiconductor layer (526M), and semiconductor layer (526L) comprise silicon. In some embodiments, the semiconductor layer (526U) and the semiconductor layer (526L) each comprise different semiconductor materials, such as silicon and silicon germanium, or vice versa.

[0061] A gate spacer (544) is positioned along the upper sidewall of the gate stack (590U), an inner spacer (554) is positioned below the gate spacer (544) along the sidewall of the gate stack (590U) and / or the gate stack (590L), and a pin / protrusion spacer may be positioned along the sidewall of the protrusion (520'). The inner spacer (554) is positioned between the semiconductor layers (526) and between the bottom semiconductor layer (526) and the protrusion (520'). The gate spacer (544), the inner spacer (554), and the pin spacer comprise a dielectric material, which may comprise silicon, oxygen, carbon, nitrogen, other suitable dielectric compositions, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbonitride, or a combination thereof). The gate spacer (544), inner spacer (554), and pin spacer may comprise different materials and / or different configurations (e.g., different number of layers). In some embodiments, the gate spacer (544), pin spacer (554), pin spacer, or combination thereof have a multilayer structure. In some embodiments, the gate spacer (544) and / or pin spacer comprises more than one set of spacers, such as a seal spacer, offset spacer, sacrificial spacer, dummy spacer, main spacer, or combination thereof. Various sets of spacers may have different compositions. In some embodiments, the gate spacer (544) is similar to the gate spacer (140) described herein (e.g., the gate spacer (544) may have a boron- and nitrogen-containing laminate structure). In some embodiments, the inner spacer (554) is similar to the inner spacer (240) described herein (e.g., the inner spacer (240) may have a boron- and nitrogen-containing laminated structure).

[0062] A gate (590) is disposed between source / drain stacks. Each source / drain stack includes each source / drain (562U), each source / drain (562L), and each isolation structure (502A) disposed between them. The source / drain (562L) and the source / drain (562U) comprise semiconductor materials, and the source / drain (562L) and the source / drain (562U) may be doped with an n-type dopant and / or a p-type dopant. In some embodiments, the source / drain (562L) and the source / drain (562U) may be formed from epitaxially grown / deposited semiconductor material(s), and the source / drain (562L) and the source / drain (562U) may be referred to as epitaxial source / drains. Source / drain (562L) and source / drain (562U) may have the same or different composition and / or material depending on the configuration of each of these transistors. In some embodiments (e.g., when forming part of an n-type transistor), source / drain (562L) and / or source / drain (562U) comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C: epitaxial source / drain). In some embodiments (e.g., when forming part of a p-type transistor), source / drain (562L) and / or source / drain (562U) comprise silicon germanium or germanium doped with boron, other p-type dopants, or a combination thereof (e.g., Si:Ge:B epitaxial source / drain). In some embodiments, the source / drain (562L) comprises silicon germanium doped with boron, and the source / drain (562U) comprises silicon doped with phosphorus, or vice versa. In some embodiments, a doped region, such as a heavily doped source / drain (HDD) region, a lightly doped source / drain (LDD) region, other doped regions, or a combination thereof, is placed in the source / drain (562L) and / or source / drain (562U).In some embodiments, the source / drain (562L) and / or the source / drain (562U) comprise a plurality of semiconductor layers, and the semiconductor layers may comprise the same or different materials, compositions, dopant types, dopant concentrations, thicknesses, etc. In some embodiments, the source / drain (562L) and / or the source / drain (562U) comprise a material and / or dopant that achieves a desired tensile stress and / or compressive stress in an adjacent channel region (e.g., formed by the semiconductor layer (526U) and the semiconductor layer (526L)). As used in this specification, source / drain regions, source / drain, epitaxial source / drain, epitaxial source / drain features, etc. may refer to the source of a device (e.g., upper transistor (TU) and / or lower transistor (TL)), the drain of a device (e.g., upper transistor (TU) and / or lower transistor (TL)), or the source and / or drain of a plurality of devices.

[0063] The ILD layer (572U) and the ILD layer (572L) comprise a dielectric material as described herein. The CESL (570L) and the CESL (570U) each comprise a dielectric material different from the material of the ILD layer (572L) and the ILD layer (572U). The ILD layer (572U) and / or the ILD layer (572L) may be configured similarly to the ILD layer described herein (e.g., ILD layer (154)). The CESL (570U) and / or the CESL (570L) may be configured similarly to the CESL described herein (e.g., CESL (152)). In some embodiments, the CESL (570U) and / or the CESL (570L) have a boron- and nitrogen-containing laminate structure as described with reference to the CESL (152).

[0064] The gate dielectric (578U) and the gate dielectric (578L) each comprise at least one dielectric gate layer. The gate dielectric (578U) and the gate dielectric (578L) may be collectively referred to as the gate dielectric (578). The gate electrode (580U) and the gate electrode (580L) are each disposed on the gate dielectric (578U) and the gate dielectric (578L), respectively. The gate dielectric (578U) and the gate dielectric (578L) may have the same or different composition, material, layer, configuration, or combination thereof. The gate electrode (580U) and the gate electrode (580L) may have the same or different composition, material, layer, configuration, or combination thereof. The gate electrode (580U) and the gate electrode (580L) each comprise at least one electrically conductive gate layer formed of an electrically conductive material. The gate dielectric (578U) and / or the gate dielectric (578L) may be similar to the gate dielectric (132) described herein. The gate electrode (580U) and / or the gate electrode (580L) may be similar to the gate electrode (134) described herein.

[0065] The hard mask (592) comprises a material different from the ILD layer (572U) and / or the subsequently formed ILD layer to achieve an etching selectivity ratio during a subsequent etching process. In some embodiments, the hard mask (592) comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, other silicon nitride, other silicon carbide, or a combination thereof. In some embodiments, the hard mask (592) comprises metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al_2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HfO_2), zirconium aluminum oxide (e.g., ZrAlO), other metal oxide, other metal nitride, or a combination thereof. In some embodiments, the dielectric constant of the hard mask (592) is greater than the dielectric constant of the isolation structure (502A), the dielectric constant of the ILD layer (572U), the dielectric constant of the CESL (570L), the dielectric constant of the gate spacer (544), or a combination thereof.

[0066] The present disclosure provides many different embodiments. An exemplary device comprises a dielectric layer having a laminate structure. The laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer. In some embodiments, the crystalline boron nitride layer is a hexagonal boron nitride layer. In some embodiments, the thickness of the crystalline boron nitride is greater than the thickness of the amorphous boron nitride layer. In some embodiments, the crystalline boron nitride layer is a first crystalline boron nitride layer, and the laminate structure further comprises a second crystalline boron nitride layer, and the amorphous boron nitride layer is disposed between the first crystalline boron nitride layer and the second crystalline boron nitride layer. In some embodiments, the first crystalline boron nitride layer and the second crystalline boron nitride layer are hexagonal boron nitride layers.

[0067] In some embodiments, the dielectric layer is a gate spacer. In some embodiments, the dielectric layer is an inner spacer. In some embodiments, the dielectric layer is a contact etching stop layer. In some embodiments, the dielectric layer is a gate isolation layer.

[0068] An exemplary transistor comprises a channel, a first source / drain, and a second source / drain. The channel is located between the first source / drain and the second source / drain. The transistor comprises a gate stack disposed over the channel and a laminated boron nitride gate spacer disposed along the sidewall of the gate stack. In some embodiments, each laminated boron nitride gate spacer comprises a crystalline boron nitride layer and an amorphous boron nitride layer. In some embodiments, the amorphous boron nitride layer is located between each sidewall of the gate stack and the crystalline boron nitride layer. In some embodiments, the crystalline boron nitride layer is located between each sidewall of the gate stack and the amorphous boron nitride layer. In some embodiments, each laminated boron nitride gate spacer comprises an amorphous boron nitride layer between the first crystalline boron nitride layer and the second crystalline boron nitride layer. In some embodiments, each laminated boron nitride gate spacer comprises a crystalline boron nitride layer between a first amorphous boron nitride layer and a second amorphous boron nitride layer. In some embodiments, each laminated boron nitride gate spacer comprises at least two crystalline boron nitride layers and at least one amorphous boron nitride layer.

[0069] An exemplary method comprises forming a dielectric layer having a laminate structure. The laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer. In some embodiments, the dielectric layer is a gate spacer, and forming the dielectric layer comprises forming a gate spacer along the sidewall of the gate stack. In some embodiments, the amorphous boron nitride layer is disposed between the sidewall of the gate stack and the crystalline boron nitride layer. In some embodiments, the crystalline boron nitride layer is disposed between the sidewall of the gate stack and the amorphous boron nitride layer. In some embodiments, forming the dielectric layer comprises performing a deposition process, and the deposition process implements a borazine precursor. In some embodiments, the deposition process also implements a nitrogen-containing plasma. In some embodiments, the deposition process implements a deposition temperature of about 200 °C to about 400 °C.

[0070] The foregoing is an overview of the features of some embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or to achieve the same effects as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations of the present invention can be made without departing from the spirit and scope of the present disclosure.

[0071] [Example 1]

[0072] In the device structure,

[0073] Includes a device, and the device,

[0074] Active region - The active region includes the channel region located between the source / drain regions - ,

[0075] A gate stack placed over the channel region, and

[0076] It includes an interconnect structure placed on top of a gate stack, and

[0077] A part of the device is formed by a dielectric layer having a laminate structure, and the laminate structure is,

[0078] Crystalline boron nitride layer, and

[0079] Amorphous boron nitride layer

[0080] A device structure that includes

[0081] [Example 2]

[0082] A device structure in which, in the first embodiment, the crystalline boron nitride layer is a hexagonal boron nitride layer.

[0083] [Example 3]

[0084] In the first embodiment,

[0085] The crystalline boron nitride layer is the first crystalline boron nitride layer, and

[0086] A device structure wherein the laminate structure further comprises a second crystalline boron nitride layer, and the amorphous boron nitride layer is disposed between the first crystalline boron nitride layer and the second crystalline boron nitride layer.

[0087] [Example 4]

[0088] A device structure in which, in the third embodiment, the first crystalline boron nitride layer and the second crystalline boron nitride layer are hexagonal boron nitride layers.

[0089] [Example 5]

[0090] A device structure in which, in the first embodiment, the thickness of the crystalline boron nitride layer is greater than the thickness of the amorphous boron nitride layer.

[0091] [Example 6]

[0092] In the first embodiment, the device further comprises a gate spacer disposed along the sidewall of the gate stack, and the gate spacer is part of the device formed by the dielectric layer, the device structure.

[0093] [Example 7]

[0094] In the first embodiment, the device further comprises an inner spacer disposed between a gate stack and a source / drain region, wherein the inner spacer is part of the device formed by a dielectric layer, the device structure.

[0095] [Example 8]

[0096] A device structure according to the first embodiment, wherein the device further comprises a contact etching stop layer disposed over a source / drain region, and the contact etching stop layer is part of the device formed by a dielectric layer.

[0097] [Example 9]

[0098] In the first embodiment, the device further comprises a gate isolation layer disposed adjacent to a gate stack, and the gate isolation layer is part of the device formed by a dielectric layer, the device structure.

[0099] [Example 10]

[0100] In transistors,

[0101] channel;

[0102] First source / drain and second source / drain - the channel is between the first source / drain and the second source / drain - ;

[0103] A gate stack placed over a channel - the gate stack includes a gate dielectric and a gate electrode, and the gate electrode is placed over the gate dielectric - ; and

[0104] Laminated boron nitride gate spacers positioned along the sidewalls of the gate stack

[0105] A transistor comprising, wherein the dielectric constant of the gate dielectric is greater than the dielectric constant of the laminated boron nitride gate spacer.

[0106] [Example 11]

[0107] A transistor in the 10th embodiment, wherein each laminated boron nitride gate spacer comprises a crystalline boron nitride layer and an amorphous boron nitride layer.

[0108] [Example 12]

[0109] A transistor in the 11th embodiment, wherein the amorphous boron nitride layer is located between each sidewall of the gate stack and the crystalline boron nitride layer.

[0110] [Example 13]

[0111] A transistor in the 11th embodiment, wherein the crystalline boron nitride layer is located between each sidewall of the gate stack and the amorphous boron nitride layer.

[0112] [Example 14]

[0113] A transistor in the 10th embodiment, wherein each laminated boron nitride gate spacer comprises an amorphous boron nitride layer between a first crystalline boron nitride layer and a second crystalline boron nitride layer.

[0114] [Example 15]

[0115] A transistor in the 10th embodiment, wherein each laminated boron nitride gate spacer comprises a crystalline boron nitride layer between a first amorphous boron nitride layer and a second amorphous boron nitride layer.

[0116] [Example 16]

[0117] In terms of the method,

[0118] The device includes the step of forming a device, and the device is,

[0119] Active region - The active region includes the channel region located between the source / drain regions - ,

[0120] A gate stack placed over the channel region, and

[0121] Interconnected structures placed on top of gate stacks

[0122] Includes,

[0123] A method comprising the step of forming a device, wherein a portion of the device is formed by a dielectric layer having a laminate structure, and the laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer.

[0124] [Example 17]

[0125] In the 16th embodiment, the device further comprises a gate spacer disposed along the sidewall of the gate stack, the gate spacer is part of the device formed by a dielectric layer, and the amorphous boron nitride layer is disposed between the sidewall of the gate stack and the crystalline boron nitride layer.

[0126] [Example 18]

[0127] In the 16th embodiment, the device further comprises a gate spacer disposed along the sidewall of the gate stack, the gate spacer is part of the device formed by a dielectric layer, and the crystalline boron nitride layer is disposed between the sidewall of the gate stack and the amorphous boron nitride layer.

[0128] [Example 19]

[0129] In the 16th embodiment, the step of forming a dielectric layer comprises performing a deposition process, wherein the deposition process implements a borazine precursor and a nitrogen-containing plasma.

[0130] [Example 20]

[0131] In the 19th embodiment, the deposition process implements a deposition temperature of about 200°C to about 400°C.

Claims

Claim 1 A device structure comprising a device, wherein the device comprises an active region—the active region comprises a channel region disposed between source / drain regions—a gate stack disposed over the channel region, and an interconnect structure disposed over the gate stack, wherein a portion of the device is formed by a dielectric layer having a laminate structure, and wherein the laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer, and wherein the thickness of the crystalline boron nitride layer is greater than the thickness of the amorphous boron nitride layer. Claim 2 A device structure according to claim 1, wherein the crystalline boron nitride layer is a hexagonal boron nitride layer. Claim 3 A device structure comprising a device, wherein the device comprises an active region—the active region comprises a channel region disposed between source / drain regions—a gate stack disposed over the channel region, and an interconnect structure disposed over the gate stack, wherein a portion of the device is formed by a dielectric layer having a laminate structure, wherein the laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer, wherein the crystalline boron nitride layer is a first crystalline boron nitride layer, and the laminate structure further comprises a second crystalline boron nitride layer, and wherein the amorphous boron nitride layer is disposed between the first crystalline boron nitride layer and the second crystalline boron nitride layer. Claim 4 delete Claim 5 A device structure according to claim 1, wherein the device further comprises a gate spacer disposed along the sidewall of the gate stack, and the gate spacer is part of the device formed by the dielectric layer. Claim 6 A device structure according to claim 1, wherein the device further comprises an inner spacer disposed between the gate stack and the source / drain regions, and the inner spacer is part of the device formed by the dielectric layer. Claim 7 A device structure according to claim 1, wherein the device further comprises a contact etching stop layer disposed over the source / drain region, and the contact etching stop layer is part of the device formed by the dielectric layer. Claim 8 A device structure according to claim 1, wherein the device further comprises a gate isolation layer disposed adjacent to the gate stack, and the gate isolation layer is a part of the device formed by the dielectric layer. Claim 9 A transistor comprising: a channel; a first source / drain and a second source / drain, wherein the channel is located between the first source / drain and the second source / drain; a gate stack disposed over the channel, wherein the gate stack comprises a gate dielectric and a gate electrode, and the gate electrode is disposed over the gate dielectric; and a laminated boron nitride gate spacer disposed along the sidewall of the gate stack, wherein the dielectric constant of the gate dielectric is greater than the dielectric constant of the laminated boron nitride gate spacer, and the laminated boron nitride gate spacer comprises a crystalline boron nitride layer and an amorphous boron nitride layer, wherein the thickness of the crystalline boron nitride layer is greater than the thickness of the amorphous boron nitride layer. Claim 10 A method comprising the step of forming a device, wherein the device comprises an active region—the active region comprises a channel region disposed between source / drain regions—a gate stack disposed over the channel region, and an interconnect structure disposed over the gate stack, wherein the step of forming the device comprises the step of forming a portion of the device by a dielectric layer having a laminate structure, wherein the laminate structure comprises a crystalline boron nitride layer and an amorphous boron nitride layer, and the thickness of the crystalline boron nitride layer is greater than the thickness of the amorphous boron nitride layer.

Images