Nonvolatile memory device providing input / output compatibility and method for setting compatibility thereof

Abstract

A non-volatile memory device for receiving a data signal (DQ) and a data strobe signal (DQS) from an external source according to the present invention comprises: a variable sampler that processes the data signal (DQ) in amplifier mode or sampler mode in response to a control signal; a selection circuit that transmits the data signal (DQ) output from the variable sampler to an output flip-flop via a delay unit or transmits it to the output flip-flop by bypassing the delay unit in response to the control signal; a converter that amplifies the data strobe signal (DQS); a clock distribution network that transmits the data strobe signal (DQS) amplified by the converter to the variable sampler or transmits the amplified data strobe signal (DQS) to the output flip-flop after a specific time delay in response to the control signal; and a path controller that generates the control signal according to an input / output mode.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a non-volatile memory device that provides input / output compatibility and a method for setting the compatibility thereof. Background Technology

[0002] Recently, various mobile and electronic devices such as smartphones, desktop computers, laptop computers, tablet PCs, and wearable devices are widely used. These electronic devices generally include storage devices for storing data. In particular, following the trend toward larger capacity and higher speeds in these electronic devices, there have been many efforts to increase the capacity of storage devices and improve their speed.

[0003] Flash memory devices, which are non-volatile memory, are utilized as storage in various fields ranging from mobile devices to computer systems. Driven by technological advancements and the demand for improved performance, the data input / output speeds of flash memory devices are rapidly increasing. In particular, vertically stacked V-NAND flash memory is showing a trend of rapidly increasing input / output operation speeds as it undergoes successive generations of development.

[0004] Input / output circuits responsible for NAND flash memory input / output have been using a matched type structure in which the delays of the data signal (DQ) and strobe signal (DQS) are pre-set. However, with the increase in input / output speeds, there is a need for input / output circuits to use an unmatched type structure suitable for high-speed input / output. In unmatched type input / output circuits, alignment of the data signal (DQ) and strobe signal (DQS) is achieved through training performed during booting.

[0005] When using unmatched I / O circuits, the data signal (DQ) can reach the sampler (or latch) via the shortest path. Therefore, unmatched I / O circuits can minimize jitter of the data signal (DQ) and allow for the application of filters that can immediately compensate for inter-symbol interference (ISI). Consequently, unmatched I / O circuits are suitable for high-speed I / O operations.

[0006] With the increase in I / O speeds in flash memory devices, unmatched I / O circuits must be applied. However, even if I / O circuits are implemented as unmatched types suitable for high-speed operation, they must be usable with hosts or memory controllers that use legacy protocols. There is a rapidly increasing demand for flash memory devices that can provide this compatibility. Prior art literature

[0007] (1) Korean Published Patent Application 10-2022-0058970 (May 10, 2022)(2) U.S. Registered Patent Application US 9,014,252 (April 21, 2015)(3) Korean Registered Patent Application 10-1948224 (February 8, 2019) The problem to be solved

[0008] The objective of the present invention is to provide a non-volatile memory device that provides input / output compatibility and a method for setting the compatibility thereof. means of solving the problem

[0009] A non-volatile memory device according to the present invention for receiving a data signal (DQ) and a data strobe signal (DQS) from an external source to achieve the above objective comprises: a variable sampler that processes the data signal (DQ) in amplifier mode or sampler mode in response to a control signal; a selection circuit that transmits the data signal (DQ) output from the variable sampler to an output flip-flop via a delay unit or transmits it to the output flip-flop by bypassing the delay unit in response to the control signal; a converter that amplifies the data strobe signal (DQS); a clock distribution network that transmits the data strobe signal (DQS) amplified by the converter to the variable sampler or transmits the amplified data strobe signal (DQS) to the output flip-flop after a specific time delay in response to the control signal; and a path controller that generates the control signal according to an input / output mode.

[0010] A non-volatile memory device according to the present invention for achieving the above objective comprises a compatible input / output circuit that aligns the delays of the data signal and the data strobe signal by setting the path of the data signal (DQ) and the path of the data strobe signal (DQS) to either a matched mode or an unmatched mode according to an input / output mode, and a memory core that includes a memory cell that stores a data signal sampled from the compatible input / output circuit, wherein in the unmatched mode, the delays of the data signal or the data strobe signal are aligned through training.

[0011] A method for setting compatibility of a non-volatile memory device according to the present invention for achieving the above objective comprises: receiving an input / output mode of a data signal from an external source; setting the path of the data signal and the data strobe signal of the input / output circuit of the non-volatile memory device to a matched type or an unmatched type according to the received input / output mode; and, when the input / output circuit is set to the unmatched type, performing training to align the data signal and the data strobe signal of the input / output circuit. Effects of the invention

[0012] According to the above-described embodiment of the present invention, a non-volatile memory device capable of high-speed input / output can be installed in legacy devices using existing low-speed interfaces. Accordingly, the non-volatile memory device of the present invention can provide high compatibility, allowing it to be installed in hosts regardless of the generation of the flash memory device. Brief explanation of the drawing

[0013] FIG. 1 is a block diagram showing a storage device including a non-volatile memory device according to an embodiment of the present invention. FIG. 2 is a block diagram exemplarily showing the configuration of the non-volatile memory device of FIG. 1. FIG. 3 is a block diagram briefly showing one embodiment of the compatible input / output device of FIG. 2. FIG. 4 is a diagram showing the paths of the data signal (DQ) and the data strobe signal (DQS) in the matched mode of the compatible input / output circuit of the present invention, respectively. FIG. 5 is a diagram showing the paths of the data signal (DQ) and the data strobe signal (DQS) in the unmatched mode of the compatible input / output circuit of the present invention, respectively. FIG. 6 is a flowchart briefly showing the path selection operation of a compatible input / output circuit of a non-volatile memory device according to an embodiment of the present invention. Figure 7 schematically shows an exemplary structure of the non-volatile memory device of Figure 2. FIG. 8 is a circuit diagram showing an exemplary structure of a memory block constituting the cell array of FIG. 2. FIG. 9 is a block diagram showing a compatible input / output circuit according to another embodiment of the present invention. FIG. 10 is a block diagram showing a storage device according to another embodiment of the present invention. FIG. 11 is a drawing for explaining a memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0014] It should be understood that both the foregoing general description and the following detailed description are exemplary and should be considered as providing additional description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the invention, and examples thereof are shown in the reference drawings. Where possible, the same reference numerals are used in the description and drawings to refer to the same or similar parts.

[0015] FIG. 1 is a block diagram showing a storage device including a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the storage device (1000) of the present invention may include a memory controller (1100) and a non-volatile memory device (1200). For example, the storage controller (1100) and the non-volatile memory device (1200) may each be provided as a single chip, a single package, or a single module. Alternatively, the storage controller (1100) and the non-volatile memory device (1200) may be formed as a single chip, a single package, or a single module and provided as storage such as an embedded memory, a memory card, a memory stick, a solid-state drive (SSD), etc.

[0016] The memory controller (1100) can perform access operations such as writing data to the non-volatile memory device (1200) or reading data stored in the non-volatile memory device (1200). The memory controller (1100) can generate a command (CMD) and an address (ADD) for accessing the non-volatile memory device (1200). In particular, the memory controller (1100) provides a data signal (DQ) and a data strobe signal (DQS) to transmit data, an address, or a command. The data signal (DQ) and the data strobe signal (DQS) must be accurately matched to ensure the reliability of the data.

[0017] The memory controller (1100) may provide an input / output mode (I / O_Mode) for selecting a method of receiving data signals (DQ) and data strobe signals (DQS) of the non-volatile memory device (1200). By providing the input / output mode (I / O_Mode), the method of receiving data signals (DQ) and data strobe signals (DQS) of the non-volatile memory device (1200) can be selected. If the transmission method of the data signals (DQ) and data strobe signals (DQS) corresponds to the conventional matched type, the compatible input / output circuit (1210) of the non-volatile memory device (1200) must be set to the matched type. At this time, the memory controller (1100) can set the compatible input / output circuit (1210) of the non-volatile memory device (1200) to the matched type through the input / output mode (I / O_Mode). On the other hand, if the transmission method of the data signal (DQ) and the data strobe signal (DQS) corresponds to an unmatched type suitable for high-speed operation, the compatible input / output circuit (1210) of the non-volatile memory device (1200) must be set to an unmatched type that aligns the data signal (DQ) and the data strobe signal (DQS) through training. At this time, the memory controller (1100) can set the compatible input / output circuit (1210) of the non-volatile memory device (1200) to an unmatched type through the input / output mode (I / O_Mode).

[0018] The non-volatile memory device (1200) outputs read data requested by the memory controller (1100) to the memory controller (1100) or stores data requested for writing by the memory controller (1100) in a memory cell. In particular, the non-volatile memory device (1200) of the present invention includes a compatible input / output circuit (1210). The compatible input / output circuit (1210) can set the alignment method of the data signal (DQ) and the data strobe signal (DQS) to a matched type or an unmatched type by the input / output mode (I / O_Mode). To this end, the compatible input / output circuit (1210) can vary the path of the data signal (DQ) and the data strobe signal (DQS) to a matched type or an unmatched type.

[0019] Here, the non-volatile memory device (1200) may include a plurality of memory blocks (BLK1 to BLKn-1). Each of the plurality of memory blocks (BLK1 to BLKn-1) has a three-dimensional memory structure in which word line layers are stacked vertically on a substrate. Each of the plurality of memory blocks (BLK1 to BLKn-1) may be managed by a storage controller (1100) through information for wear leveling, such as an erase count. The non-volatile memory device (1200) may have a C2C (Chip to Chip) structure. Here, a C2C structure may mean that after fabricating at least one upper chip including a cell region and a lower chip including a peripheral circuit region, the at least one upper chip and the lower chip are connected to each other by a bonding method. Although the advantages of the present invention have been described in this specification based on a flash memory device, the technical scope of the present disclosure is not limited thereto.

[0020] As described above, by the configuration and function of the compatible input / output circuit (1210), the non-volatile memory device (1200) of the present invention is compatible with both a matched interface and an unmatched interface. That is, the alignment method of the data signal (DQ) and data strobe signal (DQS) of the non-volatile memory device (1200) can be selected according to the type of interface of the memory controller (1100). Through this, it can be freely installed in an unmatched memory controller or an existing matched memory controller that requires high-speed data transmission.

[0021] FIG. 2 is a block diagram illustrating the configuration of a non-volatile memory device of FIG. 1. Referring to FIG. 2, the non-volatile memory device (1200) may include a compatible input / output circuit (1210) that forms an input / output terminal and a memory core (1230) that performs data storage and reading.

[0022] The compatible input / output circuit (1210) can change the alignment method of the data signal (DQ) and data strobe signal (DQS) of the non-volatile memory device (1200). The compatible input / output circuit (1210) can set the alignment method of the data signal (DQ) and data strobe signal (DQS) to a matched type or an unmatched type by the input / output mode (I / O_Mode). For example, the compatible input / output circuit (1210) can set the alignment method of the data signal (DQ) and data strobe signal (DQS) according to the input / output mode (I / O_Mode) provided by the memory controller (1100) at boot time. If the input / output mode (I / O_Mode) corresponds to the matched type, the compatible input / output circuit (1210) will set the delay size of the data signal (DQ) and data strobe signal (DQS) to a preset size. On the other hand, if the input / output mode (I / O_Mode) corresponds to an unmatched type, a path that minimizes the path of the data signal (DQ) is activated. And the compatible input / output circuit (1210) will perform training for alignment of the data signal (DQ) and the data strobe signal (DQS).

[0023] In an unmatched or matched input / output mode (I / O_Mode), when the alignment of the data signal (DQ) and the data strobe signal (DQS) is complete, the compatible input / output circuit (1210) can transmit the input / output data (I / O Data) to the memory core (1230). That is, the compatible input / output circuit (1210) can exchange the input / output data (I / O Data) with read or write circuits such as the page buffer (1270). In addition, the compatible input / output circuit (1210) may transmit the command (CMD) or address (ADD) provided through the aligned data signal (DQ) and data strobe signal (DQS) to the control circuit (1220).

[0024] The memory core (1230) may include a control circuit (1220), an address decoder (1240), a cell array (1260), and a page buffer (1280).

[0025] The control circuit (1220) controls the page buffer (1280), the address decoder (1240), and the voltage generator (not shown) in response to a command (CMD) transmitted from the outside. The control circuit (1220) can control the page buffer (1280) and the address decoder (1240) to perform program, read, and erase operations on the selected memory cell according to the command (CMD).

[0026] The address decoder (1240) can select any one of the memory blocks of the cell array (1260) in response to an address (ADD). The address decoder (1240) can select any one of the word lines of the selected memory block in response to an address (ADD). The address decoder (1240) transmits a voltage (VWL) corresponding to the operation mode to the word lines of the selected memory block. During a program operation, the address decoder (1240) transmits a program voltage (Vpgm) and a verification voltage (Vfy) to the selected word line (Selected WL), and a pass voltage (Vpass) to the unselected word line (Unselected WL). During a read operation, the address decoder (1240) transmits a read voltage (Vrd) to the selected word line (Selected WL) and a read pass voltage (Vread) to the unselected word line (Unselected WL).

[0027] The cell array (1260) is connected to an address decoder (1240) via word lines (WLs) or select lines (SSL, GSL). The cell array (1260) is connected to a page buffer (1280) via bit lines (BLs). The cell array (1260) may include a plurality of NAND cell strings. Each channel of the NAND cell strings may be formed in a vertical or horizontal direction. The cell array (1260) of the present invention will include a plurality of memory cells forming a cell string. The plurality of memory cells may be programmed, erased, and sensed by a voltage provided via bit lines (BLs) or word lines (WLs). Programming operations may be performed on a page basis, and erasing operations may be performed on a block basis.

[0028] As an embodiment of the present invention, the cell array (1260) may be provided as a three-dimensional memory array. The three-dimensional memory array may be monolithically formed at one or more physical levels of arrays of memory cells having active regions disposed on a silicon substrate and circuits associated with the operation of memory cells. The circuits associated with the operation of memory cells may be located within or on the substrate. The term monolithic means that the layers of each level of the three-dimensional array are deposited directly on the layers of the lower levels of the three-dimensional array.

[0029] As an embodiment of the present invention, a three-dimensional memory array has a vertical orientation and includes vertical NAND cell strings in which at least one memory cell is located above another memory cell. At least one memory cell includes a charge trap layer. Each vertical NAND cell string may include at least one select transistor located above the memory cells. The at least one select transistor has the same structure as the memory cells and may be formed monolithically together with the memory cells.

[0030] A configuration suitable for a three-dimensional memory array, wherein the three-dimensional memory array is composed of multiple levels and has word lines or bit lines shared between the levels, is disclosed in U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Publication No. 2011 / 0233648, and is incorporated by reference into the present invention.

[0031] The page buffer (1280) operates as a write driver or a sense amplifier. During a program operation, the page buffer (1280) transmits a bit line voltage corresponding to the data to be programmed to the bit lines (BLs) of the cell array (1260). During a read operation or a verified read operation, the page buffer (1280) senses the data stored in the selected memory cell through the bit lines (BLs). The page buffer (1280) can program the input data provided by the compatible input / output circuit (1210) into the cell array (1260). Additionally, the page buffer (1280) can sense data from the cell array (1260) when a read command is provided. The data sensed by the page buffer (1280) can be output to the memory controller (1100, see FIG. 1) through the compatible input / output circuit (1210).

[0032] As described above, the non-volatile memory device (1200) of the present invention, which includes a compatible input / output circuit (1210), can vary the alignment method of the data signal (DQ) and the data strobe signal (DQS). In particular, when an unmatched alignment method is selected, the compatible input / output circuit (1210) can perform training of the data signal (DQ) and the data strobe signal (DQS) for transmitting and receiving high-speed input / output data. Accordingly, the non-volatile memory device (1200) of the present invention can provide high compatibility regardless of the type of data interface of the memory controller (1100).

[0033] FIG. 3 is a block diagram briefly illustrating an embodiment of the compatible input / output device of FIG. 2. Referring to FIG. 3, a compatible input / output circuit (1210a) according to an embodiment may include equalizers (1211, 1216), a variable sampler (1212), a demultiplexer (1213a), a multiplexer (1213b), a CDN delay unit (1214), a flip-flop (1215), a C2C (1217), a clock distribution network (1218), and a path controller (1219).

[0034] Each of the equalizers (1211, 1216) filters and outputs the received data signal (DQ) and data strobe signals (DQS_C, DQS_T). For example, the equalizers (1211, 1216) can be configured as Decision Feedback Equalizers (DFE). The equalizers (1211, 1216) can filter by applying predetermined coefficients to the previous symbol, current symbol, and subsequent symbol to eliminate inter-symbol interference (ISI) between the received data signal (DQ) and data strobe signals (DQS_C, DQS_T).

[0035] The variable sampler (1212) receives a data signal (DQ) in either a sampler mode or an amplifier mode depending on the input / output mode (I / O_Mode). When the input / output mode (I / O_Mode) corresponds to an unmatched mode, the variable sampler (1212) operates in a sampler mode that samples the data signal (DQ) by a data strobe signal (DQS). On the other hand, when the input / output mode (I / O_Mode) corresponds to a matched mode, the variable sampler (1212) operates in an amplifier mode that amplifies the data signal (DQ). That is, in the matched mode, the variable sampler (1212) can perform the same operation as a common mode-CMOS (CML to CMOS: hereinafter C2C) converter (1217). Therefore, in matched mode, sampling of data using the data strobe signal (DQS) will occur in the flip-flop (1215). The variable sampler (1212) can be configured, for example, using a double tail latch or a strong arm latch.

[0036] The demultiplexer (1213a) and the multiplexer (1213b) transmit the path of the data signal (DQ) output from the variable sampler (1212) to the flip-flop (1215) with or without delay, depending on the input / output mode (I / O_Mode). For example, when the input / output mode (I / O_Mode) corresponds to the unmatched mode, the demultiplexer (1213a) and the multiplexer (1213b) transmit the data signal (DQ) output from the variable sampler (1212) to the flip-flop (1215) without delay. On the other hand, when the input / output mode (I / O_Mode) corresponds to the matched mode, the demultiplexer (1213a) and the multiplexer (1213b) transmit the data signal (DQ) via the CDN delay unit (1214) to the flip-flop (1215) that constitutes the output terminal of the compatible input / output circuit (1210).

[0037] The CDN delay unit (1214) applies the same delay of the data strobe signal (DQS) generated in the clock distribution network (1218) to the data signal (DQ). In particular, the CDN delay unit (1214) is used to align the delay of the data signal (DQ) with the data strobe signal (DQS) in the matched mode, where the variable sampler (1212) operates in amplifier mode. However, when the input / output mode (I / O_Mode) corresponds to the unmatched mode, the transmission of the data signal (DQ) to the CDN delay unit (1214) does not occur.

[0038] The flip-flop (1215) can be used as a sampler or a simple data latch depending on the input / output mode (I / O_Mode). When the input / output mode (I / O_Mode) corresponds to the unmatched mode, the variable sampler (1212) operates as a sampler of the data signal (DQ). At this time, the flip-flop (1215) only provides the function of transmitting the data signal (DQ) sampled by the variable sampler (1212) to the input / output data. On the other hand, when the input / output mode (I / O_Mode) corresponds to the matched mode, the variable sampler (1212) operates in amplifier mode. Thus, the flip-flop (1215) samples the data signal (DQ) with the delay aligned according to the data strobe signal (DQS) provided by the clock distribution network (1218).

[0039] The C2C converter (1217) converts a common mode signal into a CMOS signal. That is, the C2C converter (1217) converts data strobe signals (DQS_C, DQS_T) swinging in the form of differential signals into CMOS signals. Consequently, the C2C converter (1217) operates as an amplifier for the data strobe signals (DQS_C, DQS_T).

[0040] The clock distribution network (1218) delays the data strobe signal (DQS) by a preset delay size. Then, the clock distribution network (1218) transmits the data strobe signal (DQS) to the variable sampler (1212) or flip-flop (1215) in response to a select signal (SEL) provided by the path controller (1219).

[0041] The path controller (1219) selects a path through which the data signal (DQ) and the data strobe signal (DQS) are transmitted according to the input / output mode (I / O_Mode). When the input / output mode (I / O_Mode) corresponds to the unmatched mode, the path controller (1219) controls the variable sampler (1212) to operate in the same amplifier mode as the C2C converter (1217). Then, in the unmatched mode, the path controller (1219) controls the demultiplexer (1213a) and the multiplexer (1213b) to transmit the data signal (DQ) output from the variable sampler (1212) to the flip-flop (1215) without delay.

[0042] On the other hand, when the input / output mode (I / O_Mode) corresponds to the matched mode, the path controller (1219) controls the variable sampler (1212) to operate in sampler mode. Then, in the matched mode, the path controller (1219) controls the demultiplexer (1213a) and the multiplexer (1213b) so that the data signal (DQ) output from the variable sampler (1212) is transmitted to the flip-flop (1215) via the CDN delay unit (1214).

[0043] In the above description, a method for setting the transmission path of the data signal (DQ) and data strobe signal (DQS) of the compatible input / output circuit (1210a) according to the input / output mode (I / O_Mode) has been explained. In the input / output mode (I / O_Mode) of the unmatched mode, which is suitable for high-speed data transmission, the data signal (DQ) is sampled by the variable sampler (1212) and can be transmitted to the memory core (1230, see FIG. 2) without delay. Subsequently, alignment of the data signal (DQ) and the data strobe signal (DQS) can be achieved through training. On the other hand, in the input / output mode (I / O_Mode) of the matched mode, the data signal (DQ) is transmitted to the flip-flop (1215) via the CDN delay unit (1214). The CDN delay unit (1214) is a delay unit having a delay matched with the clock distribution network (1218), which is the path of the data strobe signal (DQS). Thus, compatibility of the input / output signals of the non-volatile memory device (1200) can be ensured through the compatible input / output circuit (1210a).

[0044] FIG. 4 is a diagram showing the paths of the data signal (DQ) and the data strobe signal (DQS) in the matched mode of the compatible input / output circuit of FIG. 3, respectively. Referring to FIG. 4, in the matched mode, the path (MP_DQ) of the data signal (DQ) is transmitted to the flip-flop (1215) via the CDN delay unit (1214) for alignment with the data strobe signal (DQS). The data strobe signal (DQS) will be transmitted to the flip-flop (1215) as a signal delayed by a predetermined amount through the clock distribution network (1218).

[0045] It is assumed that the input / output mode (I / O_Mode) is provided as a matched mode from the memory controller (1100). The input / output mode (I / O_Mode) may be provided from the memory controller (1100) through commands or control signals. The input / output mode (I / O_Mode) may be provided using a UIB (Universal Internal Bus) command or transmitted using a special command transmitted by the memory controller, such as a Get feature or Set feature command.

[0046] In the I / O_Mode of the matched mode, the data signal (DQ) transmitted to the equalizer (1211) is transmitted to the flip-flop (1215) along the data path (MP_DQ). That is, in the matched mode, the variable sampler (1212) acts as an amplifier for the data signal (DQ). The data signal (DQ) amplified by the variable sampler (1212) is transmitted to the CDN delay unit (1214) by a demultiplexer (1213a) controlled by the path controller (1219). The data signal (DQ) output from the CDN delay unit (1214) can be selected by the multiplexer (1213b) and transmitted to the flip-flop (1215). The path selection operation of the variable sampler (1212), demultiplexer (1213a), and multiplexer (1213b) is controlled by the path controller (1219) according to the input / output mode (I / O_Mode).

[0047] In matched mode, the data strobe signal (DQS) transmitted to the equalizer (1216) is transmitted along the data strobe path (MP_DQS) to the clock input of the flip-flop (1215). In matched mode, the data strobe signal (DQS) is amplified by the C2C converter (1217). The amplified data strobe signal (DQS) is transmitted to the clock distribution network (1218). The delay size of the clock distribution network (1218) may be provided as a predetermined value for alignment with the data signal (DQ). The data strobe signal (DQS), with its delay adjusted in the clock distribution network (1218), is transmitted to the clock input of the flip-flop (1215). Then, sampling of the data signal (DQ) in matched mode can be performed by the flip-flop (1215).

[0048] As described above, according to the path selection operation of the compatible input / output circuit (1210a) in the matched mode, the data signal (DQ) and the data strobe signal (DQS) can be matched to a predetermined delay value.

[0049] FIG. 5 is a diagram showing the paths of the data signal (DQ) and the data strobe signal (DQS) in the unmatched mode of the compatible input / output circuit of the present invention, respectively. Referring to FIG. 5, in the unmatched mode, the path (UMP_DQ) of the data signal (DQ) is transmitted to the flip-flop (1215) using the shortest path that bypasses the CDN delay unit (1214). Alignment with the data strobe signal (DQS) is achieved through training of the data signal (DQ) or the data strobe signal (DQS) performed later. In the unmatched mode, the data strobe signal (DQS) may also be transmitted to the variable sampler (1212) via the shortest delay path of the clock distribution network (1218).

[0050] An input / output mode (I / O_Mode) may be provided from the memory controller (1100) as an unmatched mode. The input / output mode (I / O_Mode) may be provided from the memory controller (1100) through commands or control signals. The input / output mode (I / O_Mode) may be provided using a Universal Internal Bus (UIB) command or transmitted using a special command transmitted by the memory controller, such as a Get feature or Set feature command. In the unmatched mode, the path controller (1219) may control the variable sampler (1212) as a sampler mode, the demultiplexer (1213a) and multiplexer (1213b) as a bypass mode, and the clock distribution network (1218) as a shortest distance mode.

[0051] In unmatched mode, the data signal (DQ) transmitted from the memory controller (1100) is filtered by the equalizer (1211). The variable sampler (1212) operates in sampler mode for sampling the data signal (DQ). At this time, the data strobe signal (DQS) used for sampling in the variable sampler (1212) is transmitted to the shortest path of the clock distribution network (1218) or to the bypassed data strobe path (UMP_DQS).

[0052] The data signal (DQ) sampled by the variable sampler (1212) is transmitted directly to the flip-flop (1215) without passing through the CDN delay unit (1214) by the demultiplexer (1213a) and multiplexer (1213b) controlled by the path controller (1219). The path selection operation by the variable sampler (1212), demultiplexer (1213a), and multiplexer (1213b) is controlled by the path controller (1219).

[0053] In unmatched mode, the data strobe signal (DQS) transmitted to the equalizer (1216) is transmitted to the variable sampler (1212) along the data strobe path (UMP_DQS). In unmatched mode, the data strobe signal (DQS) filtered by the equalizer (1216) is amplified by the C2C converter (1217). The amplified data strobe signal (DQS) is transmitted to the clock distribution network (1218). At this time, the delay size of the clock distribution network (1218) can be arbitrarily selected. Preferably, the data strobe signal (DQS) set to the shortest delay size of the clock distribution network (1218) can be transmitted to the variable sampler (1212). Then, a variable sampler (1212) operating in sampler mode will sample the data signal (DQ) using the data strobe signal (DQS) transmitted via the data strobe path (UMP_DQS). Subsequently, alignment of the data signal (DQ) and the data strobe signal (DQS) will be achieved through subsequent training.

[0054] According to the path selection operation in the unmatched mode of the compatible input / output circuit (1210a) described above, the paths of the data signal (DQ) and the data strobe signal (DQS) can be selected. Through subsequent training, alignment of the data signal (DQ) and the data strobe signal (DQS) can be achieved. Through this path setting in the unmatched mode, the compatible input / output circuit (1210a) can be reconfigured into a structure suitable for high-speed data reception.

[0055] FIG. 6 is a flowchart briefly illustrating the path selection operation of a compatible input / output circuit of a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 6, the operating mode of a variable sampler (1212, see FIG. 3) and the paths of a demultiplexer (1213a, see FIG. 3), a multiplexer (1213b, see FIG. 3), and a clock distribution network (1218, see FIG. 3) are set according to the input / output mode.

[0056] In step S110, the compatible input / output circuit (1210a, see FIG. 3) of the non-volatile memory device (1200) receives an input / output mode (I / O_Mode) from the memory controller (1100) or the host. For example, the memory controller (1100) can transmit the input / output mode (I / O_Mode) to the non-volatile memory device (1200) using a control signal, a UIB (Universal Internal Bus) command, a Get feature command, a Set feature command, etc.

[0057] In step S120, the compatible input / output circuit (1210) performs an operation branch according to the received input / output mode (I / O_Mode). For example, the compatible input / output circuit (1210a) determines whether the received input / output mode (I / O_Mode) is an unmatched mode or a matched mode. If the received input / output mode (I / O_Mode) corresponds to an unmatched mode, the procedure moves to step S130. On the other hand, if the received input / output mode (I / O_Mode) corresponds to a matched mode, the procedure moves to step S150.

[0058] In step S130, the path controller (1219) sets the variable sampler (1212) to a sampler mode for sampling the data signal (DQ) in order to set it to an unmatched mode. If the default operating mode of the variable sampler (1212) is set to sampler mode, the path controller (1219) maintains the operating mode of the variable sampler (1212) as the default operating mode, which is sampler mode. Then, the path controller (1219) sets the path of the demultiplexer (1213a) and the multiplexer (1213b) to a bypass mode that does not pass through the CDN delay unit (1214). Then, the path controller (1219) provides the data strobe signal (DQS) of the clock distribution network (1218) to the variable sampler (1212) via a select signal (SEL). Then, the paths of the data signal (DQ) and the data strobe signal (DQS) can be set to the data path (UMP_DQ) and the data strobe path (UMP_DQS) of Fig. 6, respectively.

[0059] In step S140, training of the data signal (DQ) or data strobe signal (DQS) in the unmatched mode of the compatible input / output circuit (1210a) is performed. For training, a procedure is carried out in which a training pattern is written and read from the memory controller (1100). Then, the delay value of the data signal (DQ) or data strobe signal (DQS) is fixed to provide optimal reliability.

[0060] In step S150, the path controller (1219) sets the variable sampler (1212) to amplifier mode for setting to matched mode. If the default operating mode of the variable sampler (1212) is set to sampler mode, the path controller (1219) will switch the operating mode of the variable sampler (1212) to amplifier mode. Then, the path controller (1219) sets the demultiplexer (1213a) and multiplexer (1213b) so that the data signal (DQ) passes through the CDN delay unit (1214). Then, the path controller (1219) transmits the data strobe signal (DQS) of the clock distribution network (1218) to the flip-flop (1215) via the select signal (SEL). Then, the paths of the data signal (DQ) and the data strobe signal (DQS) can be set to the data path (MP_DQ) and the data strobe path (MP_DQS) of Fig. 4, respectively.

[0061] As described above, the compatible input / output circuit (1210a) can change the path of the data signal (DQ) and the data strobe signal (DQS) according to the input / output mode (I / O_Mode). In the unmatched mode, which is optimized for high-speed data reception, the data signal (DQ) and the data strobe signal (DQS) are aligned through subsequent training. On the other hand, in the matched mode, the data signal (DQ) and the data strobe signal (DQS) can be aligned with a predetermined optimal delay value, thereby operating advantageously for relatively low-speed data reception. Due to the characteristics of this compatible input / output circuit (1210a), the non-volatile memory device (1200) can provide compatibility regardless of the generation.

[0062] FIG. 7 schematically shows an exemplary structure of the non-volatile memory device of FIG. 2. Referring to FIG. 2 and FIG. 7, the non-volatile memory device (1200, see FIG. 2) may include a first semiconductor layer (L1) and a second semiconductor layer (L2), and the first semiconductor layer (L1) may be stacked in a vertical direction (VD) with respect to the second semiconductor layer (L2). Specifically, the second semiconductor layer (L2) may be positioned below the first semiconductor layer (L1) in a vertical direction (VD), and accordingly, the second semiconductor layer (L2) may be positioned close to the substrate.

[0063] In one embodiment, the cell array (1260) of FIG. 2 may be formed on a first semiconductor layer (L1), and peripheral circuits corresponding to the control circuit (1220), address decoder (1240), page buffer circuit (1280), and / or compatible input / output circuit (1210) of FIG. 1 may be formed on a second semiconductor layer (L2). Accordingly, the non-volatile memory device (1200) may have a structure in which the cell array (1260) is positioned above the peripheral circuits (1210, 1220, 1240, 1280), i.e., a Cell Over Periphery (COP) structure. The COP structure can effectively reduce the horizontal area and improve the integration density of the non-volatile memory device (1200).

[0064] In one embodiment, the second semiconductor layer (L2) may include a substrate, and peripheral circuits (1210, 1220, 1240, 1280) may be formed on the second semiconductor layer (L2) by forming transistors and metal patterns for wiring the transistors on the substrate. After the peripheral circuits (1210, 1220, 1240, 1280) are formed on the second semiconductor layer (L2), a first semiconductor layer (L1) including a cell array (1260) may be formed, and metal patterns may be formed to electrically connect the word lines (WL) and bit lines (BL) of the cell array (1260) with the peripheral circuits (1210, 1220, 1240, 1280) formed on the second semiconductor layer (L2). For example, bit lines (BL) can be extended in a first horizontal direction (HD1), and word lines (WL) can be extended in a second horizontal direction (HD2).

[0065] As semiconductor processes develop, as the number of memory cells placed in the cell array (1260) increases—that is, as the number of stacked word lines (WL) increases—the area of ​​the cell array (1260) decreases, and accordingly, the area of ​​the peripheral circuits (1210, 1220, 1240, 1280) also decreases. In particular, the non-volatile memory device (1200) of the present invention includes a compatible input / output circuit (1210) in a form that minimizes additional configuration. Therefore, the non-volatile memory device (1200) of the present invention can provide high compatibility regardless of the memory generation without an additional increase in area.

[0066] FIG. 8 is a circuit diagram showing an exemplary structure of a memory block constituting the cell array of FIG. 2. Referring to FIG. 8, cell strings (NS) are formed between bit lines (BL0, BL1, BL2, BL3) and a common source line (CSL) to constitute a memory block (BLK).

[0067] Cell strings (NS10, NS20, …) are formed between the bit line (BL0) and the common source line (CSL). In the same way, multiple cell strings (NS11, NS21, NS12, NS22, NS13, NS23) are formed between the bit lines (BL1, BL2, BL3) and the common source line (CSL). The string select transistor (SST) of the cell strings (NS) is connected to the corresponding bit line (BL). The ground select transistor (GST) of the cell strings (NS) is connected to the common source line (CSL). Memory cells (MCs) are provided between the string select transistor (SST) and the ground select transistor (GST) of the cell string (NS).

[0068] Each of the cell strings (NS) includes a ground select transistor (GST). The ground select transistors included in the cell strings (NS) can be controlled by a ground select line (GSL). Alternatively, although not illustrated, the cell strings corresponding to each row can be controlled by different ground select lines.

[0069] The circuit structure of memory cells included in a single memory block (BLK) has been briefly described above. However, the circuit structure of the illustrated memory block is simplified for the convenience of explanation, and actual memory blocks are not limited to the illustrated example. That is, it will be well understood that a single physical block may include more semiconductor layers, bit lines (BLs), and string select lines (SSLs).

[0070] FIG. 9 is a block diagram showing a compatible input / output circuit according to another embodiment of the present invention. Referring to FIG. 9, the compatible input / output circuit (1210b) of another embodiment can use a 4-phase receiving method capable of high-speed transmission of a data signal (DQ).

[0071] A compatible input / output circuit (1210b) according to another embodiment can filter or process a data signal (DQ) and a data strobe signal (DQS) using a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and a complete feedback equalizer (CFE). Strong arm samplers can sample or amplify the data signal (DQ) filtered by each data strobe signal (DQS) delayed by 4 phases.

[0072] When the input / output mode (I / O_Mode) corresponds to unmatched mode, the demultiplexer (DEMUX) transmits the data signal (DQ) sampled by the strong arm samplers to the SR latches. At this time, a dummy delay unit (Dummy) may be inserted in front of the SR latches to match the delays of the three phases of the data signal (DQ) that do not pass through the demultiplexer (DEMUX). The outputs of the SR latches will be transmitted to the latch circuits (DINA1i, DINA1q, DINA2) to form the input data (Data). In unmatched mode, the data signal (DQ) is transmitted along the data path (UMP_DQ), and the data strobe signal (DQS) is transmitted along the clock path (UMP_DQS).

[0073] When the input / output mode (I / O_Mode) corresponds to the matched mode, the demultiplexer (DEMUX) transmits the data signal (DQ) sampled by the strong arm samplers to the latch circuits (DINA1i, DINA1q, DINA2) via the delay cell. At this time, the data strobe signal (DQS) passes through the continuous-time linear equalizer (CTLE), the variable gain amplifier (VGA), and the complete feedback equalizer (CFE). Additionally, in the matched mode, the C2C converter (1280) is activated, and the data strobe signal (DQS) amplified by the C2C converter (1280) will be provided to the latch circuits (DINA1i, DINA1q, DINA2) via the delay cell (1281) and the delay circuit (1282). In matched mode, the data signal (DQ) is transmitted along the data path (MP_DQ), and the data strobe signal (DQS) is transmitted along the clock path (MP_DQS).

[0074] FIG. 10 is a block diagram showing a storage device according to another embodiment of the present invention. Referring to FIG. 10, the storage device (2000) of the present invention may include a memory controller (2100) and a non-volatile memory device (2200). For example, the storage controller (2100) and the non-volatile memory device (2200) may each be provided as a single chip, a single package, or a single module. Alternatively, the storage controller (2100) and the non-volatile memory device (2200) may be formed as a single chip, a single package, or a single module and provided as storage such as an embedded memory, a memory card, a memory stick, a solid-state drive (SSD), etc.

[0075] The memory controller (2100) can perform access operations such as writing data to the non-volatile memory device (2200) or reading data stored in the non-volatile memory device (2200). The memory controller (2100) can generate a command (CMD) and an address (ADD) for accessing the non-volatile memory device (2200). In particular, the memory controller (2100) provides a data signal (DQ) and a data strobe signal (DQS) to transmit data, an address, or a command. The data signal (DQ) and the data strobe signal (DQS) must be accurately matched to ensure the reliability of the data.

[0076] The memory controller (2100) may provide an input / output mode (I / O_Mode) for selecting a method of receiving data signals (DQ) and data strobe signals (DQS) of the non-volatile memory device (2200). By providing the input / output mode (I / O_Mode), a method of receiving data signals (DQ) and data strobe signals (DQS) of the non-volatile memory device (2200) can be selected.

[0077] If the transmission method of the data signal (DQ) and the data strobe signal (DQS) corresponds to the conventional matched type, the compatible input / output circuit (2210) of the non-volatile memory device (2200) must be set to the matched type. At this time, the memory controller (2100) can set the compatible input / output circuit (2210) of the non-volatile memory device (2200) to the matched type through the input / output mode (I / O_Mode). On the other hand, if the transmission method of the data signal (DQ) and the data strobe signal (DQS) corresponds to the unmatched type for high-speed operation, the compatible input / output circuit (2210) of the non-volatile memory device (2200) must be set to the unmatched type that aligns the data signal (DQ) and the data strobe signal (DQS) through training. At this time, the memory controller (2100) can set the compatible input / output circuit (2210) of the non-volatile memory device (2200) to an unmatched type through the input / output mode (I / O_Mode).

[0078] The non-volatile memory device (2200) outputs read data requested by the memory controller (2100) to the memory controller (2100) or stores data requested for writing by the memory controller (2100) in a memory cell. In particular, the non-volatile memory device (2200) of the present invention includes a compatible input / output circuit (2210) and an internal DQS training unit (2230). The compatible input / output circuit (2210) can set the alignment method of the data signal (DQ) and the data strobe signal (DQS) to a matched type or an unmatched type by the input / output mode (I / O_Mode). To this end, the compatible input / output circuit (2210) can vary the path of the data signal (DQ) and the data strobe signal (DQS) to a matched type or an unmatched type.

[0079] Here, the internal DQS training unit (2230) can perform its own DQS training when the input / output mode (I / O_Mode) of the compatible input / output circuit (2210) is set to unmatched mode. To this end, the internal DQS training unit (2230) may include an internal oscillator.

[0080] As described above, the non-volatile memory device (2200) of the present invention can be compatible with either a matched interface or an unmatched interface, depending on the configuration and function of the compatible input / output circuit (2210). That is, the alignment method of the data signal (DQ) and the data strobe signal (DQS) can be selected according to the type of interface of the memory controller (2100). Through this, it can be freely installed in an unmatched controller or an existing matched controller that requires high-speed data transmission.

[0081] FIG. 11 is a drawing for illustrating a memory device according to an embodiment of the present invention. Referring to FIG. 11, the memory device (500) may have a C2C (chip to chip) structure. Here, the C2C structure may mean that at least one upper chip including a cell region (CELL) and a lower chip including a peripheral circuit region (PERI) are each manufactured, and then the at least one upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed on the uppermost metal layer of the upper chip and a bonding metal pattern formed on the uppermost metal layer of the lower chip. For example, if the bonding metal patterns are formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. As another example, the bonding metal patterns may also be formed of aluminum (Al) or tungsten (W).

[0082] The memory device (500) may include at least one upper chip including a cell region. For example, as illustrated in FIG. 11, the memory device (500) may be implemented to include two upper chips. However, this is exemplary and the number of upper chips is not limited thereto. When the memory device (500) is implemented to include two upper chips, the memory device (500) may be manufactured by first manufacturing a first upper chip including a first cell region (CELL1), a second upper chip including a second cell region (CELL2), and a lower chip including a peripheral circuit region (PERI), and then connecting the first upper chip, the second upper chip, and the lower chip to each other by a bonding method. The first upper chip may be inverted and connected to the lower chip by a bonding method, and the second upper chip may also be inverted and connected to the first upper chip by a bonding method. In the following description, the upper and lower parts of the first and second upper chips are defined based on the state before the first and second upper chips are inverted. That is, in FIG. 11, the upper part of the lower chip refers to the upper part defined based on the +Z-axis direction, and the upper part of each of the first and second upper chips refers to the upper part defined based on the -Z-axis direction. However, this is exemplary, and only one of the first and second upper chips may be inverted and connected by a bonding method.

[0083] Each of the peripheral circuit region (PERI) and the first and second cell regions (CELL1, CELL2) of the memory device (500) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0084] The peripheral circuit region (PERI) may include a first substrate (210) and a plurality of circuit elements (220a, 220b, 220c) formed on the first substrate (210). An interlayer insulating layer (215) comprising one or more insulating layers may be provided on the plurality of circuit elements (220a, 220b, 220c), and a plurality of metal wirings connecting the plurality of circuit elements (220a, 220b, 220c) may be provided within the interlayer insulating layer (215). For example, the plurality of metal wires may include a first metal wire (230a, 230b, 230c) connected to each of the plurality of circuit elements (220a, 220b, 220c), and a second metal wire (240a, 240b, 240c) formed on the first metal wire (230a, 230b, 230c). The plurality of metal wires may be made of at least one of various conductive materials. For example, the first metal wire (230a, 230b, 230c) may be formed of tungsten, which has relatively high electrical resistivity, and the second metal wire (240a, 240b, 240c) may be formed of copper, which has relatively low electrical resistivity.

[0085] In this specification, only the first metal wiring (230a, 230b, 230c) and the second metal wiring (240a, 240b, 240c) are illustrated and described, but are not limited thereto, and at least one additional metal wiring may be formed on the second metal wiring (240a, 240b, 240c). In this case, the second metal wiring (240a, 240b, 240c) may be formed of aluminum. Also, at least some of the additional metal wiring formed on the second metal wiring (240a, 240b, 240c) may be formed of copper or the like, having a lower electrical resistivity than the aluminum of the second metal wiring (240a, 240b, 240c).

[0086] The interlayer insulating layer (215) is disposed on the first substrate (210) and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0087] The first and second cell regions (CELL1, CELL2) may each include at least one memory block. The first cell region (CELL1) may include a second substrate (310) and a common source line (320). On the second substrate (310), a plurality of word lines (331-338; 330) may be stacked along a direction perpendicular to the upper surface of the second substrate (310) (Z-axis direction). String selection lines and ground selection lines may be arranged above and below the word lines (330), and a plurality of word lines (330) may be arranged between the string selection lines and the ground selection lines. Likewise, the second cell region (CELL2) includes a common source line (420) with the third substrate (410), and a plurality of word lines (431-438: 430) may be stacked along a direction perpendicular to the upper surface of the third substrate (410) (Z-axis direction). The second substrate (310) and the third substrate (410) may be made of various materials, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. A plurality of channel structures (CH) may be formed in each of the first and second cell regions (CELL1, CELL2).

[0088] In one embodiment, as illustrated in A1, a channel structure (CH) is provided in a bitline bonding area (BLBA) and extends in a direction perpendicular to the upper surface of the second substrate (310) to penetrate word lines (330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, etc. The channel layer may be electrically connected to a first metal wiring (350c) and a second metal wiring (360c) in the bitline bonding area (BLBA). For example, the second metal wiring (360c) may be a bitline and may be connected to the channel structure (CH) through the first metal wiring (350c). The bitline (360c) may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (310).

[0089] In one embodiment, as illustrated in A2, the channel structure (CH) may include a lower channel (LCH) and an upper channel (UCH) connected to each other. For example, the channel structure (CH) may be formed through a process for the lower channel (LCH) and a process for the upper channel (UCH). The lower channel (LCH) may extend in a direction perpendicular to the upper surface of the second substrate (310) and penetrate the common source line (320) and the lower word lines (331, 332). The lower channel (LCH) may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel (UCH). The upper channel (UCH) may penetrate the upper word lines (333–338). The upper channel (UCH) may include a data storage layer, a channel layer, and an embedded insulation layer, and the channel layer of the upper channel (UCH) may be electrically connected to the first metal wiring (350c) and the second metal wiring (360c). As the length of the channel increases, it may become difficult to form a channel having a constant width due to process reasons. The memory device (500) according to an embodiment of the present invention may have a channel having improved width uniformity through the lower channel (LCH) and the upper channel (UCH) formed by a sequential process.

[0090] As illustrated in A2, when a channel structure (CH) is formed to include a lower channel (LCH) and an upper channel (UCH), a word line located near the boundary between the lower channel (LCH) and the upper channel (UCH) may be a dummy word line. For example, word line (332) and word line (333) forming the boundary between the lower channel (LCH) and the upper channel (UCH) may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word line. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word line may be less than the number of pages corresponding to the memory cells connected to the normal word line. The voltage level applied to the dummy word line may differ from the voltage level applied to the normal word line, thereby reducing the impact of the non-uniform channel width between the lower channel (LCH) and the upper channel (UCH) on the operation of the memory device.

[0091] Meanwhile, in A2, the number of lower word lines (331, 332) through which the lower channel (LCH) passes is shown to be less than the number of upper word lines (333-338) through which the upper channel (UCH) passes. However, this is exemplary and the present invention is not limited thereto. As another example, the number of lower word lines through which the lower channel (LCH) passes may be formed to be equal to or greater than the number of upper word lines through which the upper channel (UCH) passes. In addition, the structure and connection relationship of the channel structure (CH) placed in the first cell area (CELL1) described above may be applied in the same way to the channel structure (CH) placed in the second cell area (CELL2).

[0092] In the bitline bonding region (BLBA), a first through-electrode (THV1) may be provided in the first cell region (CELL1), and a second through-electrode (THV2) may be provided in the second cell region (CELL2). As illustrated in FIG. 11, the first through-electrode (THV1) may penetrate a common source line (320) and a plurality of word lines (330). However, this is exemplary, and the first through-electrode (THV1) may further penetrate the second substrate (310). The first through-electrode (THV1) may include a conductive material. Alternatively, the first through-electrode (THV1) may include a conductive material surrounded by an insulating material. The second through-electrode (THV2) may also be provided in the same shape and structure as the first through-electrode (THV1).

[0093] In one embodiment, the first through electrode (THV1) and the second through electrode (THV2) may be electrically connected through the first through metal pattern (372d) and the second through metal pattern (472d). The first through metal pattern (372d) may be formed at the bottom of the first upper chip including the first cell region (CELL1), and the second through metal pattern (472d) may be formed at the top of the second upper chip including the second cell region (CELL2). The first through electrode (THV1) may be electrically connected to the first metal wiring (350c) and the second metal wiring (360c). A lower via (371d) may be formed between the first through electrode (THV1) and the first through metal pattern (372d), and an upper via (471d) may be formed between the second through electrode (THV2) and the second through metal pattern (472d). The first through metal pattern (372d) and the second through metal pattern (472d) can be connected by a bonding method.

[0094] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (252) may be formed on the uppermost metal layer of the peripheral circuit area (PERI), and an upper metal pattern (392) of the same shape as the upper metal pattern (252) may be formed on the uppermost metal layer of the first cell area (CELL1). The upper metal pattern (392) of the first cell area (CELL1) and the upper metal pattern (252) of the peripheral circuit area (PERI) may be electrically connected to each other by a bonding method. In the bitline bonding area (BLBA), the bit line (360c) may be electrically connected to the page buffer included in the peripheral circuit area (PERI). For example, some of the circuit elements (220c) of the peripheral circuit region (PERI) may provide a page buffer, and the bit line (360c) may be electrically connected to the circuit elements (220c) providing the page buffer through the upper bonding metal (370c) of the first cell region (CELL1) and the upper bonding metal (270c) of the peripheral circuit region (PERI).

[0095] Continuing, referring to FIG. 11, in the wordline bonding area (WLBA), the wordlines (330) of the first cell area (CELL1) may be extended along a second direction (X-axis direction) parallel to the upper surface of the second substrate (310) and may be connected to a plurality of cell contact plugs (341-347; 340). A first metal wiring (350b) and a second metal wiring (360b) may be connected in sequence to the upper portions of the cell contact plugs (340) connected to the wordlines (330). The cell contact plugs (340) may be connected to the peripheral circuit area (PERI) through the upper bonding metal (370b) of the first cell area (CELL1) and the upper bonding metal (270b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0096] Cell contact plugs (340) may be electrically connected to a row decoder included in the peripheral circuit region (PERI). For example, some of the circuit elements (220b) in the peripheral circuit region (PERI) provide a row decoder, and the cell contact plugs (340) may be electrically connected to the circuit elements (220b) providing the row decoder through the upper bonding metal (370b) of the first cell region (CELL1) and the upper bonding metal (270b) of the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (220b) providing the row decoder may be different from the operating voltage of the circuit elements (220c) providing the page buffer. For example, the operating voltage of the circuit elements (220c) providing the page buffer may be greater than the operating voltage of the circuit elements (220b) providing the row decoder.

[0097] Likewise, in the wordline bonding area (WLBA), the wordlines (430) of the second cell area (CELL2) may be extended along a second direction (X-axis direction) parallel to the upper surface of the third substrate (410) and may be connected to a plurality of cell contact plugs (441-447; 440). The cell contact plugs (440) may be connected to the upper metal pattern of the second cell area (CELL2), the lower metal pattern and the upper metal pattern of the first cell area (CELL1), and to the peripheral circuit area (PERI) through the cell contact plug (348).

[0098] In the wordline bonding area (WLBA), an upper bonding metal (370b) may be formed in the first cell area (CELL1), and an upper bonding metal (270b) may be formed in the peripheral circuit area (PERI). The upper bonding metal (370b) of the first cell area (CELL1) and the upper bonding metal (270b) of the peripheral circuit area (PERI) may be electrically connected to each other by a bonding method. The upper bonding metal (370b) and the upper bonding metal (270b) may be formed of aluminum, copper, or tungsten, etc.

[0099] In the external pad bonding area (PA), a lower metal pattern (371e) may be formed on the lower part of the first cell area (CELL1), and an upper metal pattern (472a) may be formed on the upper part of the second cell area (CELL2). The lower metal pattern (371e) of the first cell area (CELL1) and the upper metal pattern (472a) of the second cell area (CELL2) may be connected by a bonding method in the external pad bonding area (PA). Similarly, an upper metal pattern (372a) may be formed on the upper part of the first cell area (CELL1), and an upper metal pattern (272a) may be formed on the upper part of the peripheral circuit area (PERI). The upper metal pattern (372a) of the first cell area (CELL1) and the upper metal pattern (272a) of the peripheral circuit area (PERI) may be connected by a bonding method.

[0100] Common source line contact plugs (380, 480) may be disposed in the external pad bonding area (PA). The common source line contact plugs (380, 480) may be formed of a conductive material such as a metal, a metal compound, or doped polysilicon. The common source line contact plug (380) of the first cell area (CELL1) may be electrically connected to the common source line (320), and the common source line contact plug (480) of the second cell area (CELL2) may be electrically connected to the common source line (420). A first metal wire (350a) and a second metal wire (360a) may be stacked sequentially on the upper portion of the common source line contact plug (380) of the first cell area (CELL1), and a first metal wire (450a) and a second metal wire (460a) may be stacked sequentially on the upper portion of the common source line contact plug (480) of the second cell area (CELL2).

[0101] Input / output pads (205, 405, 406) may be disposed in the external pad bonding area (PA). Referring to FIG. 11, a lower insulating film (201) may cover the lower surface of the first substrate (210), and a first input / output pad (205) may be formed on the lower insulating film (201). The first input / output pad (205) is connected to at least one of a plurality of circuit elements (220a) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (203), and may be separated from the first substrate (210) by the lower insulating film (201). Additionally, a side insulating film may be disposed between the first input / output contact plug (203) and the first substrate (210) to electrically separate the first input / output contact plug (203) and the first substrate (210).

[0102] An upper insulating film (401) covering the upper surface of the third substrate (410) may be formed on the upper surface of the third substrate (410). A second input / output pad (405) and / or a third input / output pad (406) may be disposed on the upper insulating film (401). The second input / output pad (405) may be connected to at least one of a plurality of circuit elements (220a) disposed in the peripheral circuit area (PERI) through the second input / output contact plugs (403, 303), and the third input / output pad (406) may be connected to at least one of a plurality of circuit elements (220a) disposed in the peripheral circuit area (PERI) through the third input / output contact plugs (404, 304).

[0103] In one embodiment, the third substrate (410) may not be placed in the area where the input / output contact plug is placed. For example, as shown in B, the third input / output contact plug (404) may be separated from the third substrate (410) in a direction parallel to the upper surface of the third substrate (410) and connected to the third input / output pad (406) by penetrating the interlayer insulating layer (415) of the second cell area (CELL2). In this case, the third input / output contact plug (404) may be formed by various processes.

[0104] For example, as illustrated in B1, the third input / output contact plug (404) may be formed to extend in a third direction (Z-axis direction) and to increase in diameter toward the upper insulating film (401). That is, while the diameter of the channel structure (CH) described in A1 is formed to decrease toward the upper insulating film (401), the diameter of the third input / output contact plug (404) may be formed to increase toward the upper insulating film (401). For example, the third input / output contact plug (404) may be formed after the second cell region (CELL2) and the first cell region (CELL1) are bonded together.

[0105] Additionally, as illustrated in B2, the third input / output contact plug (404) may be formed to extend in a third direction (Z-axis direction) and to have a diameter that decreases toward the upper insulating film (401). That is, the diameter of the third input / output contact plug (404) may be formed to decrease toward the upper insulating film (401), similar to the channel structure (CH). For example, the third input / output contact plug (404) may be formed together with the cell contact plugs (440) before the bonding of the second cell region (CELL2) and the first cell region (CELL1).

[0106] In another embodiment, the input / output contact plug may be positioned to overlap with the third substrate (410). For example, as illustrated in C, the second input / output contact plug (403) may be formed by penetrating the interlayer insulating layer (415) of the second cell region (CELL2) in the third direction (Z-axis direction) and may be electrically connected to the second input / output pad (405) through the third substrate (410). In this case, the connection structure between the second input / output contact plug (403) and the second input / output pad (405) may be implemented in various ways.

[0107] For example, as illustrated in C1, an opening (408) penetrating the third substrate (410) is formed, and the second input / output contact plug (403) can be directly connected to the second input / output pad (405) through the opening (408) formed in the third substrate (410). In this case, as illustrated in C1, the diameter of the second input / output contact plug (403) can be formed to increase toward the second input / output pad (405). However, this is exemplary, and the diameter of the second input / output contact plug (403) can be formed to decrease toward the second input / output pad (405).

[0108] For example, as illustrated in C2, an opening (408) penetrating the third substrate (410) may be formed, and a contact (407) may be formed within the opening (408). One end of the contact (407) may be connected to the second input / output pad (405), and the other end may be connected to the second input / output contact plug (403). Accordingly, the second input / output contact plug (403) may be electrically connected to the second input / output pad (405) through the contact (407) within the opening (408). In this case, as illustrated in C2, the diameter of the contact (407) may be formed to increase toward the second input / output pad (405), and the diameter of the second input / output contact plug (403) may be formed to decrease toward the second input / output pad (405). For example, the third input / output contact plug (403) may be formed together with the cell contact plugs (440) before the bonding of the second cell area (CELL2) and the first cell area (CELL1), and the contact (407) may be formed after the bonding of the second cell area (CELL2) and the first cell area (CELL1).

[0109] Additionally, as illustrated in C3, a stopper (409) may be further formed on the upper surface of the opening (408) of the third substrate (410) compared to C2. The stopper (409) may be a metal wiring formed on the same layer as the common source line (420). However, this is exemplary, and the stopper (409) may be a metal wiring formed on the same layer as at least one of the word lines (430). The second input / output contact plug (403) may be electrically connected to the second input / output pad (405) through the contact (407) and the stopper (409).

[0110] Meanwhile, similar to the second and third input / output contact plugs (403, 404) of the second cell area (CELL2), the second and third input / output contact plugs (303, 304) of the first cell area (CELL1) may each be formed such that their diameter decreases as they approach the lower metal pattern (371e) or increases as they approach the lower metal pattern (371e).

[0111] Meanwhile, according to embodiments, a slit (411) may be formed in the third substrate (410). For example, the slit (411) may be formed at any location in the external pad bonding area (PA). As an example, as shown in D, the slit (411) may be located between the second input / output pad (405) and the cell contact plugs (440) when viewed from a planar perspective. However, this is exemplary, and the slit (411) may be formed such that the second input / output pad (405) is located between the slit (411) and the cell contact plugs (440) when viewed from a planar perspective.

[0112] For example, as illustrated in D1, the slit (411) may be formed to penetrate the third substrate (410). The slit (411) may be used, for example, to prevent the third substrate (410) from being finely split when forming the opening (408). However, this is exemplary, and the slit (411) may be formed to a depth of about 60 to 70% of the thickness of the third substrate (410).

[0113] Additionally, as illustrated in D2, a conductive material (412) may be formed within the slit (411). The conductive material (412) may be used, for example, to discharge leakage current generated during the operation of circuit elements within the external pad bonding area (PA) to the outside. In this case, the conductive material (412) may be connected to an external ground line.

[0114] Additionally, as illustrated in D3, an insulating material (413) may be formed within the slit (411). The insulating material (413) may be formed, for example, to electrically isolate the second input / output pad (405) and the second input / output contact plug (403) placed in the external pad bonding area (PA) from the wordline bonding area (WLBA). By forming the insulating material (413) within the slit (411), the voltage provided through the second input / output pad (405) can be blocked from affecting the metal layer placed on the third substrate (410) within the wordline bonding area (WLBA).

[0115] Meanwhile, according to embodiments, the first to third input / output pads (205, 405, 406) may be optionally formed. For example, the memory device (500) may be implemented to include only the first input / output pad (205) disposed on the upper part of the first substrate (201), or only the second input / output pad (405) disposed on the upper part of the third substrate (410), or only the third input / output pad (406) disposed on the upper part of the upper insulating film (401).

[0116] Meanwhile, according to embodiments, at least one of the second substrate (310) of the first cell region (CELL1) and the third substrate (410) of the second cell region (CELL2) may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. An additional film may be laminated after the substrate removal. For example, the second substrate (310) of the first cell region (CELL1) may be removed before or after bonding the peripheral circuit region (PERI) and the first cell region (CELL1), and an insulating film or a conductive film for connection covering the upper surface of the common source line (320) may be formed. Similarly, the third substrate (410) of the second cell region (CELL2) may be removed before or after bonding the first cell region (CELL1) and the second cell region (CELL2), and an upper insulating film (401) or a conductive film for connection covering the upper surface of the common source line (420) may be formed.

[0117] As described above, embodiments have been disclosed in the drawings and specification. Specific terms have been used herein, but they are used only for the purpose of describing the invention and are not intended to limit the meaning or the scope of the invention as described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention should be determined by the technical spirit of the appended claims.

Claims

Claim 1 A non-volatile memory device for receiving a data signal (DQ) and a data strobe signal (DQS) from the outside, comprising: a variable sampler that processes the data signal (DQ) in amplifier mode or sampler mode in response to a control signal; a selection circuit that transmits the data signal (DQ) output from the variable sampler to an output flip-flop via a delay unit or transmits it to the output flip-flop by bypassing the delay unit in response to the control signal; a converter that amplifies the data strobe signal (DQS); a clock distribution network that transmits the data strobe signal (DQS) amplified by the converter to the variable sampler or transmits the amplified data strobe signal (DQS) to the output flip-flop after a specific time delay in response to the control signal; and a path controller that generates the control signal according to an input / output mode. Claim 2 In claim 1, the path controller is a non-volatile memory device that generates a control signal such that when the input / output mode is a matched mode, the variable sampler operates in amplifier mode and the selection circuit selects the delay unit. Claim 3 In claim 2, the path controller is a non-volatile memory device that controls the clock distribution network so that the data strobe signal (DQS) amplified in the matched mode is transmitted to the output flip-flop. Claim 4 In claim 3, the delay unit is a non-volatile memory device that delays the data signal (DQ) based on the specific time delay occurring in the clock distribution network. Claim 5 In claim 1, the path controller is a non-volatile memory device that generates a control signal such that when the input / output mode is an unmatched mode, the variable sampler operates in sampler mode and the selection circuit bypasses the delay unit. Claim 6 In claim 5, the path controller is a non-volatile memory device that controls the clock distribution network so that the data strobe signal (DQS) amplified in the unmatched mode is transmitted to the variable sampler. Claim 7 A non-volatile memory device according to claim 1, wherein the selection circuit comprises: a demultiplexer that outputs the data signal (DQ) to the delay unit or bypass path in response to the control signal; and a multiplexer that selects either the delay unit or the bypass path in response to the control signal and transmits it to the output flip-flop. Claim 8 In claim 1, the variable sampler is a non-volatile memory device configured by utilizing a double-tail latch or a strong-arm latch. Claim 9 delete Claim 10 delete

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