Gate isolation features for memory and logic devices

Abstract

A semiconductor structure according to the present disclosure comprises a first active region and a second active region, a first gate structure disposed over the first active region, a second gate structure disposed over the second active region, and a gate isolation feature interposed between a sidewall of the first gate structure and a sidewall of the second gate structure. The gate isolation feature comprises a first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing with the first dielectric layer, and a second dielectric layer interfacing with the diffusion barrier liner. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner.

Description

Technology Field

[0001] Priority data

[0002] This application claims priority to U.S. provisional patent application no. 63 / 711,905 filed on October 25, 2024, the entirety of which is incorporated herein by reference. Background Technology

[0003] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have generated generations of ICs, each featuring smaller and more complex circuits than the previous generation. Throughout the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the minimum component (or line) that can be produced using the manufacturing process) has decreased. This scaling down process generally offers benefits by increasing production efficiency and lowering associated costs. However, this scaling down has also increased the complexity of IC processing and manufacturing.

[0004] For example, as integrated circuit (IC) technology advances toward smaller technology nodes, multi-gate devices are being introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and decreasing short-channel effects (SCE). Multi-gate devices generally refer to devices having a gate structure or part thereof positioned over more than one side of the channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (for example, the gate surrounds the top and sidewalls of a “fin” of semiconductor material extending from the substrate). GAA transistors have a gate structure that can extend partially or wholly around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the GAA transistor may also be referred to as a surrounding gate transistor (SGT) or a multi-bridge-channel (MBC) transistor. The channel region of the GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shapes of the channel region have also given the GAA transistor alternative names such as nanosheet transistor or nanowire transistor.

[0005] As the semiconductor industry advances toward sub-10 nanometer (nm) technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both manufacturing and design issues have led to the configuration of stacked device structures, such as complementary field effect transistors (CFETs), in which n-type multi-gate transistors and p-type multi-gate transistors are vertically stacked. While existing CFET structures and manufacturing processes are generally suitable for their intended purposes, they have not been satisfactory in all aspects. This background technology is disclosed in U.S. Patent Application Publication US2022 / 0328625 (Oct. 13, 2022). Brief explanation of the drawing

[0006] The present disclosure is best understood when read in conjunction with the following detailed description and the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not depicted to actual scale and are used for illustrative purposes only. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIG. 1 illustrates the layout of an upper device layer of an exemplary 6-transistor (6T) static random access memory (SRAM) cell implemented as a CFET structure according to one or more aspects of the present disclosure. FIG. 2 illustrates the layout of a bottom device layer of an exemplary 6T SRAM cell implemented with a CFET structure according to one or more aspects of the present disclosure. FIG. 3 illustrates the layout of an upper device layer of a logic standard cell implemented as a CFET structure according to one or more embodiments of the present disclosure. FIG. 4 illustrates the layout of a lower device layer of a logic standard cell implemented as a CFET structure according to one or more embodiments of the present disclosure. FIG. 5 illustrates a partial cross-sectional view along the AA line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4 according to one or more embodiments of the present disclosure. FIG. 6 illustrates a partial cross-sectional view along the BB' line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4 according to one or more embodiments of the present disclosure. FIG. 7 illustrates a partial cross-sectional view along the CC' line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4 according to one or more embodiments of the present disclosure. FIG. 8 illustrates a flowchart of a method for forming a gate isolation feature of a CFET structure according to one or more embodiments of the present disclosure. FIGS. 10 to 15 illustrate partial cross-sectional views of a precursor undergoing various manufacturing processes in the method of FIG. 8 according to one or more embodiments of the present disclosure. FIG. 16 is a schematic diagram illustrating oxygen blocking advantages of a gate isolation feature according to one or more embodiments of the present disclosure. FIG. 17 is a schematic diagram illustrating threshold voltage advantages of a gate isolation feature according to one or more embodiments of the present disclosure. FIG. 18 illustrates a flowchart of a method for forming different gate isolation features in different device regions according to one or more aspects of the present disclosure. FIGS. 19 to 26 illustrate partial cross-sectional views of a precursor undergoing various manufacturing processes in the method of FIG. 18 according to one or more embodiments of the present disclosure. Specific details for implementing the invention

[0007] The following disclosure provides many different embodiments or examples for implementing different features of the claimed subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0008] Spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to include other orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative terms used herein may be interpreted similarly accordingly.

[0009] Additionally, when a number or range of numbers is described as “about,” “approximately,” etc., this term is intended to encompass numbers within a reasonable range, taking into account variations that naturally occur during manufacturing, as understood by those skilled in the art. For example, a number or range of numbers includes a reasonable range containing the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with manufacturing a feature having the characteristics associated with the number. For example, a material layer having a thickness of “about 5 nm” may include a dimensional range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is known to be + / -15% by those skilled in the art.

[0010] A stacked multi-gate device refers to a semiconductor device comprising a lower multi-gate device and an upper multi-gate device stacked on top of the lower multi-gate device. If the lower multi-gate device and the upper multi-gate device have different conductivity types, the stacked multi-gate device may be referred to as a complementary field effect transistor (CFET). The multi-gate devices in a CFET may be FinFETs or GAA transistors. The gate structures for the upper multi-gate device and the second multi-gate device may be electrically coupled together or isolated from each other depending on the design. During the fabrication of a CFET on a substrate, the gate stack may be formed over a number of active regions, and a gate cutting process may be performed to divide the gate stack into a number of segments by gate isolation features. Since each of the gate isolation features is placed between two gate segments, the industry has made dedicated efforts to reduce or minimize the effective dielectric constant of the gate isolation features. The purpose of these efforts is to reduce parasitic capacitance between gate segments and increase device speed.

[0011] The reduction in the dielectric constant of gate isolation features does not occur without consequences across the board. Low-dielectric (low-k) dielectric materials within gate isolation features tend to contain oxygen and can serve as a source of oxygen during gate oxidation processes. When metals within gate structures oxidize, the device's threshold voltage can deviate from the design value. Logic devices are less sensitive to threshold voltage drop as long as they continue to switch with appropriate response times. The same cannot be said for memory devices, such as static random access memory (SRAM) devices. When there is uneven oxidation of components within gate structures at different locations within an SRAM array, the minimum supply voltage (Vmin) across the SRAM array may increase, and some SRAM cells may cease to operate properly. At least for memory devices, it is necessary to address oxygen diffusion from gate isolation features.

[0012] The present disclosure provides a plurality of methods for forming gate isolation features to reduce gate oxidation of devices within a memory structure. A method according to one embodiment forms a gate isolation trench within the gate structures of CFET structures in both logic device regions and memory device regions. A nitrogen-containing layer is deposited within the gate isolation trench. A liner is deposited over the nitrogen-containing layer. An oxygen-containing dielectric layer is deposited over the liner. A planarization process is performed to form a gate isolation feature within the gate isolation trench. The liner helps to reduce or control oxygen diffusion into the gate structures. A method according to another embodiment forms a first gate isolation trench within the gate structures of CFET structures in a logic device region and forms a second gate isolation trench within the gate structures of CFET structures in a memory device region. A nitrogen-containing dielectric layer is deposited to fill the first gate isolation trench and the second gate isolation trench. With the memory device region covered, an inner trench is formed within the nitrogen-containing dielectric layer in the first gate isolation trench. Subsequently, an oxygen-containing dielectric layer is deposited within the internal trench. Then, a planarization process is performed to form a first gate isolation feature within the logic device region and a second gate isolation feature within the memory device region. The first gate isolation feature is configured to provide high-speed switching speeds for the logic devices, and the second gate isolation feature is configured to minimize oxygen diffusion into the gate structures of the memory devices.

[0013] Gate isolation features can be implemented in CFET structures for both logic devices and memory devices. FIGS. 1 and 2 illustrate layouts of a 6-transistor (6T) static random access memory (SRAM) cell (10) having a CFET structure. FIG. 1 illustrates the layout of the upper device layer of the SRAM cell (10), and FIG. 2 illustrates the layout of the lower device layer of the SRAM cell (10). Referring to FIG. 1, in the upper device layer, the SRAM cell (10) includes a first upper active region (12T) and a second upper active region (14T) that extend longitudinally parallel to the Y direction. As illustrated in the partial cross-sectional views in FIGS. 4 and 6, each of the first upper active region (12T) and the second upper active region (14T) also includes a plurality of channel structures or nanostructures that extend longitudinally along the Y direction. The first upper gate structure (16T) engages with the first upper active region (12T) to form the first pull-down transistor (PD1). The second upper gate structure (18T) engages with the second upper active region (14T) to form the second pass gate transistor (PG2). The third upper gate structure (20T) engages with the first upper active region (12T) to form the first pass gate transistor (PG1). The fourth upper gate structure (22T) engages with the second upper active region (14T) to form the second pull-down transistor (PD2). The first upper gate structure (16T) and the second upper gate structure (18T) extend longitudinally along the X direction and are aligned along the X direction. The third upper gate structure (20T) and the fourth upper gate structure (22T) extend longitudinally along the X direction and are aligned along the X direction.The first gate isolation feature (30) extends longitudinally along the Y direction so as to be positioned between the first upper gate structure (16T) and the second upper gate structure (18T), as well as between the third upper gate structure (20T) and the fourth upper gate structure (22T). The drain of the first pull-down transistor (PD1) and the drain of the second pull-down transistor (PD2) are coupled to the ground voltage (Vss) through the first contact via (40) and the second contact via (42). The second gate isolation feature (32) cuts the first upper gate structure (16T) short. The third gate isolation feature (34) cuts the fourth upper gate structure (22T) short.

[0014] Referring to FIG. 2, in the lower device layer, the SRAM cell (10) includes a first lower active region (12B) and a second lower active region (14B) that extend parallel to the longitudinal direction along the Y direction. As illustrated in the partial cross-sectional views in FIG. 4 and FIG. 6, each of the first lower active region (12B) and the second lower active region (14B) includes a plurality of channel structures or nanostructures that also extend longitudinally along the Y direction. A first lower gate structure (16B) engages with the first lower active region (12B) to form a first pull-up transistor (PU1). A second lower gate structure (18B) engages with the second lower active region (14B) and is electrically floating. A third upper gate structure (20T) engages with the first lower active region (12B) and is electrically floating. The fourth lower gate structure (22B) engages with the second lower active region (14B) to form the second pull-up transistor (PU2). The first lower gate structure (16B) and the second lower gate structure (18B) are extended longitudinally along the X direction and aligned along the X direction. The third lower gate structure (20B) and the fourth lower gate structure (22B) are extended longitudinally along the X direction and aligned along the X direction. The first gate isolation feature (30) is extended longitudinally along the Y direction so as to be positioned between the first lower gate structure (16B) and the second lower gate structure (18B), as well as between the third lower gate structure (20B) and the fourth lower gate structure (22B). The source of the first pull-up transistor (PU1) and the source of the second pull-up transistor (PU2) are coupled to the supply voltage (Vdd) through the third contact via (44) and the fourth contact via (46). The second gate isolation feature (32) cuts the first lower gate structure (16B) short. The third gate isolation feature (34) cuts the fourth lower gate structure (22B) short.It can be seen that the first gate isolation feature (30), the second gate isolation feature (32), and the third gate isolation feature (34) extend through the upper device layer and the lower device layer.

[0015] FIGS. 3 and FIGS. 4 illustrate layouts of a logic standard cell (50) having a CFET configuration. FIG. 3 illustrates the layout of the upper device layer of the logic standard cell (50). As illustrated in FIG. 3, in the upper device layer, the logic standard cell (50) includes a first upper active region (12T) and a second upper active region (14T) that extend longitudinally parallel to the Y direction. As illustrated in the partial cross-sectional views in FIGS. 4 and FIG. 6, each of the first upper active region (12T) and the second upper active region (14T) also includes a plurality of channel structures or nanostructures that extend longitudinally along the Y direction. A first upper gate structure (16T) engages with the first upper active region (12T). A second upper gate structure (18T) engages with the second upper active region (14T). A third upper gate structure (20T) engages with the first upper active region (12T). The fourth upper gate structure (22T) engages with the second upper active region (14T). The first upper gate structure (16T) and the second upper gate structure (18T) extend longitudinally along the X direction and are aligned along the X direction. The third upper gate structure (20T) and the fourth upper gate structure (22T) extend longitudinally along the X direction and are aligned along the X direction. The first gate isolation feature (30) extends longitudinally along the Y direction so as to be positioned between the first upper gate structure (16T) and the second upper gate structure (18T), as well as between the third upper gate structure (20T) and the fourth upper gate structure (22T). The fourth gate isolation feature (36) cuts the first upper gate structure (16T) and the third upper gate structure (20T) short. The fifth gate isolation feature (38) cuts the second upper gate structure (18T) and the fourth upper gate structure (22T) short.

[0016] As illustrated in FIG. 4, in the lower device layer, the logic standard cell (50) includes a first lower active region (12B) and a second lower active region (14B) that extend longitudinally parallel to the Y direction. As illustrated in the partial cross-sectional views in FIG. 4 and FIG. 6, each of the first lower active region (12B) and the second lower active region (14B) also includes a plurality of channel structures or nanostructures that extend longitudinally along the Y direction. A first lower gate structure (16B) engages with the first lower active region (12B). A second lower gate structure (18B) engages with the second lower active region (14B). A third lower gate structure (20B) engages with the first lower active region (12B). A fourth lower gate structure (22B) engages with the second lower active region (12B). The first lower gate structure (16B) and the second lower gate structure (18B) are extended longitudinally along the X direction and aligned along the X direction. The third lower gate structure (20B) and the fourth lower gate structure (22B) are extended longitudinally along the X direction and aligned along the X direction. The first gate isolation feature (30) may be extended longitudinally along the Y direction to be positioned between the first lower gate structure (16B) and the second lower gate structure (18B), as well as between the third lower gate structure (20B) and the fourth lower gate structure (22B). The fourth gate isolation feature (36) cuts the first lower gate structure (16B) and the third lower gate structure (20B) short. The fifth gate isolation feature (38) cuts the second lower gate structure (18B) and the fourth lower gate structure (22B) short.

[0017] It can be seen that the SRAM cell (10) and the logic standard cell (50) share similarities with respect to the first gate isolation feature (30), the first upper active region (12T), the second upper active region (14T), the first lower active region (12B), the second lower active region (14B), the first upper gate structure (16T), the second upper gate structure (18T), the third upper gate structure (20T), the fourth upper gate structure (22T), the first lower gate structure (16B), the second lower gate structure (18B), the third lower gate structure (20B), and the fourth lower gate structure (22B). FIGS. 5, 6, and 7 illustrate partial cross-sectional views along line A-A' along the X direction, line B-B' along the X direction, and line C-C' along the Y direction.

[0018] FIG. 5 illustrates a partial cross-sectional view along the AA line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4. A first lower active region (12B) comprises first lower channel structures (106B) stacked on top of each other on a base pin (104). A first upper active region (12T) comprises first upper channel structures (106T) stacked on top of each other on the first lower channel structures (106B). A first lower gate structure (16B) surrounds each of the first lower channel structures (106B). A first upper gate structure (16T) surrounds each of the first upper channel structures (106T). A second upper gate structure (18T) surrounds each of the second upper channel structures (108T). A second lower gate structure (18B) surrounds each of the second lower channel structures (108B). Base pins (104) are patterned from the substrate (102), which is omitted in subsequent drawings for brevity. An isolation feature (103) is deposited on the substrate (102) and extends between the sidewalls of the base pins (104). A first gate isolation feature (30) extends between the first lower gate structure (16B) and the second lower gate structure (18B), and between the first upper gate structure (16T) and the second upper gate structure (18T). In some embodiments, the first gate isolation feature (30) extends partially into the isolation feature (103) and between the base pins (104). An insulating layer (128) is placed between the first lower channel structures (106B) and the first upper channel structures (106T). In some embodiments, the insulating layer (128) is interposed vertically between two intermediate semiconductor layers (106M). In some implementations, the first lower gate structure (16B) and the second lower gate structure (18B) are p-type gate structures and include a p-type work function metal (p-WFM) layer, and the first upper gate structure (16T) and the second upper gate structure (18T) are n-type gate structures and include an n-type work function metal (n-WFM) layer.

[0019] FIG. 6 illustrates a partial cross-sectional view along the BB' line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4. The side walls of the first lower channel structures (106B) are in contact with the first lower source / drain feature (150B). The side walls of the second lower channel structures (108B) are in contact with the second lower source / drain feature (160B). The side walls of the first upper channel structures (106T) are in contact with the first upper source / drain feature (150T). The side walls of the second upper channel structures (108B) are in contact with the second upper source / drain feature (160T). A lower contact etch stop layer (CESL) (152B) is placed over the surface of the isolation feature (103), the first lower source / drain feature (150B), and the surface of the second lower source / drain feature (160B). A lower interlayer dielectric (ILD) layer (154B) is placed over the lower CESL (152B). An upper CESL (152T) is placed over the surface of the first upper source / drain feature (150T) and the surface of the second upper source / drain feature (160T). An upper ILD layer (154T) is placed over the upper CESL (152T).

[0020] FIG. 7 illustrates a partial cross-sectional view along the CC' line in FIG. 1, FIG. 2, FIG. 3, or FIG. 4. As illustrated in FIG. 7, first lower channel structures (106B) are interposed between two first lower source / drain features (150B); and first upper channel structures (106T) are interposed between two first upper source / drain features (150T). Similarly, although not explicitly illustrated in any cross-sectional views, second lower channel structures (108B) are interposed between two second lower source / drain features (160B); and second upper channel structures (108T) are interposed between two second upper source / drain features (160T).

[0021] Methods described below, such as the method (200) in FIG. 8 and the method (400) in FIG. 18, include operations for forming different gate isolation features instead of the first gate isolation feature (30) shown in FIG. 1 through 6. That is, FIG. 1 through 7 provide details of structures around the gate isolation feature to be formed using method (200) or method (400).

[0022] FIGS. 8 and FIGS. 18 are flowcharts illustrating a method (200) and a method (400) for forming gate isolation features for CFET structures within logic device regions and memory device regions according to various aspects of the present disclosure. The methods (200 and 400) are merely illustrative and are not intended to limit the present disclosure to those explicitly exemplified in the methods (200 and 400). Additional steps may be provided before, during, and after the methods (200 and 400), and some of the described steps may be replaced, removed, or swapped for additional embodiments of the method. For the sake of simplification, not all steps are described in detail herein. The method (200) is described below in conjunction with FIGS. 9 through 15, which are partial cross-sectional views of a precursor structure (100) at different manufacturing stages according to embodiments of the method (200). The method (400) is described below in conjunction with FIGS. 19 through 26, which are partial cross-sectional views of a precursor structure (100) at different manufacturing stages according to embodiments of the method (400). Since the precursor structure (100) will be manufactured into a semiconductor device (100) at the end of the manufacturing process, the precursor structure (100) may be referred to as a semiconductor device (100) as required by context. Additionally, throughout this application and across different embodiments, similar reference numbers indicate similar features having similar structures and compositions unless otherwise excluded. Source / drain region(s) may refer to a source or a drain individually or collectively depending on the context.

[0023] The method (200) forms gate isolation features of the same type in both the logic device region and the memory device region.

[0024] Referring to FIGS. 8 and 9, the method (200) comprises a block (202) on which a hard mask layer (170) is formed on a precursor structure (100). The precursor structure (100) comprises a substrate (102) (shown by dashed lines and will be omitted in subsequent drawings), base pins (104) formed from the substrate (102), an isolation feature (103) on the substrate (102) and disposed between the base pins (104), first lower channel structures (106B), second lower channel structures (108B), first upper channel structures (106T), second upper channel structures (108T), a lower gate structure (80) surrounding the first lower channel structures (106B) and the second lower channel structures (108B), and an upper gate structure (90) surrounding the first upper channel structures (106T) and the second upper channel structures (108T).

[0025] In one embodiment, the substrate (102) may be a silicon (Si) substrate. In some other embodiments, the substrate (102) may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate (102) may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Base pins (104) are formed from the substrate (102) and may share the same composition as the substrate (102). In one embodiment, the base pin (104) may comprise silicon (Si). The isolation feature (103) may also be referred to as a shallow trench isolation (STI) feature (103). The isolation feature (103) may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials.

[0026] The first lower channel structure (106B), the second lower channel structure (108B), the first upper channel structure (106T), and the second upper channel structure (108T) are formed from a stack of epitaxial layers formed on a substrate (102). In an exemplary process, the stack of epitaxial layers comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers. After the stack is patterned to form fin-shaped structures, a dummy gate stack is formed on the fin-shaped structures. After the formation of source / drain features, the dummy gate stack is optionally removed, and a plurality of silicon germanium layers are optionally removed to release the first lower channel structure (106B), the second lower channel structure (108B), the first upper channel structure (106T), and the second upper channel structure (108T). In some embodiments, the first lower channel structure (106B), the second lower channel structure (108B), the first upper channel structure (106T), and the second upper channel structure (108T) may comprise silicon (Si). A lower gate structure (80) is deposited to surround each of the first lower channel structure (106B) and the second lower channel structure (108B). An upper gate structure (90) is deposited to surround each of the first upper channel structure (106T) and the second upper channel structure (108T). The precursor structure (100) further comprises two intermediate semiconductor layers (108M). An insulator layer (128) is positioned vertically between the two intermediate semiconductor layers (108M). The insulator layer (128) may comprise silicon oxide, silicon nitride, or silicon carbonitride to separate the lower channel structure from the upper channel structure.

[0027] The lower gate structure (80) includes an interface layer interfacing with the first lower channel structure (106B) and the second lower channel structure (108B), a gate dielectric layer (114) on the interface layer, and a lower gate electrode on the gate dielectric layer (114). In some embodiments, the interface layer may comprise silicon oxide or hafnium silicate. The gate dielectric layer (114) is formed as a high-K dielectric layer. As used and described herein, a high-K dielectric material comprises a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermal silicon oxide (~3.9). In one embodiment, the gate dielectric layer (114) may comprise hafnium oxide. Alternatively, the gate dielectric layer (114) may comprise other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In the illustrated embodiments, the lower gate structure (80) is a p-type gate structure, and the lower gate electrode comprises at least one p-type work function metal layer. In some cases, the p-type work function metal layer may comprise titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), or platinum (Pt).

[0028] The upper gate structure (90) includes an interface layer interfacing with the first upper channel structure (106T) and the second upper channel structure (108T), a gate dielectric layer (114) on the interface layer, and an upper gate electrode on the gate dielectric layer (114). In the illustrated embodiments, the upper gate structure (90) is an n-type gate structure, and the upper gate electrode includes at least one n-type work function metal layer. In some cases, the n-type work function metal layer may include titanium (Ti), aluminum (Al), tantalum carbide (TiC), tantalum carbide nitride (TiCN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or tantalum silicon nitride (TiSiN). When the n-type work function metal layer includes aluminum, they become more sensitive to oxidation due to oxygen diffusion from adjacent structures, such as gate isolation features.

[0029] In block (202), a hard mask layer (170) is deposited on the precursor (100), for example, on the upper surface of the upper gate structure (90). The hard mask layer (170) may be a single layer or a multilayer. In illustrated embodiments, the hard mask layer (170) comprises a first layer (172), a second layer (173) above the first layer (172), and a third layer (174) above the second layer (173). In some embodiments, the first layer (172) and the third layer (174) may share the same composition, whereas the second layer (173) has a composition different from that of the first layer (172) or the third layer (174). To prevent oxygen diffusion into the upper gate structure (90), there is no oxygen in the first layer (172), the second layer (173), and the third layer (174). In some embodiments, the first layer (172) and the third layer (174) comprise silicon nitride or silicon carbonitride, and the second layer comprises silicon. In one embodiment, the first layer (172) and the third layer (174) comprise silicon nitride, and the second layer comprises silicon. In some embodiments, the hard mask layer (170) is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0030] Referring to FIGS. 8, 10, and 11, the method (200) comprises a block (204), wherein a gate isolation trench (184) is formed through an upper gate structure (90) and a lower gate structure (80). Operations in the block (204) may include forming a first patterned photoresist layer (180) (shown in FIG. 10) and etching a precursor structure (100) using the first patterned photoresist layer (180) as an etching mask (shown in FIG. 11). Referring to FIG. 10, the photoresist layer (180) is deposited on a hard mask layer (170) using spin-on coating. In block (204), the first photoresist layer (180) is patterned through soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or a combination thereof. The first patterned photoresist layer (180) includes a mask opening (182). An etching process, such as dry etching (e.g., RIE etching), wet etching, or a combination thereof, is performed to etch the hard mask layer (170), the upper gate structure (90), the lower gate structure (80), and the isolation feature (103). Referring to FIG. 11, the etching in block (204) may extend vertically through the hard mask layer (170) and form a gate isolation trench (184) that divides the upper gate structure (90) into a first upper gate structure (120) and a second upper gate structure (122), and divides the lower gate structure (80) into a first lower gate structure (110) and a second lower gate structure (112). In some embodiments illustrated in FIG. 11, to ensure complete isolation of the lower gate structure (80), the gate isolation trench (184) extends at least partially into the isolation feature (103).As illustrated in FIG. 11, the sidewalls of the hard mask layer (170), the sidewalls of the first upper gate structure (120) and the second upper gate structure (122), the sidewalls of the first lower gate structure (110) and the second lower gate structure (112), the sidewalls of the isolation feature (103), and the upper surface of the isolation feature (103) are exposed in the gate isolation trench (184). After the formation of the gate isolation trench (184), any remaining first patterned photoresist layer (180) is removed from the precursor structure (100). In some cases, the gate isolation trench (184) may also be referred to as a gate cut trench.

[0031] Referring to FIGS. 8 and FIGS. 12, the method (200) comprises a block (206), wherein an oxygen-free dielectric layer (142) is deposited over a gate isolation trench (184). In some embodiments, the oxygen-free dielectric layer (142) may comprise silicon nitride and may be deposited using CVD or ALD. As illustrated in FIG. 12, the deposited oxygen-free dielectric layer (142) may be conformally deposited over the gate isolation trench (184) to interface with the sidewalls of the hard mask layer (170), the sidewalls of the first upper gate structure (120) and the second upper gate structure (122), the sidewalls of the first lower gate structure (110) and the second lower gate structure (112), the sidewalls of the isolation feature (103), and the upper surface of the isolation feature (103). The oxygen-free dielectric layer (142) may have a first thickness (T1) of about 3 nm to about 4 nm.

[0032] Referring to FIGS. 8 and FIGS. 13, the method (200) comprises a block (208), wherein an oxygen blocking layer (144) is deposited over a gate isolation trench (184). The oxygen blocking layer (144) may "block" oxygen diffusion using more than one mechanism. For example, the oxygen blocking layer (144) may be a sacrificial layer for consuming and capturing oxygen while itself is oxidized. In this example, the oxygen blocking layer (144) may comprise amorphous silicon, silicon carbonitride, or amorphous carbon. As another example, the oxygen blocking layer (144) may be a dense oxygen barrier that reduces or limits oxygen diffusion. In this example, the oxygen blocking layer (144) may comprise polymers such as polyimide. In one embodiment, the oxygen blocking layer (144) may comprise amorphous silicon. The oxygen blocking layer (144) may be referred to as a liner and has a second thickness (T2) that is smaller than the first thickness (T1). In some cases, the second thickness (T2) may be about 1 nm to 1.5 nm. The ratio of the second thickness (T2) to the first thickness (T1) may be about 1:4 to about 1:2. The oxygen blocking layer (144) may be deposited using ALD or plasma-enhanced ADL (PEALD). Although not explicitly shown in the drawings, the oxygen blocking layer (144) may be multilayer. In one example, the oxygen blocking layer (144) may include a silicon sublayer interfacing with an oxygen-free dielectric layer (142) and a silicon carbonitride sublayer interfacing with an oxygen-containing dielectric layer to be deposited. It should be noted that the additional layer interface resulting from the introduction of the oxygen blocking layer (144) also helps to slow down the diffusion of oxygen. For example, without the oxygen blocking layer (144), the oxygen-free dielectric layer (142) directly interfaces with the oxygen-containing dielectric layer (146) (to be described below). With the introduction of the oxygen blocking layer (144), the oxygen-free dielectric layer (142) interfaces with the oxygen blocking layer (144), and the oxygen blocking layer (144) interfaces with the oxygen-containing dielectric layer (146).The additional interface creates a barrier for the diffusion of oxygen from the oxygen-containing dielectric layer (146).

[0033] Referring to FIGS. 8 and FIGS. 14, the method (200) comprises a block (210), wherein an oxygen-containing dielectric layer (146) is formed over an oxygen blocking layer (144). In some embodiments, the oxygen-containing dielectric layer (146) may comprise silicon oxide and may be deposited using flowable CVD (FCVD), spin-on coating, CVD, or ALD. As illustrated in FIG. 14, in the block (210), the oxygen-containing dielectric layer (146) not only completely fills the gate isolation trench (184) but also includes a thickness over the upper surface of the oxygen blocking layer (144).

[0034] Referring to FIGS. 8 and FIGS. 15, the method (200) comprises a block (212), wherein a planarization process (300) is performed to expose upper gate structures (120 and 122). The planarization process (300) may include a chemical mechanical polishing (CMP) process. In the block (212), the planarization process (300) is performed to remove excess portions of the oxygen-free dielectric layer (142), the oxygen blocking layer (144), and the oxygen-containing layer (146) to expose the upper surfaces of the first upper gate structure (120) and the second upper gate structure (122). At this stage, a gate isolation feature (140) is substantially formed. As illustrated in FIG. 15, the gate isolation feature (140) includes an oxygen-free dielectric layer (142) interfacing with gate structures (including a first upper gate structure (120), a second upper gate structure (122), a first lower gate structure (110), and a second lower gate structure (112). The gate isolation feature (140) also includes an oxygen blocking layer (144) for shielding the oxygen-free dielectric layer (142) from oxygen diffusion from the innermost oxygen-containing dielectric layer (146).

[0035] Referring to FIG. 8, the method (200) comprises a block (214), wherein additional processes are performed. These additional processes may include the formation of middle-end-of-line (MEOL) features and the formation of back-end-of-line (BEOL) features. MEOL features may include fontside source / drain contacts, gate contact vias, backside source / drain contact vias, and backside gate contact vias. BEOL features may include a fontside interconnect structure and a backside interconnect structure. The fontside interconnect structure comprises a plurality of dielectric layers and a plurality of metal layers disposed within the plurality of dielectric layers. In some embodiments, the fontside interconnect structure comprises about 8 to about 20 metal layers. The backside interconnect structure comprises a plurality of dielectric layers and a plurality of metal layers disposed within the plurality of dielectric layers. In some embodiments, the rear interconnect structure comprises about 2 to about 10 metal layers.

[0036] Simulations and experiments have demonstrated the oxygen blocking benefits of the oxygen blocking layer (144). First, refer to FIG. 16, which plots the oxygen concentration as a function of distance from the gate isolation feature with and without the implementation of the oxygen blocking layer (144). The chart in FIG. 16 illustrates that the oxygen concentration distribution decreases toward the gate isolation feature (140). This indicates that the oxygen blocking layer (144) slows down oxygen diffusion into the gate structure and toward the channel. FIG. 17 includes a chart showing that the implementation of the oxygen blocking layer (144) reduces threshold voltage fluctuations by about 8% to about 10%. As described above, non-uniform oxidation of gate structures, particularly n-type gate structures including aluminum (Al), can increase the minimum supply voltage (Vmin) across the SRAM array and may cause some SRAM cells to stop operating properly. By reducing threshold voltage fluctuations, the oxygen blocking layer (144) reduces fluctuations or increases in Vmin when implemented in SRAM structures.

[0037] The method (400) forms different types of gate isolation features in logic device regions and memory device regions.

[0038] Referring to FIGS. 18 and 19, the method (400) comprises a block (402) wherein a hard mask layer (170) is formed over a first device region (1000) and a second device region (2000) of a precursor structure (100). The precursor structure (100) illustrated in FIG. 19 is similar to the precursor structure (100) illustrated in FIG. 9. A detailed description of the precursor structure (100) of FIG. 19 is omitted for brevity. The precursor structure (100) comprises a first device region (1000) and a second device region (2000). In some embodiments, the first device region (1000) is a memory device region comprising SRAM cells (10) illustrated in FIGS. 1 and 2, and the second device region (2000) is a logic device region comprising logic standard cells (50) illustrated in FIGS. 3 and 4. It should be noted that the method (200) has been described above without reference to different device regions, not because the precursor (100) does not include multiple device regions, but because similar operations are performed for different device regions.

[0039] The precursor structure (100) comprises a substrate (102) (shown by dotted lines and omitted in subsequent drawings) in both the first device region (1000) and the second device region (2000), base pins (104) formed from the substrate (102), an isolation feature (103) placed on the substrate (102) and between the base pins (104), first lower channel structures (106B), second lower channel structures (108B), first upper channel structures (106T), and second upper channel structures (108T). To easily explain the different arrangement of gate structures within the two device regions, the reference numbers for the upper gate structures and lower gate structures within the two device regions are different from those used in FIG. 9. Referring to FIG. 19, above the first device region (1000), a lower gate structure (1080) surrounds the first lower channel structures (106B) and the second lower channel structures (108B), and an upper gate structure (1090) surrounds the first upper channel structures (106T) and the second upper channel structures (108T). Above the second device region (2000), a lower gate structure (2080) surrounds the first lower channel structures (106B) and the second lower channel structures (108B), and an upper gate structure (2090) surrounds the first upper channel structures (106T) and the second upper channel structures (108T).

[0040] In block (402), a hard mask layer (170) is deposited over the first device region (1000) and the second device region (2000), for example, on the upper surface of the upper gate structure (1090) and the upper surface of the upper gate structure (2090). The hard mask layer (170) may be a single layer or a multilayer. In illustrated embodiments, the hard mask layer (170) comprises a first layer (172), a second layer (173) above the first layer (172), and a third layer (174) above the second layer (173). In some embodiments, the first layer (172) and the third layer (174) may share the same composition, whereas the second layer (173) has a composition different from that of the first layer (172) or the third layer (174). To prevent oxygen diffusion into the upper gate structure (90), the first layer (172), the second layer (173), and the third layer (174) are oxygen-free. In some embodiments, the first layer (172) and the third layer (174) comprise silicon nitride or silicon carbonitride, and the second layer comprises silicon. In one embodiment, the first layer (172) and the third layer (174) comprise silicon nitride, and the second layer comprises silicon. In some embodiments, the hard mask layer (170) is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0041] Referring to FIGS. 18, 20, and 21, the method (400) comprises a block (404), wherein a first gate isolation trench (184-1) is formed within a first device region (1000) and a second gate isolation trench (184-2) is formed within a second device region (2000). Operations in the block (404) may include forming a first patterned photoresist layer (180) (shown in FIG. 20) and etching a precursor structure (100) using the first patterned photoresist layer (180) as an etching mask (shown in FIG. 21). Referring to FIG. 20, the first photoresist layer (180) is deposited on a hard mask layer (170) using spin-on coating. In block (404), the first photoresist layer (180) is patterned through soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or a combination thereof. The first patterned photoresist layer (180) includes a first mask opening (182-1) over the first device region (1000) and a second mask opening (182-2) over the second device region (2000). An etching process, such as dry etching (e.g., RIE etching), wet etching, or a combination thereof, is performed to etch the hard mask layer (170), upper gate structures (1090 and 2090), lower gate structures (1080 and 2080), and isolation features (103). Referring to FIG. 21, the etching in block (404) can form a first isolation trench (184-1) that extends vertically through the hard mask layer (170) in the first device region (1000), divides the upper gate structure (1090) into a first upper gate structure (1020) and a second upper gate structure (1022), and divides the lower gate structure (1080) into a first lower gate structure (1010) and a second lower gate structure (1012).Etching in block (404) may also form a first gate isolation feature (184-2) that extends vertically through the hard mask layer (170) in the second device region (2000), divides the upper gate structure (2090) into a first upper gate structure (2020) and a second upper gate structure (2022), and divides the lower gate structure (2080) into a first lower gate structure (2010) and a second lower gate structure (2012). In some embodiments illustrated in FIG. 21, to ensure complete isolation of the lower gate structures (1080 or 2080), the gate isolation trenches (184-1 and 184-2) extend at least partially into the isolation feature (103). As illustrated in FIG. 21, the sidewalls of the hard mask layer (170), the sidewalls of the first upper gate structures (1020) and the second upper gate structure (1022), the sidewalls of the first lower gate structure (1010) and the second lower gate structure (1012), the sidewalls of the isolation feature (103), and the upper surface of the isolation feature (103) are exposed in the first gate isolation feature (184-1). In the second device region (2000), the sidewalls of the hard mask layer (170), the sidewalls of the first upper gate structures (2020) and the second upper gate structure (2022), the sidewalls of the first lower gate structure (2010) and the second lower gate structure (2012), the sidewalls of the isolation feature (103), and the upper surface of the isolation feature (103) are exposed in the second gate isolation feature (184-2). After the formation of the first gate isolation trench (184-1) and the second gate isolation trench (184-2), any remaining first patterned photoresist layer (180) is removed from the precursor structure (100). In some cases, the first gate isolation trench (184-1) and the second gate isolation trench (184-2) may also be referred to as the first gate cut trench (184-1) and the second gate cut trench (184-2).

[0042] Referring to FIGS. 18 and FIGS. 22, the method (400) comprises a block (406), wherein an oxygen-free dielectric layer (142) is placed over a first gate isolation trench (184-1) and a second gate isolation trench (184-2). In some embodiments, the oxygen-free dielectric layer (142) may comprise silicon nitride and may be deposited using CVD or ALD. As illustrated in FIG. 22, the deposited oxygen-free dielectric layer (142) may be deposited over the first gate isolation trench (184-1) and the second gate isolation trench (184-2). In illustrated embodiments, the oxygen-free dielectric layer (142) completely fills the first gate isolation trench (184-1) within the first device region (1000) and the second gate isolation trench (184-2) within the second device region (2000). In some cases, the anaerobic dielectric layer (142) deposited in the block (406) covers the upper surface of the hard mask layer (170).

[0043] Referring to FIGS. 18 and FIGS. 23, the method (400) comprises a block (408), wherein a first device region (1000) and a second device region (2000) are flattened in a flattening process (320) to thin the oxygen-free dielectric layer (142). To form a smooth and flat top surface for subsequent operations, the block (408) flattens the precursor structure (100) to reduce the thickness of the oxygen-free dielectric layer (142) on the top surface of the hard mask layer (170). In some cases, the flattening process (300) includes a chemical mechanical polishing (CMP) process.

[0044] Referring to FIG. 18 and FIG. 24, the method (400) comprises a block (410), wherein an internal trench (192) is formed by penetrating an oxygen-free dielectric layer (142) within a second gate isolation trench (184-2). Operations in the block (410) may include forming a second patterned photoresist layer (190) and etching a precursor structure (100) using the second patterned photoresist layer (190) as an etching mask. Referring to FIG. 24, the second photoresist layer (190) is deposited on a hard mask layer (170) using spin-on coating. In block (410), the second photoresist layer (190) is patterned by undergoing soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or a combination thereof. The second patterned photoresist layer (190) includes a mask opening directly above a second gate isolation trench (184-2) filled with an oxygen-free dielectric layer (142). To etch the oxygen-free dielectric layer (142) within the second gate isolation trench (184-2), an etching process such as dry etching (e.g., RIE etching), wet etching, or a combination thereof is performed. Referring to FIG. 24, etching in block (410) may form an inner trench (192) that extends vertically through the oxygen-free dielectric layer (142) within the second gate isolation trench (184-2). As illustrated in FIG. 24, the inner trench (192) is spaced apart from the sidewalls of the first upper gate structure (2020) and the second upper gate structure (2022), the sidewalls of the first lower gate structure (2010) and the second lower gate structure (2012), and the isolation feature (103) by the oxygen-free dielectric layer. In some embodiments illustrated in FIG. 24, the lower surface of the inner trench (192) may extend lower than the upper surface of the isolation feature (103).After the formation of the internal trench (192), any remaining second patterned photoresist layer (190) is removed from the precursor structure (100).

[0045] Referring to FIGS. 18 and FIGS. 25, the method (400) comprises a block (412) in which an oxygen-containing dielectric layer (146) is deposited over an inner trench (192). In some embodiments, the oxygen-containing dielectric layer (146) may comprise silicon oxide and may be deposited using flowable CVD (FCVD), spin-on coating, CVD, or ALD. As illustrated in FIG. 25, in the block (412), the oxygen-containing dielectric layer (146) not only completely fills the inner trench (192) within the second region (2000) but is also deposited over the upper surface of the oxygen-free dielectric layer (142) within the first device region (1000).

[0046] Referring to FIGS. 18 and 26, the method (400) comprises a block (414), wherein a planarization process (340) is performed to expose upper gate structures (120 and 122). The planarization process (340) may include a chemical mechanical polishing (CMP) process and functions to remove an oxygen-free dielectric layer (142) and an oxygen-containing dielectric layer (146) on the upper surface of the first upper gate structure (1020) and the second upper gate structure (1022) within the first device region (1000) and on the upper surface of the first upper gate structure (2020) and the second upper gate structure (2022) within the second device region (2000). At this point, a first type of gate isolation feature (1400) is formed in the first device region (1000), and a second type of gate isolation feature (1402) is formed in the second device region (2000). A first type of gate isolation feature (1400) is formed entirely of an oxygen-free dielectric layer (142) and helps reduce oxygen diffusion into the gate structure in contact with it. The first type of gate isolation feature (1400) is suitable for applications where device degradation is primarily caused by oxygen diffusion. A second type of gate isolation feature (1402) includes both an oxygen-free dielectric layer (142) and an oxygen-containing dielectric layer (146). The second type of gate isolation feature (1402) tends to have a smaller dielectric constant and is suitable for logic devices requiring high-speed switching and low parasitic capacitance.

[0047] Referring to FIG. 18, the method (400) comprises a block (416) where additional processes are performed. These additional processes may include the formation of middle-end-of-line (MEOL) features and back-end-of-line (BEOL) features. MEOL features may include front source / drain contacts, gate contact vias, back source / drain contact vias, and back gate contact vias. BEOL features may include a front interconnect structure and a back interconnect structure. The front interconnect structure comprises a plurality of dielectric layers and a plurality of metal layers disposed within the plurality of dielectric layers. In some embodiments, the front interconnect structure comprises about 8 to about 20 metal layers. The back interconnect structure comprises a plurality of dielectric layers and a plurality of metal layers disposed within the plurality of dielectric layers. In some embodiments, the back interconnect structure comprises about 2 to about 10 metal layers.

[0048] In one exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises a first active region and a second active region, a first gate structure disposed over the first active region, a second gate structure disposed over the second active region, and a gate isolation feature interposed between a sidewall of the first gate structure and a sidewall of the second gate structure. The gate isolation feature comprises a first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing with the first dielectric layer, and a second dielectric layer interfacing with the diffusion barrier liner. The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner, and the composition of the first dielectric layer is different from the composition of the second dielectric layer.

[0049] In some embodiments, the diffusion barrier liner comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer. In some embodiments, the first active region comprises a first plurality of nanostructures, the second active region comprises a second plurality of nanostructures, the first gate structure surrounds each of the first plurality of nanostructures, and the second gate structure surrounds each of the second plurality of nanostructures. In some embodiments, the semiconductor structure further comprises a third active region above the first active region, a fourth active region above the second active region, a third gate structure disposed above the third active region, and a fourth gate structure disposed above the fourth active region. A gate isolation feature is also interposed between the sidewall of the third gate structure and the sidewall of the fourth gate structure. In some embodiments, the third gate structure is disposed above the first gate structure, and the fourth gate structure is disposed above the second gate structure. In some embodiments, the first gate structure and the second gate structure comprise a p-type work function layer, and the third gate structure and the fourth gate structure comprise an n-type work function layer. In some embodiments, the n-type work function layer comprises titanium aluminum. In some embodiments, the diffusion barrier liner comprises a first thickness, and the first dielectric layer comprises a second thickness greater than the first thickness. In some embodiments, the ratio of the first thickness to the second thickness is about 1:4 to about 1:2. In some embodiments, the first thickness is about 1 nm to about 1.5 nm, and the second thickness is about 3 nm to about 4 nm.

[0050] In other exemplary embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises a substrate having a memory device region and a logic device region, a first gate structure and a second gate structure on the memory device region, a third gate structure and a fourth gate structure on the logic device region, a first gate isolation feature interposed between the first gate structure and the second gate structure, and a second gate isolation feature interposed between the third gate structure and the fourth gate structure. The composition of the first gate isolation feature is different from the composition of the second gate isolation feature.

[0051] In some embodiments, the first gate isolation feature comprises silicon nitride, and the second gate isolation feature comprises an outer layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, and an inner layer spaced apart from the sidewall of the first gate structure and the sidewall of the second gate structure by the outer layer. The composition of the outer layer is different from the composition of the inner layer. In some embodiments, the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer. In some embodiments, the outer layer comprises silicon nitride, and the inner layer comprises silicon oxide. In some embodiments, the semiconductor structure further comprises a first upper gate structure on the first gate structure, a second upper gate structure on the second gate structure, a third upper gate structure on the third gate structure, and a fourth upper gate structure on the fourth gate structure. The first gate isolation feature extends between the first upper gate structure and the second upper gate structure, and the second gate isolation feature extends between the third upper gate structure and the fourth upper gate structure. In some embodiments, the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprise a p-type work function metal layer, and the first upper gate structure, the second upper gate structure, the third upper gate structure, and the fourth upper gate structure comprise an n-type work function metal layer.

[0052] In another exemplary embodiment, the present disclosure relates to a method. The method comprises the steps of: providing a precursor structure—the precursor structure comprising a substrate including a first device region and a second device region, a first lower gate structure above the first device region, a first upper gate structure above the first lower gate structure, a first hard mask layer above the first upper gate structure, a second lower gate structure above the second device region, a second upper gate structure above the second lower gate structure, and a second hard mask layer above the second upper gate structure—; forming a first trench through the first hard mask layer, the first upper gate structure, and the first lower gate structure; forming a second trench through the second hard mask layer, the second upper gate structure, and the second lower gate structure; and depositing a first dielectric layer on the first device region and the second device region to fill the first trench and the second trench. The method comprises the steps of: forming the patterned mask over the first device region and the second device region while a portion of the first dielectric layer over the second trench is exposed through an opening of the patterned mask; etching the first dielectric layer within the second trench to form an inner trench; removing the patterned mask; depositing the second dielectric layer over the inner trench; and, after depositing the second dielectric layer, flattening the precursor structure to expose the upper surfaces of the first upper gate structure and the second upper gate structure and to form a first gate cut feature within the first trench and a second gate cut feature within the second trench. The composition of the first dielectric layer is different from the composition of the second dielectric layer.

[0053] In some embodiments, the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon oxide. In some embodiments, the first lower gate structure and the second lower gate structure comprise a p-type work function metal layer, and the first upper gate structure and the second upper gate structure comprise an n-type work function metal layer. In some embodiments, the first gate cut feature is positioned between the first stack of nanostructures and the second stack of nanostructures, and the first gate cut feature divides the first lower gate structure into a first gate segment and a second gate segment, the first gate segment surrounds each of the first stack of nanostructures, and the second gate segment surrounds each of the second stack of nanostructures.

[0054] The foregoing describes the features of various embodiments to better enable those skilled in the art to understand the aspects of the present disclosure. Those skilled in the art should know that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and changes can be made in this specification without departing from the spirit and scope of the present disclosure.

[0055] Book

[0056] 1. In semiconductor structures,

[0057] First active region and second active region;

[0058] A first gate structure disposed over the first active region;

[0059] A second gate structure disposed over the second active region; and

[0060] It includes a gate isolation feature interposed between the sidewall of the first gate structure and the sidewall of the second gate structure, and

[0061] The above gate isolation feature is,

[0062] A first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure,

[0063] A diffusion barrier liner interfacing with the first dielectric layer, and

[0064] It includes a second dielectric layer interfacing with the above-mentioned diffusion barrier liner, and

[0065] The second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner, and

[0066] A semiconductor structure in which the composition of the first dielectric layer is different from the composition of the second dielectric layer.

[0067] 2. A semiconductor structure according to claim 1, wherein the diffusion barrier liner comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer.

[0068] 3. In Paragraph 1,

[0069] The first active region comprises a first plurality of nanostructures, and

[0070] The second active region comprises a second plurality of nanostructures, and

[0071] The first gate structure surrounds each of the first plurality of nanostructures, and

[0072] A semiconductor structure in which the second gate structure surrounds each of the second plurality of nanostructures.

[0073] 4. In Paragraph 1,

[0074] A third active region above the first active region;

[0075] A fourth active region above the second active region;

[0076] A third gate structure disposed over the third active region; and

[0077] It further includes a fourth gate structure disposed on the fourth active region, and

[0078] The above gate isolation feature is also a semiconductor structure interposed between the sidewall of the third gate structure and the sidewall of the fourth gate structure.

[0079] 5. In Paragraph 4,

[0080] The above third gate structure is positioned on the above first gate structure, and

[0081] A semiconductor structure wherein the above-mentioned fourth gate structure is disposed on the above-mentioned second gate structure.

[0082] 6. In Paragraph 5,

[0083] The first gate structure and the second gate structure include a p-type work function layer, and

[0084] A semiconductor structure wherein the third gate structure and the fourth gate structure include an n-type work function layer.

[0085] 7. A semiconductor structure according to claim 6, wherein the n-type work function layer comprises titanium aluminum.

[0086] 8. In Paragraph 1,

[0087] The above diffusion barrier liner includes a first thickness, and

[0088] A semiconductor structure in which the first dielectric layer comprises a second thickness greater than the first thickness.

[0089] 9. A semiconductor structure according to claim 8, wherein the ratio of the first thickness to the second thickness is about 1:4 to about 1:2.

[0090] 10. In Paragraph 8,

[0091] The first thickness is about 1 nm to about 1.5 nm, and

[0092] A semiconductor structure having a second thickness of about 3 nm to about 4 nm.

[0093] 11. In semiconductor structures,

[0094] A substrate having a memory device area and a logic device area;

[0095] A first gate structure and a second gate structure above the memory device region;

[0096] A third gate structure and a fourth gate structure above the logic device area;

[0097] A first gate isolation feature interposed between the first gate structure and the second gate structure; and

[0098] It includes a second gate isolation feature interposed between the third gate structure and the fourth gate structure, and

[0099] A semiconductor structure in which the composition of the first gate isolation feature is different from the composition of the second gate isolation feature.

[0100] 12. In Paragraph 11,

[0101] The first gate isolation feature above comprises silicon nitride, and

[0102] The above second gate isolation feature is,

[0103] An outer layer interfacing with the side wall of the first gate structure and the side wall of the second gate structure, and

[0104] It includes an inner layer spaced apart from the side wall of the first gate structure and the side wall of the second gate structure by the outer layer,

[0105] A semiconductor structure in which the composition of the outer layer is different from the composition of the inner layer.

[0106] 13. A semiconductor structure according to claim 12, wherein the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer.

[0107] 14. A semiconductor structure according to claim 12, wherein the outer layer comprises silicon nitride and the inner layer comprises silicon oxide.

[0108] 15. In Paragraph 11,

[0109] A first upper gate structure above the first gate structure;

[0110] A second upper gate structure above the second gate structure;

[0111] A third upper gate structure above the third gate structure; and

[0112] It further includes a fourth upper gate structure above the fourth gate structure, and

[0113] The first gate isolation feature extends between the first upper gate structure and the second upper gate structure, and

[0114] A semiconductor structure in which the second gate isolation feature extends between the third upper gate structure and the fourth upper gate structure.

[0115] 16. In Paragraph 15,

[0116] The first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include a p-type work function metal layer, and

[0117] A semiconductor structure wherein the first upper gate structure, the second upper gate structure, the third upper gate structure, and the fourth upper gate structure comprise an n-type work function metal layer.

[0118] 17. Regarding the method,

[0119] Step of providing a precursor structure - the precursor structure is,

[0120] A substrate including a first device region and a second device region,

[0121] A first lower gate structure above the first device area,

[0122] The first upper gate structure above the first lower gate structure,

[0123] A first hard mask layer on the first upper gate structure above,

[0124] A second lower gate structure above the second device area,

[0125] The second upper gate structure above the second lower gate structure, and

[0126] Includes a second hard mask layer on the second upper gate structure above;

[0127] A step of forming a first trench by penetrating the first hard mask layer, the first upper gate structure, and the first lower gate structure;

[0128] A step of forming a second trench by penetrating the second hard mask layer, the second upper gate structure, and the second lower gate structure;

[0129] A step of depositing a first dielectric layer on the first device region and the second device region to fill the first trench and the second trench;

[0130] A step of forming the patterned mask over the first device region and the second device region while a portion of the first dielectric layer over the second trench is exposed through an opening of the patterned mask;

[0131] A step of etching the first dielectric layer in the second trench to form an internal trench;

[0132] Step of removing the patterned mask;

[0133] A step of depositing a second dielectric layer on the inner trench above; and

[0134] After depositing the second dielectric layer, the method includes the step of flattening the precursor structure to expose the upper surfaces of the first upper gate structure and the second upper gate structure, and to form a first gate cut feature in the first trench and a second gate cut feature in the second trench.

[0135] A method in which the composition of the first dielectric layer is different from the composition of the second dielectric layer.

[0136] 18. In Paragraph 17,

[0137] The first dielectric layer comprises silicon nitride, and

[0138] A method in which the second dielectric layer comprises silicon oxide.

[0139] 19. In Paragraph 17,

[0140] The first lower gate structure and the second lower gate structure include a p-type work function metal layer, and

[0141] A method in which the first upper gate structure and the second upper gate structure comprise an n-type work function metal layer.

[0142] 20. In Paragraph 17,

[0143] The above-mentioned first gate cut feature is positioned between a first stack of nanostructures and a second stack of nanostructures, and

[0144] The first gate cut feature divides the first lower gate structure into a first gate segment and a second gate segment, and

[0145] The first gate segment surrounds each of the first stacks of the nanostructures, and

[0146] A method in which the second gate segment surrounds each of the second stacks of the nanostructures.

Claims

Claim 1 A semiconductor structure comprising: a first active region and a second active region; a first gate structure disposed over the first active region; a second gate structure disposed over the second active region; and a gate isolation feature interposed between a sidewall of the first gate structure and a sidewall of the second gate structure, wherein the gate isolation feature comprises a first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing with the first dielectric layer, and a second dielectric layer interfacing with the diffusion barrier liner, wherein the second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner, the composition of the first dielectric layer is different from the composition of the second dielectric layer, and the diffusion barrier liner comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer. Claim 2 A semiconductor structure according to claim 1, wherein the first active region comprises a first plurality of nanostructures, the second active region comprises a second plurality of nanostructures, the first gate structure surrounds each of the first plurality of nanostructures, and the second gate structure surrounds each of the second plurality of nanostructures. Claim 3 A semiconductor structure comprising: a first active region and a second active region; a first gate structure disposed over the first active region; a second gate structure disposed over the second active region; a gate isolation feature interposed between a sidewall of the first gate structure and a sidewall of the second gate structure; a third active region over the first active region; a fourth active region over the second active region; and a third gate structure disposed over the third active region. A semiconductor structure comprising a fourth gate structure disposed on the fourth active region, wherein the gate isolation feature comprises a first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing with the first dielectric layer, and a second dielectric layer interfacing with the diffusion barrier liner, wherein the second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner, and the composition of the first dielectric layer is different from the composition of the second dielectric layer, and the gate isolation feature is also interposed between the sidewall of the third gate structure and the sidewall of the fourth gate structure. Claim 4 A semiconductor structure according to paragraph 3, wherein the third gate structure is disposed on the first gate structure and the fourth gate structure is disposed on the second gate structure. Claim 5 A semiconductor structure according to claim 4, wherein the first gate structure and the second gate structure comprise a p-type work function layer, and the third gate structure and the fourth gate structure comprise an n-type work function layer. Claim 6 A semiconductor structure according to claim 5, wherein the n-type work function layer comprises titanium aluminum. Claim 7 A semiconductor structure comprising: a first active region and a second active region; a first gate structure disposed over the first active region; a second gate structure disposed over the second active region; and a gate isolation feature interposed between a sidewall of the first gate structure and a sidewall of the second gate structure, wherein the gate isolation feature comprises a first dielectric layer interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure, a diffusion barrier liner interfacing with the first dielectric layer, and a second dielectric layer interfacing with the diffusion barrier liner, wherein the second dielectric layer is spaced apart from the first dielectric layer by the diffusion barrier liner, the composition of the first dielectric layer is different from the composition of the second dielectric layer, the diffusion barrier liner has a first thickness, and the first dielectric layer has a second thickness greater than the first thickness. Claim 8 A semiconductor structure according to claim 7, wherein the ratio of the first thickness to the second thickness is 1:4 to 1:

2. Claim 9 A semiconductor structure comprising: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure on the memory device region; a third gate structure and a fourth gate structure on the logic device region; a first gate isolation feature interposed between the first gate structure and the second gate structure; and a second gate isolation feature interposed between the third gate structure and the fourth gate structure, wherein the composition of the first gate isolation feature is different from the composition of the second gate isolation feature. Claim 10 In a method, the method comprises the steps of: providing a precursor structure, wherein the precursor structure comprises a substrate including a first device region and a second device region, a first lower gate structure above the first device region, a first upper gate structure above the first lower gate structure, a first hard mask layer above the first upper gate structure, a second lower gate structure above the second device region, a second upper gate structure above the second lower gate structure, and a second hard mask layer above the second upper gate structure; forming a first trench by penetrating the first hard mask layer, the first upper gate structure, and the first lower gate structure; forming a second trench by penetrating the second hard mask layer, the second upper gate structure, and the second lower gate structure; depositing a first dielectric layer on the first device region and the second device region to fill the first trench and the second trench; and the first device region and the second device while a portion of the first dielectric layer on the second trench is exposed through an opening of a patterned mask. A method comprising: forming a patterned mask over a region; etching the first dielectric layer in the second trench to form an internal trench; removing the patterned mask; depositing a second dielectric layer over the internal trench; and, after depositing the second dielectric layer, flattening the precursor structure to expose the upper surfaces of the first upper gate structure and the second upper gate structure and to form a first gate cut feature in the first trench and a second gate cut feature in the second trench, wherein the composition of the first dielectric layer is different from the composition of the second dielectric layer.

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