Light-emitting device and manufacturing method thereof

Abstract

A pixel structure comprises: a substrate including an upper surface, a lower surface, and a side surface located between the upper and lower surfaces; a circuit structure embedded in the substrate and including an upper electrode layer exposed on the upper surface, a lower electrode layer exposed on the lower surface, and an intermediate circuit layer located between the upper and lower electrodes and completely clad by the substrate; a plurality of light-emitting semiconductor elements located on the upper surface and electrically connected to the circuit structure; a non-light-emitting semiconductor element embedded in the substrate and directly connected to the intermediate circuit layer, but exposing at least one outer surface; and a transparent adhesive layer covering the plurality of light-emitting semiconductor elements and in direct contact with the substrate.

Description

Technology Field

[0001] The present invention relates to a light-emitting device and a method for manufacturing the same, and in particular to a light-emitting device having a carrier board in which a non-light-emitting semiconductor element is embedded and a method for manufacturing the same. Background Technology

[0002] A light-emitting diode belongs to the category of monochromatic light semiconductor devices, and when used as a pixel light-emitting device for a display screen, it can easily expand the color gamut of a large screen and increase clarity. The display device (100) illustrated in FIG. 1 includes a circuit carrier board (1) and a plurality of pixels (2) mounted in an array manner on the carrier board (1), and each pixel (2) includes at least one set of light-emitting diodes for red light, indigo light, and green light. A control chip (not shown) placed on the circuit carrier board (1) receives an external signal and controls the operation of the pixels.

[0003] FIGS. 2A and 2B illustrate a pixel package (2A) equipped with a conventional control chip. FIG. 2A shows a perspective view of the pixel package (2A), and FIG. 2B shows a plan view of the pixel package (2A). The pixel package (2A) includes a substrate (4), a set of light-emitting diodes (21, 22, 23) emitting red light, indigo light, and green light, a control chip (3), and a light-transmitting protective layer (24). The control chip (3) and the light-emitting diodes (21, 22, 23) are each installed on opposite sides of the substrate (4). The light-transmitting protective layer (24) covers the light-emitting diodes (21, 22, 23) and the control chip (3). Since the height, width, and length of the control chip (3) are generally more than twice that of a single light-emitting diode, the control chip (3) blocks light emission in the X direction of the light-emitting diodes (21, 22, 23), thereby deflecting the light pattern of the pixel package (2A) to one side. When the pixel package (2A) is used as the pixel (2) of FIG. 1, the image quality of the display (100) deteriorates due to the deflection of the light pattern of the pixel package (2A), and thus cannot provide a good viewing experience. The problem to be solved

[0004] This invention was made by focusing on the above-mentioned problem. means of solving the problem

[0005] The pixel structure in the present invention comprises: a substrate including an upper surface, a lower surface, and a side surface located between the upper surface and the lower surface; a circuit structure embedded in the substrate and including an upper electrode layer exposed on the upper surface, a lower electrode layer exposed on the lower surface, and an intermediate circuit layer located between the upper electrode and the lower electrode and completely clad by the substrate; a plurality of light-emitting semiconductor elements located on the upper surface and electrically connected to the circuit structure; a non-light-emitting semiconductor element embedded in the substrate and directly connected to the intermediate circuit layer, but having at least one outer surface exposed; and a transparent adhesive layer covering the plurality of light-emitting semiconductor elements and in direct contact with the substrate. Brief explanation of the drawing

[0006] Figure 1 shows a conventional LED display. FIGS. 2a and 2b show a conventional pixel package equipped with a control chip. FIG. 3 shows a plan view of a pixel package (8A) according to one embodiment. FIG. 4 shows a cross-sectional view of a pixel package (8A) along the line AA' of FIG. 3. Figure 5 shows a bottom view of a pixel package (8A). FIG. 6a shows a perspective view of the circuit structure of the pixel package (8A) and the control chip. Figure 7 shows the electrode array of the control chip. FIG. 8 shows a pixel package (8B) with a control chip embedded therein according to another embodiment. FIGS. 9 to 13 illustrate a manufacturing process of a pixel package according to one embodiment. Specific details for implementing the invention

[0007] According to one embodiment, FIGS. 3 to 5 show a pixel package (8A) with a control chip embedded therein, FIG. 3 shows a top view of the pixel package (8A), FIG. 4 shows a cross-sectional view of the pixel package (8A) along the line AA' of FIG. 3, and FIG. 5 shows a bottom view of the pixel package (8A). As shown in FIG. 3, the pixel package (8A) includes a set of light-emitting diodes (21, 22, 23), and the light-emitting diodes (21, 22, 23) are located in the middle region of the upper surface (41S1) of the substrate (4) and can emit red light, indigo light, and green light, respectively. As illustrated in FIG. 4, the pixel package (8A) includes a substrate (4), light-emitting diodes (21, 22, 23) installed on the substrate (4), a light-transmitting protective layer (24) installed on the upper surface (41S1) of the substrate (4) and covering the light-emitting diodes (21, 22, 23), and a control chip embedded in the substrate (4) and electrically connected to the light-emitting diodes (21, 22, 23) through a circuit structure (42) in the substrate (4). FIG. 5 shows a bottom view of a pixel package (8A), and a plurality of lower electrodes (423) and a control chip (3) are exposed on the bottom surface (41S2) of a substrate (4). The plurality of lower electrodes (423) are for introducing external signals and power to the control chip (3) and light-emitting diodes (21, 22, 23), and the control chip (3) is also for outputting power to the light-emitting diodes (21, 22, 23) according to the command of the external signal, so as to control the time and intensity of the light-emitting diodes (21, 22, 23) emitting red light, blue light, and green light.

[0008] In one embodiment, the number of light-emitting diodes (21, 22, 23) is three, and in another embodiment, the number of light-emitting diodes may exceed three. In one embodiment, the light-emitting diodes (21, 22, 23) are light-emitting diode dies capable of emitting light of different wavelengths or different colors, and each have a p-type semiconductor layer, an n-type semiconductor layer, a light-emitting layer located between the p-type semiconductor layer and the n-type semiconductor layer, a p-electrode connected to the p-type semiconductor layer, and an n-electrode connected to the n-type semiconductor layer. The p-electrode and the n-electrode are intended to introduce current to cause the light-emitting layer to emit light. In one embodiment, the light-emitting diode (21) is a red light-emitting diode die capable of emitting a first light, and the dominant wavelength or peak wavelength of the first light is between 600 and 660 nm. The light-emitting diode (22) is a green light-emitting diode die capable of emitting a second light, and the dominant wavelength or peak wavelength of the second light is between 510 and 560 nm. The light-emitting diode (23) is an indigo light-emitting diode die capable of emitting a third light, and the dominant wavelength or peak wavelength of the third light is between 430 and 480 nm. The structures of the light-emitting diodes (21, 22, 23) are similar, but the composition of the p-type semiconductor layer, n-type semiconductor layer, and light-emitting layer is different. The material of the light-transmitting protective layer (24) may be resin, ceramic, glass, or a combination of the above materials, and the transmittance of all wavelength bands with wavelengths of 430 to 480 nm, 510 to 560 nm, and 600 to 660 nm is greater than 50%.

[0009] As illustrated in FIG. 4, the substrate (4) comprises a circuit structure (42) and a substrate (41) that clads the circuit structure (42) and the control chip (3). The material of the substrate (41) may be ABF (Ajinomoto Build-up Film), epoxy resin, BT (Bismaleimide Triazine) resin, polyimide resin, a composite material of epoxy resin and glass fiber, or a composite material of BT resin and glass fiber. In another embodiment, the substrate (41) has a low coefficient of thermal expansion (CTE), for example, the CTE is between 1 and 100 ppm / °C (the CTE of ABF is about 3 to 10 ppm / °C, and the CTE of BT resin is about 10 to 70 ppm / °C); and to improve the process yield of the pixel package (8A), the difference in CTE between the substrate (41) and the control chip (3) is less than 10 ppm / °C. If the difference in CTE between the substrate (41) and the control chip (3) is too large (e.g., greater than 100 ppm / ℃), or if a process involving violent temperature changes is performed, such as the curing process of the substrate (41) or the process of mounting light-emitting diodes (21, 22, 23) onto the substrate (4) using Surface Mount Technology (SMT), cracks may occur at the interface between the substrate (41) and the control chip (3), causing failure of the substrate (4). In one embodiment, the substrate (4) is a coreless carrier board, and if the material of the substrate (41) is ABF, the line width / line spacing (L / S) of the circuit structure (42) may reach at least 12 / 12 μm. The material of the circuit structure (42) may be a metal such as copper, tin, aluminum, silver, gold, or a combination of these materials.

[0010] As illustrated in FIG. 4, the control chip (3) has a lower surface (32) that is exposed to the substrate (4) and forms a plane with the lower surface (41S2), an upper surface (33) that is relative to the lower surface (32), a plurality of side surfaces (34) that are located between the lower surface (32) and the upper surface (33), and the substrate (41) of the substrate (4) is covered by being in direct contact with the plurality of side surfaces (34) and the upper surface (33), and the control chip (3) has a plurality of electrodes (31) that are located on the upper surface (33) and face the light-emitting diodes (21, 22, 23). In one embodiment, as shown in FIG. 7, the upper surface (33) of the control chip (3) is shown, and the control chip (3) is provided with nine electrodes (31) installed on the upper surface (33) in an array manner (the number of electrodes (31) is not limited to nine and may be less than nine or more than nine). In FIG. 7, the outline of the electrode (31) is circular, but the outline of the electrode (31) may be square, polygonal, or other shapes. In addition, a plurality of electrodes (31) in the array may have the same or different outlines. The plurality of electrodes (31) includes electrodes (311), (312), (313), (314), (315), (316), (317), (318), and (319). The electrodes (311, 312, 313) are each electrically connected to the p-electrode or n-electrode of the light-emitting diode (21, 22, 23). The electrode (315) is electrically connected to the n-electrode or p-electrode of the light-emitting diode (21, 22, 23) (different from the electrode of the light-emitting diode (21, 22, 23) that is electrically connected to the electrode (311, 312, 313). The electrode (316) is for introducing a constant voltage (VDD). The electrode (317) is for grounding (GND). The electrode (318) is for receiving an external control signal (Data Input). The electrodes (319, 314) are reserve electrode locations required for the functional expansion of the control chip (3).

[0011] As illustrated in FIG. 4, the circuit structure (42) includes a circuit layer (421), a conductive pillar (422), and a lower electrode (423). The circuit layer (421) includes circuit layers (421a), (421b), and (421c). The conductive pillar (422) includes conductive pillars (422a), (422b), and (422c). The conductive pillar (422a) is located between the circuit layers (421a) and (421b). The conductive pillar (422b) is located between the circuit layers (421b) and (421c). The conductive pillar (422c) is located between the circuit layer (421c) and the lower electrode (423). As illustrated in FIGS. 3 and 4, the circuit layer (421a) includes an electrode pair (421ab), a connection area (421ac), and wiring (421aa) connecting the connection area (421ac) and the electrode pair (421ab). As illustrated in FIG. 4, the circuit layers (421b, 421c) are located inside the substrate (4), the circuit layer (421b) includes a connection area (421ba) and wiring (421bb), and the circuit layer (421c) includes a connection area (421cb) and wiring (421cc). Referring to FIGS. 3 and 4, the n and p electrodes of the light-emitting diodes (21, 22, 23) are connected to the electrode pair (421ab) through a conductive adhesive or solder paste (not shown), and the connection area (421cb) is connected to the electrodes (311 to 319) of the control chip (3). In the Y direction, the circuit layers (421a, 421b, 421c) overlap each other, the connection area (421ac) and (421ba) are connected to each other through a conductive pillar (422a), the connection area (421ba) and (421cb) are connected to each other through a conductive pillar (422b), and the n electrode (or p electrode) of the light-emitting diodes (21, 22, 23) is electrically connected to the electrodes (311, 312, 313) of the control chip (3) through the arrangement method described above. In one embodiment, the lower electrode (423) and the bottom surface (32) of the control chip (3) form the same plane. In another embodiment, the lower electrode (423) may be lower than the bottom surface (32) of the control chip (3).The lower electrode (423) and the connection area (421ca) are connected by a conductive pillar (422c).

[0012] As illustrated in FIG. 5, a plurality of lower electrodes (423) surround the control chip (3). When a pixel package (8A) is installed on a circuit carrier board (not shown) and connected to an electrode on the circuit carrier board through the lower electrodes (423), the uniformly distributed lower electrodes (423) prevent the pixel package (8A) from tilting or becoming crooked during the bonding process, thereby preventing the light pattern emitted from the pixel package (8A) from being deflected. In one embodiment, both the circuit structure (42) and the control chip (3) are embedded within the substrate (41) of the substrate (4). That is, the substrate (41) clads circuit layers (421a, 421b, 421c), a lower electrode (423) (the substrate (41) exposes the bottom surface of the lower electrode (423)), conductive pillars (422a, 422b, 422c) and a control chip (3) (the substrate (41) exposes the bottom surface of the control chip (3) and covers the side surface (34) and the top surface (33)). In the manufacturing process of the substrate (4), the process of bonding the control chip (3) to the circuit board by integrating the circuit structure (42) and the control chip (3) is omitted.

[0013] FIG. 6 shows a perspective view of the connection structure between the circuit structure (42) and the control chip (3). As illustrated in FIG. 6, the circuit layers (421a, 421b, 421c) have different (projected) patterns (observed in the Y direction). The circuit layer (421b) has a connection area (421bc), and the connection area (421bc) is located in an area adjacent to the corner of the control chip (3) and other than the side (32) (in the Y direction, the connection area (421bc) does not overlap with the control chip (3)), and overlaps with one lower electrode (423) in the Y direction. The lower electrode (423) electrically connected to the connection area (421bc) can be used to introduce a VDD signal (Power supply).

[0014] As illustrated in FIG. 6, the connection area (421cb) of the circuit layer (421c) is installed on the electrodes (311 to 319) of the control chip (3) and is directly connected thereto. The circuit layer (421c) has a connection area (421ca) located in an area other than the side of the control chip (3) (in the Y direction, the connection area (421ca) does not overlap with the control chip (3)). In one embodiment, wiring (412cc) is connected to the connection area (421cb) and the connection area (421ca).

[0015] FIG. 8 shows a pixel package (8B) according to another embodiment of the present application. The pixel package (8B) has a solder resist layer (44) that covers the bottom surface (41S2) and exposes the bottom electrode (423). The material of the solder resist layer (44) is an insulating material such as epoxy resin or polyimide resin.

[0016] In another embodiment, the pixel package (8A, 8B) may have a plurality of sets of light-emitting diodes (21, 22, 23) and a control chip (3) connected to the plurality of sets of light-emitting diodes (21, 22, 23) to control them. In another embodiment, the pixel package (8A, 8B) may include a plurality of sets of light-emitting diodes (21, 22, 23) and a plurality of control chips (3). The plurality of control chips (3) are connected to the plurality of light-emitting diodes (21, 22, 23) to control them.

[0017] FIGS. 9 to 13 illustrate a manufacturing process of a pixel package (8A) according to another embodiment. FIGS. 9 to 13 illustrate a manufacturing process of a pixel package (8B) according to another embodiment.

[0018] As illustrated in FIG. 9, the temporary carrier board (5) is provided with a surface (5S), and the temporary carrier board (5) can be selected from high-temperature resistant materials such as a glass carrier board, a sapphire substrate, a silicon substrate, a BT (Bismaleimide Triazine) resin carrier board, etc., and can withstand subsequent high-temperature processes. A plurality of control chips (3) are temporarily attached or fixed to the surface (5S) of the temporary carrier board (5) through the bottom surface (32). That is, a plurality of electrodes (31) of the control chips (3) face the other side relative to the carrier board (5). A plurality of lower electrodes (423) are present on the surface (5S).

[0019] As illustrated in FIG. 10, the insulating layer (61) covers the surface (5S) of the temporary carrier board (5), the lower electrode (423), and the control chip (3), and exposes a plurality of electrodes (31) of the control chip (3) to the surface (61S) of the insulating layer (61). The material of the insulating layer (61) may be ABF (Ajinomoto Build-up Film), epoxy resin, BT (Bismaleimide Triazine) resin, polyimide resin, a composite material of epoxy resin and glass fiber, or a composite material of BT resin and glass fiber. A plurality of through holes (vias) are formed in the insulating layer (61) to expose the lower electrode (423) by using a patterning process such as mechanical drilling, wet etching, or dry etching. A plurality of conductive pillars (422) connected to the lower electrode (423) are formed by filling the through holes with a conductive material, for example by electroplating or vapor deposition, to fill with metal. A patterned circuit layer (421c) is formed on the surface (61S) of the insulating layer (61) to connect the electrode (31) and the conductive pillar (422c).

[0020] As illustrated in FIG. 11, an insulating layer (62) having a surface (62S) is formed on the surface (61s) of an insulating layer (61), and the materials of the insulating layer (62) and the insulating layer (61) may be the same or different. Since the uppermost surface of the insulating layer (62) is higher than the circuit layer (421c), the insulating layer (62) can completely cover the patterned circuit layer (421c). Through a patterning process such as mechanical drilling, wet etching, or dry etching, a plurality of through holes (vias) are formed in the insulating layer (62) to expose some of the circuit layer (421c), and a conductive material is filled into the through holes, for example, by filling metal by a vapor deposition method, to form conductive pillars (422b) to connect the circuit layer (421c). A patterned circuit layer (421b) is formed on the surface (62S) of the insulating layer (62) to connect the conductive pillars (422b).

[0021] As illustrated in FIG. 12, an insulating layer (63) having a surface (6S) is formed on the surface (62S) of an insulating layer (62), and the materials of the insulating layer (63) and the insulating layers (61, 62) may be the same or different. Since the uppermost surface of the insulating layer (63) is higher than the circuit layer (421b), the insulating layer (63) can completely cover the patterned circuit layer (421b). Through a patterning process such as mechanical drilling, wet etching, or dry etching, a plurality of through holes (Via) are formed in the insulating layer (63) to expose a portion of the circuit layer (421b), and a conductive material is filled into the through holes, for example, by filling metal using a vapor deposition method, to form conductive pillars (422a) and connect the circuit layer (421b). A patterned circuit layer (421a) is formed on the surface (6S) of the insulating layer (63) to connect conductive pillars (422b), and the materials of the insulating layers (61, 62, 63) may be the same or different. The stacked insulating layers (61, 62, 63) form the substrate (41) of the substrate (4'), and the surface (6S) of the insulating layer (63) is the upper surface (41S1) of the substrate (41).

[0022] As shown in FIG. 13a, light-emitting diodes (21, 22, 23) are installed on the circuit layer (421a), and a light-transmitting protective layer (24) is installed on the upper surface (41S1) to cover the light-emitting diodes (21, 22, 23). The temporary carrier board (5) is separated from the substrate (4') so that the lower surface (41S2) of the substrate (4') is exposed, thereby forming a temporary device (2''). A separation process is performed using a cutting tool (9), and the temporary device (2") is separated into a plurality of pixel packages (8A) as shown in FIG. 4.

[0023] In some other embodiments, as shown in FIG. 13b, the temporary carrier board (5) is removed to expose the bottom surface (41S2), the bottom electrode (423), and the bottom surface (32) of the control chip (3), and then the solder resist layer (44) continues to cover the bottom surface (41S2) and the bottom surface (32) of the control chip (3) to form a temporary device (2'''). A separation process is performed using a cutting tool (9) to form a pixel package (8B) having the solder resist layer (44) as shown in FIG. 8.

[0024] In one embodiment, a pixel package (8A), a pixel package (8B), or both may be used in a display (100) as shown in FIG. 1 to replace a pixel package (2). A display (100) to which a pixel package (8A), a pixel package (8B), or both are applied has a transparent carrier board, and the display (100) may be applied to an area such as a shopping mall window, a car window, a building window, etc. Explanation of the symbols

[0025] 1: Carrier board 2, 2A, 8A, 8B: Pixel Package 21, 22, 23: Light-emitting diode 24: Light-transmitting protective layer 2": temporary device 3: Control Chip 31, 311, 312, 313, 314, 315, 316, 317, 318, 319: Electrode 32, 33: Surface 34: Surface 4, 4': Substrate 41: Entry 41S1: Upper surface 41S2: Lower surface 42: Circuit Structure 421a, 421b, 421c, 421d: Circuit layers 422a, 422b, 422c: Conductive pillars 423: Lower electrode 44: Solder resist layer 5: Temporary Carrier Board 5S: Surface 61, 62, 63: Insulating layer 6S, 61S, 62S: Surface 9: Cutting tool 100: Display

Claims

Claim 1 A pixel structure comprising a substrate, a circuit structure, a plurality of light-emitting elements, and a non-light-emitting semiconductor element, wherein the substrate comprises an upper surface, a lower surface, and a side surface located between the upper surface and the lower surface; the circuit structure comprises a first circuit layer located on the substrate and exposed to the upper surface, a plurality of lower electrodes exposed to the lower surface, a second circuit layer located between the first circuit layer and the plurality of lower electrodes and completely covered by the substrate, and a plurality of conductive pillars connecting the first circuit layer, the second circuit layer, and the plurality of lower electrodes; wherein the plurality of light-emitting elements are located on the upper surface and are electrically connected to the first circuit layer; the non-light-emitting semiconductor element comprises a bottom surface not clad by the substrate, and the non-light-emitting semiconductor element is a control chip that controls the plurality of light-emitting elements, wherein the upper surface and a plurality of side surfaces of the control chip are clad in direct contact with the substrate, and the second circuit layer is directly connected to an electrode formed on the upper surface of the control chip. Claim 2 In claim 1, the bottom surface of the non-luminescent semiconductor device forms the same plane as the bottom surface of the substrate or is lower than the bottom surface of the substrate, forming a pixel structure. Claim 3 A pixel structure according to claim 1, wherein the non-luminescent semiconductor device further comprises an upper surface and a side surface located between the upper surface and the lower surface, and the side surface and the upper surface are in direct contact with the substrate. Claim 4 In paragraph 3, the pixel structure further comprises a plurality of electrodes located on the upper surface and connected to the second circuit layer, wherein the non-luminescent semiconductor device comprises a plurality of electrodes. Claim 5 In claim 1, when viewed from the lower surface of the above description, the plurality of lower electrodes surround the bottom surface of the non-luminescent semiconductor device, forming a pixel structure. Claim 6 A pixel structure according to claim 1, further comprising a transparent adhesive layer that covers the plurality of light-emitting elements and is in direct contact with the upper surface of the substrate. Claim 7 In claim 1, the pixel structure wherein the non-luminescent semiconductor element controls the plurality of light-emitting elements to emit red light, blue light, and green light. Claim 8 In claim 1, the pixel structure comprising the material described above, ABF, epoxy resin, BT resin, polyimide resin, or epoxy resin. Claim 9 In claim 1, the above description is a pixel structure having a coefficient of thermal expansion of 1 to 100 ppm / ℃. Claim 10 A pixel structure according to claim 1, wherein the difference in the coefficient of thermal expansion between the above description and the non-luminescent semiconductor device is less than 10 ppm / ℃.

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