Display apparatus

Abstract

A display device according to an embodiment of the present specification may include a light-emitting element, a driving transistor connected to the light-emitting element and comprising a first oxide semiconductor layer and a first gate electrode, a switching transistor comprising a second oxide semiconductor layer and a second gate electrode, a data wiring supplying a data voltage, a first insulating layer disposed on the first gate electrode and the second gate electrode, and a second insulating layer disposed between the first insulating layer and the data wiring.

Description

Technology Field

[0001] This specification relates to a display device, and more specifically, to a display device comprising at least one oxide semiconductor. Background Technology

[0002] Display devices including Organic Light Emitting Diodes (OLEDs) are dominating the display field due to their excellent thinness and image quality.

[0003] A display device containing an organic light-emitting diode can form a screen in various shapes, such as by bending or folding, because the light-emitting diode can be formed on a flexible substrate. In addition, a display device containing an organic light-emitting diode can have excellent thinness. Due to these advantages of a display device containing an organic light-emitting diode, such devices can be used in various electronic products that require a thin thickness, including small electronic devices such as smartwatches, as well as mobile phones and TVs.

[0004] Recently, there has been an increasing number of cases where display devices transmit information in a static state to implement features such as Always-On Display (AOD). As a static state persists, leakage current may occur; consequently, there is a growing need for display devices equipped with new types of driving elements capable of preventing leakage current. The problem to be solved

[0005] The problem that the embodiments of this specification aim to solve is to provide a display device that effectively blocks leakage current using a transistor comprising an oxide semiconductor layer.

[0006] In addition, the problem that the embodiments of this specification aim to solve is to provide a display device in which uniform visibility of the display panel is ensured by minimizing crosstalk between the data wiring and the transistor using an insulating layer.

[0007] The problems of this specification are not limited to those mentioned above, and other technical problems may be inferred from the following embodiments. means of solving the problem

[0008] A display device according to one embodiment of the present specification may include a light-emitting element, a driving transistor connected to the light-emitting element and comprising a first oxide semiconductor layer, a switching transistor comprising a second oxide semiconductor layer, a data line supplying a data voltage, a first insulating layer disposed on the gate electrode of the switching transistor and the gate electrode of the driving transistor, and a second insulating layer disposed between the first insulating layer and the data line.

[0009] Specific details of other embodiments are included in the detailed description and drawings.

[0010] delete Effects of the invention

[0011] The display panel and display device according to the present specification can effectively block leakage current by using a transistor including an oxide semiconductor layer.

[0012] In addition, the display panel and display device according to the present specification can ensure uniform visibility of the display panel by minimizing crosstalk between the data wiring and the transistor using an insulating layer.

[0013] Since the problem to be solved, the means of solving the problem, and the effects mentioned above do not specify the essential features of the claim scope, the scope of rights of the claim is not limited by the matters described in the content of the invention. Brief explanation of the drawing

[0014] FIG. 1 is a block diagram of a display device according to one embodiment of the present specification. FIG. 2 is a pixel circuit diagram of a display device according to one embodiment of the present specification. FIG. 3 is a cross-sectional view of a display device according to one embodiment of the present specification. FIG. 4 is a plan view of a display device according to one embodiment of the present specification. FIG. 5 is an example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to one embodiment of the present specification. FIG. 6 is another example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to one embodiment of the present specification. FIG. 7 is a plan view of a display device according to another embodiment of the present specification. FIG. 8 is an example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to another embodiment of the present specification. FIG. 9 is another example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to another embodiment of the present specification. Specific details for implementing the invention

[0015] The terms used in the embodiments have been selected to be as widely used as possible, taking into account their functions in the present disclosure; however, these may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms have been arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant explanatory section. Therefore, terms used in the present disclosure should be defined not merely by their names, but based on their meanings and the overall content of the present disclosure.

[0016] When a part of a specification is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0017] The expression "at least one of a, b, and c" as used throughout the specification may encompass 'a alone', 'b alone', 'c alone', 'a and b', 'a and c', 'b and c', or 'a, b, and c all'. The advantages and features of the present invention, and the methods for achieving them, will become clear from the embodiments described below in detail together with the accompanying drawings.

[0018] Shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for describing embodiments in this specification are exemplary, and therefore the embodiments of this specification are not limited to those depicted. Furthermore, in describing embodiments, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the embodiment, such detailed description is omitted.

[0019] In cases where terms such as 'includes,' 'have,' or 'consists of' are used in this specification, other parts may be added. When a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise. Furthermore, in interpreting the component, it is interpreted to include an error range even without separate explicit description.

[0020] In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on', 'on the upper part', 'on the lower part', or 'next to', one or more other parts may be located between the two parts. When an element or layer is referred to as "on" another element or layer, it includes cases where another layer or element is placed directly on top of another element or in between.

[0021] Additionally, terms such as "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0022] The area, length, or thickness of each component described in the specification is illustrated for convenience of explanation and the present invention is not necessarily limited to the area and thickness of the illustrated components.

[0023] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or together in an associated relationship.

[0024] Furthermore, the terms described below are defined considering their functions in the implementation of this specification, and these may vary depending on the intentions or practices of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0025] The transistor constituting the pixel circuit of the present specification may include at least one of an oxide thin film transistor (Oxide TFT), an amorphous silicon transistor (a-Si TFT), and a low temperature poly silicon (LTPS) transistor.

[0026] The display devices in the following embodiments are described primarily with reference to organic light-emitting display devices. However, the embodiments of this specification are not limited to organic light-emitting display devices and may also be applied to inorganic light-emitting display devices including inorganic light-emitting materials. For example, the embodiments of this specification may also be applied to quantum dot display devices.

[0027] Expressions such as 'first,' 'second,' and 'third' are terms used to distinguish configurations by embodiment, and the embodiments are not limited to these terms. Therefore, it should be noted that even the same term may refer to different configurations depending on the embodiment.

[0028] Embodiments of the present specification will be described below with reference to the drawings.

[0029] FIG. 1 is a block diagram of a display device according to one embodiment of the present specification.

[0030] A display device (100) according to one embodiment of the present specification may be an electroluminescent display device. The electroluminescent display device may be an organic light-emitting diode (OLED) display device, a quantum-dot light-emitting diode (QD) display device, or an inorganic light-emitting diode (ILED) display device, etc.

[0031] Referring to FIG. 1, the display device (100) includes a substrate (101), a display panel (102), a gate driver (103), and a data driver (104).

[0032] The display panel (102) includes an active area (AA) provided on a substrate (101) and a non-active area (NA) disposed around the active area (AA). The substrate (101) is formed of a plastic material having flexibility to enable bending. For example, the substrate (101) may be formed of materials such as PI (Polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (polyarylate), PSF (polysulfone), or COC (cyclo-olefin copolymer), and the embodiments of this specification are not limited thereto. However, glass is not excluded as a material for the substrate (101).

[0033] The subpixel of the active area (AA) includes a transistor (or thin film transistor, or TFT (Thin Film Transistor)) that includes an oxide semiconductor layer as the active layer.

[0034] At least one of a gate driver (103) and a data driver (104) may be disposed in the non-active region (NA). The non-active region (NA) may further include a bending region (BA) in which the substrate (101) is bent.

[0035] In an embodiment, the gate driver (103) may be formed directly on the substrate (101) using a transistor that uses a polycrystalline semiconductor material as the active layer. In another embodiment, the gate driver (103) may be formed by configuring a transistor using a polycrystalline semiconductor material as the active layer and a transistor using an oxide semiconductor material as the active layer into a C-MOS. The transistor having such an oxide semiconductor layer and the transistor having such a polycrystalline semiconductor layer have high electron mobility in the channel, enabling high resolution and low power consumption.

[0036] Multiple data lines and multiple gate lines may be arranged in the active area (AA). For example, multiple data lines may be arranged in rows or columns, and multiple gate lines may be arranged in columns or rows. Subpixels (PX) may be arranged in the area defined by the data lines and gate lines.

[0037] The basic pixel may be composed of at least three subpixels among subpixels emitting white (W), red (R), green (G), or blue (B). For example, the basic pixel may be composed of subpixels in the combination of red (R), green (G), and blue (B); subpixels in the combination of white (W), red (R), and green (G); subpixels in the combination of blue (B), white (W), and red (R); or subpixels in the combination of green (G), blue (B), and white (W), or subpixels in the combination of white (W), red (R), green (G), and blue (B), and the embodiments of the present specification are not limited thereto.

[0038] A gate driving circuit included in the gate driving unit (103) may be disposed in the non-active area (NA). The gate driving circuit of the gate driving unit (103) sequentially drives each pixel row in the active area by sequentially supplying scan signals to a plurality of gate lines (GL). Here, the gate driving circuit may be a scan driving circuit. Here, a pixel row may be a row formed by pixels connected to a single gate line.

[0039] The gate driving circuit may be composed of a transistor having a polycrystalline semiconductor layer or a transistor having an oxide semiconductor layer. In the gate driving circuit, the transistor having a polycrystalline semiconductor layer and the transistor having an oxide semiconductor layer may be configured as a pair. If the transistors placed in the non-active region (NA) and the active region (AA) each use the same semiconductor material, the formation of the transistors placed in the non-active region (NA) and the active region (AA) can be carried out through the same process.

[0040] In the embodiment, the gate driving circuit may include a shift register, a level shifter, etc. The gate driving circuit may be implemented as a GIP (Gate In Panel) type and placed directly on the substrate (101).

[0041] The gate driving unit (103) can sequentially supply scan signals of an on voltage or an off voltage to a plurality of gate lines.

[0042] A display device (100) according to one embodiment of the present specification may further include a data driving circuit. When a specific gate line is opened by a gate driving unit (103), the data driving circuit can convert image data into an analog data voltage and supply it to a plurality of data lines.

[0043] In an embodiment, each of the plurality of gate lines (GL) disposed on the substrate (101) may include at least one scan line and at least one light emission control line, etc. The scan line and the light emission control line include wiring that transmits different types of gate signals, for example, a scan signal or a light emission control signal, to the gate nodes of different types of transistors, for example, a scan transistor or a light emission control transistor.

[0044] The gate driving unit (103) may include a scan driving circuit that outputs scan signals to a scan line, which is one type of gate line (GL), and a light-emitting driving circuit that outputs light-emitting control signals to a plurality of light-emitting control lines, which are other types of gate lines.

[0045] Data lines (DL) can be arranged to pass through a bending area (BA), and various data lines (DL) can be arranged to be connected to a data pad (PAD). The bending area (BA) may be an area where the substrate (101) is bent. The substrate (101) may be maintained in a flat state in areas excluding the bending area (BA).

[0046] FIG. 2 is a pixel circuit diagram of a display device according to one embodiment of the present specification. FIG. 2 is a circuit diagram of a pixel circuit driving one subpixel included in a display device.

[0047] Referring to FIG. 2, the pixel circuit (200) includes seven thin film transistors (TFTs) and one storage capacitor (Cst). One of the seven transistors may be a driving transistor and the others may be switching transistors for internal compensation, but the embodiments of this specification are not limited thereto.

[0048] In the embodiment, the driving transistor (D-TFT) may use an oxide semiconductor layer (or oxide semiconductor pattern) as the active layer (or active layer). The third switching transistor (T3) adjacent to the driving transistor (D-TFT) may also use an oxide semiconductor layer as the active layer. At least one of the other switching transistors, for example, the second switching transistor (T2), the fourth switching transistor (T4), the fifth switching transistor (T5), the sixth switching transistor (T6), and the seventh switching transistor (T7), may use a polycrystalline semiconductor layer (or a polycrystalline semiconductor pattern) as the active layer. However, this is merely an example and is not limited thereto, and at least one transistor included in the pixel circuit (200) may include an oxide semiconductor layer and at least one other transistor may include a polycrystalline semiconductor layer.

[0049] In an embodiment, the pixel circuit (200) has a data voltage (V data ), high potential voltage (V DDEL ), low voltage (V SSEL ), reset voltage (VAR), initialization voltage (V in ), can be connected to respective lines providing a light emission signal (EM) and a scan signal (Scan1[n], Scan2[n], Scan3[n], Scan3[n+1]). Accordingly, the pixel circuit (200) can be connected to a data voltage (V data ), high potential voltage (V DDEL ), low voltage (V SSEL ), reset voltage (VAR), initialization voltage (V in ), light emission signal (EM) and scan signals (Scan1[n], Scan2[n], Scan3[n], Scan3[n+1]) can be received. Here, the data voltage (V data ) is AC voltage (or alternating current voltage), and the reset voltage (VAR) and initialization voltage (V in ), high potential voltage (V DDEL ), low voltage (V SSEL ) can be a DC voltage (or direct current voltage).

[0050] The pixel circuit (200) includes a light-emitting element (OLED). The light-emitting element (OLED) may include an anode electrode, a light-emitting layer, and a cathode electrode. The anode electrode may be a pixel electrode placed in each subpixel (PX) and may be electrically connected to a driving transistor (D-TFT) of each subpixel (PX). The cathode electrode may be a common electrode placed in common across a plurality of subpixels (PX) and may have a low potential common voltage (V SSEL ) can be authorized.

[0051] FIG. 3 is a cross-sectional view of a display device according to one embodiment of the present specification. Specifically, FIG. 3 is a cross-sectional view of one driving transistor (360), two switching transistors (330, 340), and one storage capacitor (350).

[0052] Briefly illustrated with respect to one sub-pixel (PX), as shown in FIG. 3, the sub-pixel (PX) includes a driving element part (370) and a light-emitting element part (380) electrically connected to the driving element part (370) on a substrate (101). The driving element part (370) and the light-emitting element part (380) are insulated by planarization layers (320, 322).

[0053] The driving element section (370) may refer to an array section that drives a single subpixel, including a driving transistor (360), a switching transistor (330, 340), and a storage capacitor (350). The light-emitting element section (380) may refer to an array section for light emission, including an anode electrode, a cathode electrode, and a light-emitting layer disposed between them.

[0054] In FIG. 3, one driving transistor (360), two switching transistors (330, 340), and one storage capacitor (350) are shown as examples of the driving element part (370), but are not limited thereto.

[0055] In the embodiment, the driving transistor (360) and at least one switching transistor use an oxide semiconductor layer as the active layer. The oxide semiconductor layer is a layer composed of an oxide semiconductor material, which has an excellent leakage current blocking effect and is relatively inexpensive to manufacture compared to a transistor using a polycrystalline semiconductor layer. For example, the oxide semiconductor layer may be IGZO, ZnO, SnO2, Cu2O, NiO, ITZO, IAZO, etc., and the embodiments of this specification are not limited thereto. Accordingly, in order to reduce power consumption and lower manufacturing costs, one embodiment of this specification may implement the driving transistor (360) and at least one switching transistor using an oxide semiconductor layer.

[0056] Transistors utilizing a polycrystalline semiconductor layer containing a polycrystalline semiconductor material, for example, polycrystalline silicon (poly-Si), have fast operating speeds and excellent reliability. Based on these advantages of the polycrystalline semiconductor layer, FIG. 3 illustrates an example in which one of the switching transistors is manufactured using a polycrystalline semiconductor layer. The remaining transistors may be composed of transistors including an oxide semiconductor layer. However, the embodiment is not limited to that illustrated in FIG. 3.

[0057] In an embodiment, the substrate (101) may be composed of a multi-layer in which at least one organic film and at least one inorganic film are alternately stacked. For example, the substrate (101) may be formed by alternately stacking an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2), but the embodiments of this specification are not limited thereto.

[0058] According to FIG. 3, a lower buffer layer (301) may be formed on a substrate (101). The lower buffer layer (301) may be intended to block substances that can penetrate from the outside, such as moisture. The lower buffer layer (301) may be used by stacking multiple silicon oxide (SiO2) films. According to an embodiment, a second buffer layer may be further formed on the lower buffer layer (301) to protect against moisture penetration.

[0059] A first switching thin-film transistor (330) is formed on a substrate (101). The first switching thin-film transistor (330) may use a polycrystalline semiconductor layer as an active layer. The first switching transistor (330) may include a first active layer (303) that includes a channel through which electrons or holes move. The switching transistor (330) may include a first gate electrode (306), a first source electrode (317S), and a first drain electrode (317D).

[0060] The first active layer (303) may be composed of a polycrystalline semiconductor material. The first active layer (303) may have a first channel region (303C) in the center, and may have a first source region (303S) and a first drain region (303D) between the first channel region (303C).

[0061] The first source region (303S) and the first drain region (303D) may include regions that are made conductive by doping a group 5 or group 3 impurity ion, such as phosphorus (P) or boron (B), into an intrinsic polycrystalline semiconductor pattern at a predetermined concentration.

[0062] The first channel region (303C) can provide a path for electrons or holes to move, as the polycrystalline semiconductor material maintains an intrinsic state.

[0063] In an embodiment, the first switching transistor (330) may include a first gate electrode (306) that overlaps with a first channel region (303C) of the first active layer (303). A first gate insulating layer (302) may be disposed between the first gate electrode (306) and the first active layer (303).

[0064] In an embodiment, the first switching transistor (330) may be implemented in a top-gate configuration in which the first gate electrode (306) is located on top of the first active layer (303). In this case, the first capacitor electrode (305), which is composed of the first gate electrode material, and the second light-blocking layer (304) of the second switching thin-film transistor (340) may be formed through a single mask process. Accordingly, the mask process may be reduced.

[0065] In an embodiment, the first gate electrode (306) may be composed of a metallic material. For example, the first gate electrode (306) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0066] In an embodiment, a first interlayer insulating layer (307) may be deposited on the first gate electrode (306). The first interlayer insulating layer (307) may be composed of silicon nitride (SiNx). The first interlayer insulating layer (307) composed of silicon nitride (SiNx) may contain hydrogen particles. When a heat treatment process is performed after forming the first active layer (303) and depositing the first interlayer insulating layer (307) thereon, the hydrogen particles contained in the first interlayer insulating layer (307) penetrate into the first source region (303S) and the first drain region (303D), contributing to improving and stabilizing the conductivity of the polycrystalline semiconductor material. This can be called a hydrogenation process.

[0067] In an embodiment, the first switching transistor (330) may further include an upper buffer layer (310), a second gate insulating layer (313), and a second interlayer insulating layer (316) in sequence on the first interlayer insulating layer (307), and includes a first source electrode (317S) and a first drain electrode (317D) formed on the second interlayer insulating layer (316) and connected to a first source region (303S) and a first drain region (303D), respectively.

[0068] In an embodiment, the upper buffer layer (310) can separate the first active layer (303) composed of a polycrystalline semiconductor material, the second active layer (312) of the second switching transistor (340) composed of an oxide semiconductor layer, and the third active layer (311) of the driving transistor (360). The upper buffer layer (310) can provide a base on which the second active layer (312) and the third active layer (311) are formed.

[0069] In an embodiment, the second interlayer insulating layer (316) may include an interlayer insulating layer covering the second gate electrode (315) of the second switching transistor (340) and the third gate electrode (314) of the driving transistor (360). Since the second interlayer insulating layer (316) is formed on the second active layer (312) and the third active layer (311) which are composed of an oxide semiconductor material, it may be composed of an inorganic film that does not contain hydrogen particles.

[0070] In the embodiment, the first source electrode (317S) and the first drain electrode (317D) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto.

[0071] In an embodiment, the second switching transistor (340) may include a second active layer (312) formed on an upper buffer layer (310) and composed of a second oxide semiconductor layer, a second gate insulating layer (313) covering the second active layer (312), a second gate electrode (315) formed on the second gate insulating layer (313), a second interlayer insulating layer (316) covering the second gate electrode (315), and a second source electrode (318S) and a second drain electrode (318D) formed on the second interlayer insulating layer (316).

[0072] According to an embodiment, the second switching transistor (340) may further include a second light-blocking layer (304) located below the upper buffer layer (310) and overlapping with the second active layer (312). Here, the second light-blocking layer (304) may be formed on the upper surface of the first gate insulating layer (302) while being composed of the same material as the first gate electrode (306).

[0073] According to an embodiment, the second light-blocking layer (302) can be electrically connected to the second gate electrode (315) (see dotted line) to form a dual gate. When the second switching transistor (340) has a dual gate structure, the flow of current in the second channel layer (312C) can be controlled more precisely, and the display device can be manufactured in a smaller size, thereby enabling the realization of a high-resolution display device.

[0074] In an embodiment, the second active layer (312) is composed of an oxide semiconductor material and may include an intrinsic second channel region (312C) that is not doped with impurities, a second source region (312S) that is doped with impurities and conductive, and a second drain region (312D).

[0075] In the embodiments, the second source electrode (318S) and the second drain electrode (318D) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, as in the first source electrode (317S) and the first drain electrode (317D), and the embodiments of the present specification are not limited thereto.

[0076] In the embodiment, the second source electrode (318S) and the second drain electrode (318D) and the first source electrode (317S) and the first drain electrode (317D) can be simultaneously formed with the same material on the second interlayer insulating layer (316), in which case the number of mask processes can be reduced.

[0077] In an embodiment, the driving transistor (360) may be formed on the upper buffer layer (310). The driving transistor (360) may include a third active layer (311) composed of a first oxide semiconductor layer. Here, the first oxide semiconductor pattern and the third active layer are described using the same reference numerals as being substantially the same.

[0078] Conventionally, polycrystalline semiconductor patterns advantageous for high-speed operation were used as the active layer for driving transistors. However, driving thin-film transistors containing polycrystalline semiconductor patterns suffered from high power consumption due to leakage current occurring in the off state. Accordingly, the embodiments of this specification propose a driving transistor that uses an oxide semiconductor layer as the active layer, which is advantageous for blocking the generation of leakage current.

[0079] In the case of a transistor using an oxide semiconductor layer as the active layer, due to the material properties of the oxide semiconductor, the current fluctuation value for a unit voltage fluctuation value is large, and defects may occur in the low-gradation region where precise current control is required. Therefore, the embodiments of this specification provide a driving transistor in which the current fluctuation value in the active layer is relatively insensitive to the voltage fluctuation value applied to the gate electrode.

[0080] Referring to FIG. 3, the driving transistor (360) may include a third active layer (311) composed of a first oxide semiconductor layer on an upper buffer layer (310), a second gate insulating layer (313) covering the third active layer (311), a third gate electrode (314) formed on the second gate insulating layer (313) and overlapping with the second active layer (311), a second interlayer insulating layer (316) covering the third gate electrode (314), and a third source electrode (319S) and a third drain electrode (319D) disposed on the second interlayer insulating layer (316).

[0081] According to an embodiment, the driving transistor (360) may further include a first light-blocking layer (308) that overlaps with the third active layer (311) while being disposed inside the upper buffer layer (310). The first light-blocking layer (308) may be implemented in a form that is inserted inside the upper buffer layer (310).

[0082] To describe the form in which the first light-blocking layer (308) is placed inside the upper buffer layer (310) reflecting process characteristics, the first light-blocking layer (308) can be formed on the upper first sub-buffer layer (310a) placed on the first interlayer insulation layer (307). The upper second sub-buffer layer (310b) completely covers the first light-blocking layer (308) from the top, and the upper third sub-buffer layer (310c) is formed on the upper second sub-buffer layer (310b). That is, the upper buffer layer (310) has a structure in which the upper first sub-buffer layer (310a), the upper second sub-buffer layer (310b), and the upper third sub-buffer layer (310c) are stacked sequentially.

[0083] In the embodiment, the first sub-buffer layer (310a) and the third sub-buffer layer (310c) may be composed of silicon oxide (SiO2). Since the first sub-buffer layer (310a) and the third sub-buffer layer (310c) are composed of silicon oxide (SiO2) that does not contain hydrogen particles, they may serve as a basis for a second switching thin-film transistor (340) and a driving thin-film transistor (360) that use an oxide semiconductor layer, whose reliability may be compromised by hydrogen particles, as an active layer.

[0084] The upper second sub-buffer layer (310b) may be composed of silicon nitride (SiNx), which has excellent hydrogen particle capture ability. The second sub-buffer layer (310b) may be formed to completely seal the first light-blocking layer (308) by covering both the upper and side surfaces of the first light-blocking layer (308).

[0085] Hydrogen particles generated during the hydrogenation process of the first switching transistor (330) using a polycrystalline semiconductor layer as the active layer can pass through the upper buffer layer (310) and impair the reliability of the oxide semiconductor layer located on the upper buffer layer (310). That is, if hydrogen particles penetrate the oxide semiconductor layer, the transistor containing the oxide semiconductor layer may have different threshold voltages depending on the location where it is formed, or problems may arise such as changes in the conductivity of the channel.

[0086] However, since silicon nitride (SiNx) included in the upper buffer layer (310) has superior hydrogen particle capture ability compared to silicon oxide (SiO2), it can prevent reliability damage to the driving thin-film transistor (360) that occurs when hydrogen particles penetrate the oxide semiconductor layer.

[0087] In the embodiment, the first light-blocking layer (308) may be composed of a metal layer containing a titanium (Ti) material with excellent hydrogen particle capture ability. For example, the first light-blocking layer (308) may include a single layer of titanium, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, it is not limited thereto, and other metal layers containing titanium (Ti) are also possible.

[0088] Here, titanium (Ti) can capture hydrogen particles diffusing within the upper buffer layer (310) to prevent the hydrogen particles from reaching the first oxide semiconductor pattern (311). In this case, the first light-blocking layer (308) of the driving transistor (360) is formed with a metal layer such as titanium that has the ability to capture hydrogen particles, and the reliability of the oxide semiconductor pattern against hydrogen particles can be ensured by wrapping the first light-blocking layer (308) with a silicon nitride (SiNx) layer that has the ability to capture hydrogen particles.

[0089] In the embodiment, the upper second sub-buffer layer (310b) containing silicon nitride (SiNx) is not deposited on the entire surface of the display area like the upper first sub-buffer layer (310a), but may be deposited only on a part of the upper surface of the first sub-buffer layer (310a) so as to selectively cover only the first light-blocking layer (308). Since the second sub-buffer layer (310b) is formed of a different material, namely a silicon nitride (SiNx) film, than the first sub-buffer layer (310a), film lifting may occur if it is deposited on the entire surface of the display area; to compensate for this, the second sub-buffer layer (310b) may be selectively formed only at the location where the first light-blocking layer (308), which is functionally necessary, is formed.

[0090] In an embodiment, the first light-blocking layer (308) and the upper second sub-buffer layer (310b) may be formed vertically below the first oxide semiconductor layer (311) so as to overlap the first oxide semiconductor layer (311) for functional purposes. The first light-blocking layer (308) and the second sub-buffer layer (310) may be formed larger than the first oxide semiconductor layer (311) so as to completely overlap the first oxide semiconductor layer (310).

[0091] In an embodiment, the third source electrode (319S) of the driving transistor (360) can be electrically connected to the first light-blocking layer (308).

[0092] In an embodiment, the storage capacitor (350) can store a data voltage applied through a data line for a certain period and then provide it to a light-emitting element. The storage capacitor (350) may include two corresponding electrodes and a dielectric material disposed between them. The storage capacitor (350) may include a first storage electrode (305) disposed on the same layer with the same material as the first gate electrode (306) and a second storage electrode (309) disposed on the same layer with the same material as the first light-blocking layer (308). A first interlayer insulating layer (307) and an upper first sub-buffer layer (310a) may be located between the first storage electrode (305) and the second storage electrode (309). The first storage electrode (309) of the storage capacitor (350) may be electrically connected to a third source electrode (319S).

[0093] FIG. 3 illustrates an example in which a storage capacitor (350) is formed on one side, separated from the driving transistor (360). However, this is not limited thereto, and according to the embodiment, the storage capacitor (350) may be formed in a stacked form with the driving transistor (360). In this case, at least a portion of the third source electrode (319S) connected to the second capacitor electrode (306) may be omitted. As an example, a fourth gate electrode may be further formed on the third gate electrode (314) of the driving transistor (360). At this time, the third gate electrode (314) and the fourth gate electrode may be spaced apart by a predetermined distance, and a capacitor may be formed based on this. Specific examples related to this are described with reference to FIG. 6 or FIG. 9.

[0094] In an embodiment, a first flattening layer (320) and a second flattening layer (322) for flattening the top of the driving element part (370) may be disposed on the driving element part (370). The first flattening layer (320) and the second flattening layer (322) may be composed of an organic film such as polyimide or acrylic resin.

[0095] A light-emitting element part (380) is formed on the second flattening layer (322). The light-emitting element part (380) includes a first electrode (323) as an anode electrode, a second electrode (327) as a cathode electrode corresponding to the first electrode (323), and a light-emitting layer (325) interposed between the first electrode (323) and the second electrode (327). The first electrode (323) can be formed for each subpixel.

[0096] In an embodiment, the light-emitting element part (380) can be connected to the driving element part (370) through a connecting electrode (321) formed on the first flattening layer (320). For example, the first electrode (323) of the light-emitting element part (380) and the third drain electrode (319D) of the driving transistor (360) constituting the driving element part (370) can be connected to each other by the connecting electrode (321).

[0097] In an embodiment, the first electrode (323) can be connected to a connecting electrode (321) exposed through a contact hole (CH1) penetrating the second flattening layer (322). Additionally, the connecting electrode (321) can be connected to a third drain electrode (319D) exposed through a contact hole (CH2) penetrating the first flattening layer (320).

[0098] The first electrode (323) may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film may be formed as a single layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof, and the embodiments of this specification are not limited thereto. For example, the first electrode (323) may be formed as a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or as a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked, and the embodiments of this specification are not limited thereto.

[0099] In an embodiment, the light-emitting layer (325) may be formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer in the order of or in reverse order on the first electrode (323). The bank layer (324) may expose the first electrode (323) of each subpixel and may be referred to as a pixel defining film. According to an embodiment, the bank layer (324) may be formed of an opaque material, for example, black, to prevent light interference between adjacent subpixels. In this case, the bank layer (324) may include a light-blocking material composed of at least one of a color pigment, organic black, and carbon, but the embodiments of this specification are not limited thereto. A spacer (326) may be disposed on the bank layer (324).

[0100] In an embodiment, the second electrode (327), which is a cathode electrode, is formed on the upper and side surfaces of the light-emitting layer (325) and faces the first electrode (323) with the light-emitting layer (325) in between. The second electrode (327) may be integrally formed on the entire surface of the active area. When the second electrode (327) is applied to a front-emitting organic light-emitting display device, it may be made of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), but the embodiments of this specification are not limited thereto.

[0101] In an embodiment, a sealing portion (328) that inhibits moisture penetration may be further disposed on the second electrode (327). The sealing portion (328) may include a first inorganic sealing layer (328a), a second organic sealing layer (328b), and a third inorganic sealing layer (328c) that are stacked in sequence.

[0102] The first inorganic encapsulation layer (328a) and the third inorganic encapsulation layer (328c) of the encapsulation portion (328) may be formed from an inorganic material such as silicon oxide (SiOx). The second organic encapsulation layer (328b) of the encapsulation portion (328) may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but the embodiments of the present specification are not limited thereto.

[0103] FIG. 4 is a plan view of a display device according to one embodiment of the present specification. FIG. 4 shows a plan view of one area of ​​the display device where a pixel circuit (401) is arranged.

[0104] Referring to FIG. 4, the display device has a data voltage (V dataData wiring (402) providing ) may be arranged. An insulating layer (405) may be arranged in overlap with the data wiring (402). For example, an insulating layer (405) may be arranged in overlap with the data wiring (402) at the bottom of the data wiring (402). As illustrated, the width (or area) of the insulating layer (405) may be larger than that of the data wiring (402).

[0105] In an embodiment, data wiring (402) may be disposed on both sides of the pixel circuit (401). In this case, an insulating layer (405) may be disposed at the bottom of each of the data wiring (402) disposed on both sides of the pixel circuit (401).

[0106] The pixel circuit (401) may include a driving transistor and at least one switching transistor. The driving transistor may include at least one of a first gate electrode (410) and a sub-gate electrode (420). For example, the driving transistor may include a first gate electrode (410). As another example, the driving transistor may include a first gate electrode (410) and a sub-gate electrode (420).

[0107] When the driving transistor includes a first gate electrode (410) and a sub-gate electrode (420), a second gate electrode (420) may be disposed on top of the first gate electrode (410). At least a portion of the first gate electrode (410) and the second gate electrode (420) may overlap. For example, the second gate electrode (420) may be disposed on the first gate electrode (410) to cover the first gate electrode (410) with a larger area than the first gate electrode (410).

[0108] FIG. 5 is an example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to an embodiment of the present specification. Content that overlaps with FIG. 3 may be omitted below.

[0109] FIG. 5 is a conceptual diagram in which, for convenience of explanation, the driving transistor (360) of FIG. 3 is represented as the driving transistor (500) of FIG. 5, and the switching transistor (340) is represented as the switching transistor (550) of FIG. 5. In FIG. 5 and the following drawings, some components described in FIG. 3, such as the arrangement of the storage capacitor (350), may be omitted or implemented in a different embodiment. In FIG. 5, the positions of the driving transistor (500) and the switching transistor (550) are arranged differently compared to FIG. 3, but the embodiments of this specification are not limited to such examples.

[0110] Referring to FIG. 5, a first lower buffer layer (501), a second lower buffer layer (502), and a lower insulating layer (503) may be disposed on a substrate. The first lower buffer layer (501) and the second lower buffer layer (502) may be intended to block substances (e.g., moisture) that may penetrate from the outside. The first lower buffer layer (501) and the second lower buffer layer (502) may be composed of, for example, a silicon oxide (SiO2) film. The lower insulating layer (503) is a component for insulating different layers and may be composed of, for example, silicon nitride (SiNx).

[0111] In an embodiment, a semiconductor layer (504) may be formed on a substrate. The semiconductor layer (504) may include an oxide semiconductor layer or a polycrystalline semiconductor layer. The semiconductor layer (504) may be for driving a switching transistor (550). A first lower buffer layer (501) may be formed to cover the semiconductor layer (504).

[0112] A first metal layer (or light-blocking layer) (505) may be formed on the first lower buffer layer (501). The first metal layer (505) may be electrically connected to the second oxide semiconductor layer (520) of the switching transistor (550). The first metal layer (505) may be composed of, for example, molybdenum (Mo). However, it is not limited thereto, and the first metal layer (505) may be implemented as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, and the embodiments of this specification are not limited thereto. A second lower buffer layer (502) may be formed to cover the first metal layer (505).

[0113] In an embodiment, an upper buffer layer (506) may be formed on a lower insulating layer (503). The upper buffer layer (506) may include an upper first sub-buffer layer (506a), an upper second sub-buffer layer (506b), and an upper third sub-buffer layer (506c). A second metal layer (507) may be formed on the upper first sub-buffer layer (506a). The second metal layer (507) may be composed of, for example, titanium (Ti), but is not limited thereto, and may be implemented as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, and the embodiments of this specification are not limited thereto.

[0114] In an embodiment, the second metal layer (507) may be electrically connected to the source electrode (515) of the driving transistor (500). The second metal layer (507) may be formed to overlap with the first oxide semiconductor layer (509). The upper second sub-buffer layer (506b) may be formed to cover the second metal layer (507). An upper third sub-buffer layer (506c) may be formed on the upper second sub-buffer layer (506b).

[0115] A first oxide semiconductor layer (509) of a driving transistor (500) and a second oxide semiconductor layer (521) of a switching transistor (550) may be formed on the upper third sub-buffer layer (506c). The first oxide semiconductor layer (509) of the driving transistor (500) may overlap with at least a portion of the second metal layer (507). The second oxide semiconductor layer (521) of the switching transistor (550) may overlap with at least a portion of the first metal layer (505).

[0116] In an embodiment, the first oxide semiconductor layer (509) may be used as an active layer of a driving transistor (500). The first oxide semiconductor layer (509) may be referred to as an active layer or an oxide active layer according to an embodiment, but is not limited to these terms.

[0117] The gate insulating layer (511) may be formed to cover the first oxide semiconductor layer (509). The gate insulating layer (511) may be formed to correspond to the shape of the upper surface of the first oxide semiconductor layer (509) as shown in FIG. 5. However, it is not limited thereto, and the upper surface of the gate insulating layer (511) may be formed flat. The gate electrodes of the driving transistor (500) and the switching transistor (550), respectively, may be formed on the gate insulating layer (511). Specifically, the first gate electrode (510) of the driving transistor (500) may be formed on the gate insulating layer (511) so as to overlap with the first oxide semiconductor layer (509) of the driving transistor (500). The second gate electrode (520) of the switching transistor (550) may be formed on the gate insulating layer (511) so as to overlap with the second oxide semiconductor layer (521) of the switching transistor (550).

[0118] A first insulating layer (513) may be disposed to cover the first gate electrode (510) and the second gate electrode (520). The upper surface of the first insulating layer (513) may be flattened. A second insulating layer (522) may be disposed on the first insulating layer (513). The second insulating layer (522) may be disposed separately from the driving transistor (500). For example, the second insulating layer (522) may be disposed so as not to overlap with at least a portion of the driving transistor (500). As another example, the second insulating layer (522) may be disposed to overlap with the data wiring (525). Here, the data wiring (525) includes wiring that is disposed adjacent to the driving transistor (500) and is electrically connected to the driving transistor (500) to provide a data voltage (Vdata).

[0119] In an embodiment, the width (W1) of the second insulating layer (522) may be equal to or greater than the width (W2) of the data wiring (525). The area of ​​the second insulating layer (522) may be equal to or greater than the area of ​​the data wiring (525). In this case, the data wiring (525) may overlap with the second insulating layer (522). At least a portion of the second insulating layer (522) may overlap with the data wiring (525).

[0120] In the embodiment, the thickness of the first insulating layer (513) may be 1000 Å or more and 7000 Å or less, and the embodiments of the present specification are not limited thereto. As the thickness of the first insulating layer (513) is 1000 Å or more, the distance between the first gate electrode (510) and the data wiring (525) can be secured. The thickness of the second insulating layer (522) may be 1000 Å or more and 7000 Å or less, and the embodiments of the present specification are not limited thereto. As the thickness of the second insulating layer (522) is 1000 Å or more, the distance between the first gate electrode (510) and the data wiring (525) can be further secured.

[0121] In an embodiment, the gap between the first gate electrode (510) of the driving transistor (500) and the data wiring (525) can be effectively secured by the second insulating layer (522) disposed below the data wiring (525). In this case, vertical crosstalk between the first gate electrode (510) and the data wiring (525) can be blocked (or minimized). By doing so, the crosstalk of the display device is blocked, thereby ensuring brightness uniformity.

[0122] In an embodiment, the source electrode (515) and drain electrode (516) of the driving transistor (500) may be connected to the first oxide semiconductor layer (509) by passing through the first insulating layer (513) and the gate insulating layer (511). The source electrode (527) and drain electrode (528) of the switching transistor (550) may be connected to the first oxide semiconductor layer (509) by passing through the first insulating layer (513) and the gate insulating layer (511).

[0123] A first flattening layer (517) may be disposed on the source electrode (515) and drain electrode (516) of the driving transistor (500), the source electrode (527) and drain electrode (528) of the switching transistor (550), and the data wiring (525). A connection electrode (518) may be disposed through the first flattening layer (517). A second flattening layer (519) may be disposed on the connection electrode (518). A first electrode (529) of a light-emitting element may be disposed through the second flattening layer (519). The first electrode (529) may correspond to a cathode electrode. The remaining components of the light-emitting element, such as a light-emitting layer, a node electrode, a touch element, such as a touch electrode, or touch wiring, may be disposed on the first electrode (529). Here, the touch element may be disposed on a layer above the light-emitting element.

[0124] FIG. 6 is another example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to one embodiment of the present specification. In FIG. 6 below, content that overlaps with the previously described content may be omitted.

[0125] Referring to FIG. 6, a second gate electrode (610) of a driving transistor (e.g., a driving transistor (500) of FIG. 5) and a second insulating layer (612) (e.g., a second insulating layer (522) of FIG. 5) may be disposed on a first insulating layer (611) (e.g., the first insulating layer (513) of FIG. 5). A third insulating layer (613) may be disposed to cover the second gate electrode (610) and the second insulating layer (612).

[0126] On the third insulating layer (613), a source electrode (615) (e.g., source electrode (515) of FIG. 5) and a drain electrode (616) (e.g., drain electrode (516) of FIG. 6) of a driving transistor, a source electrode (627) (e.g., source electrode (517) of FIG. 5) and a drain electrode (628) (e.g., drain electrode (518) of FIG. 5) of a switching transistor (e.g., switching transistor (550) of FIG. 5) may be disposed. The source electrode (615) and the drain electrode (616) of the driving transistor may pass through the third insulating layer (613) and the first insulating layer (611) and be connected to the first oxide semiconductor (609) of the driving transistor (e.g., first oxide semiconductor (509) of FIG. 5). The source electrode (627) and drain electrode (628) of the switching transistor may be connected to the second oxide semiconductor (621) of the switching transistor, for example, the second oxide semiconductor (521) of FIG. 5, by passing through the third insulating layer (613), the first insulating layer (611), and the gate insulating layer (608), for example, the gate insulating layer (511) of FIG. 5.

[0127] As shown in FIG. 6, when a second gate electrode (610) is formed on top of a first gate electrode (601), a storage capacitor based on the first gate electrode (601) and the second gate electrode (6010) can be formed. In this case, the display device can be made more compact compared to when the storage capacitor is placed on the side of the driving transistor. Additionally, the storage capacitor can be controlled by controlling the thickness of the first insulating layer (611) in the existing configuration (e.g., first gate electrode (601) (e.g., first gate electrode (510) in FIG. 5), second gate electrode (610), first insulating layer (611)) without additional configuration. For example, the storage capacitor may increase as the thickness of the first insulating layer (611) decreases. The storage capacitor may decrease as the thickness of the first insulating layer (611) increases.

[0128] FIG. 7 is a plan view of a display device according to another embodiment of the present specification. FIG. 7 shows a plan view of one area of ​​the display device where a pixel circuit (401) is arranged. In the following, content that overlaps with the content described in FIG. 4 may be omitted.

[0129] Referring to FIG. 7, data wiring (402) may be disposed on both sides of the pixel circuit (401). An insulating layer (405) may be disposed at the bottom of the data wiring (402). The insulating layer (405) may be disposed to overlap with the remaining area of ​​the pixel circuit (401), excluding the first gate electrode (410) and the sub-gate electrode (420) of the driving transistor. For example, the insulating layer (405) may be disposed to overlap with at least one switching transistor of the pixel circuit (401). The area where the insulating layer (405) is disposed may be placed above some components of the switching transistor and below other components. A more specific example related thereto may be referenced to FIG. 8 or FIG. 9.

[0130] FIG. 8 is an example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to another embodiment of the present specification. In the following, content that overlaps with the previously described content may be omitted.

[0131] Referring to FIG. 8, a second insulating layer (820), for example, the second insulating layer (522) of FIG. 5, may be disposed on a first insulating layer (813) (e.g., the first insulating layer (513) of FIG. 5). The second insulating layer (820) may be disposed to be separated from a driving transistor (850), for example, the driving transistor (500) of FIG. 5.

[0132] For example, the second insulating layer (820) may be positioned so as not to overlap with at least some of the components included in the driving transistor (850). For example, the second insulating layer (820) may be positioned so as not to overlap with the first gate electrode (840), for example, the first gate electrode (510) of FIG. 5. For another example, the second insulating layer (820) may be positioned so as not to overlap with the first gate electrode (840) and the first oxide semiconductor layer (845), for example, the first oxide semiconductor layer (845) of FIG. 5.

[0133] As another example, the second insulating layer (820) may be disposed separately from the driving transistor (850) in terms of the configuration included in the driving transistor (850). For example, the second insulating layer (820) may be disposed on the upper side diagonally opposite to the first gate electrode (840).

[0134] When a second insulating layer (820) is disposed separately from the driving transistor (850), the source electrode (851) of the driving transistor, for example, the source electrode (515) of FIG. 5, and the drain electrode (852), for example, the drain electrode (516) of FIG. 5, may be disposed in a layer lower than the source electrode (853) of the switching transistor, for example, the source electrode (527) of FIG. 5, and the drain electrode (854), for example, the drain electrode (528) of FIG. 5. For example, the distance from the upper surface of the first insulating layer (813) to the source electrode (851) and the drain electrode (852) of the driving transistor (hereinafter, the first distance) may be smaller than the distance from the upper surface of the first insulating layer (813) to the source electrode (853) and the drain electrode (854) of the switching transistor (hereinafter, the second distance). The difference between the second distance and the first distance can correspond to the thickness of the second insulating layer (820).

[0135] The source electrode (851) and drain electrode (852) of the driving transistor may be connected to the first oxide semiconductor layer (845), for example, the first oxide semiconductor layer (509) of FIG. 5, by passing through the first insulating layer (813) and the gate insulating layer (855), for example, the gate insulating layer (511) of FIG. 5. The source electrode (853) and drain electrode (854) of the switching transistor may be connected to the second oxide semiconductor layer (847), for example, the first oxide semiconductor layer (521) of FIG. 5, by passing through the first insulating layer (813), the second insulating layer (820), and the gate insulating layer (855).

[0136] Data wiring (830), for example, data wiring (525) of FIG. 5, may be placed on the second insulating layer (820) in overlap with the second insulating layer (820). The source electrode (851) and drain electrode (852) of the driving transistor may be placed on the first insulating layer (813) in overlap with the first oxide semiconductor layer (845). The source electrode (853) and drain electrode (854) of the switching transistor may be placed on the second insulating layer (820) in overlap with the second oxide semiconductor layer (860).

[0137] FIG. 9 is another example of a cross-sectional view of a driving transistor and a switching transistor of a display device according to another embodiment of the present specification.

[0138] Referring to FIG. 9, a second insulating layer (920) and a sub-gate electrode (917) may be disposed on a first insulating layer (913). The second insulating layer (920) and the sub-gate electrode (917) may be disposed spaced apart. The sub-gate electrode (917) may be disposed within the region of a driving transistor (950). The sub-gate electrode (917) may be disposed to overlap with the first gate electrode (940) of the driving transistor (950).

[0139] In an embodiment, the second insulating layer (920) may be disposed separately from the driving transistor (950) region. For example, the second insulating layer (920) may be disposed spaced apart from the driving transistor (950) region. In this case, the second insulating layer (920) may be disposed such that at least a portion of it is included in the switching transistor region. Here, the driving transistor (950) region corresponds to the region where the components included in the driving transistor (950) are disposed. The switching transistor region corresponds to the region where the components included in the switching transistor are disposed. In this case, at least a portion of the components of the switching transistor and at least a portion of the second insulating layer (920) may overlap.

[0140] A display device and a display panel according to an embodiment of the present specification may be described as follows.

[0141] A display device according to an embodiment of the present specification may include a light-emitting element, a driving transistor connected to the light-emitting element and comprising a first oxide semiconductor layer, a switching transistor comprising a second oxide semiconductor layer, a data wiring supplying a data voltage, a first insulating layer disposed on the gate electrode of the switching transistor and the gate electrode of the driving transistor, and a second insulating layer disposed between the first insulating layer and the data wiring.

[0142] According to some embodiments of the present specification, the driving transistor further comprises a sub-gate electrode, and the sub-gate electrode may be arranged on a first insulating layer such that at least a portion overlaps with the first gate electrode.

[0143] According to some embodiments of the present specification, the width of the sub-gate electrode may be wider than the width of the first gate electrode.

[0144] According to some embodiments of the present specification, the sub-gate electrode may be disposed on the same plane as the second insulating layer. A third insulating layer covering the sub-gate electrode and the second insulating layer may be further included, and the data wiring may be disposed on the third insulating layer. The thickness of the second insulating layer may be greater than the thickness of the sub-gate electrode. In the third insulating layer, the upper surface of the region overlapping with the first gate electrode and the upper surface of the region overlapping with the second gate electrode may be on different planes.

[0145] According to some embodiments of the present specification, the second insulating layer may be further disposed on at least a portion of the first insulating layer that overlaps with the second gate electrode.

[0146] A display panel according to an embodiment of the present specification may include a light-emitting element, a driving transistor connected to the light-emitting element and comprising a first oxide semiconductor layer, a switching transistor comprising a second oxide semiconductor layer, a data wiring supplying a data voltage, a first insulating layer disposed on the gate electrode of the switching transistor and the gate electrode of the driving transistor, and a second insulating layer disposed between the first insulating layer and the data wiring.

[0147] According to some embodiments of the present specification, the driving transistor further comprises a sub-gate electrode, and the sub-gate electrode may be arranged on the first insulating layer such that at least a portion overlaps with the first gate electrode.

[0148] According to some embodiments of the present specification, the width of the sub-gate electrode may be wider than the width of the first gate electrode. The sub-gate electrode may be disposed on the same plane as the second insulating layer.

[0149] According to some embodiments of the present specification, a third insulating layer covering the sub-gate electrode and the second insulating layer may be further included, and the data wiring may be disposed on the third insulating layer. The thickness of the second insulating layer may be greater than the thickness of the sub-gate electrode.

[0150] According to some embodiments of the present specification, the upper surface of the region overlapping with the first gate electrode of the third insulating layer and the upper surface of the region overlapping with the second gate electrode may be on different planes.

[0151] According to some embodiments of the present specification, the second insulating layer may be further disposed on at least a portion of the first insulating layer that overlaps with the second gate electrode.

[0152] Although the embodiments of this specification have been described in more detail with reference to the attached drawings, this specification is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of this specification. Accordingly, the embodiments disclosed in this specification are intended to explain, not to limit, the technical spirit of this specification, and the scope of the technical spirit of this specification is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of this specification shall be interpreted by the claims below, and all technical ideas within the equivalent scope shall be interpreted as being included within the scope of rights of this specification. Explanation of the symbols

[0153] 100: Display device 101: Substrate 102: Display panel 103: Gate driver 104: Data driver AA: Active area NA: Inactive area DL: Data line GL: Gate line 200: Pixel circuit

Claims

Claim 1 A display device comprising a light-emitting element, a driving transistor connected to the light-emitting element and including a first oxide semiconductor layer and a first gate electrode, a switching transistor including a second oxide semiconductor layer and a second gate electrode, a data line supplying a data voltage, a first insulating layer disposed on the first gate electrode and the second gate electrode, and a second insulating layer disposed between the first insulating layer and the data line, wherein the second insulating layer overlaps with the data line and is spaced apart in a planar direction without overlapping with the first gate electrode of the driving transistor. Claim 2 A display device according to claim 1, wherein the driving transistor further includes a sub-gate electrode, the first gate electrode and the sub-gate electrode overlap with the first insulating layer in between to form a storage capacitor, and the second insulating layer is spaced apart in the planar direction without overlapping with the sub-gate electrode. Claim 3 A display device according to paragraph 2, wherein the width of the sub-gate electrode is wider than the width of the first gate electrode. Claim 4 A display device according to paragraph 2, wherein the sub-gate electrode is disposed on the same plane as the second insulating layer. Claim 5 A display device according to claim 4, further comprising a third insulating layer covering the sub-gate electrode and the second insulating layer, wherein the data wiring is disposed on the third insulating layer. Claim 6 A display device according to claim 4, wherein the thickness of the second insulating layer is greater than the thickness of the sub-gate electrode. Claim 7 A display device according to claim 5, wherein the upper surface of the region overlapping with the first gate electrode and the upper surface of the region overlapping with the second gate electrode in the third insulating layer are on different planes. Claim 8 A display device according to claim 1, wherein the second insulating layer is further disposed on at least a portion of the first insulating layer that overlaps with the second gate electrode. Claim 9 A display device according to claim 1, further comprising a second switching transistor that includes a polysilicon semiconductor layer and is electrically connected to the driving transistor. Claim 10 In claim 9, the display device further comprises: a substrate; a lower buffer layer disposed on the substrate; a polysilicon semiconductor layer disposed on the lower buffer layer; a first gate insulating layer disposed on the polysilicon semiconductor layer; a gate electrode of the second switching transistor disposed on the first gate insulating layer; a first interlayer insulating layer disposed on the gate electrode of the second switching transistor; an upper buffer layer disposed on the first interlayer insulating layer; the first and second oxide semiconductor layers disposed on the upper buffer layer; a second gate insulating layer disposed on the first and second oxide semiconductor layers; and the first and second gate electrodes and the gate electrode of the second switching transistor disposed on the second gate insulating layer, wherein the second insulating layer is disposed on the first insulating layer. Claim 11 A display device according to claim 10, further comprising a first source electrode and a first drain electrode disposed on the first insulating layer and electrically connected to the first oxide semiconductor layer, a second source electrode and a second drain electrode electrically connected to the second oxide semiconductor layer, and a source electrode and a drain electrode of the second switching transistor electrically connected to the polysilicon semiconductor layer, wherein the data wiring is disposed on the second insulating layer. Claim 12 A display device according to claim 10, further comprising: a first source electrode and a first drain electrode disposed on the first insulating layer and electrically connected to the first oxide semiconductor layer; a second source electrode and a second drain electrode disposed on the second insulating layer and electrically connected to the second oxide semiconductor layer, wherein the data wiring is disposed on the second insulating layer. Claim 13 A display device according to claim 11, further comprising: a sub-gate electrode of the driving transistor disposed on the first insulating layer and spaced apart from the second insulating layer in the planar direction; a third insulating layer disposed on the sub-gate electrode and the second insulating layer, wherein the first gate electrode and the sub-gate electrode overlap with the first insulating layer in between to form a storage capacitor, the second insulating layer is disposed spaced apart in the planar direction without overlapping with the storage capacitor, and the data wiring is disposed on the third insulating layer and overlaps with the second insulating layer. Claim 14 A display device according to claim 13, further comprising a first source electrode and a first drain electrode disposed on the third insulating layer and electrically connected to the first oxide semiconductor layer, and a second source electrode and a second drain electrode electrically connected to the second oxide semiconductor layer. Claim 15 A display device according to claim 9, further comprising: a first flattening layer covering the driving transistor and the switching transistor; a connecting electrode disposed on the first flattening layer and electrically connected to the driving transistor; and a second flattening layer disposed on the first flattening layer and the connecting electrode, wherein the light-emitting element is disposed on the second flattening layer and electrically connected to the connecting electrode. Claim 16 A display device according to claim 10, wherein the upper buffer layer comprises a plurality of buffer layers, and further comprises a light-blocking layer disposed on the first gate insulating layer or any one of the plurality of buffer layers and overlapping with the first oxide semiconductor layer.

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