Organic light emitting display device

Abstract

The present invention comprises a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes an organic light-emitting element that emits light by a driving current, a first transistor that controls the driving current and includes a source electrode which is a first node, a gate electrode which is a second node, and a drain electrode which is a third node, a second transistor that applies a data voltage to the first node, a third transistor that diode-connects the second node and the third node, a fourth transistor that applies an initialization voltage to the first transistor, a fifth transistor that applies a high-potential driving voltage to the first node, a sixth transistor that forms a current path between the driving transistor and the organic light-emitting element, a seventh transistor that applies a reset voltage to the fourth node which is the anode electrode of the organic light-emitting element, and a storage capacitor having one electrode connected to the second node and another electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage, wherein the pixels are driven separately into a refresh frame that programs a data voltage to the pixels and a reset frame that resets the anode electrode of the organic light-emitting element, and during the reset frame, the data voltage is maintained at a first level, and there is no separate stage for applying on-bias stress. The bezel can be reduced.

Description

Technology Field

[0001] The present invention relates to an organic light-emitting display device, and more specifically, to an organic light-emitting display device in which the driving frequency is variable. Background Technology

[0002] An organic light-emitting diode (OLED), which is a self-luminous device, comprises an anode electrode and a cathode electrode, and an organic compound layer formed between them. The organic compound layer consists of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) emits visible light. Active matrix type organic light-emitting display devices include self-luminous organic light-emitting diodes (OLEDs) and are widely used due to their advantages of fast response speed, high luminous efficiency, brightness, and high viewing angle.

[0003] An organic light-emitting display device arranges pixels, each containing an organic light-emitting element, in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data.

[0004] Each pixel includes an organic light-emitting diode, a driving transistor that controls the driving current flowing through the organic light-emitting diode according to the gate-source voltage, and at least one switch transistor that programs the gate-source voltage of the driving transistor.

[0005] As the driving of an organic light-emitting display continues, a hysteresis phenomenon occurs in which the threshold voltage (Vth) of the driving transistor changes. To alleviate the hysteresis phenomenon of the driving transistor, on-bias stress must be applied to the driving transistor so that the source-drain current (Ids) of the driving transistor can flow. To apply on-bias stress to the driving transistor, it is necessary to raise the initialization voltage, which is at a low level in a single frame, to a high level.

[0006] Accordingly, a separate stage for swinging the initialization voltage must be included in the gate driver. Consequently, the organic light-emitting display device includes a separate stage for applying on-bias stress to the gate driver, which causes problems such as increased bezel size and increased driving power consumption. The problem to be solved

[0007] The inventors of the present invention have invented an organic light-emitting display device in which a pixel circuit is newly designed to apply on-bias stress without having a separate stage.

[0008] Accordingly, the problem that the present invention aims to solve is to provide an organic light-emitting display device capable of applying on-bias stress to a driving transistor without increasing the bezel.

[0009] Another problem that the present invention aims to solve is to provide a display device capable of mitigating hysteresis of a driving transistor while minimizing power consumption.

[0010] The problems of the present invention are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0011] To solve the problem described above, an organic light-emitting display device according to an embodiment of the present invention comprises a plurality of pixels arranged in a display panel, and each of the plurality of pixels comprises an organic light-emitting element that emits light by a driving current, a first transistor that controls the driving current and includes a source electrode which is a first node, a gate electrode which is a second node, and a drain electrode which is a third node, a second transistor that applies a data voltage to the first node, a third transistor that diode-connects the second node and the third node, a fourth transistor that applies an initialization voltage to the first transistor, a fifth transistor that applies a high-potential driving voltage to the first node, a sixth transistor that forms a current path between the driving transistor and the organic light-emitting element, a seventh transistor that applies a reset voltage to the fourth node which is the anode electrode of the organic light-emitting element, and a storage capacitor having one electrode connected to the second node and another electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage, and is driven separately by a refresh frame that programs a data voltage to the pixel and a reset frame that resets the anode electrode of the organic light-emitting element, and during the reset frame, the data voltage is at a first level By maintaining it, the bezel can be reduced without providing a separate stage for applying on-bias stress.

[0012] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0013] The present invention may not include a separate stage for swinging the initialization voltage to apply on-bias stress, thereby allowing the width of the bezel to be reduced.

[0014] The present invention eliminates the need to drive a separate stage for on-bias stress, thereby reducing power consumption.

[0015] Since the present invention does not require the formation of a separate stage for on-bias stress, the manufacturing process yield of the gate driver can be improved.

[0016] The present invention can prevent leakage current of a transistor during an anode reset frame by minimizing the gate-source voltage of the transistor.

[0017] The effects according to the present invention are not limited to those exemplified above, and a wider variety of effects are included within the present invention. Brief explanation of the drawing

[0018] FIG. 1 is a block diagram of an organic light-emitting display device according to one embodiment of the present invention. FIG. 2 is a circuit diagram showing a pixel of an organic light-emitting display device according to one embodiment of the present invention. FIG. 3 is a waveform diagram showing a signal applied to a pixel of an organic light-emitting display device according to one embodiment of the present invention during one frame. FIG. 4a is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during an on-bias stress period. FIG. 4b is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during the initial period. FIG. 4c is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during a sampling period. FIG. 4d is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during an emission period. FIG. 5 is a diagram showing a gate driver of an organic light-emitting display device according to one embodiment of the present invention. FIG. 6 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment of the present invention. FIG. 7 is a waveform diagram showing a signal applied to a pixel of an organic light-emitting display device according to another embodiment of the present invention during one frame. FIG. 8a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during an on-bias stress period. FIG. 8b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during the initial period. FIG. 8c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during a sampling period. FIG. 8d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during an emission period. FIG. 9 is a drawing showing a gate driver of an organic light-emitting display device according to another embodiment of the present invention. FIG. 10 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention. FIG. 11a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during an on-bias stress period. FIG. 11b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during the initial period. FIG. 11c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during a sampling period. FIG. 11d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during an emission period. FIG. 12 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention. FIG. 13a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during an on-bias stress period. FIG. 13b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during the initial period. FIG. 13c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during a sampling period. FIG. 13d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during an emission period. Specific details for implementing the invention

[0019] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0020] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in the present invention, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0023] When an element or layer is referred to as "on" another element or layer, it includes cases where another layer or element is placed directly on top of or in between.

[0024] Additionally, terms such as first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0025] Throughout the specification, the same reference numerals refer to the same components.

[0026] The size and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

[0027] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0028] Hereinafter, the present invention will be examined in detail with reference to the drawings.

[0029] FIG. 1 is a block diagram of an organic light-emitting display device according to one embodiment of the present invention.

[0030] Referring to FIG. 1, an organic light-emitting display device according to one embodiment of the present invention includes a display panel (100), a timing control circuit (200), a data driver (300), and a gate driver (401, 402).

[0031] The display panel (100) includes a display area (A / A) for displaying images and a non-display area (N / A) located outside the display area (A / A) and having various signal lines and gate drivers (401, 402) arranged therein.

[0032] In order to display an image, a plurality of pixels (P) are arranged in a display area (A / A). In addition, n gate lines (GL1 to GLn) arranged in a first direction and m data lines (DL1 to DLm) arranged in a direction different from the first direction are arranged in the display area (A / A). The plurality of pixels (P) are electrically connected to the n gate lines (GL1 to GLn) and the m data lines (DL1 to DLm). Accordingly, a gate voltage and a data voltage are applied to each pixel (P) through the gate lines (GL1 to GLn) and the data lines (DL1 to DLm). Then, each pixel (P) implements a grayscale based on the gate voltage and the data voltage. Finally, an image is displayed in the display area (A / A) based on the grayscale displayed by each pixel (P).

[0033] Various signal lines (GL1 to GLn and DL1 to DLm) that transmit signals controlling the operation of pixels (P) placed in the display area (A / A) and gate drivers (401, 402) are arranged in the non-display area (N / A).

[0034] The timing control circuit (200) transmits the input video signal (RGB) received from the host system to the data driver (300).

[0035] The timing control circuit (200) generates control signals (GCS, DCS) to control the operation timing of the gate driver (401, 402) and the data driver (300) using timing signals such as a clock signal (DCLK), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal (DE) received together with the image data (RGB). Here, the horizontal synchronization signal (Hsync) is a signal indicating the time taken to display one horizontal line on the screen, the vertical synchronization signal (Vsync) is a signal indicating the time taken to display one frame of the screen, and the data enable signal (DE) is a signal indicating the period of supplying data voltage to a pixel (P) defined in the display panel (100).

[0036] To explain again, the timing control circuit (200) receives a timing signal, outputs a gate control signal (GCS) to the gate driver (401, 402), and outputs a data control signal (DCS) to the data driver (300).

[0037] The data driver (300) receives a data control signal (DCS) and outputs a data voltage to the data lines (DL1 to DLm).

[0038] Specifically, the data driver (300) generates a sampling signal according to the data control signal (DCS), latches the image data (RGB) according to the sampling signal to change it into a data voltage, and then supplies the data voltage to the data lines (DL1 to DLm) in response to the Source Output Enable (SOE) signal.

[0039] The data driver (300) may be connected to the bonding pad of the display panel (100) in a Chip On Glass (COG) manner, or may be placed directly on the display panel (100), or, in some cases, may be integrated and placed on the display panel (100). Additionally, the data driver (300) may be placed in a Chip On Film (COF) manner.

[0040] The gate driver (401, 402) sequentially supplies scan signals and light emission signals corresponding to gate voltages to gate lines (GL1 to GLn) according to the gate control signal (GCS).

[0041] A general gate driver (401, 402) is formed independently of the display panel (100) and can be electrically connected to the display panel in various ways. However, the gate driver (401, 402) of the organic light-emitting display device according to one embodiment of the present invention is formed in the form of a thin film pattern when manufacturing the substrate of the display panel (100) and can be embedded in a Gate In Panel (GIP) manner on a non-display area (N / A).

[0042] And, the gate driver (401, 402) can be separated into a first gate driver (401) and a second gate driver (402) placed on both sides of the display panel (100).

[0043] Specifically, the first gate driver (401) supplies a scan signal and a light emission signal to a plurality of pixels (P). Accordingly, the first gate driver (401) may include a plurality of scan driving stages and a plurality of light emission driving stages. The plurality of scan driving stages supply a scan signal to a plurality of pixels (P), and the plurality of light emission driving stages supply a light emission signal to a plurality of pixels (P).

[0044] In addition, the second gate driver (402) also supplies a scan signal and a light emission signal to a plurality of pixels (P). Accordingly, the second gate driver (402) may include a plurality of scan driving stages and a plurality of light emission driving stages. In addition, the plurality of scan driving stages supply a scan signal to a plurality of pixels (P), and the plurality of light emission driving stages supply a light emission signal to a plurality of pixels (P).

[0045] Below, the configuration and driving method of multiple pixels (P) will be explained in detail.

[0046] The switch elements constituting each of the plurality of pixels (P) can be implemented as transistors with an n-type or p-type MOSFET structure. Although n-type transistors have been exemplified in the following embodiments, the present invention is not limited thereto.

[0047] Additionally, a transistor is a three-electrode device comprising a gate electrode, a source electrode, and a drain electrode. The source electrode is the electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source electrode. The drain electrode is the electrode through which carriers exit the transistor. In other words, the flow of carriers in a MOSFET is from the source electrode to the drain electrode. In the case of an n-type MOSFET (NMOS), since the carriers are electrons, the voltage of the source electrode is lower than the voltage of the drain electrode to allow electrons to flow from the source electrode to the drain electrode. Because electrons flow from the source electrode to the drain electrode in an n-type MOSFET, the direction of the current flows from the drain electrode to the source electrode. In the case of a p-type MOSFET (PMOS), since the carriers are holes, the voltage of the source electrode is higher than the voltage of the drain electrode to allow holes to flow from the source electrode to the drain electrode. In a p-type MOSFET, current flows from the source electrode to the drain electrode because holes flow from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of a MOSFET are not fixed. For example, the source and drain electrodes of a MOSFET can be changed depending on the applied voltage. The invention should not be limited by the source and drain electrodes of the transistor in the following examples.

[0048] In addition, for convenience of explanation, high-level voltage and low-level voltage have been mentioned below, but are not limited thereto. Depending on the type of transistor, high-level voltage and low-level voltage may be changed to low-level voltage and high-level voltage, and high-level voltage may be defined as a first level and low-level voltage may be defined as a second level.

[0049] <본 발명의 일 실시예 - 제1 실시예>

[0050] FIG. 2 is a circuit diagram showing a pixel of an organic light-emitting display device according to one embodiment of the present invention.

[0051] Each pixel (P) includes an organic light-emitting diode (OLED), a driving transistor (T1), second to seventh transistors (T2 to T7), and a storage capacitor (Cstg).

[0052] An organic light-emitting diode (OLED) emits light through a driving current supplied from a driving transistor (T1). A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light-emitting diode (OLED). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into or transports holes to the emission layer, and may be, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). And, the electron transport layer is a layer that injects electrons into or transports electrons to the emission layer, and may be, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the organic light-emitting diode (OLED) is connected to the fourth node (N4), and the cathode electrode of the organic light-emitting diode is connected to the input terminal of the low potential driving voltage (VSSEL).

[0053] The driving transistor (T1) controls the driving current applied to the organic light-emitting diode (OLED) according to the source-gate voltage (Vsg). The driving transistor (T1) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The source electrode of the driving transistor (T1) is connected to a first node (N1), the gate electrode is connected to a second node (N2), and the drain electrode is connected to a third node (N3). The driving transistor (T1) may be referred to as the first transistor.

[0054] The second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1). The second transistor (T2) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The second transistor (T2) includes a source electrode connected to a data line, a drain electrode connected to the first node (N1), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a second scan signal (SC2(n)) at a low level, which is a turn-on level.

[0055] The third transistor (T3) diode-connects the gate electrode and the drain electrode. To minimize leakage current, the third transistor (T3) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The third transistor (T3) includes a drain electrode connected to the third node (N3), a source electrode connected to the second node (N2), and a gate electrode connected to a first scan signal line that transmits the first scan signal (SC1(n)). Accordingly, the third transistor (T3) diode-connects the gate electrode and the drain electrode of the driving transistor (T1) in response to the first scan signal (SC1(n)) at a high level, which is the turn-on level.

[0056] The fourth transistor (T4) applies an initialization voltage (Vini) to the third node (N3), which is the drain electrode of the driving transistor (T1). The fourth transistor (T4) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The fourth transistor (T4) includes a source electrode connected to an initialization voltage line that transmits the initialization voltage (Vini), a drain electrode connected to the third node (N3), and a gate electrode connected to a third scan signal line that transmits a third scan signal (SC3(n)). Accordingly, the fourth transistor (T4) applies the initialization voltage (Vini) to the third node (N3), which is the drain electrode of the driving transistor (T1), in response to the third scan signal (SC3(n)), which is a low level and a turn-on level.

[0057] The fifth transistor (T5) applies a high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1). The fifth transistor (T5) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The fifth transistor (T5) includes a source electrode connected to a high potential driving voltage line that transmits the high potential driving voltage (VDDEL), a drain electrode connected to the first node (N1), and a gate electrode connected to a light emission signal line that transmits a light emission signal (EM(n)). Accordingly, the fifth transistor (T5) applies the high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a low-level light emission signal (EM(n)) which is the turn-on level.

[0058] The sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED). The sixth transistor (T6) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The sixth transistor (T6) includes a source electrode connected to a third node (N3), a drain electrode connected to a fourth node (N4), and a gate electrode connected to a light-emitting signal line that transmits a light-emitting signal (EM(n)). The sixth transistor (T6) forms a current path between the third node (N3), which is the source electrode of the sixth transistor (T6), and the fourth node (N4), which is the drain electrode of the sixth transistor (T6), in response to the light-emitting signal (EM(n)). Accordingly, the sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED) in response to a low-level light-emitting signal (EM(n)) which is a turn-on level.

[0059] The seventh transistor (T7) applies a reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device. The seventh transistor (T7) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The seventh transistor (T7) includes a source electrode connected to a reset voltage line that transmits the reset voltage (VAR), a drain electrode connected to the fourth node (N4), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the seventh transistor (T7) applies the reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device, in response to the second scan signal (SC2(n)) at a low level, which is the turn-on level.

[0060] The storage capacitor (Cstg) maintains the data voltage (Vdata) stored in each pixel for one frame. The storage capacitor (Cstg) includes a first electrode connected to a second node (N2) and a second electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL). That is, one electrode of the storage capacitor (Cstg) is connected to the gate electrode of the driving transistor (T1), and the other electrode of the storage capacitor (Cstg) is connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL).

[0061] FIG. 3 is a waveform diagram showing a signal applied to a pixel of an organic light-emitting display device according to one embodiment of the present invention during one frame.

[0062] FIG. 4a is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during an on-bias stress period.

[0063] FIG. 4b is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during the initial period.

[0064] FIG. 4c is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during a sampling period.

[0065] FIG. 4d is a circuit diagram of a pixel of an organic light-emitting display device according to one embodiment of the present invention during an emission period.

[0066] Referring to FIGS. 2 to 4d, the driving of a pixel of an organic light-emitting display device according to one embodiment of the present invention is as follows.

[0067] An organic light-emitting display device according to one embodiment of the present invention can be driven separately into a refresh frame and an anode reset frame. In the refresh frame, a data voltage (Vdata) is programmed to each pixel (P), and the organic light-emitting diode (OLED) emits light. The anode reset frame may be a vertical blank frame, and the anode electrode of the organic light-emitting diode (OLED) is reset during the anode reset frame.

[0068] In an organic light-emitting display device according to one embodiment of the present invention, the anode reset frame may include a plurality of on-bias stress periods (hereinafter referred to as “stress periods”). The stress period (on-bias stress) is a period during which bias stress is applied to a first node (N1), which is the source electrode of a driving transistor (T1). Additionally, during the stress period (on-bias stress), the anode electrode of the organic light-emitting device (OLED) may be reset. And as shown in FIG. 3, during the anode reset frame, the reset voltage (VAR) is at a low level, and the initialization voltage (Vini) and data voltage (Vdata) are at a high level.

[0069] In an organic light-emitting display device according to one embodiment of the present invention, the refresh frame can be divided into an initial period, a sampling period, and an emission period. The initial period is a period for initializing the voltage of the third node (N3), which is the drain electrode of the driving transistor (T1). The sampling period is a period for sampling the threshold voltage (Vth) of the driving transistor (T1) and programming the data voltage (Vdata). The emission period is a period for emitting light from the organic light-emitting element (OLED) according to the driving current caused by the source-gate voltage of the programmed driving transistor (T1). And as shown in FIG. 3, during the refresh frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level.

[0070] Specifically, referring to FIGS. 3 and FIG. 4a, during the On Bias Stress period of the anode reset frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level. That is, during the On Bias Stress period of the anode reset frame, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In other words, in an anode reset frame containing multiple On Bias Stress periods, the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), may be a waveform containing multiple pulses. Furthermore, in an anode reset frame containing multiple On Bias Stress periods, the data voltage (Vdata) is always at a high level.

[0071] Accordingly, the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset by the reset voltage (VAR).

[0072] Then, the second transistor (T2) is turned on to apply a high-level data voltage (Vdata) to the first node (N1). The high-level data voltage (Vdata) can be selected within a voltage range sufficiently higher than the operating voltage of the organic light-emitting diode (OLED) and can be set to a voltage equal to or lower than the high-potential driving voltage (VDDEL). That is, by applying an on-bias stress to the first node (N1), which is the source electrode of the driving transistor (T1), during the on-bias stress period, the gate-source voltage (Vgs) of the driving transistor (T1) can be lowered. Accordingly, by allowing the source-drain current (Ids) of the driving transistor (T1) to flow during the on-bias stress period, the hysteresis of the driving transistor (T1) can be relieved.

[0073] And, in the anode reset frame, the initialization voltage (Vini) may be at a high level. Accordingly, a high-level third scan signal (SC3(n)) is applied to the gate electrode of the fourth transistor (T4), and a high-level initialization voltage (Vini) is applied to the source electrode of the fourth transistor (T4), so the potential difference between the gate electrode and the source electrode of the fourth transistor (T4) can be reduced. Therefore, the leakage current of the fourth transistor (T4) during the anode reset frame can be minimized.

[0074] And, referring to FIGS. 3 and FIGS. 4b, during the initial period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the third scan signal (SC3(n)) is at a low level, which is the turn-on level. Accordingly, the third transistor (T3) and the fourth transistor (T4) are turned on, and an initialization voltage (Vini) is applied to the third node (N3) and the second node (N2). As a result, the gate electrode and the drain electrode of the driving transistor (T1) are initialized to the initialization voltage (Vini). In the refresh frame, the initialization voltage (Vini) can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting diode (OLED), and can be set to a voltage equal to or lower than the low potential driving voltage (VSSEL).

[0075] And, referring to FIG. 3 and FIG. 4c, during the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the second scan signal (SC2(n)) is at a low level, which is the turn-on level. During the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In FIG. 3, the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), are shown as waveforms containing one pulse, but are not limited thereto, and the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), may be waveforms containing multiple pulses.

[0076] Accordingly, during the sampling period, the second transistor (T2) is turned on, and the data voltage (Vdata) is applied to the first node (N1). Then, the third transistor (T3) is also turned on, so that the driving transistor (T1) is diode connected, and the gate electrode and drain electrode of the driving transistor (T1) are short-circuited, so that the driving transistor (T1) operates like a diode. During the sampling period, a current (Ids) flows between the source and drain of the driving transistor (T1). Since the gate electrode and drain electrode of the driving transistor (T1) are diode connected, the voltage of the second node (N2) rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage (Vgs) of the driving transistor (T1) reaches Vth. During the sampling period, the voltage of the second node (N2) is charged to a voltage (Vdata-|Vth|) corresponding to the difference between the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (T1).

[0077] And, during the sampling period of the refresh frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level, so the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR).

[0078] Additionally, in a refresh frame, when the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), is a waveform containing multiple pulses, the second transistor (T2) is turned on, and a data voltage (Vdata) can be applied to the first node (N1). Accordingly, even in a refresh frame, bias stress can be applied to the first node (N1), which is the source electrode of the driving transistor (T1), thereby mitigating the hysteresis of the driving transistor (T1).

[0079] And, referring to FIGS. 3 and 4d, during the emission period of the refresh frame, the light-emitting signal (EM(n)) is at a low level, which is the turn-on level. Accordingly, the fifth transistor (T5) is turned on to apply a high-potential driving voltage (VDDEL) to the first node (N1). Then, the sixth transistor (T6) is also turned on to form a current path for the third node (N3) and the fourth node (N4). Eventually, the driving current (Ioled) passing through the source electrode and drain electrode of the driving transistor (T1) is applied to the organic light-emitting diode (OLED).

[0080] The relationship for the driving current (Ioled) flowing through the organic light-emitting diode (OLED) during the emission period is as shown in [Equation 1] below.

[0081] [Mathematical Formula 1]

[0082] Ioled=k / 2(Vgs+|Vth|) 2 = k / 2(Vg-Vs+|Vth|) 2 = k / 2(Vdata-|Vth|-VDD+|Vth|) 2 = k / 2(Vdata-VDD) 2

[0083] In [Equation 1], k / 2 represents a proportionality constant determined by the electron mobility, parasitic capacitance, and channel capacitance of the driving transistor (DT).

[0084] As seen in [Mathematical Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is eliminated from the relationship of the driving current (Ioled), which means that the driving current (Ioled) does not change even if the threshold voltage (Vth) changes in the display device according to the present specification. As seen, the display device according to the present specification can program the data voltage regardless of the amount of change in the threshold voltage (Vth) during the sampling period.

[0085] As mentioned above, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR) during both the stress period (On Bias Stress) of the anode reset frame and the sampling period (Sampling) of the refresh frame.

[0086] Ultimately, in an organic light-emitting display device according to one embodiment of the present invention, the anode electrode of an organic light-emitting element (OLED) can be periodically reset across refresh frames and reset frames. Accordingly, since a continuous rise in the voltage of the anode electrode of the organic light-emitting element (OLED) caused by leakage current is prevented even at low frequency driving, the anode electrode of the organic light-emitting element (OLED) can maintain a constant voltage level. Therefore, even though the driving frequency is switched to a low frequency, changes in the brightness of the organic light-emitting display device are minimized, and image quality can be improved.

[0087] FIG. 5 is a diagram showing a gate driver of an organic light-emitting display device according to one embodiment of the present invention.

[0088] For example, in order to apply on-bias stress to the driving transistor and to raise the initialization voltage from a low level to a high level within a single frame, the organic light-emitting display device may include a separate stage in the gate driver that swings the initialization voltage. In this case, as the organic light-emitting display device includes a separate stage that swings the initialization voltage to apply on-bias stress to the gate driver, the bezel is increased and power consumption may also increase as the separate stage is driven.

[0089] However, an organic light-emitting display device according to one embodiment of the present invention can apply on-bias stress to a driving transistor (T1) using a high-level data voltage (Vdata). Accordingly, in order to apply on-bias stress, an organic light-emitting display device according to one embodiment of the present invention does not require a separate stage for swinging an initialization voltage to be included in the gate driver.

[0090] Accordingly, as illustrated in FIG. 5, the first gate driver (401) positioned on the left side of the display area (A / A) and the second gate driver (402) positioned on the right side of the display area (A / A) both include only the light emission signal stage (EM), the first scan signal stage (SC1), the odd second scan signal stage (SC2_Odd), the even second scan signal stage (SC2_Even), and the third scan signal stage (SC3), and may not include a separate stage for swinging the initialization voltage to apply on-bias stress.

[0091] Accordingly, the width of each of the first gate driver (401) and the second gate driver (402) can be reduced from 400 μm to about 350 μm, and not only can the width of the bezel be reduced, but there is also no need to drive a separate stage for on-bias stress, so power consumption can also be reduced.

[0092] Additionally, since the organic light-emitting display device according to one embodiment of the present invention does not require forming a separate stage for on-bias stress, the manufacturing process yield of the gate driver can be improved.

[0093] Hereinafter, an organic light-emitting display device according to another embodiment of the present invention will be described. Compared to the organic light-emitting display device according to one embodiment of the present invention, the organic light-emitting display device according to another embodiment of the present invention differs only in the fourth transistor and the initialization voltage, while other technical features are identical.

[0094] <본 발명의 다른 실시예 - 제2 실시예>

[0095] FIG. 6 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment of the present invention.

[0096] Each pixel (P) includes an organic light-emitting diode (OLED), a driving transistor (T1), second to seventh transistors (T2 to T7), and a storage capacitor (Cstg).

[0097] An organic light-emitting diode (OLED) emits light through a driving current supplied from a driving transistor (T1). A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light-emitting diode (OLED). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into or transports holes to the emission layer, and may be, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). And, the electron transport layer is a layer that injects electrons into or transports electrons to the emission layer, and may be, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the organic light-emitting diode (OLED) is connected to the fourth node (N4), and the cathode electrode of the organic light-emitting diode is connected to the input terminal of the low potential driving voltage (VSSEL).

[0098] The driving transistor (T1) controls the driving current applied to the organic light-emitting diode (OLED) according to the source-gate voltage (Vsg). The driving transistor (T1) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The source electrode of the driving transistor (T1) is connected to a first node (N1), the gate electrode is connected to a second node (N2), and the drain electrode is connected to a third node (N3). The driving transistor (T1) may be referred to as the first transistor.

[0099] The second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1). The second transistor (T2) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The second transistor (T2) includes a source electrode connected to a data line, a drain electrode connected to the first node (N1), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a second scan signal (SC2(n)) at a low level, which is a turn-on level.

[0100] The third transistor (T3) diode-connects the gate electrode and the drain electrode. To minimize leakage current, the third transistor (T3) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The third transistor (T3) includes a drain electrode connected to the third node (N3), a source electrode connected to the second node (N2), and a gate electrode connected to a first scan signal line that transmits the first scan signal (SC1(n)). Accordingly, the third transistor (T3) diode-connects the gate electrode and the drain electrode of the driving transistor (T1) in response to the first scan signal (SC1(n)) at a high level, which is the turn-on level.

[0101] The fourth transistor (T4) applies an initialization voltage (Vini) to the third node (N3), which is the drain electrode of the driving transistor (T1). To minimize leakage current, the fourth transistor (T4) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The fourth transistor (T4) includes a source electrode connected to an initialization voltage line that transmits the initialization voltage (Vini), a drain electrode connected to the third node (N3), and a gate electrode connected to a first scan signal line of the previous stage that transmits the first scan signal (SC1(n-1)) of the previous stage. Accordingly, the fourth transistor (T4) applies the initialization voltage (Vini) to the third node (N3), which is the drain electrode of the driving transistor (T1), in response to the first scan signal (SC1(n-1)) of the previous stage at a high level, which is the turn-on level.

[0102] The fifth transistor (T5) applies a high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1). The fifth transistor (T5) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The fifth transistor (T5) includes a source electrode connected to a high potential driving voltage line that transmits the high potential driving voltage (VDDEL), a drain electrode connected to the first node (N1), and a gate electrode connected to a light emission signal line that transmits a light emission signal (EM(n)). Accordingly, the fifth transistor (T5) applies the high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a low-level light emission signal (EM(n)) which is the turn-on level.

[0103] The sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED). The sixth transistor (T6) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The sixth transistor (T6) includes a source electrode connected to a third node (N3), a drain electrode connected to a fourth node (N4), and a gate electrode connected to a light-emitting signal line that transmits a light-emitting signal (EM(n)). The sixth transistor (T6) forms a current path between the third node (N3), which is the source electrode of the sixth transistor (T6), and the fourth node (N4), which is the drain electrode of the sixth transistor (T6), in response to the light-emitting signal (EM(n)). Accordingly, the sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED) in response to a low-level light-emitting signal (EM(n)) which is a turn-on level.

[0104] The seventh transistor (T7) applies a reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device. The seventh transistor (T7) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The seventh transistor (T7) includes a source electrode connected to a reset voltage line that transmits the reset voltage (VAR), a drain electrode connected to the fourth node (N4), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the seventh transistor (T7) applies the reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device, in response to the second scan signal (SC2(n)) at a low level, which is the turn-on level.

[0105] The storage capacitor (Cstg) maintains the data voltage (Vdata) stored in each pixel for one frame. The storage capacitor (Cstg) includes a first electrode connected to a second node (N2) and a second electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL). That is, one electrode of the storage capacitor (Cstg) is connected to the gate electrode of the driving transistor (T1), and the other electrode of the storage capacitor (Cstg) is connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL).

[0106] FIG. 7 is a waveform diagram showing a signal applied to a pixel of an organic light-emitting display device according to another embodiment of the present invention during one frame.

[0107] FIG. 8a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during an on-bias stress period.

[0108] FIG. 8b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during the initial period.

[0109] FIG. 8c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during a sampling period.

[0110] FIG. 8d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment of the present invention during an emission period.

[0111] Referring to FIGS. 6 to 8d, the driving of a pixel of an organic light-emitting display device according to another embodiment of the present invention is as follows.

[0112] An organic light-emitting display device according to another embodiment of the present invention may also be driven separately into a Refresh Frame and an Anode Reset Frame. In the Refresh Frame, a data voltage (Vdata) is programmed to each pixel (P), and the organic light-emitting diode (OLED) emits light. The Anode Reset Frame may be a vertical blank frame, and the anode electrode of the organic light-emitting diode (OLED) is reset during the Anode Reset Frame.

[0113] In an organic light-emitting display device according to another embodiment of the present invention, the anode reset frame may include a plurality of stress periods (On Bias Stress). The stress period (On Bias Stress) is a period during which bias stress is applied to the first node (N1), which is the source electrode of the driving transistor (T1). Additionally, during the stress period (On Bias Stress), the anode electrode of the organic light-emitting device (OLED) may be reset. And as shown in FIG. 7, during the anode reset frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level, and the data voltage (Vdata) is at a high level.

[0114] In an organic light-emitting display device according to another embodiment of the present invention, the refresh frame can be divided into an initial period, a sampling period, and an emission period. The initial period is a period for initializing the voltage of the third node (N3), which is the drain electrode of the driving transistor (T1). The sampling period is a period for sampling the threshold voltage (Vth) of the driving transistor (T1) and programming the data voltage (Vdata). The emission period is a period for emitting light from the organic light-emitting diode (OLED) according to the driving current caused by the source-gate voltage of the programmed driving transistor (T1). And as shown in FIG. 7, during the refresh frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level.

[0115] Specifically, referring to FIGS. 7 and FIG. 8a, during the On Bias Stress period of the anode reset frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level. That is, during the On Bias Stress period of the anode reset frame, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In other words, in an anode reset frame containing multiple On Bias Stress periods, the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), may be a waveform containing multiple pulses. Furthermore, in an anode reset frame containing multiple On Bias Stress periods, the data voltage (Vdata) is always at a high level.

[0116] Accordingly, the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset by the reset voltage (VAR).

[0117] Then, the second transistor (T2) is turned on to apply a high-level data voltage (Vdata) to the first node (N1). The high-level data voltage (Vdata) can be selected within a voltage range sufficiently higher than the operating voltage of the organic light-emitting diode (OLED) and can be set to a voltage equal to or lower than the high-potential driving voltage (VDDEL). That is, by applying an on-bias stress to the first node (N1), which is the source electrode of the driving transistor (T1), during the on-bias stress period, the gate-source voltage (Vgs) of the driving transistor (T1) can be lowered. Accordingly, by allowing the source-drain current (Ids) of the driving transistor (T1) to flow during the on-bias stress period, the hysteresis of the driving transistor (T1) can be relieved.

[0118] And, referring to FIGS. 7 and FIGS. 8b, during the initial period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the first scan signal (SC1(n-1)) of the previous stage is at a high level, which is the turn-on level. Accordingly, the third transistor (T3) and the fourth transistor (T4) are turned on, and an initialization voltage (Vini) is applied to the third node (N3) and the second node (N2). As a result, the gate electrode and the drain electrode of the driving transistor (T1) are initialized to the initialization voltage (Vini). In the refresh frame, the initialization voltage (Vini) can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting diode (OLED), and can be set to a voltage equal to or lower than the low potential driving voltage (VSSEL).

[0119] And, referring to FIGS. 7 and FIGS. 8c, during the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the second scan signal (SC2(n)) is at a low level, which is the turn-on level. During the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In FIG. 7, in the refresh frame, the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), are shown as waveforms containing one pulse, but are not limited thereto, and the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), may be waveforms containing multiple pulses.

[0120] Accordingly, during the sampling period, the second transistor (T2) is turned on, and the data voltage (Vdata) is applied to the first node (N1). Then, the third transistor (T3) is also turned on, so that the driving transistor (T1) is diode connected, and the gate electrode and drain electrode of the driving transistor (T1) are short-circuited, so that the driving transistor (T1) operates like a diode. During the sampling period, a current (Ids) flows between the source and drain of the driving transistor (T1). Since the gate electrode and drain electrode of the driving transistor (T1) are diode connected, the voltage of the second node (N2) rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage (Vgs) of the driving transistor (T1) reaches Vth. During the sampling period, the voltage of the second node (N2) is charged to a voltage (Vdata-|Vth|) corresponding to the difference between the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (T1).

[0121] And, during the sampling period of the refresh frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level, so the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR).

[0122] Additionally, in a refresh frame, when the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), is a waveform containing multiple pulses, the second transistor (T2) is turned on, and a data voltage (Vdata) can be applied to the first node (N1). Accordingly, even in a refresh frame, bias stress can be applied to the first node (N1), which is the source electrode of the driving transistor (T1), thereby mitigating the hysteresis of the driving transistor (T1).

[0123] And, referring to FIGS. 7 and 8d, during the emission period of the refresh frame, the light-emitting signal (EM(n)) is at a low level, which is the turn-on level. Accordingly, the fifth transistor (T5) is turned on to apply a high-potential driving voltage (VDDEL) to the first node (N1). Then, the sixth transistor (T6) is also turned on to form a current path for the third node (N3) and the fourth node (N4). Eventually, the driving current (Ioled) passing through the source electrode and drain electrode of the driving transistor (T1) is applied to the organic light-emitting diode (OLED).

[0124] During the emission period, the relationship for the driving current (Ioled) flowing through the organic light-emitting diode (OLED) is as described above [Equation 1].

[0125] As seen in [Mathematical Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is eliminated from the relationship of the driving current (Ioled), which means that the driving current (Ioled) does not change even if the threshold voltage (Vth) changes in the display device according to the present specification. As seen, the display device according to the present specification can program the data voltage regardless of the amount of change in the threshold voltage (Vth) during the sampling period.

[0126] As mentioned above, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR) during both the stress period (On Bias Stress) of the anode reset frame and the sampling period (Sampling) of the refresh frame.

[0127] Ultimately, in an organic light-emitting display device according to another embodiment of the present invention, the anode electrode of the organic light-emitting element (OLED) can be periodically reset across refresh frames and reset frames. Accordingly, since a continuous rise in the voltage of the anode electrode of the organic light-emitting element (OLED) caused by leakage current is prevented even at low frequency driving, the anode electrode of the organic light-emitting element (OLED) can maintain a constant voltage level. Therefore, even though the driving frequency is switched to a low frequency, changes in the brightness of the organic light-emitting display device are minimized, and image quality can be improved.

[0128] FIG. 9 is a drawing showing a gate driver of an organic light-emitting display device according to another embodiment of the present invention.

[0129] An organic light-emitting display device according to another embodiment of the present invention can also apply on-bias stress to a driving transistor (T1) using a high-level data voltage (Vdata). Accordingly, in order to apply on-bias stress, an organic light-emitting display device according to another embodiment of the present invention does not require a separate stage for swinging an initialization voltage to be included in the gate driver.

[0130] Furthermore, as illustrated in FIG. 9, the first gate driver (401) positioned on the left side of the display area (A / A) and the second gate driver (402) positioned on the right side of the display area (A / A) may both include only the light emission signal stage (EM), the first scan signal stage (SC1), the odd second scan signal stage (SC2_Odd), and the even second scan signal stage (SC2_Even), and may not include the third scan signal stage.

[0131] Accordingly, the width of each of the first gate driver (401) and the second gate driver (402) can be reduced from 350 μm to 300 μm compared to an organic light-emitting display device according to one embodiment of the present invention, and the width of the bezel can be further reduced, and there is no need to drive the third scan signal stage, so power consumption can also be effectively reduced.

[0132] Hereinafter, an organic light-emitting display device according to another embodiment (third embodiment) of the present invention will be described. The organic light-emitting display device according to another embodiment (third embodiment) of the present invention and the organic light-emitting display device according to one embodiment of the present invention differ only in the drain electrode connection relationship of the fourth transistor, and other technical features are identical. Accordingly, since the signal applied to the pixel of the organic light-emitting display device according to another embodiment (third embodiment) of the present invention and the signal applied to the pixel of the organic light-emitting display device according to one embodiment of the present invention are identical, the organic light-emitting display device according to another embodiment (third embodiment) of the present invention will be described using the waveform diagram of FIG. 3.

[0133] <본 발명의 또 다른 실시예 - 제3 실시예>

[0134] FIG. 10 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention.

[0135] Each pixel (P) includes an organic light-emitting diode (OLED), a driving transistor (T1), second to seventh transistors (T2 to T7), and a storage capacitor (Cstg).

[0136] An organic light-emitting diode (OLED) emits light through a driving current supplied from a driving transistor (T1). A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light-emitting diode (OLED). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into or transports holes to the emission layer, and may be, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). And, the electron transport layer is a layer that injects electrons into or transports electrons to the emission layer, and may be, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the organic light-emitting diode (OLED) is connected to the fourth node (N4), and the cathode electrode of the organic light-emitting diode is connected to the input terminal of the low potential driving voltage (VSSEL).

[0137] The driving transistor (T1) controls the driving current applied to the organic light-emitting diode (OLED) according to the source-gate voltage (Vsg). The driving transistor (T1) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The source electrode of the driving transistor (T1) is connected to a first node (N1), the gate electrode is connected to a second node (N2), and the drain electrode is connected to a third node (N3). The driving transistor (T1) may be referred to as the first transistor.

[0138] The second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1). The second transistor (T2) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The second transistor (T2) includes a source electrode connected to a data line, a drain electrode connected to the first node (N1), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a second scan signal (SC2(n)) at a low level, which is a turn-on level.

[0139] The third transistor (T3) diode-connects the gate electrode and the drain electrode. To minimize leakage current, the third transistor (T3) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The third transistor (T3) includes a drain electrode connected to the third node (N3), a source electrode connected to the second node (N2), and a gate electrode connected to a first scan signal line that transmits the first scan signal (SC1(n)). Accordingly, the third transistor (T3) diode-connects the gate electrode and the drain electrode of the driving transistor (T1) in response to the first scan signal (SC1(n)) at a high level, which is the turn-on level.

[0140] The fourth transistor (T4) applies an initialization voltage (Vini) to the second node (N2), which is the gate electrode of the driving transistor (T1). The fourth transistor (T4) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The fourth transistor (T4) includes a source electrode connected to an initialization voltage line that transmits the initialization voltage (Vini), a drain electrode connected to the second node (N2), and a gate electrode connected to a third scan signal line that transmits a third scan signal (SC3(n)). Accordingly, the fourth transistor (T4) applies the initialization voltage (Vini) to the second node (N2), which is the gate electrode of the driving transistor (T1), in response to the third scan signal (SC3(n)) which is a low level and a turn-on level.

[0141] The fifth transistor (T5) applies a high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1). The fifth transistor (T5) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The fifth transistor (T5) includes a source electrode connected to a high potential driving voltage line that transmits the high potential driving voltage (VDDEL), a drain electrode connected to the first node (N1), and a gate electrode connected to a light emission signal line that transmits a light emission signal (EM(n)). Accordingly, the fifth transistor (T5) applies the high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a low-level light emission signal (EM(n)) which is the turn-on level.

[0142] The sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED). The sixth transistor (T6) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The sixth transistor (T6) includes a source electrode connected to a third node (N3), a drain electrode connected to a fourth node (N4), and a gate electrode connected to a light-emitting signal line that transmits a light-emitting signal (EM(n)). The sixth transistor (T6) forms a current path between the third node (N3), which is the source electrode of the sixth transistor (T6), and the fourth node (N4), which is the drain electrode of the sixth transistor (T6), in response to the light-emitting signal (EM(n)). Accordingly, the sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED) in response to a low-level light-emitting signal (EM(n)) which is a turn-on level.

[0143] The seventh transistor (T7) applies a reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device. The seventh transistor (T7) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The seventh transistor (T7) includes a source electrode connected to a reset voltage line that transmits the reset voltage (VAR), a drain electrode connected to the fourth node (N4), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the seventh transistor (T7) applies the reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device, in response to the second scan signal (SC2(n)) at a low level, which is the turn-on level.

[0144] The storage capacitor (Cstg) maintains the data voltage (Vdata) stored in each pixel for one frame. The storage capacitor (Cstg) includes a first electrode connected to a second node (N2) and a second electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL). That is, one electrode of the storage capacitor (Cstg) is connected to the gate electrode of the driving transistor (T1), and the other electrode of the storage capacitor (Cstg) is connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL).

[0145] FIG. 11a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during an on-bias stress period.

[0146] FIG. 11b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during the initial period.

[0147] FIG. 11c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during a sampling period.

[0148] FIG. 11d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention during an emission period.

[0149] Referring to FIGS. 10 to 11d, the driving of a pixel of an organic light-emitting display device according to another embodiment (third embodiment) of the present invention is as follows.

[0150] An organic light-emitting display device according to another embodiment (third embodiment) of the present invention may be driven separately into a Refresh Frame and an Anode Reset Frame. In the Refresh Frame, a data voltage (Vdata) is programmed to each pixel (P), and the organic light-emitting diode (OLED) emits light. The Anode Reset Frame may be a vertical blank frame, and the anode electrode of the organic light-emitting diode (OLED) is reset during the Anode Reset Frame.

[0151] In an organic light-emitting display device according to another embodiment (third embodiment) of the present invention, the anode reset frame may include a plurality of stress periods (On Bias Stress). The stress period (On Bias Stress) is a period during which bias stress is applied to the first node (N1), which is the source electrode of the driving transistor (T1). Additionally, during the stress period (On Bias Stress), the anode electrode of the organic light-emitting device (OLED) may be reset. And as shown in FIG. 3, during the anode reset frame, the reset voltage (VAR) is at a low level, and the initialization voltage (Vini) and data voltage (Vdata) are at a high level.

[0152] In an organic light-emitting display device according to another embodiment (third embodiment) of the present invention, the refresh frame can also be divided into an initial period, a sampling period, and an emission period. The initial period is a period for initializing the voltage of the second node (N2), which is the gate electrode of the driving transistor (T1). The sampling period is a period for sampling the threshold voltage (Vth) of the driving transistor (T1) and programming the data voltage (Vdata). The emission period is a period for emitting light from the organic light-emitting element (OLED) according to the driving current caused by the source-gate voltage of the programmed driving transistor (T1). And as shown in FIG. 3, during the refresh frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level.

[0153] Specifically, referring to FIG. 3 and FIG. 11a, during the On Bias Stress period of the anode reset frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level. That is, during the On Bias Stress period of the anode reset frame, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In other words, in an anode reset frame containing multiple On Bias Stress periods, the second scan signals (SC2(n)), namely the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), may be waveforms containing multiple pulses. Furthermore, in an anode reset frame containing multiple On Bias Stress periods, the data voltage (Vdata) is always at a high level.

[0154] Accordingly, the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset by the reset voltage (VAR).

[0155] Then, the second transistor (T2) is turned on to apply a high-level data voltage (Vdata) to the first node (N1). The high-level data voltage (Vdata) can be selected within a voltage range sufficiently higher than the operating voltage of the organic light-emitting diode (OLED) and can be set to a voltage equal to or lower than the high-potential driving voltage (VDDEL). That is, by applying an on-bias stress to the first node (N1), which is the source electrode of the driving transistor (T1), during the on-bias stress period, the gate-source voltage (Vgs) of the driving transistor (T1) can be lowered. Accordingly, by allowing the source-drain current (Ids) of the driving transistor (T1) to flow during the on-bias stress period, the hysteresis of the driving transistor (T1) can be relieved.

[0156] And, in the anode reset frame, the initialization voltage (Vini) may be at a high level. Accordingly, a high-level third scan signal (SC3(n)) is applied to the gate electrode of the fourth transistor (T4), and a high-level initialization voltage (Vini) is applied to the source electrode of the fourth transistor (T4), so the potential difference between the gate electrode and the source electrode of the fourth transistor (T4) can be reduced. Therefore, the leakage current of the fourth transistor (T4) during the anode reset frame can be minimized.

[0157] And, referring to FIG. 3 and FIG. 11b, during the initial period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the third scan signal (SC3(n)) is at a low level, which is the turn-on level. Accordingly, the third transistor (T3) and the fourth transistor (T4) are turned on, and an initialization voltage (Vini) is applied to the third node (N3) and the second node (N2). As a result, the gate electrode and the drain electrode of the driving transistor (T1) are initialized to the initialization voltage (Vini). In the refresh frame, the initialization voltage (Vini) can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting diode (OLED), and can be set to a voltage equal to or lower than the low potential driving voltage (VSSEL).

[0158] And, referring to FIG. 3 and FIG. 11c, during the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the second scan signal (SC2(n)) is at a low level, which is the turn-on level. During the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In FIG. 3, the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), are shown as waveforms containing one pulse, but are not limited thereto, and the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), may be waveforms containing multiple pulses.

[0159] Accordingly, during the sampling period, the second transistor (T2) is turned on, and the data voltage (Vdata) is applied to the first node (N1). Then, the third transistor (T3) is also turned on, so that the driving transistor (T1) is diode connected, and the gate electrode and drain electrode of the driving transistor (T1) are short-circuited, so that the driving transistor (T1) operates like a diode. During the sampling period, a current (Ids) flows between the source and drain of the driving transistor (T1). Since the gate electrode and drain electrode of the driving transistor (T1) are diode connected, the voltage of the second node (N2) rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage (Vgs) of the driving transistor (T1) reaches Vth. During the sampling period, the voltage of the second node (N2) is charged to a voltage (Vdata-|Vth|) corresponding to the difference between the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (T1).

[0160] And, during the sampling period of the refresh frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level, so the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR).

[0161] Additionally, in a refresh frame, when the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), is a waveform containing multiple pulses, the second transistor (T2) is turned on, and a data voltage (Vdata) can be applied to the first node (N1). Accordingly, even in a refresh frame, bias stress can be applied to the first node (N1), which is the source electrode of the driving transistor (T1), thereby mitigating the hysteresis of the driving transistor (T1).

[0162] And, referring to FIG. 3 and FIG. 11d, during the emission period of the refresh frame, the light-emitting signal (EM(n)) is at a low level, which is the turn-on level. Accordingly, the fifth transistor (T5) is turned on to apply a high-potential driving voltage (VDDEL) to the first node (N1). Then, the sixth transistor (T6) is also turned on to form a current path for the third node (N3) and the fourth node (N4). Eventually, the driving current (Ioled) passing through the source electrode and drain electrode of the driving transistor (T1) is applied to the organic light-emitting diode (OLED).

[0163] During the emission period, the relationship for the driving current (Ioled) flowing through the organic light-emitting diode (OLED) is as described above [Equation 1].

[0164] As seen in [Mathematical Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is eliminated from the relationship of the driving current (Ioled), which means that the driving current (Ioled) does not change even if the threshold voltage (Vth) changes in the display device according to the present specification. As seen, the display device according to the present specification can program the data voltage regardless of the amount of change in the threshold voltage (Vth) during the sampling period.

[0165] As mentioned above, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR) during both the stress period (On Bias Stress) of the anode reset frame and the sampling period (Sampling) of the refresh frame.

[0166] Ultimately, in an organic light-emitting display device according to another embodiment (third embodiment) of the present invention, the anode electrode of the organic light-emitting element (OLED) can be periodically reset across refresh frames and reset frames. Accordingly, since a continuous rise in the voltage of the anode electrode of the organic light-emitting element (OLED) caused by leakage current is prevented even at low frequency driving, the anode electrode of the organic light-emitting element (OLED) can maintain a constant voltage level. Therefore, even though the driving frequency is switched to a low frequency, changes in the brightness of the organic light-emitting display device can be minimized, and image quality can be improved.

[0167] In another embodiment of the present invention (third embodiment), the organic light-emitting display device can also apply on-bias stress to the driving transistor (T1) using a high-level data voltage (Vdata). Accordingly, in order to apply on-bias stress, the organic light-emitting display device according to another embodiment of the present invention (third embodiment) does not require a separate stage for swinging the initialization voltage to be included in the gate driver.

[0168] Accordingly, as illustrated in FIG. 5, the first gate driver (401) positioned on the left side of the display area (A / A) and the second gate driver (402) positioned on the right side of the display area (A / A) both include only the light emission signal stage (EM), the first scan signal stage (SC1), the odd second scan signal stage (SC2_Odd), the even second scan signal stage (SC2_Even), and the third scan signal stage (SC3), and may not include a separate stage for swinging the initialization voltage to apply on-bias stress.

[0169] Accordingly, the width of each of the first gate driver (401) and the second gate driver (402) can be reduced from 400 μm to about 350 μm, and not only can the width of the bezel be reduced, but there is also no need to drive a separate stage for on-bias stress, so power consumption can also be reduced.

[0170] Additionally, since the organic light-emitting display device according to another embodiment (third embodiment) of the present invention does not require forming a separate stage for on-bias stress, the manufacturing process yield of the gate driver can be improved.

[0171] Hereinafter, an organic light-emitting display device according to another embodiment (Fourth Embodiment) of the present invention will be described. Compared to the organic light-emitting display device according to another embodiment (Third Embodiment) of the present invention, the organic light-emitting display device according to another embodiment (Fourth Embodiment) of the present invention differs only in the fourth transistor and the initialization voltage, while other technical features are identical. Furthermore, since the signal applied to the pixel of the organic light-emitting display device according to another embodiment (Fourth Embodiment) of the present invention is the same as the signal applied to the pixel of the organic light-emitting display device according to another embodiment (Second Embodiment) of the present invention, the organic light-emitting display device according to another embodiment (Fourth Embodiment) of the present invention will be described using the waveform diagram of FIG. 7.

[0172] <본 발명의 또 다른 실시예- 제4 실시예>

[0173] FIG. 12 is a circuit diagram showing a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention.

[0174] Each pixel (P) includes an organic light-emitting diode (OLED), a driving transistor (T1), second to seventh transistors (T2 to T7), and a storage capacitor (Cstg).

[0175] An organic light-emitting diode (OLED) emits light through a driving current supplied from a driving transistor (T1). A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light-emitting diode (OLED). The organic compound layer may include at least one hole transport layer and an electron transport layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into or transports holes to the emission layer, and may be, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). And, the electron transport layer is a layer that injects electrons into or transports electrons to the emission layer, and may be, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the organic light-emitting diode (OLED) is connected to the fourth node (N4), and the cathode electrode of the organic light-emitting diode is connected to the input terminal of the low potential driving voltage (VSSEL).

[0176] The driving transistor (T1) controls the driving current applied to the organic light-emitting diode (OLED) according to the source-gate voltage (Vsg). The driving transistor (T1) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The source electrode of the driving transistor (T1) is connected to a first node (N1), the gate electrode is connected to a second node (N2), and the drain electrode is connected to a third node (N3). The driving transistor (T1) may be referred to as the first transistor.

[0177] The second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1). The second transistor (T2) may be a p-type MOSFET (PMOS) or a Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistor. The second transistor (T2) includes a source electrode connected to a data line, a drain electrode connected to the first node (N1), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the second transistor (T2) applies a data voltage (Vdata) supplied from a data line to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a second scan signal (SC2(n)) at a low level, which is a turn-on level.

[0178] The third transistor (T3) diode-connects the gate electrode and the drain electrode. To minimize leakage current, the third transistor (T3) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The third transistor (T3) includes a drain electrode connected to the third node (N3), a source electrode connected to the second node (N2), and a gate electrode connected to a first scan signal line that transmits the first scan signal (SC1(n)). Accordingly, the third transistor (T3) diode-connects the gate electrode and the drain electrode of the driving transistor (T1) in response to the first scan signal (SC1(n)) at a high level, which is the turn-on level.

[0179] The fourth transistor (T4) applies an initialization voltage (Vini) to the second node (N2), which is the gate electrode of the driving transistor (T1). To minimize leakage current, the fourth transistor (T4) may be an n-type MOSFET (NMOS) or an oxide thin-film transistor. The fourth transistor (T4) includes a source electrode connected to an initialization voltage line that transmits the initialization voltage (Vini), a drain electrode connected to the second node (N2), and a gate electrode connected to a first scan signal line of the previous stage that transmits the first scan signal (SC1(n-1)) of the previous stage. Accordingly, the fourth transistor (T4) applies the initialization voltage (Vini) to the second node (N2), which is the gate electrode of the driving transistor (T1), in response to the first scan signal (SC1(n-1)) of the previous stage at a high level, which is the turn-on level.

[0180] The fifth transistor (T5) applies a high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1). The fifth transistor (T5) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The fifth transistor (T5) includes a source electrode connected to a high potential driving voltage line that transmits the high potential driving voltage (VDDEL), a drain electrode connected to the first node (N1), and a gate electrode connected to a light emission signal line that transmits a light emission signal (EM(n)). Accordingly, the fifth transistor (T5) applies the high potential driving voltage (VDDEL) to the first node (N1), which is the source electrode of the driving transistor (T1), in response to a low-level light emission signal (EM(n)) which is the turn-on level.

[0181] The sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED). The sixth transistor (T6) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The sixth transistor (T6) includes a source electrode connected to a third node (N3), a drain electrode connected to a fourth node (N4), and a gate electrode connected to a light-emitting signal line that transmits a light-emitting signal (EM(n)). The sixth transistor (T6) forms a current path between the third node (N3), which is the source electrode of the sixth transistor (T6), and the fourth node (N4), which is the drain electrode of the sixth transistor (T6), in response to the light-emitting signal (EM(n)). Accordingly, the sixth transistor (T6) forms a current path between the driving transistor (T1) and the organic light-emitting diode (OLED) in response to a low-level light-emitting signal (EM(n)) which is a turn-on level.

[0182] The seventh transistor (T7) applies a reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device. The seventh transistor (T7) may be a p-type MOSFET (PMOS) or a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The seventh transistor (T7) includes a source electrode connected to a reset voltage line that transmits the reset voltage (VAR), a drain electrode connected to the fourth node (N4), and a gate electrode connected to a second scan signal line that transmits a second scan signal (SC2(n)). Accordingly, the seventh transistor (T7) applies the reset voltage (VAR) to the fourth node (N4), which is the anode of the organic light-emitting device, in response to the second scan signal (SC2(n)) at a low level, which is the turn-on level.

[0183] The storage capacitor (Cstg) maintains the data voltage (Vdata) stored in each pixel for one frame. The storage capacitor (Cstg) includes a first electrode connected to a second node (N2) and a second electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL). That is, one electrode of the storage capacitor (Cstg) is connected to the gate electrode of the driving transistor (T1), and the other electrode of the storage capacitor (Cstg) is connected to a high-potential driving voltage line that transmits a high-potential driving voltage (VDDEL).

[0184] FIG. 13a is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during an on-bias stress period.

[0185] FIG. 13b is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during the initial period.

[0186] FIG. 13c is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during a sampling period.

[0187] FIG. 13d is a circuit diagram of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention during an emission period.

[0188] Referring to FIGS. 12 to 13d, the driving of a pixel of an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention is as follows.

[0189] An organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention may also be driven separately into a Refresh Frame and an Anode Reset Frame. In the Refresh Frame, a data voltage (Vdata) is programmed to each pixel (P), and the organic light-emitting diode (OLED) emits light. The Anode Reset Frame may be a vertical blank frame, and the anode electrode of the organic light-emitting diode (OLED) is reset during the Anode Reset Frame.

[0190] In an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention, the anode reset frame may include a plurality of stress periods (On Bias Stress). The stress period (On Bias Stress) is a period during which bias stress is applied to the first node (N1), which is the source electrode of the driving transistor (T1). Additionally, during the stress period (On Bias Stress), the anode electrode of the organic light-emitting device (OLED) may be reset. And as shown in FIG. 7, during the anode reset frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level, and the data voltage (Vdata) is at a high level.

[0191] In an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention, the refresh frame can be divided into an initial period, a sampling period, and an emission period. The initial period is a period for initializing the voltage of the second node (N2), which is the gate electrode of the driving transistor (T1). The sampling period is a period for sampling the threshold voltage (Vth) of the driving transistor (T1) and programming the data voltage (Vdata). The emission period is a period for emitting light from the organic light-emitting element (OLED) according to the driving current caused by the source-gate voltage of the programmed driving transistor (T1). And as shown in FIG. 7, during the refresh frame, the reset voltage (VAR) and the initialization voltage (Vini) are at a low level.

[0192] Specifically, referring to FIG. 7 and FIG. 13a, during the On Bias Stress period of the anode reset frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level. That is, during the On Bias Stress period of the anode reset frame, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In other words, in an anode reset frame containing multiple On Bias Stress periods, the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), may be a waveform containing multiple pulses. Furthermore, in an anode reset frame containing multiple On Bias Stress periods, the data voltage (Vdata) is always at a high level.

[0193] Accordingly, the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset by the reset voltage (VAR).

[0194] Then, the second transistor (T2) is turned on to apply a high-level data voltage (Vdata) to the first node (N1). The high-level data voltage (Vdata) can be selected within a voltage range sufficiently higher than the operating voltage of the organic light-emitting diode (OLED) and can be set to a voltage equal to or lower than the high-potential driving voltage (VDDEL). That is, by applying an on-bias stress to the first node (N1), which is the source electrode of the driving transistor (T1), during the on-bias stress period, the gate-source voltage (Vgs) of the driving transistor (T1) can be lowered. Accordingly, by allowing the source-drain current (Ids) of the driving transistor (T1) to flow during the on-bias stress period, the hysteresis of the driving transistor (T1) can be relieved.

[0195] And, referring to FIG. 7 and FIG. 13b, during the initial period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the first scan signal (SC1(n-1)) of the previous stage is at a high level, which is the turn-on level. Accordingly, the third transistor (T3) and the fourth transistor (T4) are turned on, and an initialization voltage (Vini) is applied to the third node (N3) and the second node (N2). As a result, the gate electrode and the drain electrode of the driving transistor (T1) are initialized to the initialization voltage (Vini). In the refresh frame, the initialization voltage (Vini) can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting diode (OLED), and can be set to a voltage equal to or lower than the low potential driving voltage (VSSEL).

[0196] And, referring to FIG. 7 and FIG. 13c, during the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, and the second scan signal (SC2(n)) is at a low level, which is the turn-on level. During the sampling period of the refresh frame, the first scan signal (SC1(n)) is at a high level, which is the turn-on level, the odd-numbered second scan signal (SC2_Odd(n)) is at a low level, which is the turn-on level, and the even-numbered second scan signal (SC2_Even(n)) is at a low level, which is the turn-on level. In FIG. 7, in the refresh frame, the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), are shown as waveforms containing one pulse, but are not limited thereto, and the second scan signal (SC2(n)), the odd second scan signal (SC2_Odd(n)) and the even second scan signal (SC2_Even(n)), may be waveforms containing multiple pulses.

[0197] Accordingly, during the sampling period, the second transistor (T2) is turned on, and the data voltage (Vdata) is applied to the first node (N1). Then, the third transistor (T3) is also turned on, so that the driving transistor (T1) is diode connected, and the gate electrode and drain electrode of the driving transistor (T1) are short-circuited, so that the driving transistor (T1) operates like a diode. During the sampling period, a current (Ids) flows between the source and drain of the driving transistor (T1). Since the gate electrode and drain electrode of the driving transistor (T1) are diode connected, the voltage of the second node (N2) rises due to the current flowing from the source electrode to the drain electrode until the gate-source voltage (Vgs) of the driving transistor (T1) reaches Vth. During the sampling period, the voltage of the second node (N2) is charged to a voltage (Vdata-|Vth|) corresponding to the difference between the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (T1).

[0198] And, during the sampling period of the refresh frame, the second scan signal (SC2(n)) is at a low level, which is the turn-on level, so the seventh transistor (T7) is turned on and applies a reset voltage (VAR) to the fourth node (N4). That is, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR).

[0199] Additionally, in a refresh frame, when the second scan signal (SC2(n)), specifically the odd-numbered second scan signal (SC2_Odd(n)) and the even-numbered second scan signal (SC2_Even(n)), is a waveform containing multiple pulses, the second transistor (T2) is turned on, and a data voltage (Vdata) can be applied to the first node (N1). Accordingly, even in a refresh frame, bias stress can be applied to the first node (N1), which is the source electrode of the driving transistor (T1), thereby mitigating the hysteresis of the driving transistor (T1).

[0200] And, referring to FIG. 7 and FIG. 13d, during the emission period of the refresh frame, the light-emitting signal (EM(n)) is at a low level, which is the turn-on level. Accordingly, the fifth transistor (T5) is turned on to apply a high-potential driving voltage (VDDEL) to the first node (N1). Then, the sixth transistor (T6) is also turned on to form a current path for the third node (N3) and the fourth node (N4). Eventually, the driving current (Ioled) passing through the source electrode and drain electrode of the driving transistor (T1) is applied to the organic light-emitting diode (OLED).

[0201] During the emission period, the relationship for the driving current (Ioled) flowing through the organic light-emitting diode (OLED) is as described above [Equation 1].

[0202] As seen in [Mathematical Equation 1], the threshold voltage (Vth) component of the driving transistor (DT) is eliminated from the relationship of the driving current (Ioled), which means that the driving current (Ioled) does not change even if the threshold voltage (Vth) changes in the display device according to the present specification. As seen, the display device according to the present specification can program the data voltage regardless of the amount of change in the threshold voltage (Vth) during the sampling period.

[0203] As mentioned above, the anode electrode of the organic light-emitting diode (OLED) is reset to the reset voltage (VAR) during both the stress period (On Bias Stress) of the anode reset frame and the sampling period (Sampling) of the refresh frame.

[0204] Ultimately, in an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention, the anode electrode of the organic light-emitting element (OLED) can be periodically reset across refresh frames and reset frames. Accordingly, since a continuous rise in the voltage of the anode electrode of the organic light-emitting element (OLED) caused by leakage current is prevented even at low frequency driving, the anode electrode of the organic light-emitting element (OLED) can maintain a constant voltage level. Therefore, even though the driving frequency is switched to a low frequency, changes in the brightness of the organic light-emitting display device are minimized, and image quality can be improved.

[0205] An organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention can also apply on-bias stress to a driving transistor (T1) using a high-level data voltage (Vdata). Accordingly, in order to apply on-bias stress, an organic light-emitting display device according to another embodiment (fourth embodiment) of the present invention does not require a separate stage for swinging an initialization voltage to be included in the gate driver.

[0206] Furthermore, as illustrated in FIG. 9, the first gate driver (401) positioned on the left side of the display area (A / A) and the second gate driver (402) positioned on the right side of the display area (A / A) may both include only the light emission signal stage (EM), the first scan signal stage (SC1), the odd second scan signal stage (SC2_Odd), and the even second scan signal stage (SC2_Even), and may not include the third scan signal stage.

[0207] Accordingly, the width of each of the first gate driver (401) and the second gate driver (402) can be reduced from 350 μm to 300 μm compared to the organic light-emitting display device according to another embodiment (third embodiment) of the present invention, and the width of the bezel can be further reduced, and there is no need to drive the third scan signal stage, so power consumption can also be effectively reduced.

[0208] An organic light-emitting display device according to various embodiments of the present invention can be described as follows.

[0209] To solve the problem described above, an organic light-emitting display device according to an embodiment of the present invention comprises a plurality of pixels arranged in a display panel, and each of the plurality of pixels comprises an organic light-emitting element that emits light by a driving current, a first transistor that controls the driving current and includes a source electrode which is a first node, a gate electrode which is a second node, and a drain electrode which is a third node, a second transistor that applies a data voltage to the first node, a third transistor that diode-connects the second node and the third node, a fourth transistor that applies an initialization voltage to the first transistor, a fifth transistor that applies a high-potential driving voltage to the first node, a sixth transistor that forms a current path between the driving transistor and the organic light-emitting element, a seventh transistor that applies a reset voltage to the fourth node which is the anode electrode of the organic light-emitting element, and a storage capacitor having one electrode connected to the second node and another electrode connected to a high-potential driving voltage line that transmits a high-potential driving voltage, and is driven separately by a refresh frame that programs a data voltage to the pixel and a reset frame that resets the anode electrode of the organic light-emitting element, and during the reset frame, the data voltage is at a first level By maintaining it, the bezel can be reduced without providing a separate stage for applying on-bias stress.

[0210] According to another feature of the present invention, the reset frame includes a plurality of on-bias stress periods, and during the on-bias stress period, the second transistor is turned on to apply a first level data voltage to the first node, and the seventh transistor is turned on to reset the fourth node to a reset voltage.

[0211] According to another feature of the present invention, the third transistor is an n-type oxide thin-film transistor, and the first, second, and fourth to seventh transistors may each be a p-type LTPS (Low-Temperature Polycrystalline Silicon) thin-film transistor.

[0212] According to another feature of the present invention, during a refresh frame, the initialization voltage applied to the fourth transistor may be at a second level, and during a reset frame, the initialization voltage applied to the fourth transistor may be at a first level.

[0213] According to another feature of the present invention, the third transistor and the fourth transistor are n-type oxide thin-film transistors, and the first transistor, the second transistor, and the fifth to seventh transistors may each be p-type LTPS (Low-Temperature Polycrystalline Silicon) thin-film transistors.

[0214] According to another feature of the present invention, during the refresh frame and reset frame, the initialization voltage applied to the fourth transistor may be at a second level.

[0215] According to another feature of the present invention, a first transistor comprises a source electrode connected to a first node, a drain electrode connected to a third node, and a gate electrode connected to a second node; a second transistor comprises a source electrode connected to a data line transmitting a data voltage, a drain electrode connected to a first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; a third transistor comprises a source electrode connected to a second node, a drain electrode connected to a third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; a fourth transistor comprises a source electrode connected to an initialization voltage line transmitting an initialization voltage, a drain electrode connected to a third node, and a gate electrode connected to a third scan signal line transmitting a third scan signal; a fifth transistor comprises a source electrode connected to a high-potential driving voltage line, a drain electrode connected to a first node, and a gate electrode connected to a light-emitting signal line transmitting a light-emitting signal; a sixth transistor comprises a source electrode connected to a third node, a drain electrode connected to a fourth node, and a gate electrode connected to a light-emitting signal line; and a seventh transistor comprises a reset electrode transmitting a reset voltage. It may include a source electrode connected to a voltage line, a drain electrode connected to a fourth node, and a gate electrode connected to a second scan signal line.

[0216] According to another feature of the present invention, the first transistor includes a source electrode connected to a first node, a drain electrode connected to a third node, and a gate electrode connected to a second node; the second transistor includes a source electrode connected to a data line transmitting a data voltage, a drain electrode connected to a first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor includes a source electrode connected to a second node, a drain electrode connected to a third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor includes a source electrode connected to an initialization voltage line transmitting an initialization voltage, a drain electrode connected to a third node, and a gate electrode connected to a first scan signal line of a previous stage transmitting a first scan signal of a previous stage; the fifth transistor includes a source electrode connected to a high potential driving voltage line, a drain electrode connected to a first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; the sixth transistor includes a source electrode connected to a third node, a drain electrode connected to a fourth node, and a gate electrode connected to a light emission signal line; and the seventh transistor It may include a source electrode connected to a reset voltage line that transmits a reset voltage, a drain electrode connected to a fourth node, and a gate electrode connected to a second scan signal line.

[0217] According to another feature of the present invention, a first transistor comprises a source electrode connected to a first node, a drain electrode connected to a third node, and a gate electrode connected to a second node; a second transistor comprises a source electrode connected to a data line transmitting a data voltage, a drain electrode connected to a first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; a third transistor comprises a source electrode connected to a second node, a drain electrode connected to a third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; a fourth transistor comprises a source electrode connected to an initialization voltage line transmitting an initialization voltage, a drain electrode connected to a second node, and a gate electrode connected to a third scan signal line transmitting a third scan signal; a fifth transistor comprises a source electrode connected to a high potential driving voltage line, a drain electrode connected to a first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; a sixth transistor comprises a source electrode connected to a third node, a drain electrode connected to a fourth node, and a gate electrode connected to a light emission signal line; and a seventh transistor comprises a reset electrode transmitting a reset voltage. It may include a source electrode connected to a voltage line, a drain electrode connected to a fourth node, and a gate electrode connected to a second scan signal line.

[0218] According to another feature of the present invention, the first transistor includes a source electrode connected to a first node, a drain electrode connected to a third node, and a gate electrode connected to a second node; the second transistor includes a source electrode connected to a data line transmitting a data voltage, a drain electrode connected to a first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor includes a source electrode connected to a second node, a drain electrode connected to a third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor includes a source electrode connected to an initialization voltage line transmitting an initialization voltage, a drain electrode connected to a second node, and a gate electrode connected to a first scan signal line of a previous stage transmitting a first scan signal of a previous stage; the fifth transistor includes a source electrode connected to a high potential driving voltage line, a drain electrode connected to a first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; the sixth transistor includes a source electrode connected to a third node, a drain electrode connected to a fourth node, and a gate electrode connected to a light emission signal line; and the seventh transistor It may include a source electrode connected to a reset voltage line that transmits a reset voltage, a drain electrode connected to a fourth node, and a gate electrode connected to a second scan signal line.

[0219] According to another feature of the present invention, the refresh frame is divided into an initial period, a sampling period, and an emission period, and during the initial period, the second node or the third node is initialized with an initialization voltage, and during the sampling period, the second node is charged with a voltage corresponding to the difference between the data voltage and the threshold voltage (Vth) of the first transistor, and during the emission period, a driving current flows through the organic light-emitting element so that the organic light-emitting element can emit light.

[0220] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims below, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0221] 100: Display panel 200: Timing control circuit 300: Data driver 401: 1st Gate Driver 402: 2nd Gate Driver GL1 to GLn: Gate lines DL1 to DLm: Data lines P: Pixel N / A: Non-display area A / A: Display area VDDEL: High potential driving voltage VSSEL: Low potential driving voltage Vdata: Data voltage Vini: Initialization voltage VAR: Reset voltage SC1(n): First scan signal SC1(n-1): First scan signal of the previous stage SC2(n): Second scan signal SC3(n): 3rd scan signal EM(n): light emission signal Cstg: capacitor T1: First transistor T2: Second transistor T3: Third transistor T4: 4th transistor T5: Fifth transistor T6: 6th transistor T7: The 7th transistor OLED: Organic light-emitting diode N1: Node 1 N2: Node 2 N3: 3rd node N4: 4th node

Claims

Claim 1 An organic light-emitting display device comprising: a plurality of pixels arranged on a display panel, wherein each of the plurality of pixels comprises: an organic light-emitting element that emits light by a driving current; a first transistor that controls the driving current and includes a source electrode which is a first node, a gate electrode which is a second node, and a drain electrode which is a third node; a second transistor that applies a data voltage to the first node; a third transistor located between the second node and the third node and made of an n-type oxide; a fourth transistor connected to an initialization voltage line that transmits an initialization voltage and applies the initialization voltage to the first transistor; and a seventh transistor connected to a reset voltage line that transmits a reset voltage and applies a reset voltage to the fourth node which is the anode electrode of the organic light-emitting element, wherein the gate electrode of the second transistor and the gate electrode of the seventh transistor are connected to the same scan signal line, so that the second transistor and the seventh transistor are simultaneously turned on and turned off. Claim 2 An organic light-emitting display device according to claim 1, wherein the device is driven separately into a refresh frame that programs the data voltage to the pixel and a reset frame that resets the anode electrode of the organic light-emitting element, wherein during the refresh frame, the data voltage alternates between various voltage levels, and during the reset frame, the data voltage is maintained at a first level, wherein in the refresh frame, the second transistor is turned on to apply the data voltage alternating between various voltage levels to the first node, and the seventh transistor is turned on to apply the reset voltage to the anode electrode, and in the reset frame, the second transistor is turned on to apply the data voltage maintained at the first level to the first node, and the seventh transistor is turned on to apply the reset voltage to the anode electrode. Claim 3 An organic light-emitting display device according to claim 2, wherein the reset frame includes a plurality of on-bias stress periods, and during the on-bias stress periods, the second transistor is turned on to apply the first level data voltage to the first node, and the seventh transistor is turned on to reset the fourth node to the reset voltage. Claim 4 An organic light-emitting display device according to claim 3, further comprising: a fifth transistor that applies a high-potential driving voltage to the first node; a sixth transistor that forms a current path between the first transistor and the organic light-emitting element; and a storage capacitor having one electrode connected to the second node and another electrode connected to a high-potential driving voltage line that transmits the high-potential driving voltage. Claim 5 An organic light-emitting display device according to claim 4, wherein each of the first transistor, the second transistor, and the fourth to seventh transistors is a p-type LTPS (Low-Temperature Polycrystalline Silicon) thin-film transistor. Claim 6 An organic light-emitting display device according to claim 5, wherein during the refresh frame, the initialization voltage applied to the fourth transistor is at a second level, and during the reset frame, the initialization voltage applied to the fourth transistor is at a first level. Claim 7 An organic light-emitting display device according to claim 4, wherein the fourth transistor is an n-type oxide thin-film transistor, and each of the first transistor, the second transistor, and the fifth to seventh transistors is a p-type LTPS (Low-Temperature Polycrystalline Silicon) thin-film transistor. Claim 8 An organic light-emitting display device according to claim 7, wherein the initialization voltage applied to the fourth transistor during the refresh frame and the reset frame is a second level. Claim 9 In claim 4, the first transistor includes a source electrode connected to the first node, a drain electrode connected to the third node, and a gate electrode connected to the second node; the second transistor includes a source electrode connected to a data line transmitting the data voltage, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor includes a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor includes a source electrode connected to an initialization voltage line transmitting the initialization voltage, a drain electrode connected to the third node, and a gate electrode connected to a third scan signal line transmitting a third scan signal; the fifth transistor includes a source electrode connected to the high potential driving voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; and the sixth transistor includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a light emission signal line. An organic light-emitting display device comprising a gate electrode for connection, wherein the seventh transistor comprises a source electrode connected to a reset voltage line that transmits a reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the second scan signal line. Claim 10 In claim 4, the first transistor comprises a source electrode connected to the first node, a drain electrode connected to the third node, and a gate electrode connected to the second node; the second transistor comprises a source electrode connected to a data line transmitting the data voltage, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor comprises a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor comprises a source electrode connected to an initialization voltage line transmitting the initialization voltage, a drain electrode connected to the third node, and a gate electrode connected to a first scan signal line of the previous stage transmitting a first scan signal of the previous stage; the fifth transistor comprises a source electrode connected to the high potential driving voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; and the sixth transistor comprises a source electrode connected to the third node, a drain electrode connected to the fourth node, and An organic light-emitting display device comprising a gate electrode connected to the light-emitting signal line, wherein the seventh transistor comprises a source electrode connected to a reset voltage line transmitting a reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the second scan signal line. Claim 11 In claim 4, the first transistor includes a source electrode connected to the first node, a drain electrode connected to the third node, and a gate electrode connected to the second node; the second transistor includes a source electrode connected to a data line transmitting the data voltage, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor includes a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor includes a source electrode connected to an initialization voltage line transmitting the initialization voltage, a drain electrode connected to the second node, and a gate electrode connected to a third scan signal line transmitting a third scan signal; the fifth transistor includes a source electrode connected to the high potential driving voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; and the sixth transistor includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a light emission signal line. An organic light-emitting display device comprising a gate electrode for connection, wherein the seventh transistor comprises a source electrode connected to a reset voltage line that transmits a reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the second scan signal line. Claim 12 In claim 4, the first transistor comprises a source electrode connected to the first node, a drain electrode connected to the third node, and a gate electrode connected to the second node; the second transistor comprises a source electrode connected to a data line transmitting the data voltage, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line transmitting a second scan signal; the third transistor comprises a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to a first scan signal line transmitting a first scan signal; the fourth transistor comprises a source electrode connected to an initialization voltage line transmitting the initialization voltage, a drain electrode connected to the second node, and a gate electrode connected to a first scan signal line of the previous stage transmitting a first scan signal of the previous stage; the fifth transistor comprises a source electrode connected to the high potential driving voltage line, a drain electrode connected to the first node, and a gate electrode connected to a light emission signal line transmitting a light emission signal; and the sixth transistor comprises a source electrode connected to the third node, a drain electrode connected to the fourth node, and An organic light-emitting display device comprising a gate electrode connected to the light-emitting signal line, wherein the seventh transistor comprises a source electrode connected to a reset voltage line transmitting a reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the second scan signal line. Claim 13 In claim 4, the refresh frame is divided into an initial period, a sampling period, and an emission period, and during the initial period, the second node or the third node is initialized with the initialization voltage, and during the sampling period, the second node is charged with a voltage corresponding to the difference between the data voltage and the threshold voltage (Vth) of the first transistor, and during the emission period, the driving current flows through the organic light-emitting element, so that the organic light-emitting element emits light, an organic light-emitting display device. Claim 14 An organic light-emitting display device according to claim 4, wherein during the on-bias stress period, the second transistor is turned on according to a second scan signal, and during the on-bias stress period, the second scan signal includes a plurality of pulses. Claim 15 A display panel having a plurality of pixels; and a gate driver comprising, for each of the plurality of pixels, a light emission signal stage for supplying a light emission signal, a first scan signal stage for supplying a first scan signal, and a second scan signal stage for supplying a second scan signal, wherein each of the plurality of pixels comprises: an organic light-emitting element that emits light by a driving current; a first transistor that controls the driving current and includes a source electrode as a first node, a gate electrode as a second node, and a drain electrode as a third node; a second transistor that applies a data voltage to the first node in response to the second scan signal; a third transistor that diode-connects the second node and the third node in response to the first scan signal; a fourth transistor that applies an initialization voltage to the first transistor in response to the first scan signal of the previous stage; a fifth transistor that applies a high-potential driving voltage to the first node in response to the light emission signal; and a sixth transistor that forms a current path between the first transistor and the organic light-emitting element in response to the light emission signal. An organic light-emitting display device comprising a seventh transistor that applies a reset voltage to a fourth node, which is the anode electrode of the organic light-emitting element, in response to the second scan signal, wherein the gate electrode of the second transistor and the gate electrode of the seventh transistor are connected to the same scan signal line to which the second scan signal is supplied, so that the second transistor and the seventh transistor are simultaneously turned on and turned off. Claim 16 A display panel having a plurality of pixels; and a gate driver comprising, for each of the plurality of pixels, a light emission signal stage for supplying a light emission signal, a first scan signal stage for supplying a first scan signal, a second scan signal stage for supplying a second scan signal, and a third scan signal stage for supplying a third scan signal, wherein each of the plurality of pixels comprises: an organic light-emitting element that emits light by a driving current; a first transistor that controls the driving current and includes a source electrode as a first node, a gate electrode as a second node, and a drain electrode as a third node; a second transistor that applies a data voltage to the first node in response to the second scan signal; a third transistor that diode-connects the second node and the third node in response to the first scan signal; a fourth transistor connected to an initialization voltage line that transmits an initialization voltage and applies the initialization voltage to the first transistor in response to the third scan signal; a fifth transistor that applies a high-potential driving voltage to the first node in response to the light emission signal; and a sixth transistor that forms a current path between the first transistor and the organic light-emitting element in response to the light emission signal. An organic light-emitting display device comprising a seventh transistor connected to a reset voltage line transmitting a reset voltage and applying the reset voltage to a fourth node, which is the anode electrode of the organic light-emitting element, in response to the second scan signal, wherein the gate electrode of the second transistor and the gate electrode of the seventh transistor are connected to the same scan signal line to which the second scan signal is supplied, so that the second transistor and the seventh transistor are simultaneously turned on and turned off.

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