Handling loss of power for uninterruptible power supply efficiency

Abstract

Mechanisms and methods for reducing CPU power upon interruption of power supply are described. In some embodiments, the device may include an input that receives an indicator that the supply voltage to the computer system has been interrupted. The device may include an output that provides an indicator for reducing the processor power consumption level. The device may also include a circuit that establishes an indicator for reducing the processor power level based on the indicator that the supply voltage to the computer system has been interrupted.

Description

Background Technology

[0001] Computer systems often receive power transmitted to and distributed to end users, such as residential or business customers. For practical reasons, this power is typically delivered in the form of alternating current (AC). Accordingly, end users can power the computer system using an AC source, such as an electrical outlet.

[0002] The transmission of such power may occasionally be interrupted, for example, during a power outage. If this happens, an Uninterruptible Power Supply (UPS) can provide backup power.

[0003] Meanwhile, computer systems can incorporate persistent memory technologies that use Intel Optane™ as persistent or non-volatile far memory. (Optane™ is a trademark of Intel Corporation of Santa Clara, California.) Systems containing persistent memory can experience distributed power interruption events, and subsequently, data can be protected from loss by having a UPS provide an energy source to flush modified persistent memory contents within volatile near memory to far memory. Brief explanation of the drawing

[0004] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, while the drawings are intended to aid in explanation and understanding, they are merely for assistance and should not be construed as limiting the present disclosure to the specific embodiments depicted therein. FIG. 1 illustrates a scenario of power loss notification according to some embodiments of the present disclosure. FIG. 2 illustrates a flowchart for power loss detection and subsequent processor throttling according to some embodiments of the present disclosure. FIG. 3 illustrates mechanisms for reducing processor power upon notification of power loss according to some embodiments of the present disclosure. FIG. 4 illustrates methods for reducing processor power upon notification of power loss according to some embodiments of the present disclosure. FIG. 5 illustrates a computer system or computing device having mechanisms for reducing processor power upon notification of power loss, according to some embodiments. Specific details for implementing the invention

[0005] In the following description, numerous details are discussed to provide a more thorough description of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other cases, to avoid obscuring the embodiments of the present disclosure, well-known structures and devices are depicted in block diagram form rather than in detail.

[0006] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a greater number of configuration signal paths, and / or may have arrows at one or more ends to indicate the direction of information flow. These indications are not intended to be limiting. Rather, lines are used in connection with one or more exemplary embodiments to facilitate a better understanding of the circuit or logic unit. As indicated by design requirements or preferences, any represented signal may actually include one or more signals that can move in any direction and be implemented in any suitable type of signaling scheme.

[0007] Throughout this specification and in the claims, the term “connected” means a direct electrical, mechanical, or magnetic connection between connected objects without any intermediate devices. The term “coupled” means a direct electrical, mechanical, or magnetic connection between connected objects or an indirect connection through one or more passive or active intermediate devices. The terms “circuit” or “module” may refer to one or more passive and / or active components arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of the singular expressions (“a,” “an,” and “the”) includes plural references. The meaning of “in” includes “in” and “on”.

[0008] The terms “substantially,” “close,” “approximately,” “near,” and “about” generally refer to being within + / - 10% of the target value. Unless otherwise specified, the use of ordinal adjectives “first,” “second,” and “third,” etc., to describe common objects is merely to indicate that different instances of similar objects are being referred to, and is not intended to imply that the objects thus described must exist in a given sequence in time, space, order, or any other way.

[0009] It should be understood that the terms used in this manner are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein may operate in orientations different from those exemplified or otherwise described herein.

[0010] In the detailed description and claims, terms such as "left," "right," "front," "rear," "top," "bottom," "above," and "below" are used for descriptive purposes, if any, and are not necessarily intended to describe permanent relative positions.

[0011] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases “A, B, and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0012] Additionally, the various elements of combinatorial and sequential logic discussed in this disclosure may relate to both physical structures (such as AND gates, OR gates, or XOR gates) and composite or otherwise optimized collections of devices implementing logic structures that are Boolean equivalents of the logic under discussion.

[0013] Power transmitted to and distributed to computer systems, such as alternating current (AC) power, may be interrupted. In such events, an Uninterruptible Power Supply (UPS) may act as a battery providing backup power to keep the computer system operational by supplying power to prevent sudden power loss and to protect data from loss. Computer systems utilizing a UPS (e.g., an offline UPS located outside the system chassis) or a platform battery may include client desktop systems, laptop systems, workstations, and servers.

[0014] In the case of a computer system utilizing a UPS, AC power can supply power to the UPS, and the UPS can supply power to the computer system's Power Supply Unit (PSU). The UPS itself may also have a battery that is being charged by AC power. Under normal operation, the standby UPS can supply AC power to the PSU. (In comparison, the continuous UPS can supply power to the PSU from a battery that may be continuously charged.) If a sudden power loss occurs, the standby UPS can transition to supplying power to the PSU from the battery.

[0015] Meanwhile, computer systems may also incorporate "near-field memory" (e.g., Dynamic Random Access Memory (DRAM)) which may be closer to the central processor unit (CPU) in the system's architecture, and "far-field memory" which may be further away from the CPU. In some systems, near-field memory may include volatile memory such as DRAM. In some systems, far-field memory may include non-volatile memory such as Optane™-based memory.

[0016] Computer systems may use near memory and far memory to implement a persistent memory model. In this model, near memory can be cached by DRAM, and data within near memory can be represented as "persistent." Additionally, the contents of near memory can become "dirty" (for example, their values ​​have changed relative to the values ​​stored in the corresponding parts of far memory).

[0017] In the event of AC power loss, computer systems implementing a persistent memory model may be configured to "flush" back any dirty near-field memory marked as persistent—that is, write back to far-field memory—in addition to CPU cache flushes. For example, in the event of AC power loss, the system may be configured to flush portions of the near-field memory marked as persistent—e.g., the contents of a DRAM cache or DDR (Double Data Rate) cache, which may have a relatively large capacity—to Optane™ far-field memory. Persistent memory may incorporate a large volatile cache (e.g., DDR cache) close to the processor to improve performance.

[0018] In computer systems implementing a persistent memory model, using a UPS can protect the state and / or contents of CPU caches and near-field memory, as there would otherwise be insufficient residual energy to complete a flush in the event of AC power loss. Some computing system designs that support persistent memory may incorporate a UPS rated to support platform peak power (e.g., the amount of peak power supplied to the computer system by the PSU). For example, an exemplary design incorporating a 1000-watt (W) rated PSU may incorporate a 1000-W rated UPS. The disadvantage of a "full-size" UPS (e.g., a UPS rated to continuously supply peak power per full power rating of the PSU) is that it may add additional Bill of Materials (BOM) costs to Original Equipment Manufacturers (OEMs).

[0019] However, a UPS can be temporarily "overloaded" and supply more power than its nominal rating. Modern UPS designs provide the rated continuous maximum power (P) for a window of time that can be 1 to 10 seconds. MAX It can support 125% to 150% of ). For example, in some designs, the UPS can be temporarily overloaded up to 140% of its continuous power rating. As a result, a UPS with a lower continuous-power rating can temporarily supply power to a full-size UPS.

[0020] Returning to a previous exemplary design integrating a 1000 W PSU, a UPS rated for 715 W continuous power can operate to supply 1000 W intermittently. Since smaller UPS units (e.g., UPS units with lower continuous power ratings) can be significantly cheaper than full-size UPS units, using smaller UPS units can relatively reduce BOM costs for OEMs (from approximately $7 for systems with 250 W PSUs to approximately $10 for systems with 1000 W PSUs).

[0021] Accordingly, in the various embodiments disclosed herein, for computer systems implementing persistent memory, the UPS may have a power-supply rating lower than the power-supply rating of the PSU it serves. In the event of an AC power loss event, the UPS may temporarily supply power to the PSU in excess of its own power-supply rating to match the power-supply rating of the PSU. Subsequently, in response to the AC power loss event, the power consumption of the CPU may be reduced (e.g., throttling). For example, the CPU may "fold back" or reduce its power consumption when its power level 4 (PL4) drops to a lower frequency. Throttling of the CPU's power may occur within the time window in which the UPS is temporarily supplying power in excess of its power-supply rating.

[0022] Subsequently, at the end of the time window, the throttling of the CPU's power may be completed, and the UPS may supply power according to the power-supply rating, which may then be sufficient to meet the system's power consumption, taking into account the reduced power consumption of the throttled CPU. In some embodiments, the time window may be as long as at least one cycle of the supplied AC power. For AC power supplied at 60 Hertz, the time window may be at least 16.6 milliseconds (ms). For AC power supplied at 50 Hertz, the time window may be at least 20 ms.

[0023] During and / or thereafter, the system may be properly powered to flush back any dirty near memory marked as "persistent" to far memory. The flush may be supported by a more efficient and cost-effective UPS capable of providing sufficient power to the throttled CPU. After the flush, the computer system may be shut down. When AC power is subsequently restored to the system, the CPU can be expected to remain stable because the flush will maintain the persistence of the memory.

[0024] Because a smaller UPS (e.g., a UPS with a lower continuous-power rating) may not supply the full power that a PSU can provide to the system for an infinite amount of time, the load must be folded back or reduced within a finite amount of time. This can ultimately be made possible by a combination of two methods. First, the design may include a UPS capable of supplying power exceeding its continuous-power rating for that specific amount of time following an AC loss event (e.g., until power folds back from running from the UPS's internal battery). Second, the design may provide a method to drop power below the UPS continuous-power limit (e.g., fold back) within that specific time following an AC loss event (e.g., when the voltage transitions from being supplied via AC to being supplied via the UPS's battery's DC output).

[0025] Based on the foregoing, a mathematical formula indicating the effective UPS power for a reduced-size UPS to support the mechanisms and methods discussed in this specification may be as follows:

[0026]

[0027] Here: P platform_max can be the platform's maximum power consumption (e.g., the PSU's total power rating); P dGFX_max can be the maximum power consumption of a high-power third-party graphics card. In the mathematical formula above, P dGFX_max is included for completeness. However, in consumer systems where integrated graphics are used, P dGFX_max Note that may be 0 watts. Furthermore, in some embodiments, P platform_max It may already include the power consumption of the graphics card and / or other additional components.

[0028] Mechanisms and methods for reducing CPU power upon interruption of power supply are disclosed herein. This can advantageously facilitate the flushing of persistent memory from near memory circuits (or devices) to far memory circuits (or devices) while avoiding the use of more expensive full-size UPSs to support persistent memory data durability. This can, ultimately, advantageously reduce significant BOM costs (e.g., for OEMs).

[0029] In some embodiments, persistent memory may not be flushed from near memory to far memory. These embodiments can still advantageously avoid the use of more expensive full-size UPS, which can ultimately advantageously reduce significant BOM costs.

[0030] FIG. 1 illustrates a scenario of power loss notification according to some embodiments of the present disclosure. A scenario (100) illustrating the flow of notification of AC loss to a UPS and subsequent switching from AC power includes an AC line state (112), a UPS output state (114), a power loss indicator (116), and a system load state (118).

[0031] In the preceding time (122) prior to the AC loss event (120), the AC line state (112) may have an oscillating voltage (e.g., a sinusoidal voltage). The AC line below may be coupled to a UPS, and the UPS may have a selected output from the AC line, or from a battery charged by the AC line (e.g., in a standby UPS). Thus, in the preceding time (122), the UPS may choose to pass the AC line state to the UPS output (and the UPS output state (114) may reflect the AC line state (112)). In that time frame, the system load state (118) is at maximum PPEAK It can be power consumption (132).

[0032] In the event of an AC loss event (120), the UPS may switch to selecting to pass the oscillating voltage derived from its battery to the UPS output. The process may be T which can be 10 ms or less. SWITCHOVER It can be completed after time (124). Meanwhile, the interruption of AC power in the AC loss event (120) can trigger the delivery of an AC loss message (117) on the power loss indicator (116).

[0033] Following an AC loss event (120)—for example, upon receipt of an AC loss message (117)—the computer system may initiate a foldback process to throttle CPU power consumption (and, therefore, power consumption of the computer system). Additionally, T, which may be 20 ms or less. FOLDBACK After time (126), the total load on the UPS is P PEAK From power consumption (132) P FOLDBACK It can be folded back (or throttled) due to power consumption (138).

[0034] Therefore, T FOLDBACK In a subsequent time (128) after time (126), the UPS may choose to pass the oscillating voltage derived from its battery to the UPS output. In that time frame, the power consumption of the computer system is at maximum P FOLDBACK It may be power consumption (138).

[0035] In some embodiments, at the preceding time (122), the permissible UPS output power may not be limited to the same maximum continuous power as when on the DC phase (e.g., when on the UPS battery) when on the AC phase. For example, when on the AC phase, the output power may be limited only by the wires from the AC input to the output outlet. In some embodiments, at the subsequent time (128), P FOLDBACK Power consumption (138) may be less than the maximum allowable continuous power when on the battery. For some embodiments, the PSU supplying the system load may be operable to maintain its output within the regulation even if one full cycle of AC power is lost for at least 20 ms to support, for example, 50 Hz AC. (Fig. 1 illustrates an alternating AC line state (112) and UPS output state (114) at 50 Hz, but in some embodiments, the AC line state (112) and / or UPS output state (114) may alternate at a different frequency).

[0036] Off-the-shelf UPS devices can be hosted on a computer system via a Universal Serial Bus (USB) connection and can support Human Interface Device (HID) interfaces and drivers in an operating system environment. In some embodiments, the AC loss message may be a USB message (e.g., a USB message associated with the UPS as an HID). Thus, using a USB-based UPS as an example, the detection of an AC power loss event can be communicated to the computer system via an inbox HID miniport driver.

[0037] In some embodiments, a software mechanism may notify a power agent of a computer system (e.g., a power controller or P-unit that can be executed by pCode firmware) to lower processor frequencies and / or core frequencies further in the event of an AC loss event. An exemplary software flow for initiating CPU throttling may be described as follows:

[0038]

[0039] When the AC loss indication is transmitted to the power agent, it can lower PL4. Additionally, in some embodiments, a warning message may be displayed to notify the user of the AC loss.

[0040] Off-the-shelf USB-based UPS devices can comply with USB HID specifications and, accordingly, support various types of communication to an operating system (OS), for example, via USB HID messaging. Such messaging may include an "AC present" indicator, a "battery present" indicator, a "battery charge" and / or "battery discharge" indicator, a "battery full charge capacity" and / or "battery remaining capacity" indicator, and / or a "shutdown imminent" indicator.

[0041] FIG. 2 illustrates a flowchart for power loss detection and subsequent processor throttling according to some embodiments of the present disclosure. The flow (200) may include a UPS part (210), an OS part (220), a power agent part (230), and a CPU part (240).

[0042] In the UPS section (210), the UPS for the computer system can detect an AC loss event. In the OS section (220), the UPS can communicate the AC loss event to the OS of the computer system. For example, in the first OS section (221), a USB HID message indicating an AC loss event can be communicated to the client driver of the OS. In the second OS section (222), the client driver can check the AC loss event for the battery driver of the OS. Then, in the third OS section (223), the battery driver can sequentially communicate the AC loss event to the power engine plug-in driver of the OS.

[0043] In the power agent section (230), the OS can communicate an AC loss event to the power agent (230) of the computer system (e.g., a power controller or P-unit), and the power agent can then initiate flushing dirty persistent near-field memory contents to far-field memory. In the CPU section (240), the power agent can throttle processor power (e.g. by throttling the processor frequency) and thereby reduce the CPU load on the UPS.

[0044] FIG. 3 illustrates mechanisms for reducing processor power upon notification of power loss according to some embodiments of the present disclosure. The design (300) may include a UPS (310) and a computer system (320). Although the UPS (310) is depicted as being outside the computer system (320), in some embodiments it may be located within the computer system (320).

[0045] The computer system (320) may include AC loss handling circuitry (330), one or more voltage regulator devices (342), one or more processors (344), one or more near-field memory circuits (346), and one or more far-field memory circuits (348). The AC loss handling circuitry (330) may have an input (e.g., a USB interface) that receives an indicator of power loss and an output that provides an indicator for reducing the processor power consumption level. In some embodiments, the AC loss handling circuitry may be part of a P-unit or a power controller. In some embodiments, signaling may be received from a UPS (310) on an interface and processed to generate an input to the AC loss handling circuitry (330).

[0046] The regulator devices (342) may include a PSU. In some embodiments, the regulator devices (342) may include a voltage regulator module (e.g., on the motherboard, or within the same package or die as the processor). In some embodiments, the AC loss handling circuit (330) may indicate a reduction in the processor power consumption level to the regulator devices (342). In some embodiments, the AC loss handling circuit (330) may indicate a reduction in the processor power consumption level to the processors (344).

[0047] Processors (344) may include a memory controller circuit capable of interfacing with near-field memory circuits (346) and / or far-field memory circuits (348). In some embodiments, the memory controller circuit may be integrated with the processors (344) at the package level or die level, and in other embodiments, the memory controller circuit may be integrated with the processors (344) outside the package level or die level. In some embodiments, the near-field memory circuits (346) may be coupled to the far-field memory circuits (348) and communicate with them.

[0048] In some embodiments, an indicator that the supply voltage has been interrupted may be accompanied by an indicator or its assertion that dirty near-field memory content (e.g., the content of near-field memory circuits (346)) indicated as "continuous" must be flushed to far-field memory (i.e., far-field memory circuits (348)). In other embodiments, flushing the near-field memory content to far-field memory may not occur.

[0049] Accordingly, in various embodiments, a computer system (such as the computer system (300)) may include a device (e.g., an AC loss handling circuit (330)) having an input that receives an indicator that the supply voltage to the system has been interrupted, and an output that provides an indicator for reducing the processor power consumption level. The device may also have a circuit that establishes an indicator for reducing the processor power level based on the indicator that the supply voltage to the system has been interrupted.

[0050] In various embodiments, the indicator that the supply voltage to the system has been interrupted may include an AC loss message. In some embodiments, the supply voltage may be an AC voltage. In some embodiments, the indicator that the supply voltage to the system has been interrupted may include an indicator that the supply voltage has dropped to a no-voltage level.

[0051] For some embodiments, an indicator for reducing the processor power consumption level may include an indicator for throttling the processor frequency. In some embodiments, an indicator for reducing the processor power consumption level may include an indicator for flushing at least a portion of the contents of the first memory to the second memory. In various embodiments, the first memory may include a near memory (e.g., DRAM or DDR cache device), the second memory may include a far memory (e.g., Optane™ memory device), and either or both may include a persistent memory.

[0052] In some embodiments, the supply voltage may correspond to a power of a first magnitude (e.g., an AC voltage corresponding to a power of a first magnitude, such as an RMS (root-mean-square) magnitude). The UPS supplies the system with a first magnitude (e.g., P) for a predetermined time length following an indicator that the supply voltage to the system has been interrupted. PEAK The UPS can supply a voltage having power of a magnitude (magnitude of power consumption (132)) and, following a predetermined time length, supply a second magnitude (e.g., P) to the system FOLDBACK A voltage having power of size (size of power consumption (138)) can be supplied, and the first size is larger than the second size.

[0053] In some embodiments, the first size may be at least 40 percent larger than the second size. For some embodiments, the predetermined time length may be 20 milliseconds or less.

[0054] Alternatively, in various embodiments, a computer system (such as the computer system (300)) may include an input having a first indicator that the AC voltage supplied to the system has stopped (e.g., an AC loss handling circuit (330)), and an output providing a second indicator for flushing at least a portion of the contents of the first memory to the second memory. The device may also have a circuit for establishing the second indicator based on the first indicator.

[0055] In some embodiments, the first indicator may include an AC loss message (e.g., based on an AC loss detection event notified to the UPS via USB). In some embodiments, the second indicator may include at least one of an indicator for reducing the processor power consumption level or an indicator for throttling the processor frequency.

[0056] In various embodiments, the first memory may include a near memory (e.g., a DRAM or DDR cache device), the second memory may include a far memory (e.g., an Optane™ memory device), and either or both may include a persistent memory.

[0057] In some embodiments, the AC voltage supplied to the system may correspond to a first magnitude of power (such as an RMS magnitude). The UPS may supply a voltage having a first magnitude of power to the system for a predetermined time length following an indicator that the supply voltage to the system has been interrupted, and the UPS may supply a voltage having a second magnitude of power to the system following a predetermined time length, wherein the first magnitude is greater than the second magnitude.

[0058] In some embodiments, the first size may be at least 40 percent larger than the second size. For some embodiments, the predetermined time length may be 20 milliseconds or less.

[0059] FIG. 4 illustrates methods for reducing processor power upon notification of power loss according to some embodiments of the present disclosure. The method (400) may include receiving (410), providing (420), and establishing (430). In receiving (410), an indicator that the supply voltage to the computer system has been interrupted may be received. In providing (420), an indicator for reducing the processor power consumption level may be provided (e.g., to one or more voltage regulators and / or one or more processors). In establishing (430), an indicator for reducing the processor power level may be established based on the indicator that the supply voltage to the computer system has been interrupted.

[0060] In some embodiments, the supply voltage may be an AC voltage. An indicator that the supply voltage to the computer system has been interrupted may include an AC loss message, and an indicator that the supply voltage to the computer system has been interrupted may include an indicator that the supply voltage has dropped to a no-voltage level.

[0061] For some embodiments, an indicator for reducing the processor power consumption level may include an indicator for throttling the processor frequency. For some embodiments, an indicator for reducing the processor power consumption level may include an indicator for flushing at least a portion of the contents of the first memory to the second memory. The first memory may include a near memory (e.g., DRAM or DDR cache device), and the second memory may include a far memory (e.g., Optane™ memory device), and either or both may include a persistent memory.

[0062] In some embodiments, the supply voltage may correspond to a first magnitude of power. The UPS may be operable to supply a voltage having a first magnitude of power to the computer system for a predetermined time length following an indication that the supply voltage to the computer system has been interrupted, and the UPS may be operable to supply a voltage having a second magnitude of power to the computer system following a predetermined time length, wherein the first magnitude is greater than the second magnitude. For some embodiments, the first magnitude may be at least 40 percent greater than the second magnitude. In some embodiments, the predetermined time length may be 20 milliseconds or less.

[0063] The actions in the flowchart with reference to FIG. 4 are depicted in a specific order, but the order of the actions may be modified. Accordingly, the illustrated embodiments may be performed in different orders, and some actions may be performed in parallel. Some of the actions and / or operations listed in FIG. 4 are optional depending on the specific embodiments. The numbering of the presented actions is for clarity and is not intended to define the order in which various actions must occur. Additionally, operations from various flows may be utilized in various combinations.

[0064] In some embodiments, the device may include means for performing various actions and / or operations of the methods of FIG. 4.

[0065] Additionally, in some embodiments, the machine-readable storage medium may have executable instructions that, when executed, cause one or more processors to perform an operation including the method of FIG. 4. Such a machine-readable storage medium may include any of various storage media such as magnetic storage media (e.g., magnetic tapes or magnetic disks), optical storage media (e.g., optical disks), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash memory-based storage media), or any other type of (tangible) storage medium or non-transient storage medium.

[0066] FIG. 5 illustrates a computer system or computing device having mechanisms for reducing processor power upon notification of power loss, according to some embodiments. It should be noted that elements of FIG. 5 having the same reference numbers (or names) as elements of any other figure may operate or function in any manner similar to that described, but are not limited thereto.

[0067] In some embodiments, the device (500) may include a suitable computing device such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, etc. It will be understood that certain components are generally illustrated, and not all components of such devices are illustrated in the device (500). In various embodiments, the device (500) may include a computer system (320).

[0068] In some embodiments, the device (500) may include a System-on-Chip (SoC) (501). Exemplary boundaries of the SoC (501) are illustrated using dashed lines in FIG. 5, and some exemplary components are illustrated as being included within the SoC (501). However, the SoC (501) may include any suitable components of the device (500).

[0069] In some embodiments, the device (500) may include a processor (504). The processor (504) may include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. Processing operations performed by the processor (504) may include the execution of an operating system or operating platform in which applications and / or device functions are executed in turn. Processing operations may include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the computing device (500) to another device, and / or similar ones. Processing operations may also include operations related to audio I / O and / or display I / O.

[0070] In some embodiments, the processor (504) may include a plurality of processing cores (508a, 508b, and 508c) (also referred to as cores). Although three cores (508a, 508b, and 508c) are illustrated in FIG. 5, the processor (504) may include any suitable number of cores, for example, tens of cores or even hundreds of cores. The cores (508a, 508b, and / or 508c) may be implemented on a single integrated circuit (IC) chip. Furthermore, the chip may include one or more shared and / or private caches, buses or interconnects, graphics and / or memory controllers, and / or other components. In various embodiments, the processor (504) may include one or more processors (344).

[0071] In some embodiments, the processor (504) may include a cache (506). In some embodiments, sections of the cache (506) may be dedicated to individual cores (e.g., a first section of the cache (506) may be dedicated to core (508a), a second section of the cache (506) may be dedicated to core (508b), and so on). In some embodiments, one or more sections of the cache (506) may be shared among two or more of the cores. The cache (506) may be divided into different levels, e.g., a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0072] In some embodiments, the cores (508a, 508b, and / or 508c) may include a fetch unit for fetching instructions (including instructions having conditional branches) for execution by the core. The instructions may be fetched from memory (530) (which may include any of various storage devices). The cores (508a, 508b, and / or 508c) may also include a decode unit for decoding the fetched instructions. In some embodiments, the decode unit may decode the fetched instructions into a plurality of micro-operations. The cores (508a, 508b, and / or 508c) may also include a schedule unit for performing various operations associated with storing the decoded instructions. In some embodiments, the scheduling unit may hold data from the decode unit until instructions are ready to be dispatched, for example, until all source values ​​of the decoded instructions become available. In some embodiments, the scheduling unit may schedule and / or issue (or dispatch) the decoded instructions to the execution unit for execution.

[0073] The execution unit can execute dispatched instructions after they have been decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In some embodiments, the execution unit may include more than one type of execution unit (e.g., an imaging compute unit, a graphics compute unit, a general-purpose compute unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and / or division, and may include one or more arithmetic logic units (ALUs). In some embodiments, a co-processor (not shown) may perform various arithmetic operations together with the execution unit.

[0074] Additionally, the execution unit may execute instructions out of order. Accordingly, in some embodiments, the cores (508a, 508b, and / or 508c) may include an out-of-order processor core. The cores (508a, 508b, and / or 508c) may also include a retirement unit. The retirement unit may retire executed instructions after the executed instructions have been committed. For some embodiments, the retirement of executed instructions may result in the processor state being committed from the execution of the instructions, the physical registers used by the instructions being deallocated, etc. The cores (508a, 508b, and / or 508c) may also include a bus unit that enables communication between the components of the core and other components through one or more buses. The cores (508a, 508b, and / or 508c) may additionally include one or more registers that store data accessed by various components of the core (such as values ​​associated with assigned app priorities and / or subsystem states (modes)).

[0075] In some embodiments, the device (500) may include one or more connectivity circuitries (531) that may include hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks, etc.) to enable the device (500) to communicate with external devices. The device (500) may be isolated from external devices such as other computing devices, wireless access points or base stations, etc.

[0076] In some embodiments, the connectivity circuits (531) may include circuits that are oriented toward a number of different types of connectivity (e.g., connectivity protocols). To generalize, the connectivity circuits (531) may include cellular connectivity circuits, wireless connectivity circuits, etc. The cellular connectivity circuits of the connectivity circuits (531) generally refer to cellular network connectivity provided by wireless carriers, for example, through GSM (global system for mobile communications) or its variations or derivatives, through CDMA (code division multiple access) or its variations or derivatives, through TDM (time division multiplexing) or its variations or derivatives, through 3GPP (3rd Generation Partnership Project) UMTS (Universal Mobile Telecommunications Systems) system or its variations or derivatives, through 3GPP LTE (Long-Term Evolution) system or its variations or derivatives, through 3GPP LTE-A (LTE-Advanced) system or its variations or derivatives, through 5G (Fifth Generation) wireless system or its variations or derivatives, through 5G mobile network system or its variations or derivatives, through 5G NR (New Radio) system or its variations or derivatives, or through other cellular service standards. It is possible.

[0077] The wireless connectivity circuits (or wireless interfaces) of the connectivity circuits (531) may generally refer to non-cellular wireless connectivity and may include personal area networks (e.g., Bluetooth, Near Field, etc.), local area networks (e.g., Wi-Fi), wide area networks (e.g., WiMAX), and / or other wireless communications. For some embodiments, the connectivity circuits (531) may include network interfaces, such as wired or wireless interfaces, so that the system embodiment can be integrated into a wireless device (e.g., a cell phone or personal digital assistant).

[0078] In some embodiments, the device (500) may include a control hub (532) that may represent hardware devices and / or software components involved in interacting with one or more I / O devices. The control hub (532) may be a chipset, a platform control hub (PCH), and / or similar. Through the control hub (532), the processor (504) may communicate with a display (522) (or one or more displays), one or more peripheral devices (524), one or more storage devices (528), one or more other external devices (529), etc.

[0079] The control hub (532) may provide one or more connection points for additional devices that connect to the device (500) to which a user can interact with the system. In some embodiments, devices that may be attached to the device (500) (e.g., external devices (529)) may include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, and / or other I / O devices for use with specific applications, such as card readers or other devices.

[0080] As mentioned above, the control hub (532) can interact with audio devices, a display (522), etc. In some embodiments, input through a microphone or other audio device may provide input or commands for one or more applications or functions of the device (500). Additionally, audio output may be provided instead of or in addition to the display output. In some embodiments, if the display (522) includes a touch screen, the display (522) may also function as an input device that can be managed at least partially by the control hub (532). Additional buttons or switches may also be present on the computing device (500) to provide I / O functions managed by the control hub (532). In some embodiments, the control hub (532) may manage devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the device (500). The input can be part of direct user interaction and can also provide environmental input to the system to influence actions (e.g., filtering for noise, adjusting displays for brightness detection, applying a flash to a camera, or other features).

[0081] In some embodiments, the control hub (532) can be connected to various devices using any suitable communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, HDMI (High Definition Multimedia Interface), Firewire, etc.

[0082] In some embodiments, the display (522) may represent hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual and / or tactile display for a user to interact with the device (500). The display (522) may include a display interface, a display screen, and / or a hardware device used to provide the display to the user. In some embodiments, the display (522) may include a touch screen (or touchpad) device that provides both output and input to the user. In some embodiments, the display (522) may communicate directly with the processor (504). The display (522) may be an internal display device (e.g., in a mobile electronic device or a laptop device) or an external display device attached via a display interface (e.g., DisplayPort, etc.). For some embodiments, the display (522) may be a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0083] In some embodiments, in addition to (or instead of) the processor (504), the device (500) may include a graphics processing unit (GPU) (not shown in the drawing). The GPU may include one or more graphics processing cores capable of controlling one or more modes of displaying content on the display (522).

[0084] In some embodiments, the control hub (532) may include software components (e.g., drivers, protocol stacks, etc.) for making peripheral device connections to, for example, peripheral devices (524), as well as hardware interfaces and connectors.

[0085] It will be understood that the device (500) may not only be a peripheral device for other computing devices but may also have peripheral devices connected thereto. The device (500) may have a "docking" connector for connecting to other computing devices for purposes such as managing content on the device (500) (e.g., downloading and / or uploading, modifying, and / or synchronizing content). Additionally, the docking connector may allow the device (500) to connect to specific peripheral devices (e.g., audiovisual systems and / or other systems) that enable the computing device (500) to control content output.

[0086] In addition to a proprietary docking connector or other proprietary connection hardware, the device (500) may make peripheral connections through common or standard-based connectors. These connectors may include a Universal Serial Bus (USB) connector (which may include any of a number of different hardware interfaces), a DisplayPort connector or MiniDisplayPort (MDP) connector, a High Definition Multimedia Interface (HDMI) connector, a FireWire connector, or other types of connectors.

[0087] In some embodiments, the connectivity circuits (531) may be coupled to the control hub (532) in addition to being coupled directly to, for example, the processor (504), or instead thereof. In some embodiments, the display (522) may be coupled to the control hub (532) in addition to being coupled directly to, for example, the processor (504), or instead thereof.

[0088] In some embodiments, the device (500) may include memory (530) which can be coupled to the processor (504) via a memory interface (534). The memory (530) may include memory devices for storing information in the device (500). The memory devices may include non-volatile memory devices (the state may not change when power to the memory device is interrupted) and / or volatile memory devices (the state may be indeterminate or lost when power to the memory device is interrupted). The memory (530) may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other memory devices (e.g., a memory device having performance suitable for serving as process memory). In some embodiments, memory (530) may operate as system memory for the device (500) to store data and instructions for use when one or more processors (e.g., processor (504)) execute an application or process. Memory (530) may store application data, user data, music, photos, documents, or other data, and system data (whether long-term or temporary) related to the execution of applications and functions of the device (500).

[0089] Various embodiments and elements of examples may also be provided as a machine-readable medium (e.g., memory (530)) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). The machine-readable medium (e.g., memory (530)) may include, but is not limited to, flash memory, optical discs, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. Some embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that can be transmitted by data signals from a remote computer (e.g., server) to a requesting computer (e.g., client) via a communication link (e.g., modem or network connection). In various embodiments, the cache (506) and / or memory (530) may include one or more near memory circuits (346) and / or one or more far memory circuits (348).

[0090] In some embodiments, one or more measuring circuits and / or sensors of the device (500) may include, for example, temperature measuring circuits (540) for measuring the temperature of various components of the device (500). In some embodiments, the temperature measuring circuits (540) may be embedded in, coupled with, or attached to various components where the temperature is measured and monitored. For some embodiments, the temperature measuring circuits (540) may measure the temperatures of one or more of (or within) cores (508a, 508b, 508c), a voltage regulator (514), memory (530), the motherboard of the SoC (501), and / or any other suitable component of the device (500).

[0091] In some embodiments, the measurement circuits and / or sensors of the device (500) may include one or more power measurement circuits (542) for measuring, for example, power consumed by one or more components of the device (500). In some embodiments, the power measurement circuits (542) may measure power, voltage, and / or current. In some embodiments, the power measurement circuits (542) may be embedded, coupled, or attached to various components where power, voltage, and / or current consumption is measured and monitored. In some embodiments, the power measurement circuits (542) may measure: power, voltage, and / or current supplied by a voltage regulator (514) (which may include one or more voltage regulators); power supplied to the SoC (501); power supplied to the device (500); power consumed by the processor (504) (or any other component) of the device (500); and so on.

[0092] In some embodiments, the device (500) may include one or more voltage regulator circuits within the voltage regulator (514). The voltage regulator (514) may generate signals at appropriate voltage levels, and these signals may be supplied to operate any appropriate components of the device (500). For example, the voltage regulator (514) is illustrated as supplying one or more signals (e.g., voltage signals) to the processor (504) of the device (500). In some embodiments, the voltage regulator (514) may receive one or more Voltage Identification (VID) signals and generate voltage signals (e.g., to the processor (504)) at appropriate levels based on the VID signals. Various types of VRs may be utilized for the voltage regulator (514). In some embodiments, the voltage regulator (514) may include a "buck" voltage regulator, a "boost" voltage regulator, a combination of buck and boost voltage regulators, low dropout (LDO) regulators, switching DC-DC regulators, etc. Buck voltage regulators may be used in power delivery applications where the input voltage is converted to the output voltage at a ratio less than 1. Boost voltage regulators may be used in power delivery applications where the input voltage is converted to the output voltage at a ratio greater than 1. In some embodiments, each processor core may have its own voltage regulator, which can be controlled by a Power Control Unit (PCU) (510a), a PCU (510b), and / or a Power Management Integrated Circuit (PMIC) (512). In some embodiments, each core may have a network of distributed LDOs to provide efficient control for power management.LDOs can be digital, analog, or a combination of digital or analog LDOs.

[0093] In some embodiments, the device (500) may include one or more clock generator circuits within the clock generator (516). The clock generator (516) generates clock signals at appropriate frequency levels, and these clock signals may be supplied to any appropriate components of the device (500). For example, the clock generator (516) is illustrated as supplying clock signals to the processor (504) of the device (500). In some embodiments, the clock generator (516) may receive one or more Frequency Identification (FID) signals and, based on the FID signals, generate clock signals at appropriate frequencies.

[0094] In some embodiments, the device (500) may include a battery (518) that supplies power to various components of the device (500). For example, the battery (518) is illustrated as supplying power to the processor (504). Although not illustrated in the drawings, the device (500) may include a charging circuit for recharging the battery based on AC power received, for example, from an AC adapter.

[0095] In some embodiments, the device (500) may include a PCU (510a) and / or a PCU (510b) (which may also be referred to as a Power Management Unit (PMU), power controller, etc.). In some embodiments, the PCU (510a) may be implemented by one or more of the cores (508a, 508b, and / or 508c), as symbolically illustrated using a dashed box labeled PCU (510a). In some embodiments, the PCU (510b) may be implemented outside the cores, as symbolically illustrated using a dashed box labeled PCU (510b). The PCU (510a) and / or the PCU (510b) may implement various power management operations for the device (500). The PCU (510a) and / or PCU (510b) may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for the device (500). In some embodiments, the PCU (510a) and / or PCU (510b) may include an AC loss handling circuit (330).

[0096] In some embodiments, the device (500) may include a PMIC (512) to implement various power management operations for the device (500), for example. In some embodiments, the PMIC (512) may be a Reconfigurable Power Management IC (RPMIC) and / or an Intel® Mobile Voltage Positioning (IMVP). In some embodiments, the PMIC may be located within an IC chip separate from the processor (504). The PMIC may implement various power management operations for the device (500). The PMIC (512) may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for the device (500).

[0097] In some embodiments, the device (500) may include a PCU (510a), a PCU (510b), and / or a PMIC (512). In some embodiments, any one of the PCU (510a), the PCU (510b), and / or the PMIC (512) may not be present in the device (500), and thus these components are illustrated using dashed lines.

[0098] Various power management operations of the device (500) may be performed by the PCU (510a), PCU (510b), and PMIC (512), or by a combination thereof. In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may select a power state (e.g., P-state) for various components of the device (500). In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may select a power state for various components of the device (500) (e.g., according to the ACPI (Advanced Configuration and Power Interface) specification). In some embodiments, for example, the PCU (510a), PCU (510b), and / or PMIC (512) can cause various components of the device (500) to transition to a sleep state, an active state, an appropriate C state (e.g., a C0 state according to ACPI specifications, or other appropriate C states), etc.

[0099] In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may control the voltage output by the voltage regulator (514) and / or the frequency of the clock signal output by the clock generator, for example, by outputting VID signals and / or FID signals, respectively. In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may control features related to battery power usage, charging of the battery (518), and power saving operation.

[0100] The clock generator (516) may include a phase locked loop (PLL), a frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor (504) may have its own clock source. Thus, each core may operate at a frequency independent of the operating frequency of other cores. In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may perform adaptive or dynamic frequency scaling or adjustment. For some embodiments, the clock frequency of a processor core may be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) can determine the operating conditions of each core of the processor, and when the PCU (510a), PCU (510b), and / or PMIC (512) determine that the core is operating below a target performance level, the core clocking source (e.g., the core's PLL) can opportunistically adjust the frequency and / or power supply voltage of the core without lock loss. In some embodiments, if a core is drawing current from a power supply rail that is less than the total current allocated to that core (or processor (504)), the PCU (510a), PCU (510b) and / or PMIC (512) may temporarily increase the power drawing to that core (or processor (504)) by, for example, increasing the clock frequency and / or power supply voltage level, so that the core or processor (504) can perform at a higher performance level. Thus, in various embodiments, the voltage and / or frequency may be temporarily increased to the processor (504) without compromising product reliability.

[0101] In some embodiments, the PCU (510a), PCU (510b), and / or PMIC (512) may perform power management operations based at least partially on receiving, for example, measurements from power measurement circuits (542), temperature measurement circuits (540), the charge level of the battery (518), and / or any other suitable information that may be used for power management. For this purpose, the PMIC (512) may be communicably coupled to one or more sensors to detect and / or detect various values ​​of one or more factors and / or variations thereof that affect the power and / or thermal behavior of the system or platform. Examples of one or more factors may include current, voltage droop, temperature, operating frequency, operating voltage, power consumption, core-to-core communication activity, etc. Sensors for one or more of these factors may be provided in physical proximity (and / or thermally contacted or thermally coupled thereto) to one or more components or logic / IP blocks of a computing system (e.g., a computing system of device (500)). Additionally, in some embodiments, the sensor(s) may be directly coupled to the PCU (510a), PCU (510b), and / or PMIC (512) to enable the PCU (510a), PCU (510b), and / or PMIC (512) to manage processor core energy based at least partially on value(s) detected by one or more of the sensors.

[0102] An exemplary software stack of the device (500) is also illustrated (although not all elements of the software stack are illustrated). In various embodiments, the processor (504) may execute application programs (550), an operating system (OS) (552), one or more power management (PM) specific application programs (e.g., generally referred to as PM applications (558)), and / or similar ones. PM applications (558) may also be executed by a PCU (510a), a PCU (510b), and / or a PMIC (512). The OS (552) may also include one or more PM applications (556a, 556b, 556c), etc. The OS (552) may also include various drivers (554a, 554b, 554c), etc., some of which may be specific for power management purposes. In some embodiments, the device (500) may additionally include a Basic Input / Output System (BIOS) (520). The BIOS (520) may communicate with the OS (552) (e.g., through one or more of the drivers (554a, 554b, 554c, etc.), communicate with the processor (504), and so on.

[0103] In various embodiments, one or more of PM applications (558), drivers included in the OS (552) (e.g., drivers (554a, 554b, 554c, etc.)), PM applications included in the OS (552) (e.g., PM applications (556a, 556b, 556c, etc.)), BIOS (520), etc. may be used to implement power management specific tasks. For example, these components may be used to control the voltage and / or frequency of various components of the device (500), to control the wake-up state, sleep state, and / or any other appropriate power state of various components of the device (500), to control battery power usage, to control the charging of the battery (518), to control features related to power saving operations, etc.

[0104] In this specification, references to “examples,” “one example,” “some examples,” or “other examples” mean that a specific feature, structure, or characteristic described in relation to the examples is included in at least some examples, not necessarily all examples. Various appearances of “examples,” “one example,” or “some examples” do not necessarily refer to the same examples. Where the specification states that a component, feature, structure, or characteristic “may, might,” or “could” be included, it is not required that the specific component, feature, structure, or characteristic be included. Where the specification or claims refer to a singular element (“a” or “an”), it does not mean that only one of the elements exists. Where the specification or claims refer to an “additional” element, it does not exclude the existence of more than one additional element.

[0105] Furthermore, specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0106] Although the present disclosure has been described with specific embodiments, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the embodiments discussed. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications, and variations, falling within the broad scope of the appended claims.

[0107] Additionally, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be illustrated in the presented drawings to simplify description and discussion and to avoid obscuring the disclosure. Additionally, arrangements may be illustrated in block diagram form to avoid obscuring the disclosure, and may be illustrated with consideration of the fact that specific details regarding the implementation of such block diagram arrangements are largely dependent on the platform on which the disclosure is to be implemented (i.e., such specific details must be good within the sight of a person skilled in the art). Although specific details (e.g., circuits) are provided to describe exemplary embodiments of the disclosure, it should be apparent to a person skilled in the art that the disclosure may be practiced without such specific details or with modifications to such specific details. Accordingly, the description should be considered exemplary rather than restrictive.

[0108] The following examples relate to additional embodiments. Specific details in these examples may be used anywhere in one or more embodiments. All optional features of the device described herein may also be implemented in relation to a method or process.

[0109] Example 1 provides a device, the device comprising: an input receiving an indicator that the supply voltage to the computer system has been interrupted; an output providing an indicator for reducing the processor power consumption level; and a circuit for establishing an indicator for reducing the processor power level based on the indicator that the supply voltage to the computer system has been interrupted.

[0110] In Example 2, in the device of Example 1, the supply voltage is an AC voltage.

[0111] In Example 3, in any one of the devices of Examples 1 to 2, the indicator that the supply voltage to the computer system has been interrupted includes an AC loss message.

[0112] In Example 4, in any one of the devices of Examples 1 to 3, the indicator that the supply voltage to the computer system has been interrupted includes an indicator that the supply voltage has dropped to a no-voltage level.

[0113] In Example 5, in any one of the devices of Examples 1 to 4, the indicator for reducing the processor power consumption level includes an indicator for throttling the processor frequency.

[0114] In Example 6, in any one of the devices of Examples 1 to 5, the indicator for reducing the processor power consumption level includes an indicator for flushing at least a portion of the contents of the first memory to the second memory.

[0115] In Example 7, in the device of Example 6, the first memory is a persistent memory.

[0116] In Example 8, in any one of Examples 1 to 7, the supply voltage corresponds to a first magnitude of power; the UPS supplies a voltage having the first magnitude of power to the computer system for a predetermined time length following an indicator that the supply voltage to the computer system has been interrupted; and the UPS supplies a voltage having a second magnitude of power to the computer system following the predetermined time length, wherein the first magnitude is greater than the second magnitude.

[0117] In Example 9, in the device of Example 8, the first size is at least 40 percent larger than the second size.

[0118] In Example 10, in any one of the devices of Examples 8 to 9, the predetermined time length is 20 milliseconds or less.

[0119] Example 11 provides a device, the device comprising: an input receiving a first indicator that the AC voltage supplied to the system has stopped; an output providing a second indicator for flushing at least a portion of the contents of a first memory to a second memory; and a circuit for establishing the second indicator based on the first indicator.

[0120] In Example 12, in the device of Example 11, the first indicator includes an AC loss message.

[0121] In Example 13, in any one of the devices of Examples 11 to 12, the second indicator comprises: an indicator for reducing the processor power consumption level, or an indicator for throttling the processor frequency.

[0122] In Example 14, in any one of the devices from Example 11 to Example 13, the first memory is a persistent memory.

[0123] In Example 15, in any one of the devices of Examples 11 to 14, the AC voltage supplied to the system corresponds to a first magnitude of power; the UPS supplies the system with a voltage having the first magnitude of power for a predetermined time length following an indicator that the supply voltage to the system has been interrupted; and the UPS supplies the system with a voltage having a second magnitude of power following the predetermined time length, wherein the first magnitude is greater than the second magnitude.

[0124] In Example 16, in the device of Example 15, the first size is at least 40 percent larger than the second size.

[0125] In Example 17, in any one of the devices of Examples 15 to 16, the predetermined time length is 20 milliseconds or less.

[0126] Example 18 provides a system comprising a memory, a processor coupled to said memory, a UPS, a wireless interface that enables said processor to communicate with another device, and a component, said component comprising: an input receiving an indicator that an AC voltage supplied to said system has been interrupted; an output providing an indicator to said processor for reducing a processor power consumption level; and a circuit for establishing an indicator for reducing a processor power level based on the indicator that an AC voltage for said system has been interrupted.

[0127] In Example 19, in the system of Example 18, an indicator that the supply voltage for the system has been interrupted includes at least one of an indicator that the supply voltage has dropped to a no-voltage level, or an AC loss message; and an indicator for reducing the processor power consumption level includes at least one of an indicator for throttling the processor frequency, or an indicator for flushing at least a portion of the contents of the memory to additional memory; and the first memory is a persistent memory.

[0128] In Example 20, in any one of the systems of Examples 18 to 19, the AC voltage supplied to the system corresponds to a first magnitude of power; the UPS supplies the system with a voltage having the first magnitude of power for a predetermined time length following an indicator that the supply voltage to the system has been interrupted; the UPS supplies the system with a voltage having a second magnitude of power following the predetermined time length; and the first magnitude is at least 40 percent larger than the second magnitude.

[0129] Example 21 provides a method, which comprises: receiving an indicator that the supply voltage to the computer system has been interrupted; providing an indicator for reducing the processor power consumption level; and establishing an indicator for reducing the processor power level based on the indicator that the supply voltage to the computer system has been interrupted.

[0130] In Example 22, in the method of Example 21, the supply voltage is an AC voltage; the indicator that the supply voltage to the computer system has been interrupted includes an AC loss message; and the indicator that the supply voltage to the computer system has been interrupted includes an indicator that the supply voltage has dropped to a no-voltage level.

[0131] In Example 23, in any one of the methods of Examples 21 to 22, the indicator for reducing the processor power consumption level includes an indicator for throttling the processor frequency; the indicator for reducing the processor power consumption level includes an indicator for flushing at least a portion of the contents of the first memory to the second memory; and the first memory is a persistent memory.

[0132] In Example 24, in any one of the methods of Examples 21 to 23, the supply voltage corresponds to a power of a first magnitude; the UPS supplies a voltage having the power of the first magnitude to the computer system for a predetermined time length following an indicator that the supply voltage to the computer system has been interrupted; the UPS supplies a voltage having the power of the second magnitude to the computer system following the predetermined time length, wherein the first magnitude is greater than the second magnitude; the first magnitude is at least 40 percent greater than the second magnitude; and the predetermined time length is 20 milliseconds or less.

[0133] A summary is provided to enable the reader to ascertain the attributes and key points of the technical disclosure. It is submitted with the understanding that this summary is not intended to limit the scope or meaning of the claims. The following claims are incorporated herein by reference to the detailed description, and each claim stands independently as a distinct embodiment.

Claims

Claim 1 An uninterruptible power supply comprising: memory storing instructions; and a processor, wherein the processor executes the instructions to deliver alternating current (AC) power from an AC power source to a computer system, to detect a power loss in the AC power source, and in response to the detection of the power loss, to provide a signal indicating the power loss to the computer system and to provide AC power based on a battery to the computer system, wherein the uninterruptible power supply provides AC power greater than the rated continuous maximum power of the uninterruptible power supply during a window of time, and the processor of the computer system flushes at least a portion of the contents of a volatile memory to a non-volatile memory in response to the signal and during the window of time while the uninterruptible power supply is providing AC power exceeding the rated continuous maximum power of the uninterruptible power supply. Claim 2 In claim 1, the time window is at least as long as a single cycle of the AC power supply, an uninterruptible power supply. Claim 3 An uninterruptible power supply according to claim 1, wherein the signal provided to the computer system includes a Universal Serial Bus (USB) message. Claim 4 An uninterruptible power supply, wherein the processor of the computer system responds to the signal and throttles the frequency of the processor during the time window while the uninterruptible power supply provides the AC power in excess of the rated continuous maximum power of the uninterruptible power supply. Claim 5 An uninterruptible power supply, wherein the volatile memory in paragraph 1 is a continuous memory. Claim 6 An uninterruptible power supply, wherein the processor of the uninterruptible power supply executes the instructions to provide AC power based on the battery to the computer system after the time window at a power level below the rated continuous maximum power. Claim 7 In claim 1, the uninterruptible power supply is temporarily overloaded by at least 40% during the time window. Claim 8 An uninterruptible power supply according to claim 1, wherein the time window is 20 milliseconds or less. Claim 9 An uninterruptible power supply, wherein the processor of the uninterruptible power supply executes the instructions to provide a human interface device (HID) driver for providing the signal to the computer system. Claim 10 In claim 1, the uninterruptible power supply is temporarily overloaded during the time window to 125% to 150% of the rated continuous maximum power. Claim 11 In claim 1, the AC power based on the battery is an uninterruptible power supply device that matches the power supply rating of the power supply unit in the computer system. Claim 12 As a computer system, a power supply unit (PSU); volatile memory and non-volatile memory powered by the PSU; A computer system comprising a processor powered by the PSU, wherein the PSU is powered by an alternating current (AC) power source at the power supply rating of the PSU, and subsequently powered by AC power based on the battery of an uninterruptible power supply (UPS) at the power supply rating of the PSU during a time window following a interruption in the AC power source - the UPS is temporarily overloaded to the rated continuous maximum power of the UPS to provide the AC power at the power supply rating of the PSU - and subsequently, at a power level below the rated continuous maximum power of the UPS, is powered by AC power based on the battery of the UPS at the time window, and the processor receives a signal from the UPS indicating an interruption in the AC power source, and in response to the signal, flushes at least a portion of the contents of the volatile memory to the non-volatile memory and throttles the frequency of the processor during the time window in which the UPS is temporarily overloaded. Claim 13 A computer system according to claim 12, further comprising a universal serial bus (USB) interface that receives a signal indicating interruption from the AC power source from a human interface device (HID) driver of the UPS. Claim 14 In paragraph 12, the time window is a computer system of a predetermined length of time during which the UPS is temporarily overloaded. Claim 15 In paragraph 14, the above UPS is temporarily overloaded to at least 40% of the rated continuous maximum power of the UPS, in a computer system. Claim 16 In paragraph 14, the above UPS is a computer system that is temporarily overloaded for at least 20 milliseconds. Claim 17 A system comprising: an uninterruptible power supply (UPS); and a computer system comprising an interface, a processor, a power supply unit (PSU), volatile memory and non-volatile memory, wherein the UPS detects that the alternating current (AC) power supplied to the computer system has been interrupted, and in response to the detection, operates under an overload condition for the rated continuous maximum power of the UPS in a time window, wherein the overload condition is to supply AC power to the computer system based on a battery at a power level that matches the power supply rating of the PSU, and the UPS further provides a signal to the interface indicating that the AC power supplied to the computer system has been interrupted, and the processor, in response to receiving the signal from the interface, flushes data from the volatile memory to the non-volatile memory during the time window while the UPS operates under the overload condition. Claim 18 In claim 17, the system wherein the processor throttles the frequency of the processor after the flushing of the data in response to receiving the signal from the interface. Claim 19 In paragraph 17, the system wherein the UPS supplies AC power to the computer system based on the battery at a power level that is less than or equal to the rated continuous maximum power of the UPS after the time window. Claim 20 delete

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