Transceiver, method of driving the same, and display device

Abstract

A transceiver may include a transmitter that transmits clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern through a line, and a receiver that receives the clock embedded data, detects clock embedded-related errors from the clock embedded data, and outputs an error flag corresponding to the clock embedded-related error to the transmitter.

Description

Technology Field

[0001] The present invention relates to a transceiver. More specifically, the present invention relates to a transceiver, a method of operating such a transceiver, and a display device. Background Technology

[0002] Generally, a display device can communicate with a processor using the MIPI (Mobile Industry Processor Interface) protocol. When communicating using the MIPI protocol, data lines for transmitting data and clock lines for transmitting clock signals may be used. The use of clock lines may increase physical or spatial costs and increase power consumption.

[0003] To prevent increased physical or spatial costs and power consumption associated with the use of clock lines, a clock-embedded data method may be used to transmit clock information via data lines without clock lines. However, handling clock-embedded related errors (error detection, transmission, etc.) that may occur depending on the clock-embedded data method may be problematic. The problem to be solved

[0004] One objective of the present invention is to provide a transceiver capable of handling clock-embedded-related errors, a method for driving the transceiver, and a display device.

[0005] However, the objectives of the present invention are not limited to such objectives, and may be expanded in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0006] To achieve one objective of the present invention as described above, a transceiver according to embodiments may include a transmitter that transmits clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern through a line, and a receiver that receives the clock embedded data, detects a clock embedded-related error from the clock embedded data, and outputs an error flag corresponding to the clock embedded-related error to the transmitter.

[0007] In one embodiment, the clock embedded related error may not be included in the error defined in the MIPI (Mobile Industry Processor Interface) D-PHY & DSI standard specification.

[0008] In one embodiment, the clock embedded related error may include at least one of a loss of lock error, an initialization error, a start pattern error, a end pattern error, and an encoding key error.

[0009] In one embodiment, at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error may be optionally masked.

[0010] In one embodiment, the receiver may include a receiving unit that samples the clock embedded data to generate a first encoded data and a control signal, a decoder that decodes the first encoded data to generate a first data, a receiving control unit that receives the control signal and the first data, and a main control unit that outputs the error flag.

[0011] In one embodiment, the receiving unit and the decoder can detect the clock-embedded related error.

[0012] In one embodiment, the clock embedded related error detected by the receiving unit can be transmitted to the main control unit through the receiving control unit, and the clock embedded related error detected by the decoder can be transmitted to the main control unit through the receiving unit and the receiving control unit.

[0013] In one embodiment, the clock embedded related error detected by the receiving unit can be transmitted directly to the main control unit, and the clock embedded related error detected by the decoder can be transmitted to the main control unit through the receiving unit.

[0014] In one embodiment, the transmitter may include a transmission control unit that generates second data, an encoder that encodes the second data to generate second encoded data, and a transmission unit that generates the clock embedded data based on the second encoded data.

[0015] In one embodiment, the error flag may include one of a pulse of a high voltage level, a pulse of a low voltage level, a signal increasing from the low voltage level to the high voltage level, and a signal decreasing from the high voltage level to the low voltage level.

[0016] In one embodiment, the width of the pulse at the high voltage level and the width of the pulse at the low voltage level can be optionally adjusted.

[0017] In one embodiment, the receiver can generate a clock signal using the clock training pattern and the encoded payload.

[0018] To achieve one objective of the present invention as described above, a method for driving a transmitter and receiver according to embodiments may include the steps of: a transmitter transmitting clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern to a receiver via a line; a step of detecting a clock embedded-related error from the clock embedded data; and a step of the receiver outputting an error flag corresponding to the clock embedded-related error to the transmitter.

[0019] In one embodiment, the clock embedded related error may include at least one of a loss of lock error, an initialization error, a start pattern error, a end pattern error, and an encoding key error.

[0020] In one embodiment, the driving method of the transceiver may further include the step of selectively masking at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error.

[0021] In one embodiment, the error flag may include one of a pulse of a high voltage level, a pulse of a low voltage level, a signal increasing from the low voltage level to the high voltage level, and a signal decreasing from the high voltage level to the low voltage level.

[0022] In one embodiment, the driving method of the transceiver may further include the step of selectively adjusting the width of the pulse at the high voltage level and the width of the pulse at the low voltage level.

[0023] In one embodiment, the driving method of the transmitter and receiver may further include the step of the transmitter transmitting a reset signal to the receiver based on the error flag.

[0024] To achieve one objective of the present invention as described above, a display device according to embodiments may include a display panel comprising a plurality of pixels, a display panel driver comprising a data driver providing data voltages to the pixels and a timing controller controlling the driving of the data driver, and a receiver that receives clock embedded data comprising a clock training pattern, a start pattern, an encoded payload, and an end pattern, detects a clock embedded-related error from the clock embedded data, and outputs an error flag corresponding to the clock embedded-related error.

[0025] In one embodiment, the display panel driver may be a TED (TCON Embedded Driver) in which the timing control unit is embedded in the data driver, and the display panel driver may include the receiver. Effects of the invention

[0026] In the transceiver, the driving method of the transceiver, and the display device according to embodiments of the present invention, clock-embedded-related errors are detected from clock-embedded data and an error flag corresponding to the clock-embedded-related error is output, thereby allowing clock-embedded-related errors that are not included in the errors defined in the MIPI D-PHY & DSI standard specifications to be processed efficiently.

[0027] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0028] FIG. 1 is a block diagram showing a transceiver according to one embodiment of the present invention. FIG. 2 is a diagram illustrating the operation of a transmitter according to an embodiment of the present invention. FIG. 3 is a diagram illustrating the operation of a receiver according to an embodiment of the present invention. Figure 4 is a table showing the errors defined in the MIPI D-PHY & DSI standard specifications. Figure 5 is a table showing clock embedded related errors. FIG. 6 is a diagram illustrating the detection and transmission of clock-embedded related errors according to an embodiment of the present invention. FIG. 7 is a diagram illustrating the detection and transmission of clock-embedded related errors according to an embodiment of the present invention. FIG. 8 is a table for explaining the masking of clock-embedded related errors according to one embodiment of the present invention. FIG. 9 is a table for explaining error flags according to embodiments of the present invention. FIG. 10 is a drawing for explaining a method of driving a transceiver according to an embodiment of the present invention. FIG. 11 is a block diagram showing a display device and a processor according to an embodiment of the present invention. Specific details for implementing the invention

[0029] Hereinafter, a transceiver, a method for driving a transceiver, and a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical or similar reference numerals are used for identical components in the attached drawings.

[0030] FIG. 1 is a block diagram showing a transceiver (100) according to one embodiment of the present invention.

[0031] Referring to FIG. 1, the transceiver (100) may include a transmitter (110), a receiver (120), and a line (130).

[0032] The transmitter (110) can transmit Clock Embedded Data (CEDT) including a clock training pattern, a start pattern, an encoded payload, and an end pattern through the line (130). The receiver (120) can receive the Clock Embedded Data (CEDT), detect a clock-embedded error from the Clock Embedded Data (CEDT), and output an error flag (ER_FG) corresponding to the clock-embedded error to the transmitter (120). The transmitter (110) can transmit a reset signal (RS) to the receiver (120) based on the error flag (ER_FG).

[0033] The transmitter (110) may include a transmission unit (111), a transmission control unit (112), and an encoder (113). The receiver (120) may include a reception unit (121), a reception control unit (122), a decoder (123), and a main control unit (124).

[0034] The transmitting unit (111) can be connected to the receiving unit (121) via a line (130). The transmitting unit (111) and the receiving unit (121) can be referred to as a data channel. The transmitting unit (111) and the receiving unit (121) may correspond to the Physical Layer and / or Data Link Layer of the OSI (Open Systems Interconnection) 7-layer model, the Network Interface Layer of the TCP / IP (Transmission Control Protocol / Internet Protocol) model, or the Physical Layer of the MIPI (Mobile Industry Processor Interface) protocol. The Physical Layer of the MIPI protocol can be configured according to various predetermined specifications, such as D-PHY, C-PHY, and M-PHY. Below, an exemplary case is described in which the transmitting unit (111) and the receiving unit (121) are configured according to the D-PHY specification of the Physical Layer of the MIPI protocol.

[0035] The transmission control unit (112) and the reception control unit (122) may correspond to the Network Layer and / or Transport Layer of the OSI 7-layer model, the Internet Layer and / or Transport Layer of the TCP / IP model, or the Protocol Layer of the MIPI protocol. The Protocol Layer of the MIPI protocol may be configured according to various predefined specifications, such as DSI (Display Serial Interface) and CSI (Camera Serial Interface). Below, an exemplary case is described in which the transmission control unit (112) and the reception control unit (122) are configured according to the DSI specification among the Protocol Layers of the MIPI protocol.

[0036] The main control unit (124) may correspond to the Session Layer, Presentation Layer, and / or Application Layer of the OSI 7-layer model, the Application Layer of the TCP / IP model, or the Application Layer of the MIPI protocol. Below, an example is described where the main control unit (124) corresponds to the Application Layer of the MIPI protocol.

[0037] In one embodiment, the transmitting unit (111), the transmitting control unit (112), and the encoder (113) may be configured separately from each other in hardware, or two or more of them may be integrated in hardware. In another embodiment, the transmitting unit (111), the transmitting control unit (112), and the encoder (113) may be configured separately from each other in software, or two or more of them may be integrated in software. The transmitter (110) may be configured as part (hardware or software) of another controller (e.g., AP (Application Processor), GPU (Graphics Processing Unit), CPU (Central Processing Unit), etc.), or may be configured as independent hardware (e.g., a transmission-only IC).

[0038] In one embodiment, the receiving unit (121), the receiving control unit (122), the decoder (123), and the main control unit (124) may be configured to be separate from each other in hardware, or two or more of these may be integrated in hardware. In another embodiment, the receiving unit (121), the receiving control unit (122), the decoder (123), and the main control unit (124) may be configured to be separate from each other in software, or two or more of these may be integrated in software. The receiver (120) may be configured as part (hardware or software) of another controller (e.g., TCON (Timing Controller), TED (TCON Embedded Driver), D-IC (Driver IC), etc.), or may be configured as independent hardware (e.g., a receiving-only IC).

[0039] The transmission control unit (112) may provide the encoder (113) with second data (DT2) containing a payload. The payload may be effective data to be transmitted. The payload may contain variable values ​​rather than a predetermined pattern. The encoder (113) may encode the second data (DT2) to generate second encoded data (EDT2) containing an encoded payload, and may provide the second encoded data (EDT2) to the transmission unit (111). The transmission unit (111) may generate clock embedded data (CEDT) based on the second encoded data (EDT2) and transmit the clock embedded data (CEDT) through the line (130). The transmitting unit (111) can generate clock embedded data (CEDT) by adding other data to the second encoded data (EDT2) according to a predetermined protocol.

[0040] The receiving unit (121) can generate a first encoded data (EDT1) containing the encoded payload by sampling the clock embedded data (CEDT). The receiving unit (121) can generate a clock signal using the clock embedded data (CEDT) and can sample the clock embedded data (CEDT) based on the clock signal. For example, the receiving unit (121) may include a Clock Data Recovery (CDR) circuit. The receiving unit (121) can provide the first encoded data (EDT1) to a decoder (123). The decoder (123) can decode the first encoded data (EDT1) to generate a first data (DT1) containing the payload and can provide the first data (DT1) to a receiving control unit (122).

[0041] The receiving unit (121) can sample clock embedded data (CEDT) to generate a necessary control signal (HS) according to the protocol. The receiving unit (121) can provide the control signal (HS) to the receiving control unit (122). In one embodiment, the receiver (120) may further include a delay unit, and the delay unit may provide the control signal (HS) to the receiving control unit (122) by delaying it by a decoding time. Here, the decoding time may be the time required for the decoder (123) to decode the first encoded data (EDT1) to generate the first data (DT1).

[0042] The main control unit (124) can output an error flag (ER_FG) corresponding to the clock embedded related error.

[0043] FIG. 2 is a diagram for explaining the operation of a transmitter (110) according to one embodiment of the present invention.

[0044] Referring to FIG. 2, the encoder (113) can receive second data (DT2) containing a payload (PL). The encoder (113) can generate an encoded payload (EPL) by encoding the payload (PL), and can generate second encoded data (EDT2) by adding data before and after the encoded payload (EPL). For example, the second encoded data (EDT2) may sequentially include a clock training pattern (CLK-T), a start pattern (STP), an encoded payload (EPL), and an end pattern (EDP).

[0045] A clock training pattern (CLK-T) may include clock information. A receiver (120) may generate a clock signal having a specific frequency and a specific phase using the clock information. The clock signal generated by the clock data recovery circuit of the receiver (120) may have its frequency and phase changed undesirably due to external factors (noise, temperature, etc.). The receiver (120) may correct the frequency and phase of the clock signal using the clock training pattern (CLK-T). In one embodiment, the clock training pattern (CLK-T) may be a pattern in which one 1 and one 0 are repeated (e.g., 01010101...). In another embodiment, the clock training pattern (CLK-T) may include a plurality of consecutive 0s and a plurality of consecutive 1s repeated (e.g., 0000111100001111...). In the other embodiment above, the frequency information and phase information indicated by the clock training pattern (CLK-T) may vary depending on the number of consecutive zeros or the number of consecutive ones.

[0046] The Start Pattern (STP) may be a pattern that signals the start of transmission of the Encoded Payload (EPL). The Start Pattern (STP) may be a pattern that the Encoded Payload (EPL) cannot include (=is prohibited from use). For example, the Start Pattern (STP) may be composed of 24b'011100_000000_111111_110001'.

[0047] The encoded payload (EPL) may contain clock information. For example, if there are many consecutive zeros or consecutive ones in the encoded payload (EPL), the signal transitions are insufficient, so the phase correction of the clock signal at the receiving unit (121) may not be sufficiently performed, and consequently, skew of the clock signal may occur. Therefore, the encoder (113) may encode the payload (PL) such that the transitions (changes from 0 to 1 or changes from 0 to 1) of the encoded payload (EPL) are sufficiently numerous compared to the payload (PL). Additionally, the encoder (113) may encode the payload (PL) such that the encoded payload (EPL) periodically has bits of a specific rule.

[0048] The termination pattern (EDP) may be a pattern that signals the end of transmission of the encoded payload (EPL). For example, the termination pattern (EDP) may consist of 24b'011100_111111_000000_110001'. The termination pattern (EDP) is a pattern that the encoded payload (EPL) cannot include (=is prohibited from use).

[0049] The transmitting unit (111) can receive a second encoded data (EDT2) containing an encoded payload (EPL). The transmitting unit (111) can transmit other data before and after the second encoded data (EDT2) according to a predetermined protocol. For example, if the predetermined protocol is the MIPI protocol, the transmitting unit (111) can sequentially transmit a first pattern (HS-zero), a second pattern (HS-sync), the second encoded data (EDT2), a third pattern (HS-trail), and a fourth pattern (HS-exit).

[0050] The first pattern (HS-zero) may be a pattern for indicating a waiting period after entering high-speed mode from low-power mode. For example, the first pattern (HS-zero) may be a pattern of repeating 0s. The second pattern (HS-sync) may be a pattern indicating the start of transmission of the second encoded data (EDT2). For example, the second pattern (HS-sync) may have the value OxB8h or the value 00011101. The third pattern (HS-trail) may be a pattern indicating the end of transmission of the second encoded data (EDT2). The third pattern (HS-trail) may be a pattern of repeating values ​​opposite to the last data of the second encoded data (EDT2). For example, if the last data (bit) of the second encoded data (EDT2) is 0, the third pattern (HS-trail) may be a pattern of repeating 1s. The fourth pattern (HS-exit) may be a pattern indicating that the high-speed mode is terminated and the low-power mode is started.

[0051] FIG. 3 is a drawing for explaining the operation of a receiver (120) according to one embodiment of the present invention.

[0052] Referring to FIG. 3, the receiving unit (121) can sample clock-embedded data (CEDT) and provide the first encoded data (EDT1) containing the encoded payload (EPL) to the decoder (123).

[0053] The decoder (123) can decode the first encoded data (EDT1) (i.e., the encoded payload (EPL)) to generate the first data (DT1) and provide the first data (DT1) to the receiving control unit (122). The first data (DT1) may include a payload (PL) and a dummy pattern (DMY).

[0054] The dummy pattern (DMY) may be pre-encoded to be embedded in the encoded payload (EPL) in the encoder (113) or may be added in the decoder (123). The dummy pattern (DMY) may be data with the same value repeated. For example, when the last value of the payload (PL) is 0, the dummy pattern (DMY) may be data with 1 repeated, and when the last value of the payload (PL) is 1, the dummy pattern (DMY) may be data with 0 repeated.

[0055] Figure 4 is a table showing the errors defined in the MIPI D-PHY & DSI standard specifications.

[0056] Referring to FIG. 4, when an error defined in the MIPI D-PHY & DSI standard specification occurs, the receiver (120) can transmit an error signal to the transmitter (110). For example, the error signal may be a 16-bit signal, and a state error may be pre-set for each bit.

[0057] For example, the bit at address 0 of the above error signal may indicate whether a Start of Transmission (SoT) error has occurred, and the SoT error may be an error that occurs when transmission is not performed according to the protocol defined by the MIPI alliance.

[0058] For example, the bit at address 1 of the error signal may indicate whether an SoT synchronization error has occurred. When a state error corresponding to each address is detected, the bit at that address may be 1, and when a state error corresponding to each address is not detected, the bit at that address may be 0.

[0059] Figure 5 is a table showing clock embedded related errors.

[0060] Referring to FIG. 5, clock embedded related errors may include at least one of a Loss of Lock Error, an Initialization Error, a Start Pattern Error (STP Error), an End Pattern Error (EDP Error), and an Encoding Key Error. The clock embedded related errors are errors that may occur in the method of embedding clock information into data, and may not be included in the errors defined in the aforementioned MIPI D-PHY & DSI standard specifications.

[0061] The above-mentioned locking loss error may indicate a state in which the Clock Data Recovery (CDR) circuit fails to properly recover the clock signal during High Speed ​​Data Transmission (HSDT) operation and exits the locking state. The above-mentioned initialization error may indicate a state in which normal locking is not achieved even though the Clock Data Recovery circuit has terminated the initialization operation based on the Clock Training Pattern (CLK_T).

[0062] The above start pattern error may indicate a case where the start pattern (STP) is not entered correctly, or a case where the start pattern (STP) is entered correctly but an error occurs during the data recovery process (e.g., clock data recovery). The above end pattern error may indicate a case where the end pattern (EDP) is not entered correctly.

[0063] The above encoding key error may indicate a case where the input encoding key is a forbidden pattern that cannot occur based on the encoding protocol.

[0064] FIG. 6 is a diagram illustrating the detection and transmission of clock-embedded related errors (ER) according to an embodiment of the present invention.

[0065] Referring to FIG. 6, the receiving unit (121) and the decoder (123) can detect clock-embedded related errors (ER). In one embodiment, the receiving unit (121) can detect at least one of the locking loss error, the initialization error, the start pattern error, and the end pattern error, and the decoder (123) can detect the encoding key error.

[0066] Clock embedded related error (ER) detected by the receiving unit (121) can be transmitted to the main control unit (124) through the receiving control unit (122), and clock embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) through the receiving unit (121) and the receiving control unit (122). In other words, clock embedded related error (ER) detected by the receiving unit (121) can be transmitted to the main control unit (124) through a path (①) passing through the receiving control unit (122), and clock embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) through a path (①+②) passing through the receiving unit (121) and the receiving control unit (122).

[0067] FIG. 7 is a diagram illustrating the detection and transmission of clock-embedded related errors (ER) according to an embodiment of the present invention.

[0068] Referring to FIG. 7, clock embedded related error (ER) detected by the receiving unit (121) can be transmitted directly to the main control unit (124), and clock embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) through the receiving unit (121). In other words, clock embedded related error (ER) detected by the receiving unit (121) can be transmitted to the main control unit (124) through a path (③) that does not pass through the receiving control unit (122), and clock embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) through a path (②+③) that passes through the receiving unit (121) but does not pass through the receiving control unit (122).

[0069] FIG. 8 is a table for explaining the masking of clock-embedded related errors according to one embodiment of the present invention.

[0070] Referring to FIG. 8, at least one of the clock embedded related errors may be optionally masked. In one embodiment, at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error may be optionally masked.

[0071] For example, as illustrated in FIG. 8, when the locking loss error is selectively masked, the main control unit (124) may not output an error flag (ER_FG) even if the receiving unit (121) detects the locking loss error. Additionally, as illustrated in FIG. 8, when the initialization error is not selectively masked, the main control unit (124) may output an error flag (ER_FG) when the receiving unit (121) detects the initialization error.

[0072] FIG. 9 is a table for explaining error flags (ER_FG) according to embodiments of the present invention.

[0073] Referring to FIG. 9, the error flag (ER_FG) may include one of a pulse (HP) at a high voltage level (HVL), a pulse (LP) at a low voltage level (LVL), a signal increasing from a low voltage level (LVL) to a high voltage level (HVL) (LTHS), and a signal decreasing from a high voltage level (HVL) to a low voltage level (LVL) (HTLS). The high voltage level (HVL) in the signal increasing from a low voltage level (LVL) to a high voltage level (HVL) (LTHS) may indicate the occurrence of the clock-embedded related error, and the low voltage level (LVL) in the signal decreasing from a high voltage level (HVL) to a low voltage level (LVL) (HTLS) may indicate the occurrence of the clock-embedded related error.

[0074] In one embodiment, the width (WT) of the pulse (HP) at the high voltage level (HVL) and the width (WT) of the pulse (LP) at the low voltage level (LVL) may be optionally adjustable. The width and / or frequency of the clock signal of the transmitter (110) may be different from the width and / or frequency of the clock signal of the receiver (120), or the setting for detecting the error flag (ER_FG) of the transmitter (110) may be different from the setting for generating the error flag (ER_FG) of the receiver (120). Accordingly, the width (WT) of the pulse (HP) at the high voltage level (HVL) and the width (WT) of the pulse (LP) at the low voltage level (LVL) may be increased or decreased so that the error flag (ER_FG) generated by the receiver (120) can be detected by the transmitter (110).

[0075] FIG. 10 is a drawing for explaining a method of driving a transceiver (100) according to an embodiment of the present invention.

[0076] Referring to FIG. 10, first, the transmitter (110) can transmit clock embedded data (CEDT) to the receiver (120) through the line (130).

[0077] Next, the receiver (120) can detect clock-embedded related errors (ER) from the clock-embedded data (CEDT). The receiving unit (121) and the decoder (123) can detect clock-embedded related errors (ER) including at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error. In one embodiment, the receiving unit (121) can detect at least one of the locking loss error, the initialization error, the start pattern error, and the end pattern error, and the decoder (123) can detect the encoding key error.

[0078] Next, the receiving unit (121) and the decoder (123) can transmit clock-embedded related errors (ER) to the main control unit (124). In one embodiment, the clock-embedded related error (ER) detected by the receiving unit (121) can be transmitted to the main control unit (124) via the receiving control unit (122), and the clock-embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) via the receiving unit (121) and the receiving control unit (122). In another embodiment, the clock-embedded related error (ER) detected by the receiving unit (121) can be transmitted directly to the main control unit (124), and the clock-embedded related error (ER) detected by the decoder (123) can be transmitted to the main control unit (124) via the receiving unit (121).

[0079] Next, the main control unit (124) may output an error flag (ER_FG) corresponding to a clock-embedded error (ER) to the transmitter (110). The error flag (ER_FG) may include one of a pulse at a high voltage level, a pulse at a low voltage level, a signal increasing from the low voltage level to the high voltage level, and a signal decreasing from the high voltage level to the low voltage level.

[0080] In one embodiment, the width of the pulse at the high voltage level and the width of the pulse at the low voltage level can be selectively adjusted so that an error flag (ER_FG) can be detected by the transmitter (110).

[0081] In one embodiment, at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error may be optionally masked. Accordingly, even if an optionally masked clock embedded related error (ER) occurs, the main control unit (124) may not output an error flag (ER_FG).

[0082] Next, the transmitter (110) may transmit a reset signal (RS) to the receiver (120) based on an error flag (ER_FG). Based on the reset signal (RS) transmitted from the transmitter (110), the receiver (120) may be initialized, or the receiver (120) may initialize the reception of clock embedded data (CEDT).

[0083] FIG. 11 is a block diagram showing a display device (200) and a processor (300) according to one embodiment of the present invention.

[0084] Referring to FIG. 11, the display device (200) may include a display panel (210), a scan driver (220), and a display panel driver (230). The display panel driver (230) may include a data driver (232) and a timing control unit (234).

[0085] A display panel (210) can display an image. The display panel (210) may include a plurality of pixels (PX). The pixels (PX) may be arranged in a substantial matrix form. Each of the pixels (PX) may emit light, and the display panel (210) may display an image in which the light is combined. In one embodiment, each of the pixels (PX) may emit at least one of red, green, blue, and white light.

[0086] The scan driver (220) can generate scan signals (SS) based on a scan control signal (SCS). The scan driver (220) can provide scan signals (SS) to pixels (PX). In one embodiment, the scan driver (220) can be mounted on a display panel (210) in the form of a circuit.

[0087] The data driver (232) can generate data voltages (VDT) based on the data control signal (DCS) and image data (ID). The data driver (232) can generate data voltages (VDT) corresponding to the image data (ID). The data driver (232) can provide data voltages (VDT) to pixels (PX).

[0088] The timing control unit (234) can control the operation of the scan drive unit (220). The timing control unit (234) can generate a scan control signal (SCS) based on a control signal. The control signal may include a clock signal, a horizontal synchronization signal, a vertical synchronization signal, etc. The timing control unit (234) can provide the scan control signal (SCS) to the scan drive unit (220).

[0089] The timing control unit (234) can control the operation of the data driving unit (232). The timing control unit (234) can generate a data control signal (DCS) and image data (ID) based on the control signal and input image data, and can provide the data control signal (DCS) and image data (ID) to the data driving unit (232).

[0090] In one embodiment, the display panel driver (230) may be a TED (TCON Embedded Driver) in which the timing control unit (234) is embedded in the data driver (232). In the above embodiment, the display panel driver (230) may include the aforementioned receiver (120).

[0091] The processor (300) may be one of an Application Processor (AP), a Graphics Processing Unit (GPU), and a Central Processing Unit (CPU). The processor (300) may include the aforementioned transmitter (110). Industrial applicability

[0092] The transceiver and display device according to exemplary embodiments of the present invention can be applied to a display device included in a computer, laptop, mobile phone, smartphone, smartpad, PMP, PDA, MP3 player, etc.

[0093] Although a transceiver, a method for driving a transceiver, and a display device according to exemplary embodiments of the present invention have been described above with reference to the drawings, the described embodiments are exemplary and may be modified and changed by those skilled in the art without departing from the technical spirit of the present invention as described in the following claims. Explanation of the symbols

[0094] 100: Transmitter / Receiver 110: Transmitter 111: Transmitter unit 112: Transmission control unit 113: Encoder 120: Receiver 121: Receiving unit 122: Receiver control unit 123: Decoder 124: Main control unit 210: Display panel 230: Display panel drive unit 232: Data driver 234: Timing control unit

Claims

Claim 1 A transmitter that transmits clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern through a line; and a receiver that receives the clock embedded data, detects a clock embedded-related error from the clock embedded data, and outputs an error flag corresponding to the clock embedded-related error to the transmitter, wherein the clock training pattern includes clock information, and the receiver generates a clock signal having a specific frequency and a specific phase using the clock information. Claim 2 A transceiver according to claim 1, wherein the clock embedded related error is not included in the error defined in the MIPI (Mobile Industry Processor Interface) D-PHY & DSI standard specification. Claim 3 A transceiver according to claim 1, wherein the clock embedded related error includes at least one of a loss of lock error, an initialization error, a start pattern error, a end pattern error, and an encoding key error. Claim 4 A transceiver according to claim 3, wherein at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error is optionally masked. Claim 5 In claim 1, the receiver comprises: a receiving unit that samples the clock embedded data to generate a first encoded data and a control signal; a decoder that decodes the first encoded data to generate a first data; a receiving control unit that receives the control signal and the first data; and a main control unit that outputs the error flag. Claim 6 In claim 5, the receiving unit and the decoder are a transceiver that detects the clock-embedded related error. Claim 7 A transceiver according to claim 6, wherein the clock-embedded related error detected by the receiving unit is transmitted to the main control unit through the receiving control unit, and the clock-embedded related error detected by the decoder is transmitted to the main control unit through the receiving unit and the receiving control unit. Claim 8 A transceiver according to claim 6, wherein the clock-embedded related error detected by the receiving unit is transmitted directly to the main control unit, and the clock-embedded related error detected by the decoder is transmitted to the main control unit through the receiving unit. Claim 9 In claim 5, the transmitter comprises: a transmission control unit that generates second data; an encoder that encodes the second data to generate second encoded data; and a transmission unit that generates the clock embedded data based on the second encoded data, thereby forming a transceiver. Claim 10 A transceiver according to claim 1, wherein the error flag comprises one of a pulse of a high voltage level, a pulse of a low voltage level, a signal increasing from the low voltage level to the high voltage level, and a signal decreasing from the high voltage level to the low voltage level. Claim 11 A transceiver according to claim 10, wherein the width of the pulse at the high voltage level and the width of the pulse at the low voltage level are optionally adjustable. Claim 12 In claim 1, the receiver is a transceiver that generates the clock signal using the clock training pattern and the encoded payload. Claim 13 A method for operating a transmitter and receiver, comprising the steps of: transmitting clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern to a receiver via a line; detecting a clock embedded-related error from the clock embedded data; and the receiver outputting an error flag corresponding to the clock embedded-related error to the transmitter, wherein the clock training pattern includes clock information, and the receiver generates a clock signal having a specific frequency and a specific phase using the clock information. Claim 14 A method for driving a transceiver according to claim 13, wherein the clock embedded related error includes at least one of a loss of lock error, an initialization error, a start pattern error, a end pattern error, and an encoding key error. Claim 15 A method for driving a transceiver according to claim 14, further comprising the step of selectively masking at least one of the locking loss error, the initialization error, the start pattern error, the end pattern error, and the encoding key error. Claim 16 A driving method of a transceiver according to claim 13, wherein the error flag comprises one of a pulse of a high voltage level, a pulse of a low voltage level, a signal increasing from the low voltage level to the high voltage level, and a signal decreasing from the high voltage level to the low voltage level. Claim 17 A driving method for a transceiver according to claim 16, further comprising the step of selectively adjusting the width of the pulse at the high voltage level and the width of the pulse at the low voltage level. Claim 18 A method for driving a transmitter and receiver according to claim 13, further comprising the step of the transmitter transmitting a reset signal to the receiver based on the error flag. Claim 19 A display device comprising: a display panel including a plurality of pixels; a display panel driver including a data driver providing data voltages to the pixels and a timing controller controlling the driving of the data driver; and a receiver that receives clock embedded data including a clock training pattern, a start pattern, an encoded payload, and an end pattern, detects a clock embedded-related error from the clock embedded data, and outputs an error flag corresponding to the clock embedded-related error, wherein the clock training pattern includes clock information, and the receiver generates a clock signal having a specific frequency and a specific phase using the clock information. Claim 20 In claim 19, the display panel driving unit is a TED (TCON Embedded Driver) in which the timing control unit is embedded in the data driving unit, and the display panel driving unit includes the receiver, a display device.

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