Directional selective junction clean with field polymer protections

Abstract

A process for cleaning junction interfaces for manufacturing semiconductor devices is described, comprising forming low-resistance electrical connections between vertically separated regions. Etching may be performed to remove silicon oxide on the silicon surface at the bottom of a recessed feature. Methods and apparatus for etching the bottom oxide of a hole or trench while minimizing effects on the corners of metal gate structures and on the underlying epitaxial and dielectric layers in the field are described. A method for etching features comprises a reaction chamber equipped with a combination of capacitively coupled plasma and inductively coupled plasma. CHxFy gases and plasma are used to form a protective layer, which enables selective etching of the bottom silicon dioxide by NH3-NF3 plasma. Ideally, silicon oxide on the EPI is removed to ensure low-resistance electrical contact, while the epitaxial layer and field / corner dielectric layers are etched only minimally or not at all.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor processing. More specifically, the embodiments of the present disclosure relate to methods for etching layers. Background Technology

[0002] Integrated circuits are made possible by processes that create complexly patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods to remove the exposed material. Chemical etching is used for various purposes, including transferring a photoresist pattern to underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. Often, for example, it is desirable to have an etching process that etches one material more quickly than another material, enabling the pattern transfer process. Such an etching process is said to be selective for the first material. As a result of the diversity of materials, circuits, and processes, etching processes have been developed selectively for various materials.

[0003] Dry etchings generated from localized plasmas formed within the substrate processing area can penetrate into more constrained trenches than wet etchings and may exhibit less deformation of the remaining intricate structures. However, even if the etching process can be selective for the first material compared to the second material, some unwanted etching of the second material may still occur.

[0004] To achieve low junction contact resistance and reach nodes of less than 5 nm, junction clean must completely remove silicon oxide from the epitaxial surface through minimal dielectric etching of the fields and trench shoulders required for self-alignment contact (SAC), which is implemented to avoid low epi loss, minimal critical dimension (CD) blowout, as well as contact misalignment, degraded performance, and unwanted yield loss.

[0005] There are three commonly used cleaning / etching methods: isotropic cleaning using ammonium fluoride (NH4F) or ammonium fluoride-hydrogen fluoride (NH4F-HF) formed by an NH3-HF gas mixture or a remote NH3-NF3 plasma; CH x F y Directional dry etching based on chemical and polymer protection; and directional selective etching based on plasma using NH4F. Each method has problems, resulting in CD blowout, or field loss, or epitaxial loss, or high field loss.

[0006] Therefore, improved systems and methods that can be used to produce high-quality devices and structures are needed.

[0007] One or more embodiments of the present disclosure relate to an etching method. In one or more embodiments, the method comprises the step of flowing a gas mixture into a processing volume of a processing chamber — the processing gas is CH₄ x F yThe method comprises: generating plasma within a processing volume; forming a polymer layer on the bottom surface and sidewall of a feature on a substrate—wherein the top surface of the feature is located on metal gate structures, and the bottom surface of the feature includes a dielectric layer on the top surface of an epitaxial layer, and the epitaxial layer has a certain thickness—; and removing the dielectric layer—wherein the thickness of the epitaxial layer is reduced to less than about 10 nm.

[0008] Other embodiments relate to a processing chamber. In one or more embodiments, the processing chamber comprises a chamber body having a lid, a bottom wall, and at least one side wall that defines a processing volume; a nozzle connected to a gas line and fluidly communicating with the processing volume; a gas source located outside the chamber body and fluidly communicating with the gas line; and a substrate support comprising an electrostatic chuck. In one or more embodiments, one of the lid and the electrostatic chuck is connected to an RF power source, and the other of the lid and the electrostatic chuck is connected to electrical ground to generate plasma within the gas volume.

[0009] Further embodiments include, when executed by a controller of the processing chamber, an operation in which the processing chamber flows gas into the processing volume of the processing chamber — the processing gas is CH x F yThe present invention relates to a non-transient computer-readable medium comprising instructions for performing operations including: generating plasma within a processing volume; forming a polymer layer on the bottom surface and sidewall of a feature on a substrate—wherein the top surface of the feature is located on metal gate structures, and the bottom surface of the feature includes a dielectric layer on the top surface of an epitaxial layer, and the epitaxial layer has a certain thickness—; removing the dielectric layer—wherein the thickness of the epitaxial layer is reduced to less than about 10 nm. Brief explanation of the drawing

[0010] In a manner that the features listed above of the present disclosure can be understood in detail, a more specific description of the present disclosure, which has been briefly summarized above, may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings are merely illustrative of typical embodiments of the present disclosure and should not be construed as limiting the scope of the present disclosure, as the present disclosure may allow for other equally valid embodiments.

[0011] FIG. 1 illustrates a cross-sectional view of a processing chamber according to one or more embodiments of the present invention.

[0012] FIG. 2 illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0013] FIG. 3 illustrates a process flow diagram of a method according to one or more embodiments.

[0014] FIG. 4a illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0015] FIG. 4b illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0016] FIG. 5 illustrates a process flow diagram of a method according to one or more embodiments.

[0017] FIG. 6a illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0018] FIG. 6b illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0019] FIG. 6c illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0020] FIG. 6d illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0021] FIG. 6e illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0022] FIG. 7 illustrates a process flow diagram of a method according to one or more embodiments.

[0023] FIG. 8a illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0024] FIG. 8b illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0025] FIG. 8c illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0026] FIG. 9 illustrates a cross-sectional view of partially manufactured semiconductor devices during a method according to one or more embodiments.

[0027] FIG. 10 illustrates a cluster tool according to one or more embodiments of the present disclosure. Specific details for implementing the invention

[0028] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. Other embodiments of the present disclosure are possible and may be implemented or carried out in various ways.

[0029] As used herein, the term "approximately" means nearly or almost, and implies a variation of ±15% or less of the presented numerical value or range. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, or ±1% will satisfy the definition of approximately.

[0030] As used in this specification and the appended claims, the terms “substrate” or “wafer” refer to a surface or part of a surface on which a process is performed. Furthermore, it will be understood by those skilled in the art that, unless the context clearly indicates otherwise, a reference to a substrate may also refer to only a part of the substrate. Additionally, a reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0031] As used herein, the term “substrate” refers to any substrate, or a material surface formed on the substrate, on which film processing is performed during the manufacturing process. For example, substrate surfaces on which processing may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, SOI (silicon on insulator), carbon-doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include (but are not limited to) semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneale, UV cure, e-beam cure, and / or bake the substrate surface. In the present disclosure, in addition to processing the film directly on the substrate surface itself, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layer as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0032] In one or more embodiments, the process for manufacturing semiconductor devices comprises forming electrical connections between vertically separated regions. In one or more embodiments, etching may be performed to etch a recessed feature (also referred to as a trench or contact hole) into a dielectric material (often silicon dioxide (SiO2)). Subsequently, this hole may be filled with a conductive material to electrically connect the vertically separated regions. Specific embodiments of the present invention relate to methods and apparatus for etching a contact hole. In some other embodiments, the methods and apparatus described herein may be used to etch vias, trenches, or other recessed features.

[0033] Processing chambers capable of implementing embodiments of the present invention may be included within processing platforms such as the Producer® system, Centris®, Centura®, Endura®, etc., available from Applied Materials, Inc. of Santa Clara, California. FIG. 1 illustrates a cross-sectional view of one embodiment of a processing chamber.

[0034] In one or more embodiments, the method for etching features comprises a reaction chamber equipped with radio frequency generators. During etching, CH x F yGases and plasma are used to selectively etch silicon dioxide. Ideally, silicon oxide is removed with the epitaxial layer being etched minimally or not etched at all. In one or more embodiments, an epitaxial layer of up to 10 nm is removed. In other embodiments, an epitaxial layer of less than 9 nm, or less than 8 nm, or less than 7 nm, or less than 6 nm, or less than 5 nm, or less than 4 nm, or less than 3 nm, or less than 2 nm, or less than 1 nm is removed.

[0035] Referring to FIG. 1, in one or more embodiments, the advanced plasma etching chamber (100) comprises CH₄, which includes but is not limited to methyl fluoride (CH₃F), fluoroform (CHF₃), hexafluoro-1,3-butadiene (C₄F₆), octafluorocyclobutane (C₄F₆), methane (CH₄), carbon tetrafluoride (CF₄), hexafluoroethane (C₂F₆), ethylene (C₂H₄), ethane (C₂H₆), as well as argon (Ar), hydrogen (H₂), ammonia (NH₃), nitrogen trifluoride (NF₃), helium (He), nitrogen (N₂), oxygen (O₂), carbon monoxide (CO), carbon dioxide (CO₂), sulfur hexafluoride (SF₆), and hydrogen fluoride (HF). x F yGases are provided, and inductively coupled plasma (ICP) is used as a source through vertical or planar coils (122) on the top (lead) (126) of the chamber. The gases can enter the chamber (100) through gas lines (124), a hub (128), and a nozzle (132). In one or more embodiments, a high-voltage DC power supply (130) is used in an electrostatic chuck (e-chuck) (114) that holds a wafer (or substrate) (134). In one or more embodiments, a vacuum chamber comprising an upper liner (120), a lower liner (106), a cathode liner (102), a chamber lid (126), a chamber screen door (116), an edge ring (118), a cathode (108), an RF plate (112), an RF match (110), a plasma screen (104), a pumping, and an electrostatic chuck (114) having high thermal uniformity is advantageously provided, with e-chucking utilizing rapid heating and cooling to hold a wafer. In one or more embodiments, the electrostatic chuck (114) is essential.

[0036] In one or more embodiments, the electrostatic chuck ("ESC") (114) is partially a pedestal. The pedestal may include one or more of a DC electrode embedded within the ESC and a cooling / heating base. In an embodiment, the processing chamber includes a cathode (108). In an embodiment, the ESC includes other ceramic materials, such as aluminum oxide (Al2O3) material, aluminum nitride (AlN), or a mixture of various types of ceramics known to those skilled in the art of manufacturing electronic devices, such as aluminum oxide and silicon oxide. A power supply (e.g., a high-voltage DC power supply) may be connected to the electrostatic chuck (114). In some embodiments, the electrostatic chuck (114) includes a heater (not shown) capable of raising the temperature of the wafer / substrate to a first temperature.

[0037] As illustrated in FIG. 1, a substrate can be loaded through an opening (136) and placed on an electrostatic chuck (114). The chamber (100) includes a nozzle (132) for introducing one or more process gases through a gas line (124). In some embodiments, a polymer film is deposited on a wafer / substrate of the chamber (100) while the electrostatic chuck (114) is maintained at a temperature of about 30°C and a pressure of about 10 mTorr, and a plasma is generated above the wafer level by applying about 600 watts to the coils on the top of the lead. In some embodiments, two RF powers of about 100 to about 1000 watts at 13.56 MHz and 2 MHz are delivered to the electrostatic chuck to generate a dual-bias plasma at the wafer level.

[0038] In an embodiment, the processing chamber (100) is an ICP (inductively coupled plasma) system. In an embodiment, the processing chamber is a system having a combination of ICP (inductively coupled plasma) and CCP (capacitively coupled plasma).

[0039] In one or more embodiments, special coatings or bulk materials are implemented in the upper liner (120), lower liner (106), cathode liner (102), chamber lid (126), nozzle (132), edge ring (118) and other process kits to accommodate a number of plasma chemicals. In one or more embodiments, the special coatings or bulk materials include one or more ceramics including, but not limited to, alumina, yttrium, zirconium oxide (ZrO2), HPM®, PAC3®, etc.

[0040] Referring to FIG. 2, a cross-sectional view of a partially manufactured semiconductor device (200) during an etching process according to one or more embodiments is illustrated. FIG. 3 illustrates a process flow diagram for performing an etching process according to various embodiments. The method of FIG. 3 will be described in relation to the partially manufactured device illustrated in FIG. 2. The method (300) begins in operation (302), in which a substrate is provided in a reaction chamber equipped with a plasma generator for generating a capacitively coupled plasma or an inductively coupled plasma, or a combination thereof. In one or more embodiments, the partially manufactured semiconductor device (200) comprises a metal gate structure (202) which may include one or more of a gate dielectric (e.g., hafnium oxide (HfO2, or other high-k dielectric material)), a metal gate (204), a cap layer (206), and spacers (212 and 214). A feature (201) exists between the metal gate structures (202). In one or more embodiments, a dielectric layer (208) is located at the bottom of the feature (201). As used in this context, the term “feature” refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, and peaks having a top and two sidewalls. Features may have any suitable aspect ratio (ratio of the feature’s depth to the feature’s width). In some embodiments, the aspect ratio is about 2:1, 3:1, 4:1, 5:1, 10:1, or 15:1 or greater. In one or more embodiments, the feature has a height-to-width aspect ratio of at least 5:1.

[0041] In one or more embodiments, the feature (201) includes at least one sidewall and a bottom surface. The dielectric layer (208) may include any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric layer (208) includes silicon dioxide (SiO2). In one or more embodiments, the dielectric layer is on the top surface of the epitaxial layer (210).

[0042] In operation (304), a first etching operation is performed in a reaction chamber. The first etching operation is an inductively coupled plasma (ICP) etching operation. In one or more embodiments, if field dielectric loss is not an issue, bond cleaning can be simplified by introducing a diluent gas (e.g., He or Ar) into the chamber, chucking the wafer onto the electrostatic chuck using an ICP plasma, ammonia (NH3) and nitrogen trifluoride (NF3), striking the plasma with ICP for only a few seconds to form ammonium fluoride (NH4F) on the wafer / substrate, creating a thin ammonium fluorosilicate ((NH4)2SiF6) as protection for the epitaxial layer, turning on the bias for a specific time to remove the target silicon dioxide (SiO2), and then pumping, purging, and sublimating the internal or external reaction byproducts (silicate) before moving to the bond metal silicide module.

[0043] FIG. 4 illustrates a cross-sectional view of a partially manufactured semiconductor device (400) during an etching process according to one or more embodiments. FIG. 5 illustrates a process flowchart for performing an etching process according to various embodiments. The method of FIG. 5 will be described in relation to the partially manufactured device illustrated in FIG. 4. In one or more embodiments, the partially manufactured semiconductor device (400) comprises a metal gate structure (402) that may include one or more of a gate dielectric (e.g., hafnium oxide (HfO2, or other high-k dielectric material), a metal gate (404), or a cap layer (406) and spacers (412 and 416). A feature (401) is located between the metal gate structures (402). In one or more embodiments, a dielectric layer (408) is located at the bottom of the feature (401). The dielectric layer (408) may comprise any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric layer (408) comprises silicon dioxide (SiO2). In one or more embodiments, the dielectric layer is located on the top surface of the epitaxial layer (410).

[0044] In one or more embodiments, CH mixed with diluent gases (e.g., He or Ar), with or without bias, to provide polymer protection. x F y The ICP plasma of is used to deposit a carbon-based polymer layer (414), followed by NH3 / NF3 directional selective plasma cleaning. In one or more embodiments, CH x F yThe gases include methyl fluoride (CH3F), fluoroform (CHF3), hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), methane (CH4), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), ethylene (C2H4), ethane (C2H6), etc., as well as one or more of argon (Ar), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), helium (He), nitrogen (N2), oxygen (O2), carbon monoxide (CO), carbon dioxide (CO2), sulfur hexafluoride (SF6), and hydrogen fluoride (HF). In one or more embodiments, the polymer is deposited on at least one sidewall and bottom surface of the feature (401). In some embodiments, the aspect ratio of the feature (401) is about 2:1, 3:1, 4:1, 5:1, 10:1, or 15:1 or greater. In one or more embodiments, the polymer is deposited with a thickness in the range of about 5 nm to about 30 nm, or in the range of about 8 nm to about 25 nm, or in the range of about 10 nm to about 18 nm.

[0045] In one or more embodiments, since the NH3 / NF3 plasma also etches the carbon-based polymer layer (414), the carbon-based polymer layer (414) may be consumed before reaching the removal (e.g., > 4 nm) of the target entire dielectric layer (408) (e.g., silicon dioxide (SiO2)). In one or more embodiments, a cyclic process of polymer deposition and NH3 / NF3 plasma cleaning may be implemented to always maintain field protection. In one or more embodiments, the plasma cleaning step time is controlled so that the field dielectrics do not come into contact with the NH3 / NF3 plasma.

[0046] Other embodiments include an initial CH for etching silicon dioxide (SiO2) until about 1 nm remains on the top of the epitaxial layer (410). x F yIt relates to the passivation and etching balance of chemicals. Subsequently, in one or more embodiments, there is a transition to ammonia / nitrogen trifluoride (NH3 / NF3) directional selective plasma cleaning to remove the dielectric layer (408) (e.g., silicon dioxide (SiO2)), which is CH x F y It stops perfectly in the epitaxial layer (410) with much better selectivity than chemicals.

[0047] silicidation module.

[0048] FIGS. 6a through 6e illustrate cross-sectional views of a partially manufactured semiconductor device (600) during an etching process according to one or more embodiments. FIG. 7 illustrates a process flowchart for performing an etching process according to various embodiments. The method of FIG. 7 will be described in relation to the partially manufactured device illustrated in FIGS. 6a through 6e. In one or more embodiments, the partially manufactured semiconductor device (600) comprises a metal gate structure (602) which may include one or more of a gate dielectric (e.g., hafnium oxide (HfO2) or other high-k dielectric material), a metal gate (604), and a cap layer (606). A feature (601) is located between the metal gate structures (602). In one or more embodiments, a dielectric layer (608) is located at the bottom of the feature (601). The dielectric layer (608) may comprise any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric layer (608) comprises silicon dioxide (SiO2). In some embodiments, the aspect ratio of the feature (601) is about 2:1, 3:1, 4:1, 5:1, 10:1, or 15:1 or greater. In one or more embodiments, the dielectric layer is on the top surface of the epitaxial layer (610). In one or more embodiments, polymer (614) deposition and NH3 / NF3 plasma cleaning occur in cycles—the plasma cleaning time per cycle is adjusted to maintain a polymer thickness (616) of several nanometers.

[0049] In one or more embodiments, CH x F yThe gases include methyl fluoride (CH3F), fluoroform (CHF3), hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), methane (CH4), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), ethylene (C2H4), ethane (C2H6), etc., as well as one or more of argon (Ar), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), helium (He), nitrogen (N2), oxygen (O2), carbon monoxide (CO), carbon dioxide (CO2), sulfur hexafluoride (SF6), and hydrogen fluoride (HF). In one or more embodiments, the polymer is deposited on at least one sidewall and bottom surface of the feature (601).

[0050] In one or more embodiments, it is necessary to deposit a polymer (614) on the field, but deposition of the polymer at the bottom of the trench is not desirable. In one or more embodiments, RF power pulsing including plasma power of both source and bias, gas flow, pressure, oxygen (O2) or carbon dioxide (CO2) or carbon monoxide (CO), and the addition of diluent gases, as well as advanced level-to-level pulsing, may be used to optimize the polymer deposition process with a minimum coating at the bottom of the trench. In one or more embodiments, level-to-level pulsing demonstrated a thick polymer on the field and a minimal or no inner trench.

[0051] FIGS. 8a through 8c illustrate cross-sectional views of a partially manufactured semiconductor device (800) during an etching process according to one or more embodiments. In one or more embodiments, the partially manufactured semiconductor device (800) comprises a metal gate structure (802) which may include one or more of a gate dielectric (e.g., hafnium oxide (HfO2) or other high-k dielectric material), a metal gate (804), and a cap layer (806). A feature (801) is located between the metal gate structures (802). In one or more embodiments, a dielectric layer (808) is located at the bottom of the feature (801). The dielectric layer (808) may comprise any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric layer (808) comprises silicon dioxide (SiO2). In one or more embodiments, in order to protect the trench shoulders next to the field, the polymer coverage on the shoulder needs to be adjusted accordingly, along with adjustment for the minimum polymer at the bottom of the trench. In one or more embodiments, this includes a two-step polymer deposition process, as illustrated in FIGS. 8a through 8c.

[0052] Referring to FIG. 9, additionally, in one or more embodiments, a polymer stripping process using ICTP with ammonia (NH3) or a mixture of nitrogen (N2) and hydrogen (H2) may be used to remove any polymer residue (862) emitting methane (CH4) (858) and / or hydrogen fluoride (HF) (860) from the wafer and bonding contact trenches (852), which is essential to ensure a pristine epitaxial layer interface before silicide. In one or more embodiments, this may be performed in the same chamber or separate chambers as proposed in the present invention.

[0053] Additional embodiments of the present disclosure relate to processing tools (900) that can be used with one or more of the processing chambers of the embodiments to perform the described methods, as illustrated in FIG. 10.

[0054] The cluster tool (900) includes at least one central transfer station (921, 931) having multiple sides. A robot (925, 935) is positioned within the central transfer station (921, 931) and configured to move a robot blade and a wafer to each of the multiple sides.

[0055] The cluster tool (900) includes a plurality of processing chambers (902, 904, 906, 908, 910, 912, 914, 916, and 918) (also referred to as process stations) connected to a central transfer station. The various processing chambers provide distinct processing areas separated from adjacent process stations. A processing chamber may be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, a transfer space(s), a wafer orienter / degassing chamber, a cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, and a thermal treatment (RTP) chamber, a plasma oxidation chamber, a plasma nitriding chamber, and an atomic layer deposition (ALD) chamber. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0056] In the embodiment illustrated in FIG. 10, a factory interface (950) is connected to the front of a cluster tool (900). The factory interface (950) includes a loading chamber (954) and an unloading chamber (956) on the front (951) of the factory interface (950). Although the loading chamber (954) is shown on the left and the unloading chamber (956) is shown on the right, those skilled in the art will understand that this represents only one possible configuration.

[0057] The size and shape of the loading chamber (954) and the unloading chamber (956) may vary, for example, depending on the substrates processed in the cluster tool (900). In the illustrated embodiment, the loading chamber (954) and the unloading chamber (956) are sized to hold a wafer cassette having a plurality of wafers positioned within the cassette.

[0058] The robot (952) is located within the factory interface (950) and can move between the loading chamber (954) and the unloading chamber (956). The robot (952) can transfer a wafer from a cassette in the loading chamber (954) to the load lock chamber (960) via the factory interface (950). The robot (952) can also transfer a wafer from the load lock chamber (962) to a cassette in the unloading chamber (956) via the factory interface (950). As will be understood by those skilled in the art, the factory interface (950) may have more than one robot (952). For example, the factory interface (950) may have a first robot that transfers wafers between the loading chamber (954) and the load lock chamber (960), and a second robot that transfers wafers between the load lock chamber (962) and the unloading chamber (956).

[0059] The illustrated cluster tool (900) has a first section (920) and a second section (930). The first section (920) is connected to a factory interface (950) via load lock chambers (960, 962). The first section (920) includes a first transfer chamber (921) in which at least one robot (925) is positioned. The robot (925) is also referred to as a robotic wafer transfer mechanism. The first transfer chamber (921) is centrally located relative to the load lock chambers (960, 962), process chambers (902, 904, 916, 918), and buffer chambers (922, 924). In some embodiments, the robot (925) is a multi-arm robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber (921) includes more than one robotic wafer transfer mechanism. A robot (925) within the first transfer chamber (921) is configured to move wafers between chambers surrounding the first transfer chamber (921). Individual wafers are transported on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0060] After processing the wafer in the first section (920), the wafer can be transferred to the second section (930) through a pass-through chamber. For example, the chambers (922, 924) may be unidirectional or bidirectional pass-through chambers. The pass-through chambers (922, 924) may be used to cool the wafer before processing in the second section (930), for example, or to enable wafer cooling or post-processing before moving it back to the first section (920).

[0061] The system controller (990) communicates with the first robot (925), the second robot (935), a plurality of first processing chambers (902, 904, 916, 918), and a plurality of second processing chambers (906, 908, 910, 912, 914). The system controller (990) may be any suitable component capable of controlling the processing chambers and the robots. For example, the system controller (990) may be a computer comprising a central processing unit, memory, suitable circuits, and storage.

[0062] The processes may generally be stored in the memory of the system controller (990) as a software routine that causes the process chamber to perform the processes of the present disclosure when executed by the processor. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Part or all of the method of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed in hardware using a computer system, for example as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor, converts the general-purpose computer to a special-purpose computer (controller) to control the chamber operation so that the processes are performed.

[0063] Spatially relative terms such as “bottom,” “below,” “lower,” “top,” and “upper” may be used herein for ease of description to explain the relationship of one element or feature to other element(s) or feature(s) as exemplified in the drawings. It will be understood that spatially relative terms are intended to include different orientations of the device during use or operation, in addition to the orientations depicted in the drawings. For example, if the device of the drawings is flipped, the elements described as “below” or “bottom” of other elements or features will be oriented “top” of other elements or features. Thus, the exemplary term “below” may include both top and bottom orientations. The device may be oriented differently (rotated 90 degrees or other orientations), and the spatially relative terms used herein are interpreted accordingly.

[0064] In the context describing the materials and methods discussed herein (particularly in the context of the following claims), the use of singular expressions and similar references shall be interpreted to include both singular and plural forms unless otherwise indicated herein or otherwise evident in the context. Unless otherwise indicated herein, references to ranges of values ​​herein are intended merely to serve as a shorthand method for individually referring to each individual value within the range, and each individual value is included in the specification as if each individual value were individually mentioned herein. All methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise evident in the context. Any and all examples provided herein, or the use of exemplary language (e.g., “e.g.,”) are intended merely to make the materials and methods more self-evident and are not limited in scope unless otherwise claimed. No language in this specification shall be interpreted as representing any unclaimed element as essential to the practice of the disclosed materials and methods.

[0065] Throughout this specification, references to “one embodiment,” “specific embodiments,” “one or more embodiments,” or “exemplars” mean that a specific feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Accordingly, the appearance of phrases such as “in one or more embodiments,” “in specific embodiments,” “in one embodiment,” or “in an embodiment” in various places throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, specific features, structures, materials, or features are combined in any suitable manner.

[0066] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments merely illustrate the applications and principles of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

Claim 1 As a processing chamber, a chamber body having a lid defining a processing volume, a bottom wall, and at least one side wall; a nozzle connected to a gas line and fluidly communicating with said processing volume; a gas source located outside the chamber body and fluidly communicating with said gas line - said gas source is CH x F y Includes a gas comprising -; a plurality of coils located on the lead of the chamber body and close to the gas line - the plurality of coils are configured to generate an inductively coupled plasma (ICP) of the gas within the processing volume -; a substrate support including an electrostatic chuck - the electrostatic chuck is configured to generate a capacitively coupled plasma (CCP) of the gas within the gas-processing volume, wherein one of the lead and the electrostatic chuck is connected to an RF power source, and the other of the lead and the electrostatic chuck is connected to an electrical ground to generate plasma within the processing volume -; A controller configured to cause the processing chamber to perform the following operations: an operation of forming a polymer layer on the bottom surface and sidewall of a feature on a substrate by flowing an ICP of gas into the processing volume of the processing chamber ― the feature is located between a first metal gate structure and a second metal gate structure, and the bottom surface of the feature includes a dielectric layer on the top surface of an epitaxial layer ―, and an operation of selectively removing the dielectric layer by flowing a CCP of gas into the processing volume of the processing chamber, the processing chamber comprising Claim 2 A processing chamber according to claim 1, further comprising a heater. Claim 3 A processing chamber according to claim 1, further comprising at least one edge ring on the uppermost surface of the electrostatic chuck. Claim 4 In paragraph 3, a processing chamber further comprising a substrate on the uppermost surface of the electrostatic chuck. Claim 5 In paragraph 4, the processing chamber, wherein the first metal gate structure and the second metal gate structure comprise one or more of a metal gate, a cap layer, and a spacer. Claim 6 A non-transient computer-readable medium containing commands that cause the processing chamber to perform the following operations when executed by a controller of the processing chamber: the operation of flowing gas into the processing volume of the processing chamber — the gas is CH x F y Includes —; an operation of generating an inductively coupled plasma (ICP) of gas within a processing volume; an operation of forming a polymer layer on the bottom surface and sidewall of a feature on a substrate — the feature is located between a first metal gate structure and a second metal gate structure, and the bottom surface of the feature includes a dielectric layer on the top surface of an epitaxial layer —; and an operation of selectively removing the dielectric layer by flowing a capacitively coupled plasma (CCP) of gas within a processing volume of a processing chamber. Claim 7 In claim 6, a non-transient computer-readable medium comprising commands that cause the processing chamber to perform the following additional operations when executed by a controller of the processing chamber: an operation of stripping a polymer layer with an ammonia (NH3) or nitrogen (N2) / hydrogen (H2) plasma. Claim 8 A processing chamber according to claim 1, wherein the gas is selected from one or more of methyl fluoride (CH3F), fluoroform (CHF3), hexafluoro-1,3-butadiene (C4F6), octafluorocyclobutane (C4F8), methane (CH4), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), ethylene (C2H4), ethane (C2H6), argon (Ar), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), helium (He), nitrogen (N2), oxygen (O2), carbon monoxide (CO), carbon dioxide (CO2), sulfur hexafluoride (SF6), and hydrogen fluoride (HF). Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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