Method for monitoring process of semiconductor devices
Patent Information
- Application Number
- KR1020240042564
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2044-03-28
Smart Images

Figure 112024034944037-PAT00005_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a process monitoring method for a semiconductor device, and more specifically, to an invention capable of organically controlling the development time of a photoresist using a monitoring pattern. Background Technology
[0002] Generally, in semiconductor manufacturing processes, circuit patterning techniques utilizing etching processes are used, which have high process difficulty but few restrictions on pattern size and shape.
[0003] For example, in the case of circuit patterning techniques using an etching process, it is a technique that forms semiconductor circuit patterns after selectively removing unnecessary metal parts from a wafer using a liquid or gaseous etchant.
[0004] These etching processes can be classified into wet or dry etching processes depending on the material causing the etching reaction.
[0005] Specifically, dry etching is a method of removing specific parts of a metal using reactive gases, ions, etc., while wet etching is a method of removing specific parts of a metal through a chemical reaction using a solution.
[0006] However, in technology fields such as LEDs or power semiconductors, where devices are large and use high currents, metals such as copper, gold, and platinum, which are thick and difficult to etch, are often used; therefore, a lift-off process is utilized instead of an etching process.
[0007] However, in the case of such a lift-off process, if a sufficient undercut shape is not secured during the photoresist development stage, a metal fence occurs where metal is deposited on the sides of the photoresist during the metal deposition stage.
[0008] When such metal fences are formed, open failures and passivation cracks occur during subsequent metal processes, leading to an increase in the defect rate of semiconductor devices. Prior art literature
[0009] Korean Patent Publication No. KR 10-2008-0073836 A (Method for forming metal wiring of a semiconductor device) The problem to be solved
[0010] Accordingly, the process monitoring method for a semiconductor device according to one embodiment of the disclosed invention is an invention created to solve the problems of the prior art described above, and more specifically, can provide a process monitoring method for a semiconductor device that forms a monitoring pattern in any area of a semiconductor wafer substrate and detects it in real time to control the time at which a development step is performed.
[0011] In addition, a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention can provide a process monitoring method for a semiconductor device that can prevent the formation of a metal fence by measuring the amount of removal of a monitoring pattern over time and sufficiently securing an undercut shape of the photoresist. means of solving the problem
[0012] A process monitoring method for a semiconductor device according to one embodiment of the disclosed invention may include a coating step of applying a photoresist to the surface of a wafer, an exposure step of irradiating light onto the photoresist, a developing step of removing a portion of the photoresist from the wafer using a developer, a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist, and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together.
[0013] The process monitoring method of the semiconductor device described above may further include a step of controlling the time during which the development step is performed by forming a monitoring pattern in any area of the wafer.
[0014] The above monitoring pattern can be formed in the outer region of the wafer during the coating step.
[0015] The above monitoring pattern can be detected in real time, and if the amount of photoresist removed included in the above monitoring pattern is measured to be greater than or equal to a reference value, the above development step can be terminated.
[0016] In order to prevent the occurrence of a metal fence during the deposition step, the time at which the development step is performed for each wafer can be adjusted differently using the monitoring pattern.
[0017] The coating step may include a spin coating step of applying the photoresist to the wafer and then rotating the wafer.
[0018] The above photoresist may be a negative photoresist (Negative PR).
[0019] The photoresist removed in the above development step may be a photoresist that was not irradiated with light in the exposure step.
[0020] A process monitoring method for a semiconductor device according to one embodiment of the disclosed invention comprises a photolithography step of forming a circuit pattern using a photoresist on the surface of a wafer, a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist, and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together, wherein the photolithography step may include a step of forming a monitoring pattern on the wafer.
[0021] The process monitoring method of the semiconductor device described above may further include a step of controlling the time during which the development step is performed by forming a monitoring pattern in any area of the wafer.
[0022] The above monitoring pattern can be formed in the outer region of the wafer during the coating step.
[0023] The process monitoring method of the semiconductor device described above can detect the monitoring pattern in real time and, if the amount of photoresist removed included in the monitoring pattern is measured to be greater than or equal to a reference value, the development step can be terminated.
[0024] The process monitoring method for the semiconductor device described above can use the monitoring pattern to control the time at which the development step is performed differently for each wafer so as to prevent the occurrence of a metal fence during the deposition step included in the photolithography step.
[0025] The above photoresist may be a negative photoresist (Negative PR).
[0026] A process monitoring method for a semiconductor device according to one embodiment of the disclosed invention comprises a coating step of applying a photoresist to the surface of a wafer, an exposure step of irradiating light onto the photoresist, a developing step of removing a portion of the photoresist from the wafer using a developer, a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist, and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together, wherein the coating step may include a step of forming a monitoring pattern in any area of the wafer. Effects of the invention
[0027] A process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of being able to control the time at which a development step is performed by forming a monitoring pattern in any area of a semiconductor wafer substrate and detecting it in real time.
[0028] In addition, the process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of preventing the formation of a metal fence by measuring the amount of removal of a monitoring pattern over time and sufficiently securing the undercut shape of the photoresist.
[0029] In addition, the process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of being able to consistently secure the undercut shape of the photoresist for each wafer regardless of wafer characteristic deviations. Brief explanation of the drawing
[0030] FIG. 1 is a diagram illustrating a state in which a metal fence is formed on a wafer in a semiconductor device process according to the prior art. Figure 2 is a drawing showing an enlarged view of the indicated area of Figure 1. FIG. 3 is a drawing illustrated to exemplarily explain the process of forming a metal fence in a lift-off process according to the prior art. Figure 4 is a photograph showing the state in which a metal fence is formed on a semiconductor wafer. FIG. 5 is a diagram illustrating a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention. FIG. 6 is a drawing showing region A forming a monitoring pattern according to a process monitoring method of a semiconductor device according to one embodiment of the disclosed invention. FIG. 7 is a diagram illustrating a state in which a monitoring pattern changes over time in a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention. FIG. 8 is a drawing illustrating a state in which an undercut shape of a photoresist is precisely realized using a monitoring pattern in a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention. FIG. 9 is a diagram illustrating a comparison between semiconductor metal wiring according to the prior art and semiconductor metal wiring generated according to a process monitoring method of a semiconductor device according to one embodiment of the disclosed invention. Specific details for implementing the invention
[0031] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and various modifications that may replace the embodiments and drawings of this specification may exist at the time of filing this application.
[0032] Additionally, the same reference numerals or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.
[0033] Furthermore, the terms used herein are for describing embodiments and are not intended to limit or / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.
[0034] In this specification, terms such as “comprising” or “having” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and do not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.
[0035] Additionally, terms including ordinal numbers, such as "first," "second," etc., used in this specification may be used to describe various components, but said components are not limited by said terms, and said terms are used solely for the purpose of distinguishing one component from another.
[0036] For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.
[0037] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.
[0039] FIG. 1 is a diagram illustrating a state in which a metal fence is formed on a wafer in a semiconductor device process according to the prior art. FIG. 2 is a diagram illustrating an enlarged view of the indicated area in FIG. 1. FIG. 3 is a diagram illustrating, by way of example, the process of forming a metal fence in a lift-off process according to the prior art. FIG. 4 is a photograph illustrating a state in which a metal fence is formed on a semiconductor wafer.
[0040] Referring to FIGS. 1 to 4, the lift-off process of a semiconductor device process according to the prior art is a process of creating a microstructure on a surface using a sacrificial material.
[0041] For example, a lift-off process of a semiconductor device process according to the prior art is a process of forming a negative pattern of a pattern to be etched on a wafer using a photosensitive polymer, and forming a patterned metal surface by removing the coated photosensitive polymer after depositing a metal.
[0042] However, if the photoresist is not sufficiently removed during the development stage of the photosensitive polymer forming a negative pattern on the wafer, resulting in an incomplete undercut shape, metal is deposited on the sides of the photoresist during the metal deposition stage, causing a metal fence to form.
[0043] The occurrence of such metal fences leads to problems such as open failures and passivation cracks in subsequent metal processes, resulting in an increased defect rate of semiconductor devices.
[0044] In the case of an open failure, it is a phenomenon in which a part that needs to be connected on the wafer is broken, causing electrical defects in the circuit.
[0045] In addition, passivation cracks are a phenomenon in which cracks occur within the protective layer or chip due to the metal fence, causing a break in the circuit.
[0046] Accordingly, the disclosed invention is an invention designed to solve various problems arising from the inability to sufficiently remove photoresist in the prior art.
[0047] A process monitoring method using a monitoring pattern according to the disclosed invention will be described below.
[0049] FIG. 5 is a diagram illustrating a process monitoring method for a semiconductor device according to an embodiment of the disclosed invention. FIG. 6 is a diagram showing region A forming a monitoring pattern according to the process monitoring method for a semiconductor device according to an embodiment of the disclosed invention. FIG. 7 is a diagram illustrating a state in which a monitoring pattern changes over time in the process monitoring method for a semiconductor device according to an embodiment of the disclosed invention. FIG. 8 is a diagram illustrating a state in which an undercut shape of a photoresist is precisely realized using a monitoring pattern in the process monitoring method for a semiconductor device according to an embodiment of the disclosed invention.
[0050] Referring to FIGS. 5 to 8, a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention may include the step (s110) of applying a photoresist to the surface of a wafer.
[0051] More specifically, the step (s110) of applying a photoresist to the surface of a wafer can be referred to as a coating step.
[0052] Additionally, the step of applying a photoresist to the surface of a wafer (s110) may include the step of evenly applying a photoresist (PR), which is a light-sensitive material, to the surface of the wafer.
[0053] Specifically, the step (s110) of applying a photoresist to the surface of a wafer may include a spin coating step of rotating the wafer after applying the photoresist to the wafer.
[0054] For example, the spin coating step may include applying a photoresist on the surface of a substrate and rapidly rotating the wafer in a vacuum to apply the photoresist from the center of the wafer toward the outer edge.
[0055] However, in this spin coating step, the viscosity of the photoresist and the spinner rotational speed of the wafer exist as factors affecting the thickness and uniformity of the photoresist.
[0056] For example, the lower the viscosity of the photoresist and the faster the wafer rotation speed, the thinner the thickness of the photoresist applied to the wafer surface becomes.
[0057] However, when coating photoresist using this spin coating method, the problem of edge beading may occur.
[0058] More specifically, the EDGE BEADING phenomenon is a phenomenon in which photoresist is formed around the edges of a mask pattern.
[0059] Generally, this phenomenon may indicate the formation of photoresist pooling around the edges of the mask pattern due to the failure to properly control the flow of the photoresist.
[0060] In addition, the EDGE BEADING phenomenon is a phenomenon in which the edges of the photoresist are coated thicker than the center during spin coating.
[0061] If this phenomenon occurs, a decrease in pattern precision may occur, which can reduce the accuracy and precision of the mask pattern.
[0062] In addition, EDGE BEADING forms an improper photoresist layer at the edges of the mask pattern, which can cause problems with attachment and connection of parts in subsequent processes.
[0063] In addition, if EDGE BEADING occurs, the repeatability of the process may be reduced, and there is a problem in that it is difficult to obtain consistent results.
[0064] Therefore, in the case of the disclosed invention, there is a technical effect of being able to suppress problems caused by EDGE BEADING and the associated metal fence formation by using the monitoring pattern described below.
[0065] Subsequently, a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention may include a step (S120) of irradiating light onto a photoresist coated on a wafer.
[0066] More specifically, the step (S120) of irradiating light onto the photoresist applied to the wafer can be referred to as an exposure step.
[0067] Specifically disclosed invention may include a step of designing a circuit to be drawn on a wafer using a computer-aided design (CAD) system prior to the photolithography step.
[0068] This drawing, designed as an electronic circuit pattern, contains precision circuits designed by engineers, and that precision determines the integration density of the semiconductor.
[0069] Afterwards, the designed circuit pattern is reborn as a photomask by forming a microcircuit with chromium (Cr) on a substrate made by processing high-purity quartz.
[0070] A mask, also called a reticle, is a film that preserves the circuit pattern intact and functions as a base plate.
[0071] For example, the mask can be manufactured larger than the semiconductor circuit for finer patterning.
[0072] The step of irradiating light onto the photoresist coated on the wafer (S120) can pattern the circuit designed on the photoresist of the wafer by using an exposure device (Stepper) to pass light through a mask containing a circuit pattern.
[0073] This process is called stepper exposure, and in semiconductor manufacturing, stepper exposure can be defined as the process of selectively irradiating light.
[0074] In addition, the monitoring pattern of the disclosed invention can be formed on a wafer during the exposure step.
[0075] More specifically, the process monitoring method of a semiconductor device disclosed in the present invention can control the time during which a development step is performed by forming a monitoring pattern in any area of a wafer.
[0076] Specifically, the exposure step of the process monitoring method for a semiconductor device of the disclosed invention may include the step of forming a monitoring pattern on an outer region of a wafer.
[0077] As illustrated in FIG. 6, the process monitoring method of the semiconductor device of the disclosed invention can design the outermost portion, which is an unused space where the device is not patterned on a wafer substrate, and form a monitoring pattern in this space.
[0078] For example, the monitoring pattern may include a photoresist, and the photoresist included in the monitoring pattern may not be irradiated with light during the exposure step.
[0079] The subsequent process regarding monitoring patterns will be described later.
[0080] Subsequently, a process monitoring method for a semiconductor device according to one embodiment of the disclosed invention may include a step (S130) of removing a portion of the photoresist from a wafer using a developer.
[0081] The step (S130) of removing a portion of the photoresist from the wafer can be named a developing step.
[0082] More specifically, the developing process is a process of forming a circuit pattern by spraying a developer onto a wafer and selectively removing exposed or unexposed areas.
[0083] Photoresist (PR) uniformly coated on a wafer can be classified as positive or negative depending on how it reacts to light.
[0084] In the case of positive photoresist, unexposed areas remain during the development stage, while in the case of negative photoresist, exposed areas remain during the development stage.
[0085] The process monitoring method for a semiconductor device according to the disclosed invention is limited to semiconductor fields used in applications where the device size is large and high current is used, and metal is etched according to the lift-off process.
[0086] Accordingly, the photoresist used in the process monitoring method of a semiconductor device according to the disclosed invention may be composed of a negative photoresist.
[0087] In the step (S130) of removing a portion of the photoresist from the wafer, the disclosed invention may include a step (S140) of adjusting the development time by detecting a change in the monitoring pattern in real time.
[0088] The step (s140) of detecting a change in the monitoring pattern in real time and adjusting the development time may include a step of measuring in real time the amount of photoresist of the monitoring pattern removed during the development step and determining the time to end the development step accordingly.
[0089] More specifically, the process monitoring method of the disclosed invention may include an electronic measuring device.
[0090] For example, the electronic measuring device of the disclosed invention may include a shooting unit for capturing a monitoring pattern, a calculation unit for detecting the degree of removal of the monitoring pattern based on the captured image and calculating the removal amount, and a notification unit for notifying the user when the removal amount of the monitoring pattern reaches a set reference value.
[0091] Accordingly, the process monitoring method for a semiconductor device according to the disclosed invention has the technical effect of precisely measuring the amount of removal of a monitoring pattern using an electronic measuring device and, based thereon, securing an undercut shape of the photoresist in the outer region of the wafer coated with a thickness similar to that of the monitoring pattern.
[0092] In addition, the process monitoring method for a semiconductor device according to the disclosed invention can adjust the time at which the development step is performed differently for each wafer using the aforementioned monitoring pattern so as to prevent the occurrence of a metal fence in the deposition step to be described later.
[0093] Subsequently, the process monitoring method for a semiconductor device according to the disclosed invention may include the step (S150) of applying a metal thin film to the surface of a wafer and a residual photoresist.
[0094] More specifically, the step (S150) of applying a metal thin film to the surface of the wafer and the remaining photoresist can be referred to as a deposition step.
[0095] Metal deposition in semiconductor manufacturing refers to the process of depositing metal onto a semiconductor substrate to form electrical connections within a semiconductor chip or to implement various functions.
[0096] In the case of the photoresist according to the disclosed invention, as it is composed of a negative photoresist, the upper part where light is irradiated hardens more strongly than the lower part, and accordingly, the shape of the remaining photoresist after the development step may have a shape in which the width narrows from the upper part to the lower part.
[0097] Accordingly, the undercut shape of the photoresist according to the disclosed invention can be implemented in a shape where the thin film deposited on the portion to be formed with a metal pattern and the thin film formed on the photoresist can be separated from each other, thereby having the advantage of being implemented with a simpler process.
[0098] Subsequently, the process monitoring method of a semiconductor device according to the disclosed invention may include a step (S160) of removing the residual photoresist and the metal thin film applied to the surface of the residual photoresist together.
[0099] More specifically, the step (S160) of removing the metal thin film applied to the surface of the residual photoresist together can be named a lift-off step.
[0100] Specifically, in fields such as LEDs and power semiconductors where devices are large and high currents are used, materials that are thick and resistant to etching (such as Cu, Au, and Pt) are often utilized.
[0101] Therefore, in these fields, the lift-off process of the disclosed invention is mainly used instead of the dry etching process of metal.
[0102] In addition, as described above, the disclosed invention detects the amount of removal of a monitoring pattern in real time and terminates the development step when the amount of removal of the monitoring pattern is greater than or equal to a preset threshold value, thereby ensuring a sufficient undercut shape of the photoresist and consequently providing a technical effect in which a metal fence may not be generated during the deposition process.
[0103] In addition, as illustrated in FIGS. 7 and 8, the disclosed invention can detect the amount of removal of the monitoring pattern by measuring the change in the monitoring pattern over time in real time.
[0104] In addition, the step of applying the aforementioned photoresist to the surface of a wafer, irradiating light onto the photoresist, removing a portion of the photoresist from the wafer using a developer, and adjusting the execution time of the development step by detecting changes in the monitoring pattern in real time can be collectively referred to as a photolithography step of forming a circuit pattern on the surface of a wafer using photoresist.
[0105] In addition, the photolithography step of forming a circuit pattern using photoresist on the surface of the wafer described above, the deposition step of applying a metal thin film, and the lift-off step of removing the photoresist may be collectively referred to as the lift-off process.
[0107] FIG. 9 is a diagram illustrating a comparison between semiconductor metal wiring according to the prior art and semiconductor metal wiring generated according to a process monitoring method of a semiconductor device according to one embodiment of the disclosed invention.
[0108] Referring to FIG. 9, as shown in FIG. 9 (a), in the case of semiconductor metal wiring produced using a lift-off process according to the prior art, it can be seen that inconsistent wiring is formed due to the insufficient formation of the undercut shape, which causes metal fences to form.
[0109] However, as shown in Fig. 9(b), in the case of semiconductor metal wiring generated according to the process monitoring method of the semiconductor device of the disclosed invention, it can be confirmed that a uniform metal wiring is formed by ensuring a sufficient undercut shape in the development (DEVELOP) stage through the monitoring pattern, so that metal fences are not formed during metal deposition.
[0110] A process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of being able to control the time at which a development step is performed by forming a monitoring pattern in any area of a semiconductor wafer substrate and detecting it in real time.
[0111] In addition, the process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of preventing the formation of a metal fence by measuring the amount of removal of a monitoring pattern over time and sufficiently securing the undercut shape of the photoresist.
[0112] In addition, the process monitoring method for a semiconductor device according to one embodiment of the disclosed invention has the advantage of being able to consistently secure the undercut shape of the photoresist for each wafer regardless of wafer characteristic deviations.
[0113] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on the operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.
[0114] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.
[0115] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.
[0116] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims.
Claims
Claim 1 A method for process monitoring of a semiconductor device, characterized by comprising: a coating step of applying a photoresist (PR) to the surface of a wafer; an exposure step of irradiating light onto the photoresist; a developing step of removing a portion of the photoresist from the wafer using a developing solution; a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist; and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together. Claim 2 A method for process monitoring of a semiconductor device, characterized by further including the step of forming a monitoring pattern in any area of the wafer according to claim 1 to control the time during which the lift-off step is performed. Claim 3 A method for process monitoring of a semiconductor device according to paragraph 2, characterized in that the monitoring pattern is formed in the outer region of the wafer during the coating step. Claim 4 A method for monitoring the process of a semiconductor device according to claim 2, characterized in that the above-mentioned monitoring pattern is detected in real time, and when the amount of photoresist removed included in the above-mentioned monitoring pattern is measured to be greater than or equal to a reference value, the above-mentioned development step is terminated. Claim 5 A process monitoring method for a semiconductor device according to claim 4, characterized by using the monitoring pattern to control the time at which the development step is performed differently for each wafer so as to prevent the occurrence of a metal fence during the deposition step. Claim 6 A method for process monitoring of a semiconductor device according to claim 1, wherein the coating step comprises a spin coating step of applying the photoresist to the wafer and then rotating the wafer. Claim 7 A method for process monitoring of a semiconductor device, characterized in that, in claim 1, the photoresist is a negative photoresist (Negative PR). Claim 8 A method for process monitoring of a semiconductor device according to claim 7, characterized in that the photoresist removed in the development step is a photoresist that has not been irradiated with light in the exposure step. Claim 9 A process monitoring method for a semiconductor device, comprising: a photolithography step of forming a circuit pattern using a photoresist on the surface of a wafer; a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist; and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together, wherein the photolithography step comprises a step of forming a monitoring pattern on the wafer. Claim 10 A method for process monitoring of a semiconductor device, characterized by further including, in claim 9, a step of forming a monitoring pattern in any area of the wafer and controlling the time during which the forming step is performed. Claim 11 A method for process monitoring of a semiconductor device according to claim 10, characterized in that the monitoring pattern is formed in the outer region of the wafer during the photolithography step. Claim 12 A method for process monitoring of a semiconductor device according to claim 10, characterized in that, when the amount of photoresist removed included in the monitoring pattern is measured to be greater than or equal to a reference value by detecting the monitoring pattern in real time, the forming step is terminated. Claim 13 A process monitoring method for a semiconductor device according to claim 9, characterized by using the monitoring pattern to control the time at which the development step is performed differently for each wafer so as to prevent the occurrence of a metal fence in the deposition step included in the photolithography step. Claim 14 A method for process monitoring of a semiconductor device, characterized in that, in claim 9, the photoresist is a negative photoresist (Negative PR). Claim 15 A method for process monitoring of a semiconductor device, comprising: a coating step of applying a photoresist to the surface of a wafer; an exposure step of irradiating light onto the photoresist; a developing step of removing a portion of the photoresist from the wafer using a developing solution; a deposition step of applying a metal thin film to the surface of the wafer and the remaining photoresist; and a lift-off step of removing the remaining photoresist and the metal thin film applied to the surface of the photoresist together; wherein the coating step comprises a step of forming a monitoring pattern in any area of the wafer.
Citation Information
Patent Citations
Photoresist pattern generation method and Method for forming Metallization using the same
KR1020130122870A
Patterning process
KR1020210150868A
Dual coating and lift-off method for protecting patterned dielectric-metal coatings
US20160307750A1