Package substrate and semiconductor package incuding the same

Abstract

The technical concept of the present invention comprises a base insulating layer including a first surface and a second surface opposite to each other; a first main line pattern provided on the first surface of the base insulating layer; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and extending between the first main line pattern and the plurality of first conductive pads; and a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through-grooves spaced apart from the first main line pattern; wherein each of the plurality of first branch line patterns includes a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through-grooves are superimposed on the first cut portions of the plurality of first branch line patterns to provide a package substrate.

Description

Technology Field

[0001] The technical concept of the present invention relates to a package substrate and a semiconductor package including the same. Background Technology

[0002] Generally, semiconductor packages are manufactured by mounting semiconductor chips on printed circuit boards and molding them with molding resin. Recently, to improve the productivity of semiconductor package manufacturing, semiconductor packages are manufactured by mounting multiple semiconductor chips on a panel-shaped substrate in which multiple printed circuit boards are connected, molding the multiple semiconductor chips with molding resin, and then cutting the multiple printed circuit boards to separate them into individual units. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a package substrate and a semiconductor package including the same. means of solving the problem

[0004] To solve the above-mentioned problem, the technical concept of the present invention comprises: a base insulating layer including a first surface and a second surface opposite to each other; a first main line pattern provided on the first surface of the base insulating layer; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and extending between the first main line pattern and the plurality of first conductive pads; and a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through-grooves spaced apart from the first main line pattern; wherein each of the plurality of first branch line patterns includes a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through-grooves are superimposed on the first cut portions of the plurality of first branch line patterns to provide a package substrate.

[0005] To solve the above-mentioned problem, the technical concept of the present invention comprises: a base insulating layer including a first surface and a second surface opposite to each other; a first main line pattern provided on the first surface of the base insulating layer and extending in a first direction; a plurality of first conductive pads provided on the first surface of the base insulating layer; and a plurality of first branch line patterns provided on the first surface of the base insulating layer and extending between the first main line pattern and the plurality of first conductive pads. The package substrate comprises: a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through-grooves; wherein contact points between the plurality of first branch line patterns and the first main line pattern are spaced apart along the first direction, and the plurality of first branch line patterns each include a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through-grooves overlap the first cut portions of the plurality of first branch line patterns, and among the plurality of first through-grooves, two first through-grooves adjacent in the first direction are spaced apart in a second direction perpendicular to the first direction with the first main line pattern in between from a planar perspective.

[0006] To solve the above-mentioned problem, the technical concept of the present invention comprises: a package substrate; and a semiconductor chip mounted on the package substrate; wherein the package substrate comprises: a base insulating layer including a first surface and a second surface opposite to each other; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and connected to the plurality of first conductive pads; and a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through-grooves; wherein the plurality of first branch line patterns each include a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through-grooves provide a semiconductor package superimposed on the first cut portions of the plurality of first branch line patterns. Effects of the invention

[0007] According to exemplary embodiments of the present invention, damage to the package substrate can be prevented, thereby improving the reliability of the package substrate and the reliability of the semiconductor package manufactured using the package substrate. Brief explanation of the drawing

[0008] FIG. 1 is a layout diagram showing a package substrate according to exemplary embodiments of the present invention. Figure 2 is a bottom view of a package substrate showing the area marked "II" in Figure 1. Figure 3 is a cross-sectional view of a package substrate along the line III-III' of Figure 1. FIGS. 4a to 4e are cross-sectional views illustrating a method for manufacturing a package substrate according to exemplary embodiments of the present invention. FIGS. 5a to 5h are bottom views showing package substrates according to exemplary embodiments of the present invention. FIGS. 6a and FIGS. 6b are cross-sectional views showing package substrates according to exemplary embodiments of the present invention. FIG. 7 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Figure 8 is a bottom view showing a part of the semiconductor package of Figure 7. FIGS. 9a to 9c are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments of the present invention. FIGS. 10a through 10f are bottom views showing semiconductor packages according to exemplary embodiments of the present invention. FIG. 10g is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0010] FIG. 1 is a layout diagram showing a package substrate (10) according to exemplary embodiments of the present invention. FIG. 2 is a bottom view of the package substrate (10) showing the area marked "II" in FIG. 1. FIG. 3 is a cross-sectional view of the package substrate (10) along the line III-III' in FIG. 1.

[0011] Referring to FIGS. 1 to 3, a package substrate (10) may include a first region (R1) and a second region (R2) that are separated or partitioned from each other in a planar view. The package substrate (10) may include one or more first regions (R1), and the first region (R1) may be an area on which electronic components, such as a semiconductor chip (210), are mounted. As shown in FIG. 1, the first region (R1) may have a rectangular shape in a planar view, but is not limited thereto, and the first region (R1) may have a polygonal shape, such as a pentagon, or a circle shape in a planar view. The second region (R2) may surround the first region (R1) in a planar view. That is, the second region (R2) may extend along the edge of the first region (R1) in a planar view. The second region (R2) may include a scribe lane (SL) that is removed through a cutting process. As illustrated in FIG. 1, the package substrate (10) may include a plurality of first regions (R1) and a second region (R2) that separates the plurality of first regions (R1) from each other. The arrangement and number of the plurality of first regions (R1) shown in FIG. 1 are exemplary, and the plurality of first regions (R1) may be arranged in a two-dimensional array form having two or more rows and two or more columns.

[0012] The package substrate (10) may include a base insulating layer (111), a first insulating layer (120), a second insulating layer (130), an internal wiring structure (115), a plurality of first conductive pads (141), a plurality of first conductive cover layers (145), a first main line pattern (150), and a plurality of first branch line patterns (160).

[0013] The base insulating layer (111) may generally have a flat plate or panel shape. The base insulating layer (111) may include a first surface (1111) and a second surface (1113) opposite each other, and the first surface (1111) and the second surface (1113) may each be flat. Hereinafter, a direction parallel to the first surface (1111) or the second surface (1113) of the base insulating layer (111) is defined as a horizontal direction (e.g., X direction and / or Y direction), and a direction perpendicular to the first surface (1111) or the second surface (1113) of the base insulating layer (111) is defined as a vertical direction (e.g., Z direction). Additionally, hereinafter, the horizontal width of any component may refer to a length along the horizontal direction (e.g., X direction and / or Y direction), and the vertical height or thickness of any component may refer to a length along the vertical direction (e.g., Z direction).

[0014] The base insulating layer (111) may include at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the base insulating layer (111) may include at least one material selected from polyimide, FR-4 (Flame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, and liquid crystal polymer.

[0015] A first insulating layer (120) may be provided on a first surface (1111) of a base insulating layer (111). The first insulating layer (120) may extend along the first surface (1111) of the base insulating layer (111) and cover the first surface (1111) of the base insulating layer (111). For example, the first insulating layer (120) may be formed of a solder resist.

[0016] A second insulating layer (130) may be provided on a second surface (1113) of a base insulating layer (111). The second insulating layer (130) may extend along the second surface (1113) of the base insulating layer (111) and cover the second surface (1113) of the base insulating layer (111). For example, the second insulating layer (130) may be formed of a solder resist.

[0017] The internal wiring structure (115) may include a conductive layer provided inside the base insulating layer (111), a conductive layer provided on a first surface (1111) and / or a second surface (1113) of the base insulating layer (111), and / or a conductive via extending in a vertical direction (e.g., Z direction) within the base insulating layer (111). The conductive via may be connected to the conductive layer provided inside the base insulating layer (111) and / or the conductive layer provided on the first surface (1111) and / or the second surface (1113) of the base insulating layer (111). The internal wiring structure (115) may be electrically connected to a plurality of first conductive pads (141), a first main line pattern (150), and / or a plurality of first branch line patterns (160).

[0018] A plurality of first conductive pads (141) may be provided on a first surface (1111) of a base insulating layer (111). A plurality of first conductive pads (141) may be positioned to overlap with first pad openings (129) of the first insulating layer (120). A plurality of first conductive pads (141) may function as pads to which connecting members (e.g., conductive bumps, conductive wires, solder balls) for electrical and physical connection between the package substrate (10) and other electronic components are attached. A plurality of first conductive pads (141) may be disposed within a first region (R1) of the package substrate (10).

[0019] For example, a plurality of first conductive pads (141) may include metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or alloys thereof.

[0020] A plurality of first conductive cover layers (145) may extend along the surface of a plurality of first conductive pads (141). A plurality of first conductive cover layers (145) may be disposed within a first pad opening (129) of a first insulating layer (120). A plurality of first conductive cover layers (145) may be barrier layers configured to cover a plurality of first conductive pads (141) to prevent oxidation and / or damage to the plurality of first conductive pads (141).

[0021] For example, a plurality of first conductive cover layers (145) may include nickel (Ni), gold (Au), palladium (Pd), or a combination thereof. For example, a plurality of first conductive cover layers (145) may be formed through an electroplating process.

[0022] A first main line pattern (150) is provided on a first surface (1111) of a base insulating layer (111) and may extend along the first surface (1111) of the base insulating layer (111). For example, the first main line pattern (150) may extend linearly along the first surface (1111) of the base insulating layer (111) in a planar view. The first main line pattern (150) may be placed within a second region (R2) of a package substrate (10) between first regions (R1) of adjacent package substrates (10). In exemplary embodiments, the first main line pattern (150) may be placed within a scribe lane (SL) within the second region (R2) of the package substrate (10) and may extend along the extension direction (e.g., X direction and / or Y direction) of the scribe lane (SL) within the second region (R2) of the package substrate (10). When the first main line pattern (150) is placed within the scribe lane (SL), the first main line pattern (150) can be removed during the cutting process for the package substrate (10). The first main line pattern (150) may include a conductive material. For example, the material of the first main line pattern (150) may be substantially the same or similar to the material of the plurality of first conductive pads (141) described above.

[0023] The horizontal width (W1) of the first main line pattern (150) may be generally uniform. In exemplary embodiments, the horizontal width (W1) of the first main line pattern (150) may be between 15 micrometers (μm) and 150 μm, or between 30 μm and 100 μm.

[0024] A plurality of first branch line patterns (160) may extend between a first main line pattern (150) and a plurality of first conductive pads (141). A first end of each of the plurality of first branch line patterns (160) may be in contact with the first main line pattern (150), and a second end of each of the plurality of first branch line patterns (160) may be connected to a corresponding first conductive pad (141) among the plurality of first conductive pads (141). In a planar view, each of the plurality of first branch line patterns (160) may have a line shape extending from the first main line pattern (150) to a corresponding first conductive pad (141) among the plurality of first conductive pads (141). In exemplary embodiments, the first main line pattern (150) and the plurality of first branch line patterns (160) may be used as paths through which electricity is applied during an electroplating process to form a plurality of first conductive cover layers (145). A plurality of first branch line patterns (160) may include a conductive material. For example, the material of the plurality of first branch line patterns (160) may be substantially the same or similar to the material of the first main line pattern (150) and / or the material of the plurality of first conductive pads (141).

[0025] The horizontal width (W2) of each of the plurality of first branch line patterns (160) may be generally uniform. In exemplary embodiments, the horizontal width (W2) of each of the plurality of first branch line patterns (160) may be substantially the same or similar to the horizontal width (W1) of the first main line pattern (150). In exemplary embodiments, the horizontal width (W2) of each of the plurality of first branch line patterns (160) may be between 15 μm and 150 μm, or between 30 μm and 100 μm.

[0026] As illustrated in FIG. 3, when the first main line pattern (150) is extended in a first horizontal direction (e.g., Y direction), contact points between a plurality of first branch line patterns (160) and the first main line pattern (150) may be spaced apart from each other in the first horizontal direction (e.g., Y direction). Additionally, as illustrated in FIG. 3, some of the plurality of first branch line patterns (160) may be connected to first conductive pads (141) in a first region (R1) of the package substrate (10) located on one side (e.g., left) of the first main line pattern (150), and other parts of the plurality of first branch line patterns (160) may be connected to first conductive pads (141) in a first region (R1) of the package substrate (10) located on the other side (e.g., right) of the first main line pattern (150).

[0027] The first insulating layer (120) may include a plurality of first through-grooves (121) superimposed on the extension paths of a plurality of first branch line patterns (160) in a planar view. The plurality of first through-grooves (121) may be positioned adjacent to the scribe lane (SL) and spaced laterally from the first main line pattern (150). The plurality of first through-grooves (121) may penetrate the first insulating layer (120) in a vertical direction (e.g., Z direction), and a portion of the first surface (1111) of the base insulating layer (111) may be exposed through the plurality of first through-grooves (121). As illustrated in FIG. 3, the plurality of first through-grooves (121) may each have a rectangular shape in a planar view. Alternatively, the plurality of first through-grooves (121) may have a polygonal shape, such as a pentagon, or a circular shape.

[0028] Each of the plurality of first through-grooves (121) may have a first horizontal width (L1) in a first horizontal direction (e.g., Y direction) that is the extension direction of the first main line pattern (150) and a second horizontal width (L2) in a second horizontal direction (e.g., X direction) perpendicular to the first horizontal direction. In exemplary embodiments, the first horizontal width (L1) of each of the plurality of first through-grooves (121) may be larger than the horizontal width (W2) of each of the plurality of first branch line patterns (160). In exemplary embodiments, the first horizontal width (L1) of each of the plurality of first through-grooves (121) may be 80 μm to 12 millimeters (mm). In exemplary embodiments, the second horizontal width (L2) of each of the plurality of first through-grooves (121) may be 80 μm to 400 μm.

[0029] In exemplary embodiments, the distance (D1) between the two first through-grooves (121) closest in the first horizontal direction (e.g., Y direction) among the plurality of first through-grooves (121) may be 12 mm or less. Here, the two first through-grooves (121) closest in the first horizontal direction (e.g., Y direction) among the plurality of first through-grooves (121) may refer to the two first through-grooves (121) closest in the distance between their centers along the first horizontal direction (e.g., Y direction) in a planar view. In some embodiments, the two first through-grooves (121) closest in the first horizontal direction (e.g., Y direction) may partially overlap in the second horizontal direction (e.g., X direction) in a planar view.

[0030] In exemplary embodiments, a plurality of first through-grooves (121) may each partially overlap the scribe lane (SL) in a planar view. That is, a portion of each of the plurality of first through-grooves (121) may be within the scribe lane (SL), and another portion of each of the plurality of first through-grooves (121) may be outside the scribe lane (SL). When a portion of the package substrate (10) corresponding to the scribe lane (SL) is removed through a cutting process on the package substrate (10), the plurality of first through-grooves (121) may be exposed through the cut surface.

[0031] A plurality of first branch line patterns (160) may each include a first segment (161) and a second segment (163) spaced apart with a first cut portion (165) in between. Since a plurality of first branch line patterns (160) each have a first cut portion (165), the plurality of first branch line patterns (160) may have a discontinuously extended line shape. The first segment (161) may be connected to a first main line pattern (150), and the second segment (163) may be connected to a corresponding first conductive pad (141) among a plurality of first conductive pads (141). A plurality of first through grooves (121) of the first insulating layer (120) may overlap with the first cut portions (165) of the plurality of first branch line patterns (160). For example, a first cut portion (165) of any one of the plurality of first branch line patterns (160) may overlap with a corresponding first through-groove (121) among the plurality of first through-groos (121). For example, to form the first cut portions (165) in the plurality of first branch line patterns (160), a plurality of conductive line patterns constituting the plurality of first branch line patterns (160) may be formed, and then parts of the plurality of conductive line patterns exposed through the plurality of first through-groos (121) of the first insulating layer (120) may be removed by an etching process.

[0032] As illustrated in FIG. 3, a plurality of first through-grooves (121) are arranged in a first horizontal direction (e.g., Y direction) and may be arranged in an asymmetrical or zigzag shape from a planar perspective. In exemplary embodiments, two first through-grooves (121) adjacent to each other in the first horizontal direction (e.g., Y direction) among the plurality of first through-grooves (121) may be offset in the first horizontal direction (e.g., Y direction) and the second horizontal direction (e.g., X direction). At this time, two first through-grooves (121) adjacent to each other in the first horizontal direction (e.g., Y direction) among the plurality of first through-grooves (121) may be spaced apart from each other with the first main line pattern (150) in between.

[0033] FIGS. 4a to 4e are cross-sectional views illustrating a method for manufacturing a package substrate (10) according to exemplary embodiments of the present invention. Hereinafter, with reference to FIGS. 4a to 4e, the method for manufacturing a package substrate (10) described with reference to FIGS. 1 to 3 will be explained.

[0034] Referring to FIG. 4a, a panel-shaped structure is prepared. The structure may include a base insulating layer (111), a first insulating layer (120), a second insulating layer (130), an internal wiring structure (115), a plurality of first conductive pads (141), a first main line pattern (150), and a plurality of first preliminary branch line patterns (169).

[0035] Referring to FIG. 4b, a plurality of first conductive cover layers (145) are formed on a plurality of first conductive pads (141). The plurality of first conductive cover layers (145) may be formed to cover the surfaces of the plurality of first conductive pads (141) exposed through the pad openings of the first insulating layer (120). The plurality of first conductive cover layers (145) may be formed through an electroplating process. When the electroplating process is performed, power for electroplating may be provided to the plurality of first conductive pads (141) through an electrical connection path passing through a first main line pattern (150) and a plurality of first branch line patterns (160).

[0036] Referring to FIG. 4c, a portion of the first insulating layer (120) is removed to form a plurality of first through-grooves (121) that expose a plurality of first preliminary branch line patterns (169) in the first insulating layer (120). For example, a plurality of first through-grooves (121) can be formed in the first insulating layer (120) through methods such as laser drilling or etching.

[0037] Referring to FIGS. 4c and 4d, a plurality of first preliminary branch line patterns (169) exposed through a plurality of first through-grooves (121) are removed to form a plurality of first branch line patterns (160). For example, a portion of a plurality of first preliminary branch line patterns (169) exposed through a plurality of first through-grooves (121) can be removed through an etching process. As a portion of a plurality of first preliminary branch line patterns (169) exposed through a plurality of first through-grooves (121) is removed, a first segment (161) extending from a first main line pattern (150) and a second segment (163) extending from a corresponding first conductive pad (141) among a plurality of first conductive pads (141) are separated from each other by a first cut portion (165).

[0038] Referring to FIG. 4e, an electrical test is performed on the package substrate (10). For example, an electrical test on the package substrate (10) can be performed by contacting a probe (PB) to at least one of the plurality of first conductive pads (141). Since the plurality of first branch line patterns (160) are formed to each have a first cut portion (165), the plurality of first conductive pads (141) are not electrically connected to each other through the plurality of first branch line patterns (160) and the first main line pattern (150). Since the plurality of first conductive pads (141) are not electrically connected to each other through the plurality of first branch line patterns (160) and the first main line pattern (150), an electrical test on the package substrate (10) can be performed by contacting a probe (PB) to the plurality of first conductive pads (141).

[0039] FIGS. 5a to 5h are bottom views showing package substrates (11, 12, 13, 14, 15, 16, 17, 18) according to exemplary embodiments of the present invention. Hereinafter, the package substrates (11, 12, 13, 14, 15, 16, 17, 18) shown in FIGS. 5a to 5h will be described with a focus on the differences from the package substrate (10) described with reference to FIGS. 1 to 3.

[0040] Referring to FIG. 5a, a plurality of first through-holes (121) may be located outside the scribe lane (SL). During the cutting process for the package substrate (11), the plurality of first through-holes (121) located outside the scribe lane (SL) are not removed, and the plurality of first through-holes (121) may remain within the first insulating layer (120) even after the cutting process.

[0041] Referring to FIG. 5b, each of the plurality of first through-grooves (121) may have their entirety inside the scribe lane (SL). That is, from a planar perspective, each of the plurality of first through-grooves (121) may have their entirety overlapping the scribe lane (SL). The plurality of first through-grooves (121) inside the scribe lane (SL) may be removed through a cutting process on the package substrate (12).

[0042] Referring to FIG. 5c, the first through-grooves (121) on one side (e.g., left) of the first main line pattern (150) may have an asymmetric or zigzag arrangement, and the first through-grooves (121) on the other side (e.g., right) of the first main line pattern (150) may have an asymmetric or zigzag arrangement. In other words, some of the first through-grooves (121) on one side of the first main line pattern (150) may be offset in a second horizontal direction (e.g., X direction), and some of the first through-grooves (121) on the other side of the first main line pattern (150) may be offset in a second horizontal direction (e.g., X direction).

[0043] In exemplary embodiments, at least one of the first through-grooves (121) on one side of the first main line pattern (150) may be at least partially overlapping the scribe lane (SL), and at least another of the first through-grooves (121) on one side of the first main line pattern (150) may be outside the scribe lane (SL). Additionally, at least one of the first through-grooves (121) on the other side of the first main line pattern (150) may be at least partially overlapping the scribe lane (SL), and at least another of the first through-grooves (121) on the other side of the first main line pattern (150) may be outside the scribe lane (SL). When a portion of the package substrate (13) corresponding to the scribe lane (SL) is removed through a cutting process on the package substrate (13), the first through-grooves (121) that overlap at least partially with the scribe lane (SL) may be removed in whole or in part.

[0044] Referring to FIG. 5d, the first through-grooves (121) located on one side (e.g., left) of the first main line pattern (150) may have an asymmetric or zigzag arrangement, and the first through-grooves (121) located on the other side (e.g., right) of the first main line pattern (150) may have an asymmetric or zigzag arrangement. In this case, the first through-grooves (121) located on one side of the first main line pattern (150) and the first through-grooves (121) located on the other side of the first main line pattern (150) may both be outside the scribe lane (SL). In this case, the plurality of first through-grooves (121) located outside the scribe lane (SL) are not removed by the cutting process for the package substrate (14), and the plurality of first through-grooves (121) may remain within the first insulating layer (120) even after the cutting process.

[0045] Referring to FIG. 5e, the first insulating layer (120) has a groove (127) disposed adjacent to a scribe lane (SL) area, and the package substrate (15) may include a conductive pattern (119) exposed to the outside through the groove (127) of the first insulating layer (120). The conductive pattern (119) may be provided on a first surface (1111 in FIG. 2) of a base insulating layer (111 in FIG. 2). The conductive pattern (119) may be a pattern configured to transmit an input / output data signal, a power signal, and / or a ground signal provided to the package substrate (15).

[0046] Referring to FIG. 5f, the first insulating layer (120) may include one or more bridge grooves (123) extending between some of the first through grooves (121). The bridge grooves (123) penetrate the first insulating layer (120), and a portion of the first surface (1111) of the base insulating layer (111) may be exposed through the bridge grooves (123). For example, the bridge grooves (123) may extend linearly in a planar view. For example, the bridge grooves (123) may extend in a direction parallel to the extension direction of the first main line pattern (150).

[0047] In exemplary embodiments, first through-grooves (121) on one side (e.g., left) of the first main line pattern (150) may be interconnected through bridge grooves (123), and first through-grooves (121) on the other side (e.g., right) of the first main line pattern (150) may be interconnected through bridge grooves (123). In this case, as illustrated in FIG. 5f, from a planar perspective, the first insulating layer (120) may include a trench that extends linearly in a direction parallel to the extension direction of the first main line pattern (150).

[0048] In exemplary embodiments, a plurality of first through-grooves (121) and a plurality of bridge grooves (123) may each partially overlap the scribe lane (SL) in a planar view. When a portion of the package substrate (16) corresponding to the scribe lane (SL) is removed through a cutting process on the package substrate (16), the plurality of first through-grooves (121) and a plurality of bridge grooves (123) may be exposed through the cut surface.

[0049] Referring to FIG. 5g, the first insulating layer (120) may further include one or more bridge grooves (123) extending between some of the first through grooves (121). The plurality of first through grooves (121) and the plurality of bridge grooves (123) may be outside the scribe lane (SL). In this case, the plurality of first through grooves (121) and one or more bridge grooves (123) outside the scribe lane (SL) are not removed by a cutting process for the package substrate (17), and the plurality of first through grooves (121) and one or more bridge grooves (123) may remain within the first insulating layer (120) even after the cutting process.

[0050] Referring to FIG. 5h, the first insulating layer (120) may further include one or more bridge grooves (123) extending between some of the first through grooves (121). The plurality of first through grooves (121) and one or more bridge grooves (123) may be located within the scribe lane (SL). That is, from a planar perspective, the plurality of first through grooves (121) and one or more bridge grooves (123) may each have their entirety superimposed on the scribe lane (SL). The plurality of first through grooves (121) and one or more bridge grooves (123) located within the scribe lane (SL) may be removed through a cutting process for the package substrate (18).

[0051] FIGS. 6a and 6b are cross-sectional views showing package substrates (19, 20) according to exemplary embodiments of the present invention. Hereinafter, the package substrates (19, 20) shown in FIGS. 6a and 6b will be described with a focus on the differences from the package substrate (10) described with reference to FIGS. 1 to 3.

[0052] Referring to FIG. 6a together with FIGS. 1 to 3, the package substrate (19) may include one or more second conductive pads (171), one or more second conductive cover layers (175), a second main line pattern (180), and one or more second branch line patterns (190).

[0053] A second conductive pad (171) may be provided on a second surface (1113) of a base insulating layer (111). The second conductive pad (171) may be positioned to overlap with a second pad opening (139) of the second insulating layer (130). The second conductive pad (171) may function as a pad to which a connecting member (e.g., a conductive bump, a conductive wire, a solder ball) for electrical and physical connection between the package substrate (19) and other electronic components is attached. The second conductive pad (171) may be placed within a first region (R1) of the package substrate (19). For example, the material of the second conductive pad (171) may be the same or similar to the material of a plurality of first conductive pads (141).

[0054] The second conductive cover layer (175) may extend along the surface of the second conductive pad (171). The second conductive cover layer (175) may be disposed within the second pad opening (139) of the second insulating layer (130). The second conductive cover layer (175) may be a barrier layer configured to cover the second conductive pad (171) to prevent oxidation and / or damage to the second conductive pad (171). For example, the material of the second conductive cover layer (175) may be the same or similar to the material of the first conductive cover layer (145).

[0055] A second main line pattern (180) is provided on a second surface (1113) of a base insulating layer (111) and may extend along the second surface (1113) of the base insulating layer (111). For example, the second main line pattern (180) may extend linearly along the second surface (1113) of the base insulating layer (111) in a planar view. The second main line pattern (180) may be placed within a second region (R2) of a package substrate (19) located between first regions (R1) of adjacent package substrates (19). In exemplary embodiments, the second main line pattern (180) may be placed within a scribe lane (SL) within the second region (R2) of the package substrate (19) and may extend along the extension direction (e.g., X direction and / or Y direction) of the scribe lane (SL) within the second region (R2) of the package substrate (19). When the second main line pattern (180) is placed within the scribe lane (SL), the second main line pattern (180) can be removed during the cutting process for the package substrate (19). For example, the material of the second main line pattern (180) may be the same or similar to the material of the first main line pattern (150). Additionally, the dimensions of the second main line pattern (180) (e.g., horizontal width) may be the same or similar to the dimensions of the first main line pattern (150).

[0056] The second branch line pattern (190) may extend between the second main line pattern (180) and the second conductive pad (171). A first end of the second branch line pattern (190) may be in contact with the second main line pattern (180), and a second end of the second branch line pattern (190) may be connected to the second conductive pad (171). In a planar view, the second branch line pattern (190) may have a line shape extending from the second main line pattern (180) to the second conductive pad (171). In exemplary embodiments, the second main line pattern (180) and the second branch line pattern (190) may be used as paths through which electricity is applied during an electroplating process to form the second conductive cover layer (175). That is, when the electroplating process for forming the second conductive cover layer (175) is carried out, power for electroplating can be provided to the second conductive pad (171) through an electrical connection path passing through the second main line pattern (180) and the second branch line pattern (190). For example, the material of the second branch line pattern (190) may be the same or similar to the material of the first branch line pattern (160). Additionally, the dimensions of the second branch line pattern (190) (e.g., horizontal width) may be the same or similar to the dimensions of the first branch line pattern (160).

[0057] In exemplary embodiments, when the second main line pattern (180) extends in a first horizontal direction (e.g., Y direction), a plurality of second branch line patterns (190) may be spaced apart from each other in the first horizontal direction (e.g., Y direction). At this time, the contact points between the plurality of second branch line patterns (190) and the second main line pattern (180) may be spaced apart from each other in the first horizontal direction (e.g., Y direction). Additionally, as with the plurality of first branch line patterns (160) shown in FIG. 3, a portion of the plurality of second branch line patterns (190) may be connected to second conductive pads (171) in a first region (R1) of the package substrate (19) located on one side (e.g., left) of the second main line pattern (180), and another portion of the plurality of second branch line patterns (190) may be connected to second conductive pads (171) in a first region (R1) of the package substrate (19) located on the other side (e.g., right) of the second main line pattern (180).

[0058] The second insulating layer (130) may include one or more second through-grooves (131) that overlap the extension path of one or more second branch line patterns (190) in a planar view. The second through-grooves (131) may be positioned adjacent to the scribe lane (SL) and laterally spaced from the second main line pattern (180). The second through-grooves (131) may be positioned so that the entirety thereof overlaps the scribe lane (SL) or only a part thereof overlaps the scribe lane (SL). Alternatively, the second through-grooves (131) may be positioned outside the scribe lane (SL). The second through-grooves (131) may penetrate the second insulating layer (130) in a vertical direction (e.g., Z direction), and a part of the second surface (1113) of the base insulating layer (111) may be exposed through the second through-grooves (131). The shape and dimensions (e.g., horizontal width) of the second through-groove (131) may be the same or similar as the shape and dimensions of the first through-groove (121).

[0059] The second branch line pattern (190) may include a third segment (191) and a fourth segment (193) spaced apart with the second cut portion (195) in between. Since the second branch line pattern (190) has the third cut portion, the second branch line pattern (190) may have a discontinuously extended line shape. The third segment (191) may be connected to the second main line pattern (180), and the fourth segment (193) may be connected to the second conductive pad (171). The second through-groove (131) of the second insulating layer (130) may overlap with the second cut portion (195) of the second branch line pattern (190). For example, the second cut portion (195) of the second branch line pattern (190) may overlap with the second through-groove (131). For example, to form a second cutting portion (195) in the second branch line pattern (190), a conductive line pattern constituting the second branch line pattern (190) is formed, and then a portion of the conductive line pattern exposed through the second through-groove (131) of the insulating layer can be removed by an etching process.

[0060] In exemplary embodiments, a plurality of second branch line patterns (190) are provided on a second surface (1113) of a base insulating layer (111), and the second insulating layer (130) may include a plurality of second through-grooves (131) superimposed on the extension paths of the plurality of second branch line patterns (190). The arrangement of the plurality of second through-grooves (131) may be substantially the same or similar as the arrangement of the plurality of first through-grooves (121). For example, similar to the arrangement of the plurality of first through-grooves (121) shown in FIG. 3, the plurality of second through-grooves (131) may be arranged in an asymmetrical or zigzag shape.

[0061] In exemplary embodiments, the second insulating layer (130) may further include one or more bridge grooves extending between some of the second through grooves (131). A portion of the second surface (1113) of the base insulating layer (111) may be exposed through the bridge grooves of the second insulating layer (130). For example, the bridge grooves of the second insulating layer (130) may extend linearly in a planar view. The shape and arrangement of the bridge grooves of the second insulating layer (130) may be similar to the shape and arrangement of the bridge grooves (123) of the first insulating layer (120) described with reference to FIG. 5f, FIG. 5g, and FIG. 5h.

[0062] Referring to FIG. 6b, the second branch line pattern (190) can be connected to one of the first branch line patterns (160) through an internal wiring structure (115). During the electroplating process to form the second conductive cover layer (175), power for electroplating can be provided to the second conductive pad (171) through an electrical connection path passing through the first main line pattern (150), the first branch line pattern (160), the internal wiring structure (115), and the second branch line pattern (190). In this case, the second main line pattern (180 in FIG. 6a) can be omitted.

[0063] FIG. 7 is a cross-sectional view showing a semiconductor package (50) according to exemplary embodiments of the present invention. FIG. 8 is a bottom view showing a part of the semiconductor package (50) of FIG. 7.

[0064] Referring to FIGS. 7 and 8, the semiconductor package (50) may include a package substrate (30), a semiconductor chip (210), a chip connection bump (220), an underfill layer (230), a molding layer (240), and an external connection terminal (250).

[0065] The package substrate (30) may be, for example, a printed circuit board. The package substrate (30) may include a base insulating layer (111), a first insulating layer (120), a second insulating layer (130), an internal wiring structure (115), a plurality of first conductive pads (141), a plurality of first conductive cover layers (145), a first main line pattern (150), a plurality of first branch line patterns (160a), a plurality of second conductive pads (171), and a plurality of second conductive cover layers (175). For example, the package substrate (30) may be a structure obtained through a cutting process in which any one of the package substrates (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20) described above with reference to FIGS. 1 to 6b is cut along a scribe lane (SL). The first region (R1) of the package substrate (30) corresponds to the first region (R1) of any one of the package substrates (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20) described above with reference to FIGS. 1 to 6b, and the second region (R2a) of the package substrate (30) may correspond to the removal of the scribe lane (SL) from the second region (R2) of any one of the package substrates (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20) described above with reference to FIGS. 1 to 6b.

[0066] As illustrated in FIGS. 7 and 8, a plurality of first through-grooves (121) may be provided at the edge of the first insulating layer (120). The plurality of first through-grooves (121) may be spaced apart from each other along the edge of the first insulating layer (120) or along the side of the package substrate (30). The plurality of first through-grooves (121) may be exposed to the outside of the package substrate (30) through the side of the package substrate (30). Additionally, the ends of a plurality of first branch line patterns (160a) connected to the plurality of first through-grooves (121) may be exposed to the outside of the package substrate (30) or to the outside of the first insulating layer (120). For example, the package substrate (30) may be a structure obtained by cutting the package substrate (10) illustrated in FIG. 3 or a similar package substrate along a scribe lane (SL).

[0067] A semiconductor chip (210) may be mounted on a package substrate (30). For example, the semiconductor chip (210) may be mounted on the package substrate (30) in a face-down manner. A chip connection bump (220) may be interposed between a chip pad (211) of the semiconductor chip (210) provided on the bottom surface of the semiconductor chip (210) and a second conductive pad (171) of the package substrate (30). The chip connection bump (220) may be configured to electrically connect the semiconductor chip (210) and the package substrate (30). The chip connection bump (220) may include, for example, solder.

[0068] In exemplary embodiments, the semiconductor chip (210) may be a memory chip and may include a volatile memory chip and / or a non-volatile memory chip. The volatile memory chip may include, for example, a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (ZRAM), or a twin transistor RAM (TTRAM). Additionally, the non-volatile memory chip may include, for example, a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM (STT-MRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM, or an insulator resistance change memory. In exemplary embodiments, the semiconductor chip (210) may be a logic chip. The above logic chip may include, for example, an artificial intelligence semiconductor, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, and an application processor.

[0069] The underfill layer (230) is provided between the semiconductor chip (210) and the package substrate (30) and can surround the chip connection bump (220). The underfill layer (230) can be formed to fill the gap between the semiconductor chip (210) and the package substrate (30) through a capillary underfill process.

[0070] A molding layer (240) is provided on a package substrate (30) and can cover at least a portion of a semiconductor chip (210). The molding layer (240) may include a photosensitive material such as an epoxy mold compound (EMC) or a photo-imaginable encapsulant (PIE).

[0071] The external connection terminal (250) can be connected to the first conductive pad (141) of the package substrate (30). The external connection terminal (250) can electrically and physically connect the semiconductor package (50) and the external device on which the semiconductor package (50) is mounted. The external connection terminal (250) may be a solder ball or a solder bump.

[0072] FIGS. 9a to 9c are cross-sectional views illustrating a method for manufacturing a semiconductor package (50) according to exemplary embodiments of the present invention. Hereinafter, with reference to FIGS. 9a to 9c, the method for manufacturing a semiconductor package (50) described with reference to FIGS. 7 and 8 will be described.

[0073] Referring to FIG. 9a, a preliminary package substrate (30p) is prepared. The preliminary package substrate (30p) may be a panel-shaped structure comprising a plurality of first regions (R1) spaced apart from each other by a second region (R2) containing a scribe lane (SL), as in the package substrate (10) illustrated in FIG. 1.

[0074] After preparing a preliminary package substrate (30p), a semiconductor chip (210) is mounted on the preliminary package substrate (30p). The semiconductor chip (210) can be attached to the preliminary package substrate (30p) through chip connection bumps (220). Although FIG. 9a shows that one semiconductor chip (210) is mounted on the preliminary package substrate (30p), multiple semiconductor chips (210) can be mounted on the preliminary package substrate (30p). After mounting the semiconductor chip (210) on the preliminary package substrate (30p), an underfill process is performed to form an underfill layer (230) that fills the gap between the semiconductor chip (210) and the preliminary package substrate (30p).

[0075] Referring to FIG. 9b, after forming the underfill layer (230), a molding layer (240) covering the semiconductor chip (210) is formed on the pre-package substrate (30p).

[0076] Referring to FIG. 9c, a cutting process is performed to cut the result of FIG. 9b along the scribe lane (SL). The cutting process may include a cutting process using a sawing blade and / or a cutting process using a laser beam. As the result of FIG. 9b is cut along the scribe lane (SL), the result of FIG. 9b is separated into a plurality of semiconductor packages (50), and the preliminary package substrate (30p) may be separated into a plurality of package substrates (30). Additionally, a portion of each of the plurality of first through-grooves (121) located within the scribe lane (SL) is removed through the cutting process, and another portion of each of the plurality of first through-grooves (121) remaining after the cutting process may be exposed laterally through the cut surface (i.e., the side of the semiconductor package (50)) formed through the cutting process.

[0077] As described above, in order to perform an electrical test process on the package substrate during the manufacturing stage of the package substrate, it is necessary to form a cut portion in each of the branch line patterns utilized in the electroplating process prior to performing the electrical test process. To form a cut portion in each of the branch line patterns, a groove having a width corresponding to the width of the scribe lane (see SL in FIG. 1) of the package substrate may be formed in the insulating layer covering the branch line patterns, and then a portion of each of the branch line patterns may be removed. However, if the groove in the insulating layer is formed widely with a width similar to that of the scribe lane, problems such as damage to the package substrate and damage to the wiring within the package substrate may occur near the groove in the insulating layer during a process in which a relatively large amount of pressure is applied to the package substrate, such as the molding process.

[0078] However, according to exemplary embodiments of the present invention, each of the first through-grooves (121) of the first insulating layer (120) is formed at a position overlapping each of the first branch line patterns (160), so that the first through-grooves (121) required to form the first cutting portion (165) in each of the first branch line patterns (160) can be formed in a relatively small size. Furthermore, by forming the first through-grooves (121) in an asymmetric or zigzag shape, the concentration of stress on a specific part of the package substrate (10) can be relieved. Accordingly, according to exemplary embodiments of the present invention, damage to the package substrate (30) can be prevented, thereby improving the reliability of the package substrate (30) and the reliability of the semiconductor package (50) manufactured using the package substrate (30).

[0079] FIGS. 10a to 10g are drawings showing semiconductor packages (51, 52, 53, 54, 55, 56, 57) according to exemplary embodiments of the present invention, FIGS. 10a to 10f are bottom views showing parts of each of the semiconductor packages (51, 52, 53, 54, 55, 56), and FIG. 10g is a cross-sectional view showing the semiconductor package (57). Hereinafter, the semiconductor packages (51, 52, 53, 54, 55, 56, 57) illustrated in FIGS. 10a to 10g will be described with a focus on the differences from the semiconductor package (50) described with reference to FIGS. 7 and 8.

[0080] Referring to FIG. 10a, the first through-grooves (121) may be spaced apart from each other along the edge of the first insulating layer (120) or the edge of the semiconductor package (51). The first through-grooves (121) may be spaced apart from the edge of the package substrate (31) in a direction toward the center of the package substrate (31). The first through-grooves (121) may not be exposed through the side of the semiconductor package (51) or the side of the package substrate (31). For example, the package substrate (31) may be a structure obtained by cutting the package substrate (11) shown in FIG. 5a or a similar package substrate along the scribe lane (SL).

[0081] Referring to FIG. 10b, the first through-grooves (121) may have an asymmetric or zigzag arrangement. For example, the first through-grooves (121) may be spaced apart from each other in a first horizontal direction (e.g., Y direction) parallel to the extension direction of the edge of the first insulating layer (120), and two first through-grooves (121) adjacent in the first horizontal direction (e.g., Y direction) may be offset in a second horizontal direction (e.g., X direction) perpendicular to the extension direction of the edge of the first insulating layer (120). In exemplary embodiments, some of the first through-grooves (121) may be exposed through the side of the semiconductor package (52) or the side of the package substrate (32), and other parts of the first through-grooves (121) may not be exposed through the side of the semiconductor package (52) or the side of the package substrate (32). For example, the package substrate (32) may be a structure obtained by cutting the package substrate (13) shown in FIG. 5c or a similar package substrate along the scribe lane (SL).

[0082] Referring to FIG. 10c, the first through-grooves (121) may have an asymmetric or zigzag arrangement, and the first through-grooves (121) may not all be exposed through the side of the package substrate (33). For example, the package substrate (33) may be a structure obtained by cutting the package substrate (14) shown in FIG. 5d or a similar package substrate along the scribe lane (SL).

[0083] Referring to FIG. 10d, the first insulating layer (120) may include a groove (127) disposed adjacent to the edge of the first insulating layer (120) and a conductive pattern (119) provided within the groove (127). The conductive pattern (119) may be a pattern configured to transmit an input / output data signal, a power signal, and / or a ground signal provided to the package substrate (34). For example, the package substrate (34) may be a structure obtained by cutting the package substrate (15) shown in FIG. 5e or a similar package substrate along a scribe lane (SL).

[0084] Referring to FIG. 10e, the first insulating layer (120) may include one or more bridge grooves (123) extending between some of the first through grooves (121). For example, the plurality of first through grooves (121) may be interconnected through the bridge grooves (123). When the plurality of first through grooves (121) are connected through the bridge grooves (123), the first insulating layer (120) may include a trench extending linearly along the edge of the first insulating layer (120). The plurality of first through grooves (121) and the bridge grooves (123) may be exposed through the side of the semiconductor package (55) or the side of the package substrate (35). For example, the package substrate (35) may be a structure obtained by cutting the package substrate (16) shown in FIG. 5f or a similar package substrate along the scribe lane (SL).

[0085] Referring to FIG. 10f, a plurality of first through-grooves (121) and bridge grooves (123) are spaced apart from the edge of the first insulating layer (120) or the edge of the semiconductor package (56) and may not be exposed through the side of the semiconductor package (56) or the side of the package substrate (36). For example, the package substrate (36) may be a structure obtained by cutting the package substrate (17) shown in FIG. 5g or a similar package substrate along the scribe lane (SL).

[0086] Referring to FIG. 10g, the package substrate (37) may include one or more second branch line patterns (190a) connected to the second conductive pad (171). The second main line pattern (180) is provided on the second surface (1113) of the base insulating layer (111) and may extend along the second surface (1113) of the base insulating layer (111). The second insulating layer (130) may include a second through-groove (131) superimposed on the second main line pattern (180) in a planar view. The second through-groove (131) may be located at the edge of the second insulating layer (130) or spaced apart from the edge of the second insulating layer (130). A molding layer (240) is filled into the second through-hole (131), and the molding layer (240) may come into contact with the second surface (1113) of the base insulating layer (111) through the second through-hole (131). For example, a plurality of spaced-apart second branch line patterns (190a) are provided on the second surface (1113) of the base insulating layer (111), and the second insulating layer (130) may include a plurality of second through-holes (131) arranged along the extension paths of the plurality of second branch line patterns (190a) in a planar view. The plurality of second through-holes (131) may be spaced apart from each other along the edge of the second insulating layer (130). The arrangement of the plurality of second through-holes (131) may be substantially the same or similar to the arrangement of the plurality of first through-holes (121). For example, similar to the arrangement of the plurality of first through-grooves (121) shown in FIG. 3, the plurality of second through-grooves (131) may be arranged in an asymmetrical or zigzag shape. For example, the package substrate (37) may be a structure obtained by cutting along a scribe lane (SL) a package substrate similar to the package substrate (19) shown in FIG. 6a, the package substrate (20) shown in FIG. 6b, or any one of the package substrates (19, 20) shown in FIG. 6a and FIG. 6b.

[0087] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0088] 10: Package substrate 111: Base insulating layer 120: First insulating layer 121: First through groove 130: Second insulating layer 141: First conductive pad 150: 1st Main Line Pattern 160: 1st Branch Line Pattern

Claims

Claim 1 A package substrate comprising: a base insulating layer including a first surface and a second surface opposite to each other; a first main line pattern provided on the first surface of the base insulating layer; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and extending between the first main line pattern and the plurality of first conductive pads; and a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through grooves spaced apart from the first main line pattern; wherein each of the plurality of first branch line patterns includes a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through grooves are spaced apart from each other in a direction parallel to the extension direction of the first main line pattern so as to overlap each of the first cut portions of the plurality of first branch line patterns. Claim 2 A package substrate according to claim 1, wherein the first main line pattern extends in a first direction along the first surface of the base insulating layer, and among the plurality of first through grooves, two first through grooves adjacent in the first direction are spaced apart in a second direction perpendicular to the first direction. Claim 3 A package substrate according to claim 2, characterized in that the first main line pattern is disposed between two first through-grooves adjacent in the first direction among the plurality of first through-grooves from a planar perspective. Claim 4 A package substrate according to claim 1, wherein the first main line pattern extends in a first direction along the first surface of the base insulating layer, and the first insulating layer further includes a bridge groove extending between some of the first through grooves of the plurality of first through grooves. Claim 5 A package substrate according to claim 4, characterized in that the bridge groove is linearly extended from a planar perspective. Claim 6 A package substrate according to claim 1, further comprising: a second conductive pad provided on the second surface of the base insulating layer; a second branch line pattern provided on the second surface of the base insulating layer and connected to the second conductive pad; and a second insulating layer provided on the second surface of the base insulating layer and including a second through-groove; wherein the second branch line pattern includes a third segment and a fourth segment spaced apart with a second cut portion in between, and the second through-groove overlaps the second cut portion of the second branch line pattern. Claim 7 A package substrate according to claim 6, characterized in that the third segment of the second branch line pattern is connected to the first main line pattern. Claim 8 A package substrate according to claim 6, further comprising a second main line pattern provided on the second surface of the base insulating layer and connected to the third segment of the second branch line pattern, wherein the second through-groove is spaced apart from the second main line pattern. Claim 9 A package substrate according to claim 1, further comprising a plurality of first conductive cover layers on the plurality of first conductive pads. Claim 10 A package substrate according to claim 1, wherein each of the plurality of first through grooves has a first horizontal width in a first direction parallel to the extension direction of the first main line pattern and a second horizontal width in a second direction perpendicular to the first direction, wherein the first horizontal width is between 80㎛ and 12mm and the second horizontal width is between 80㎛ and 400㎛. Claim 11 A base insulating layer comprising a first surface and a second surface opposite to each other; a first main line pattern provided on the first surface of the base insulating layer and extending in a first direction; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and extending between the first main line pattern and the plurality of first conductive pads; A package substrate comprising: a first insulating layer provided on the first surface of the base insulating layer and including a plurality of first through grooves; wherein contact points between the plurality of first branch line patterns and the first main line pattern are spaced apart along the first direction, and the plurality of first branch line patterns each include a first segment and a second segment spaced apart with a first cut portion in between, and the plurality of first through grooves overlap the first cut portions of the plurality of first branch line patterns, and among the plurality of first through grooves, two first through grooves adjacent in the first direction are spaced apart in a second direction perpendicular to the first direction with the first main line pattern in between from a planar perspective. Claim 12 A semiconductor package comprising: a package substrate; and a semiconductor chip mounted on the package substrate; wherein the package substrate comprises: a base insulating layer having a first surface and a second surface opposite to each other; a plurality of first conductive pads provided on the first surface of the base insulating layer; a plurality of first branch line patterns provided on the first surface of the base insulating layer and connected to the plurality of first conductive pads; and a first insulating layer provided on the first surface of the base insulating layer and having a plurality of first through grooves; wherein the plurality of first branch line patterns each include a first segment and a second segment spaced apart with a first cut portion between them, and the plurality of first through grooves are arranged spaced apart from each other in a first direction parallel to one edge of the package substrate so as to overlap the first cut portions of the plurality of first branch line patterns. Claim 13 delete Claim 14 A semiconductor package according to claim 12, wherein two first through-grooves adjacent in the first direction among the plurality of first through-grooves are spaced apart in a second direction perpendicular to the first direction. Claim 15 A semiconductor package according to claim 12, characterized in that at least one of the plurality of first through-grooves is exposed through the side of the package substrate. Claim 16 A semiconductor package according to claim 12, wherein the plurality of first through-grooves are spaced apart from the edge of the package substrate toward the center of the package substrate. Claim 17 A semiconductor package according to claim 16, characterized in that the ends of the plurality of first branch line patterns are exposed to the outside of the package substrate. Claim 18 A semiconductor package according to claim 12, wherein the first insulating layer further comprises a bridge groove extending between at least some of the plurality of first through-grooves. Claim 19 A semiconductor package according to claim 18, wherein the bridge groove is linearly extended in a planar view. Claim 20 A semiconductor package according to claim 12, further comprising: a second conductive pad provided on the second surface of the base insulating layer; a second branch line pattern provided on the second surface of the base insulating layer and connected to the second conductive pad; and a second insulating layer provided on the second surface of the base insulating layer and including a second through-groove; wherein the second branch line pattern includes a third segment and a fourth segment spaced apart with a second cut portion in between, and the second through-groove overlaps the second cut portion of the second branch line pattern.

Images