Three dimensional nonvolatile memory device including horizontal channel region

Abstract

A three-dimensional non-volatile memory device includes a memory cell array comprising a plurality of memory cells repeatedly arranged on a substrate along a first horizontal direction and a second horizontal direction parallel to and mutually orthogonal to the main surface of the substrate, and a vertical direction perpendicular to the main surface. The memory cell array includes a plurality of horizontal channel regions that extend long in the first horizontal direction on the substrate and overlap each other at positions spaced apart along the vertical direction, and a vertical word line that penetrates the plurality of horizontal channel regions in the vertical direction.

Description

Technology Field

[0001] The technical concept of the present invention relates to a non-volatile memory device, and in particular to a three-dimensional non-volatile memory device comprising a plurality of memory cells arranged repeatedly in three dimensions. Background Technology

[0002] Due to the development of electronic technology, the down-scaling of semiconductor devices is progressing rapidly, and high integration density is required to increase the storage capacity of semiconductor memory devices used in electronic devices. In particular, there is a need to develop technology for a three-dimensional non-volatile memory device having a structure that can secure the reliability required of memory cells even as the number of stacked memory cells overlapping vertically on a substrate increases. The background technology of the present invention is disclosed in Korean Published Patent Application No. 10-2020-0078048 (July 1, 2020). The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a three-dimensional non-volatile memory device having a structure advantageous for miniaturization and high integration of a three-dimensional memory cell array, and a structure capable of ensuring the reliability required of said memory cells even when the number of stacked memory cells overlapped in a vertical direction on a substrate in a three-dimensional memory cell array increases. means of solving the problem

[0004] A three-dimensional non-volatile memory device according to one embodiment of the technical concept of the present invention comprises a substrate having a main surface, a memory cell array including a plurality of memory cell strings that are each extended along a first horizontal direction parallel to the main surface and repeatedly arranged along a second horizontal direction parallel to the main surface and orthogonal to the first horizontal direction and a vertical direction perpendicular to the main surface, a plurality of bit lines connected to one side of each of the plurality of memory cell strings and overlapping each other at positions spaced apart along the vertical direction, and at least one source line spaced apart from the plurality of bit lines in the first horizontal direction with the plurality of memory cell strings in between and connected to the other side of each of the plurality of memory cell strings, wherein each of the plurality of memory cell strings includes a plurality of ring channel portions that define a plurality of local holes spaced apart from each other and regularly arranged along the first horizontal direction, a horizontal channel region including a plurality of connection portions arranged between each of the plurality of ring channel portions, and a plurality of vertical word lines penetrating the horizontal channel region in the vertical direction through the plurality of local holes.

[0005] A three-dimensional non-volatile memory device according to another embodiment of the technical concept of the present invention comprises a substrate having a main surface, a plurality of horizontal channel regions that overlap each other at positions spaced apart along a vertical direction on the substrate and each extend parallel to the main surface, a plurality of inter-cell insulation patterns interposed one by one between each of the plurality of horizontal channel regions, and a plurality of vertical word lines penetrating the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction, wherein each of the plurality of horizontal channel regions includes a plurality of ring channel portions that define a plurality of first local holes spaced apart from each other and a plurality of connecting portions disposed between each of the plurality of ring channel portions, wherein the plurality of inter-cell insulation patterns include a plurality of second local holes aligned with the plurality of first local holes in the vertical direction, and the plurality of vertical word lines penetrate the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction through the plurality of first local holes and the plurality of second local holes.

[0006] A three-dimensional non-volatile memory device according to another aspect of the technical concept of the present invention comprises a substrate having a main surface, a memory cell array including a plurality of memory cell strings that are each extended along a first horizontal direction parallel to the main surface and repeatedly arranged along a second horizontal direction parallel to the main surface and orthogonal to the first horizontal direction and a vertical direction perpendicular to the main surface, a plurality of bit lines connected to one side of each of the plurality of memory cell strings and overlapping each other at positions spaced apart along the vertical direction, and at least one source line spaced apart from the plurality of bit lines in the first horizontal direction with the plurality of memory cell strings in between and connected to the other side of each of the plurality of memory cell strings, wherein each of the plurality of memory cell strings includes a plurality of ring channel portions defining a plurality of local holes that are regularly arranged along the first horizontal direction and spaced apart from each other, a horizontal channel region including a plurality of connection portions arranged between each of the plurality of ring channel portions, and a plurality of vertical word lines penetrating the horizontal channel region in the vertical direction through the plurality of local holes. Effects of the invention

[0007] A three-dimensional non-volatile memory device according to the technical concept of the present invention may have a channel all-around structure in which a horizontal channel region in each of the multiple memory cells sharing a single vertical word line wraps around the perimeter of the vertical word line. Accordingly, when an electric field is applied from the vertical word line to the horizontal channel region during the operation of the three-dimensional non-volatile memory device, the concentration of the electric field in the interface dielectric layer interposed between the vertical word line and the horizontal channel region can be prevented. Furthermore, when an interface dielectric layer and a ferroelectric layer that sequentially wrap around the vertical word line are included between the vertical word line and the horizontal channel region, a structure is implemented that can increase the electric field applied to the ferroelectric layer while preventing electric field concentration in the interface dielectric layer during the operation of the three-dimensional non-volatile memory device, thereby improving dipole switching efficiency and, as a result, securing a relatively large memory window in the three-dimensional non-volatile memory device. In addition, the three-dimensional non-volatile memory device according to the technical concept of the present invention has a structure in which memory cell strings extend horizontally along the length direction of the plurality of horizontal channel regions, thereby preventing problems such as WOC (worst on cell current) degradation even when the number of stacked memory cells stacked in the vertical direction increases, and providing excellent operating characteristics.

[0008] A three-dimensional non-volatile memory device according to the technical concept of the present invention can be obtained by first forming a plurality of horizontal channel regions, a plurality of bit lines, and a common source line, and then forming a plurality of ferroelectric layers and a plurality of vertical word lines. In this way, since the formation of the ferroelectric layer, which is made of a material that is relatively susceptible to thermal budget, is carried out in a relatively later process, the possibility of degradation of the ferroelectric properties of the ferroelectric layer during the manufacturing process of the three-dimensional non-volatile memory device, and / or the possibility of defects such as oxygen vacancies caused by unwanted intermixing between the ferroelectric layer and the adjacent metal-containing film, can be significantly reduced. Accordingly, the reliability of the three-dimensional non-volatile memory device can be improved. Brief explanation of the drawing

[0009] FIG. 1a is a cross-sectional view of a three-dimensional non-volatile memory device according to embodiments of the technical concept of the present invention. FIG. 1b is a plan view illustrating the configuration at the first vertical level of the three-dimensional non-volatile memory device exemplified in FIG. 1a. FIG. 1c is a plan view illustrating the configuration at the second vertical level of the three-dimensional non-volatile memory device exemplified in FIG. 1a. FIG. 1d is a partial enlarged plan view of the part labeled "EX1" in FIG. 1b. FIG. 1e is a partially enlarged cross-sectional view of the part labeled "EX2" in FIG. 1a, corresponding to the cross-sectional view along the line X1 - X1' in FIG. 1d. FIG. 1f is an enlarged plan view of the horizontal channel region included in the three-dimensional non-volatile memory device exemplified in FIG. 1a. FIG. 2 is a schematic perspective view of a portion of the three-dimensional non-volatile memory device exemplified in FIG. 1a. FIG. 3 is a perspective view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIG. 4 is a plan view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIG. 5 is a plan view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIG. 6 is a plan view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIG. 7a is a partial enlarged plan view of a portion corresponding to the part labeled "EX1" in FIG. 1b among three-dimensional non-volatile memory devices according to other embodiments of the technical concept of the present invention. Figure 7b is a cross-sectional view along the X6 - X6' line of Figure 7a. FIG. 8a is a plan view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIGS. 8B and FIGS. 8C are drawings for explaining a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention, respectively, and are cross-sectional views illustrating various structures along the X7 - X7' line of FIG. 8A. FIG. 9 is a cross-sectional view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIG. 10 is a cross-sectional view illustrating a three-dimensional non-volatile memory device according to other embodiments of the technical concept of the present invention. FIGS. 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, 19a, 20a, and 21a are cross-sectional views illustrated in process order to explain a method for manufacturing a three-dimensional non-volatile memory device according to embodiments of the technical concept of the present invention, and FIGS. 11b, 12b, 13b, 14b, 15b, 16b, 17b, 18b, 19b, 20b, and 21b respectively illustrate the configuration at the first vertical level of FIGS. 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, 19a, 20a, and 21a. It is a floor plan. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] FIGS. 1a to 1f and FIG. 2 are drawings for explaining a three-dimensional non-volatile memory element (100) according to embodiments of the technical concept of the present invention. More specifically, FIG. 1a is a cross-sectional view of a three-dimensional non-volatile memory element (100). FIG. 1b is a plan view illustrating the configuration at the first vertical level (LV1) on the substrate (110) in FIG. 1a. FIG. 1c is a plan view illustrating the configuration at the second vertical level (LV2) on the substrate (110) in FIG. 1a. FIG. 1d is a partial enlarged plan view of the portion marked "EX1" in FIG. 1b. FIG. 1e is a partial enlarged cross-sectional view of the portion marked "EX2" in FIG. 1a, corresponding to the cross-section along the X1 - X1' line in FIG. 1d. FIG. 1f is an enlarged plan view of a horizontal channel region (130) included in the three-dimensional non-volatile memory element (100). FIG. 2 is a schematic perspective view of a portion of the three-dimensional non-volatile memory element (100) exemplified in FIG. 1a.

[0012] Referring to FIGS. 1a to 1f and FIG. 2, a three-dimensional non-volatile memory element (100) may include a substrate (110) having a main surface (110M) and a memory cell array (MCA) disposed on the substrate (110).

[0013] A memory cell array (MCA) may include a plurality of memory cell strings (MS) that are extended along a first horizontal direction (X direction) parallel to the main surface (110M) of the substrate (110). Each of the plurality of memory cell strings (MS) may be repeatedly arranged along a second horizontal direction (Y direction) parallel to the main surface (110M) of the substrate (110) and orthogonal to the first horizontal direction (X direction), and a vertical direction (Z direction) perpendicular to the main surface (110M) of the substrate (110).

[0014] A memory cell array (MCA) may include a plurality of bit lines (BL) disposed on one side of a plurality of memory cell strings (MS). The plurality of bit lines (BL) may be disposed to overlap each other at positions spaced apart along the vertical direction (Z direction). Each of the plurality of bit lines (BL) may be extended along a second horizontal direction (Y direction). Each of the plurality of bit lines (BL) may be connected to one side of each of a first group of memory cell strings (MS) disposed on the same plane at the same vertical level on the substrate (110) among the plurality of memory cell strings (MS). The first group of memory cell strings (MS) may share one bit line (BL).

[0015] A memory cell array (MCA) may include a common source line (CSL) disposed on the other side of a plurality of memory cell strings (MS). The common source line (CSL) may be spaced apart from a plurality of bit lines (BL) in a first horizontal direction (X direction) with the plurality of memory cell strings (MS) in between. The common source line (CSL) may include a main source line portion (MSL) that extends along a second horizontal direction (Y direction) on a substrate (110), and a plurality of branch source line portions (BSL) that branch from the main source line portion (MSL) toward a channel horizontal channel area (130) and each of the plurality of memory cell strings (MS) contact the channel horizontal channel area (130). In exemplary embodiments, the plurality of branch source line portions (BSL) may be omitted, in which case the main source line portion (MSL) may directly contact the channel horizontal channel area (130) of each of the plurality of memory cell strings (MS).

[0016] Each of the plurality of memory cell strings (MS) may include a horizontal channel region (130) having a planar shape that extends along a first horizontal direction (X direction) and a plurality of vertical word lines (WL) that penetrate the horizontal channel region (130).

[0017] As illustrated in FIG. 1f, the horizontal channel area (130) may include a plurality of ring channel portions (130L) defining a plurality of local holes (130H), and a plurality of connecting portions (130C) disposed one by one between each of the plurality of ring channel portions (130L) so that two adjacent ring channel portions (130L) among the plurality of ring channel portions (130L) are connected to each other. The plurality of local holes (130H) may be regularly arranged along a first horizontal direction (X direction) and spaced apart from each other.

[0018] As illustrated in FIG. 1f, a plurality of ring channel portions (130L) and a plurality of connecting portions (130C) may be repeatedly arranged along a straight line extending in a first horizontal direction (X direction). However, the technical concept of the present invention is not limited to that illustrated in FIG. 1f, and various modifications and changes are possible within the scope of the technical concept of the present invention. For example, a plurality of ring channel portions (130L) and a plurality of connecting portions (130C) may each be configured to be repeatedly arranged in a zigzag direction along the first horizontal direction (X direction). A plurality of vertical word lines (WL) may penetrate the horizontal channel area (130) in a vertical direction (Z direction) through a plurality of local holes (130H) formed in the horizontal channel area (130).

[0019] As illustrated in FIGS. 1a, 1b, and 1f, the horizontal channel region (130) may include ohmic contact portions (130A, 130B) at both ends of the first horizontal direction (X direction). The ohmic contact portions (130A, 130B) of the horizontal channel region (130) may include a first ohmic contact portion (130A) in contact with the bit line (BL) and a second ohmic contact portion (130B) in contact with the common source line (CSL). In other exemplary embodiments, the horizontal channel region (130) may not include ohmic contact portions (130A, 130B).

[0020] In exemplary embodiments, a plurality of horizontal channel regions (130) may be composed of undoped polysilicon, doped polysilicon, a compound semiconductor material, an oxide semiconductor material, a two-dimensional semiconductor material, or a combination thereof. The compound semiconductor material may be selected from a group IV-IV compound semiconductor, a group III-V compound semiconductor, a group II-VI compound semiconductor, and a group IV-VI compound semiconductor. The group IV-IV compound semiconductor may be selected from SiGe, SiC, SiGeC, GeSn, SiSn, and SiGeSn. The group III-V compound semiconductor may be composed of a compound semiconductor comprising at least one element among In, Ga, and Al as a group III element and at least one element among As, P, and Sb as a group V element. The group III-V compound semiconductor may be composed of a binary, ternary, or quaternary compound comprising two, three, or four elements selected from group III and group V. The above binary compound is selected from InP, GaAs, GaP, InAs, InSb, and GaSb, and the above ternary compound may be selected from InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and GaAsP, but is not limited thereto. The above II-VI compound semiconductor may be composed of a binary, ternary, or quaternary compound containing two, three, or four elements selected from Group II and Group VI. The above II-VI compound semiconductor may be selected from CdSe, ZnTe, CdS, ZnS, ZnSe, and HgCdTe, but is not limited thereto. The above IV-VI compound semiconductor may be composed of PbS, but is not limited thereto.

[0021] The above oxide semiconductor material may be selected from IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, AlSnInZnO, SiInZnO, AlZnSnO, GaZnSnO, and ZrZnSnO, but is not limited thereto.

[0022] In exemplary embodiments, the two-dimensional semiconductor material may be composed of a transition metal dichalcogenide or a bipolar semiconductor material that utilizes both electrons and holes as driving charges. For example, the two-dimensional semiconductor material may be MoS2, MoSe2, WS2, NbS2, TaS2, ZrS2, HfS2, TcS2, ReS2, CuS2, GaS2, InS2, SnS2, GeS2, PbS2, WSe2, NbSe2, TaSe2, ZrSe2, HfSe2, TcSe2, ReSe2, CuSe2, GaSe2, InSe2, SnSe2, GeSe2, PbSe2, MoTe2, WTe2, NbTe2, TaTe2, ZrTe2, HfTe2, TcTe2, ReTe2, CuTe2, GaT e2 It can be selected from InTe2, SnTe2, GeTe2, and PbTe2, but is not limited to these.

[0023] In this specification, the materials listed above refer to materials composed of elements included in each term, and are not chemical formulas representing stoichiometric relationships.

[0024] In exemplary embodiments, a plurality of horizontal channel regions (130) may be made of doped polysilicon. In this case, as illustrated in FIG. 1a, FIG. 1b, and FIG. 1f, the plurality of horizontal channel regions (130) may include ohmic contact portions (130A, 130B). Here, the ohmic contact portions (130A, 130B) may have a higher doping concentration than other parts of the horizontal channel regions (130). In other exemplary embodiments, the plurality of horizontal channel regions (130) may be made of an oxide semiconductor material or a two-dimensional material. In this case, the plurality of horizontal channel regions (130) may not include ohmic contact portions (130A, 130B).

[0025] As illustrated in FIG. 1b and FIG. 2, in a memory cell array (MCA), a plurality of memory cells (MC) may be repeatedly arranged along a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction). A plurality of memory cell strings (MS) may each include a plurality of memory cells (MC) regularly arranged along the first horizontal direction (X direction).

[0026] As illustrated in FIG. 2, a memory cell array (MCA) may include a first group of horizontal channel regions (130) that overlap each other at positions spaced apart along the vertical direction (Z direction). Among a plurality of vertical word lines (WL), a first group of vertical word lines (WL) arranged in a row along the first horizontal direction (X direction) may penetrate the first group of horizontal channel regions (130) in the vertical direction (Z direction). Among a plurality of memory cell strings (MS), a second group of memory cell strings (MS) that overlap each other at positions spaced apart along the vertical direction (Z direction) on the substrate (110) may share the first group of vertical word lines (WL).

[0027] As illustrated in FIGS. 1a and 1c, the memory cell array (MCA) may include a plurality of inter-cell insulation patterns (122P) that are interposed one by one between each of a plurality of horizontal channel regions (130) in the vertical direction (Z direction) and overlap with the plurality of horizontal channel regions (130) in the vertical direction (Z direction). The plurality of inter-cell insulation patterns (122P) may be interposed one by one between each of a first group of horizontal channel regions (130) that overlap each other at positions spaced apart along the vertical direction (Z direction) on the substrate (110). A plurality of local holes (122H) that are aligned in the vertical direction (Z direction) with the local holes (130H) of each of the plurality of horizontal channel regions (130) may be formed in the plurality of inter-cell insulation patterns (122P). A plurality of vertical word lines (WL) can penetrate a plurality of inter-cell insulation patterns (122P) and a plurality of horizontal channel regions (130) in a vertical direction (Z direction) through a plurality of local holes (122H, 130H).

[0028] Each of the plurality of vertical word lines (WL) may include a plurality of first local regions surrounded by a plurality of horizontal channel regions (130) and a plurality of second local regions surrounded by a plurality of inter-cell insulation patterns (122P). In each of the plurality of vertical word lines (WL), the plurality of first local regions and the plurality of second local regions may be arranged alternately one by one along the vertical direction (Z direction).

[0029] As illustrated in FIG. 1b, a memory cell array (MCA) may include a plurality of inter-string insulation patterns (124P) arranged at the same vertical level as a plurality of horizontal channel regions (130). An inter-string insulation pattern (124P) may be arranged between each of a first group of memory cell strings (MS) arranged on the same plane at the same vertical level on the substrate (110) among a plurality of memory cell strings (MS). The inter-string insulation pattern (124P) may be interposed between two adjacent memory cell strings (MS) among the first group of memory cell strings (MS) to provide a separation distance between them. In a memory cell array (MCA), a plurality of inter-string insulation patterns (124P) arranged on the same plane at the same vertical level on the substrate (110) may have a sidewall in contact with an adjacent horizontal channel region (130), a sidewall in contact with a bit line (BL), and a sidewall in contact with a common source line (CSL).

[0030] The constituent material of the inter-string insulation pattern (124P) may be made of a material having an etching selectivity ratio with respect to the constituent material of the inter-cell insulation pattern (122P). In exemplary embodiments, the inter-cell insulation pattern (122P) may be made of a silicon oxide film and the inter-string insulation pattern (124P) may be made of a silicon nitride film, but is not limited thereto.

[0031] As illustrated in FIGS. 1a to 1e and FIG. 2, a memory cell array (MCA) may include a plurality of ferroelectric layers (160) and a plurality of interface dielectric layers (140). Each of the plurality of ferroelectric layers (160) and the plurality of interface dielectric layers (140) may have a ring shape when viewed in a plane (e.g., an XY plane).

[0032] A plurality of ferroelectric layers (160) may each be positioned between a vertical word line (WL) and a horizontal channel region (130). A plurality of ferroelectric layers (160) may each penetrate a first group of horizontal channel regions (130) and a first group of inter-cell insulation patterns (122P) that overlap each other at positions spaced apart along the vertical direction (Z direction) through a plurality of local holes (130H) and a plurality of local holes (122H) in the vertical direction (Z direction).

[0033] A plurality of ferroelectric layers (160) are each arranged to surround the outer surface of the vertical word line (WL) along the circumference of the vertical word line (WL) and may come into contact with the outer surface of the vertical word line (WL). A plurality of ferroelectric layers (160) may each have a cylindrical shape that surrounds the vertical word line (WL) and extends long in the vertical direction (Z direction). A plurality of memory cells (MC) that overlap each other along the vertical direction (Z direction) may share one vertical word line (WL) and one ferroelectric layer (160).

[0034] A plurality of interface dielectric layers (140) may be arranged on a substrate (110) at the same vertical level as a plurality of horizontal channel regions (130). In each of the plurality of memory cells (MC), the interface dielectric layer (140) may be interposed between the ferroelectric layer (160) and the horizontal channel region (130). As illustrated in FIG. 1a and FIG. 1e, a cell-to-cell insulation pattern (122P) may be interposed between each of the first group of interface dielectric layers (140) that overlap each other at positions spaced apart along the vertical direction (Z direction) on the substrate (110) among the plurality of interface dielectric layers (140).

[0035] As illustrated in FIG. 1e, the horizontal channel region (130) and the interface dielectric layer (140) may each penetrate the local hole (130H) of the horizontal channel region (130) in the vertical direction (Z direction), but may not penetrate the local hole (122H) of the inter-cell insulation pattern (122P). The horizontal channel region (130) and the interface dielectric layer (140) may be placed within a space defined by two inter-cell insulation patterns (122P) adjacent to each other in the vertical direction (Z direction) among a plurality of inter-cell insulation patterns (122P) surrounding the vertical word line (WL) and the ferroelectric layer (160). The horizontal channel region (130) and the interface dielectric layer (140) may each have a maximum vertical length (VL1) defined by two inter-cell insulation patterns (122P) adjacent to each other in the vertical direction (Z direction).

[0036] In other exemplary embodiments, the interface dielectric layer (140) may have a structure that extends along the vertical direction (Z direction) by penetrating the local holes (130H) of the horizontal channel region (130) and the local holes (122H) of the inter-cell insulation pattern (122P), similar to the vertical word line (WL) and the ferroelectric layer (160). In this case, a plurality of memory cells (MC) that overlap each other along the vertical direction (Z direction) may share a single interface dielectric layer (140).

[0037] In exemplary embodiments, a plurality of ferroelectric layers (160) may comprise at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr. For example, a plurality of ferroelectric layers (160) may comprise hafnium-based oxides, for example, hafnium oxide (HfO), hafnium zirconium oxide (HZO), hafnium titanium oxide, or hafnium silicon oxide. The ferroelectric film (134) may further comprise a dopant as needed. The dopant may be composed of at least one element selected from Si, Al, Zr, Y, La, Gd, Sc, Sr, Mg, and Ba, but is not limited thereto. In other exemplary embodiments, a plurality of ferroelectric layers (160) may be formed as a stacked structure comprising a plurality of ferroelectric sublayers made of different materials. In yet another exemplary embodiment, a plurality of ferroelectric layers (160) may be formed as a stacked structure of at least one ferroelectric sublayer and a dielectric layer. The constituent material of each of the above-mentioned ferroelectric sublayers may be selected from the materials exemplified above as the constituent material of the plurality of ferroelectric layers (160). The dielectric layer may be composed of a silicon oxide film, a high dielectric film, or a combination thereof. The high dielectric film may be composed of a metal oxide or a metal oxynitride having a dielectric constant greater than that of the silicon oxide film. The plurality of interface dielectric layers (140) may be composed of a silicon oxide film, but are not limited thereto.

[0038] A plurality of vertical word lines (WL), a plurality of bit lines (BL), and a common source line (CSL) may each be made of a metal, a conductive metal nitride, a conductive semiconductor material, or a combination thereof. In exemplary embodiments, a plurality of vertical word lines (WL), a plurality of bit lines (BL), and a common source line (CSL) may each be made of W, Al, Cu, Co, Mo, Ti, Ta, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but are not limited thereto.

[0039] As illustrated in FIG. 1a, a lower insulating film (112) and an etching stop layer (114) may be disposed between the substrate (110) and the memory cell array (MCA). In exemplary embodiments, the lower insulating film (112) may be made of a silicon oxide film and the etching stop layer (114) may be made of an aluminum oxide film, but is not limited thereto.

[0040] As illustrated in FIGS. 1a, 1b, and 1c, a side adjacent to a plurality of bit lines (BL) of a memory cell array (MCA) may be covered with a separating insulating film (152). A pair of memory cell arrays (MCAs) adjacent to each other in a first horizontal direction (X direction) with the plurality of bit lines (BL) in between may be electrically separated from each other by the separating insulating film (152) and may have a symmetrical structure centered on the separating insulating film (152). The separating insulating film (152) may be made of a silicon nitride film, a silicon oxide film, or a combination thereof, but is not limited thereto.

[0041] In the memory cell array (MCA) of the three-dimensional non-volatile memory device (100) described with reference to FIGS. 1a to 1f and FIG. 2, a configuration in which three vertical word lines (WL) penetrate one horizontal channel region (130) and three memory cells (MC) share one horizontal channel region (130) and three memory cell strings (MS) share one bit line (BL) has been described as an example, but the technical concept of the present invention is not limited thereto. For example, the number of vertical word lines (WL) penetrating one horizontal channel region (130), the number of memory cells (MC) sharing one horizontal channel region (130), and the number of memory cell strings (MS) sharing one bit line (BL) can each be selected in various ways as needed.

[0042] The three-dimensional non-volatile memory device (100) described with reference to FIGS. 1a to 1f and FIG. 2 includes a plurality of horizontal channel regions (130) that overlap each other at positions spaced apart along the vertical direction (Z direction) and a plurality of vertical word lines (WL) that penetrate the plurality of horizontal channel regions (130) in the vertical direction (Z direction). The three-dimensional non-volatile memory device (100) has a channel all-around structure in which a plurality of horizontal channel regions (130) surround the perimeter of the vertical word line (WL) in transistors sharing a single vertical word line (WL). Accordingly, when an electric field is applied from the vertical word line (WL) to the horizontal channel region (130) during the operation of the three-dimensional non-volatile memory device (100), it is possible to prevent the electric field from concentrating on the interface dielectric layer (140) interposed between the vertical word line (WL) and the horizontal channel region (130). In addition, an interface dielectric layer (140) and a ferroelectric layer (160) are sequentially interposed between a horizontal channel region (130) and a vertical word line (WL), thereby implementing a structure that prevents electric field concentration in the interface dielectric layer (140) during operation of the three-dimensional non-volatile memory device (100) while increasing the electric field applied to the ferroelectric layer (160), thereby improving dipole switching efficiency. Accordingly, a relatively large memory window can be secured in the three-dimensional non-volatile memory device (100), and reliability can be improved.

[0043] In addition, the three-dimensional non-volatile memory device (100) may have a structure in which a plurality of memory cell strings (MS) are extended horizontally (e.g., in the X direction) along the length direction of each of the plurality of horizontal channel regions (130). Accordingly, even if the number of stacked memory cells (MC) stacked in the vertical direction (Z direction) in the three-dimensional non-volatile memory device (100) increases, problems such as WOC (worst on cell current) degradation can be prevented, and excellent operating characteristics can be provided for each of the plurality of memory cells (MC).

[0044] FIG. 3 is a perspective view for explaining a three-dimensional non-volatile memory device (200) according to other embodiments of the technical concept of the present invention.

[0045] Referring to FIG. 3, the three-dimensional non-volatile memory element (200) has a configuration generally identical to that described with reference to FIG. 1a to 1f and FIG. 2 for the three-dimensional non-volatile memory element (100). However, the memory cell array (MCA2) of the three-dimensional non-volatile memory element (200) may include a plurality of source lines (SL) instead of a common source line (CSL).

[0046] Multiple source lines (SL) may be positioned at positions that overlap each other and are spaced apart along the vertical direction (Z direction). Each of the multiple source lines (SL) may be connected to one side of each of a first group of memory cell strings (MS) that are positioned on the same plane at the same vertical level on the substrate (110) among the multiple memory cell strings (MS) constituting a single memory cell array (MCA2). Each of the multiple source lines (SL) may be shared by the first group of memory cell strings (MS). The constituent material of the multiple source lines (SL) is as described for the constituent material of the common source line (CSL) exemplified in FIGS. 1a to 1c and FIG. 2.

[0047] FIG. 4 is a plan view for explaining a three-dimensional non-volatile memory device (300) according to other embodiments of the technical concept of the present invention.

[0048] Referring to FIG. 4, the three-dimensional non-volatile memory element (300) has a configuration generally identical to that of the three-dimensional non-volatile memory element (100) described with reference to FIG. 1a to 1f and FIG. 2. However, the memory cell array (MCA3) of the three-dimensional non-volatile memory element (300) may include an air gap (AG) instead of an inter-string insulation pattern (124P). In this specification, the term "air" may refer to the atmosphere or other gases that may be present during the manufacturing process.

[0049] An air gap (AG) may be interposed between two adjacent memory cell strings (MS) among a first group of memory cell strings (MS) that are placed on the same plane at the same vertical level on the substrate (110) among a plurality of memory cell strings (MS) constituting a single memory cell array (MCA2), thereby providing a separation distance between them. In the memory cell array (MCA3), a portion of each of a plurality of horizontal channel regions (130), bit lines (BL), and common source lines (CSL) may be exposed to the air gap (AG).

[0050] FIG. 5 is a plan view for illustrating a three-dimensional non-volatile memory device (400) according to other embodiments of the technical concept of the present invention.

[0051] Referring to FIG. 5, the three-dimensional non-volatile memory element (400) has a configuration generally identical to that of the three-dimensional non-volatile memory element (100) described with reference to FIG. 1a to 1f and FIG. 2. However, the memory cell array (MCA4) of the three-dimensional non-volatile memory element (400) has a plurality of memory cell strings (MS4) extending along a first horizontal direction (X direction) between a bit line (BL) and a common source line (CSL), and each of the plurality of memory cell strings (MS4) may include a single horizontal channel region (430).

[0052] The horizontal channel region (430) may include ohmic contact portions (430A, 430B) at both ends of the first horizontal direction (X direction). The ohmic contact portions (430A, 430B) of the horizontal channel region (430) may include a first ohmic contact portion (430A) in contact with the bit line (BL) and a second ohmic contact portion (430B) in contact with the common source line (CSL). In other exemplary embodiments, the horizontal channel region (430) may not include the ohmic contact portions (430A, 430B).

[0053] In each of the multiple memory cell strings (MS4), multiple vertical word lines (WL) can penetrate a single horizontal channel area (430) in a vertical direction (Z direction). Here, the number of vertical word lines (WL) penetrating a single horizontal channel area (430) may be at least four. The multiple vertical word lines (WL) penetrating a single horizontal channel area (430) may be arranged in a straight line along a first horizontal direction (X direction).

[0054] Among a plurality of memory cell strings (MS4), an inter-string insulation pattern (424) may be disposed between each of a first group of memory cell strings (MS4) that are placed on the same plane (e.g., XY plane) at the same vertical level. The inter-string insulation pattern (424) may be interposed between two adjacent memory cell strings (MS4) among the first group of memory cell strings (MS4) to provide a separation distance between them. The inter-string insulation pattern (424) may be made of a silicon nitride film, an air gap, or a combination thereof.

[0055] The more detailed configuration of the plurality of memory cell strings (MS4) and horizontal channel region (430) is generally the same as described for the plurality of memory cell strings (MS) and horizontal channel region (130) included in the memory cell array (MCA) with reference to FIGS. 1a to 1f and FIG. 2.

[0056] FIG. 6 is a plan view for illustrating a three-dimensional non-volatile memory device (500) according to other embodiments of the technical concept of the present invention.

[0057] Referring to FIG. 6, the three-dimensional non-volatile memory element (500) has a configuration generally identical to that of the three-dimensional non-volatile memory element (100) described with reference to FIG. 1a to 1f and FIG. 2. However, the memory cell array (MCA5) of the three-dimensional non-volatile memory element (500) has a plurality of memory cell strings (MS5) extending along a first horizontal direction (X direction) between a bit line (BL) and a common source line (CSL), and each of the plurality of memory cell strings (MS5) may include a single horizontal channel region (530).

[0058] A horizontal channel region (530) may include ohmic contact portions (530A, 530B) at both ends of a first horizontal direction (X direction). The ohmic contact portions (530A, 530B) of the horizontal channel region (530) may include a first ohmic contact portion (530A) in contact with a bit line (BL) and a second ohmic contact portion (530B) in contact with a common source line (CSL). In other exemplary embodiments, the horizontal channel region (530) may not include ohmic contact portions (530A, 530B).

[0059] In each of the multiple memory cell strings (MS5), multiple vertical word lines (WL) can penetrate a single horizontal channel area (530) in a vertical direction (Z direction). Here, the number of vertical word lines (WL) penetrating a single horizontal channel area (530) may be at least four. The multiple vertical word lines (WL) penetrating a single horizontal channel area (530) may be arranged in a zigzag manner along a first horizontal direction (X direction).

[0060] Among a plurality of memory cell strings (MS5), an inter-string insulation pattern (524) may be disposed between each of a first group of memory cell strings (MS5) that are placed on the same plane (e.g., XY plane) at the same vertical level. The inter-string insulation pattern (524) may be interposed between two memory cell strings (MS5) that are adjacent to each other among the first group of memory cell strings (MS5) to provide a separation distance between them. The inter-string insulation pattern (524) may be made of a silicon nitride film, an air gap, or a combination thereof.

[0061] The more detailed configuration of the plurality of memory cell strings (MS5) and horizontal channel region (530) is generally the same as described for the plurality of memory cell strings (MS) and horizontal channel region (130) included in the memory cell array (MCA) with reference to FIGS. 1a to 1f and FIG. 2.

[0062] In the three-dimensional non-volatile memory device (500) exemplified in FIG. 6, a plurality of vertical word lines (WL) penetrating a single horizontal channel region (530) are arranged in a zigzag manner along a first horizontal direction (X direction), thereby further reducing the size of the three-dimensional non-volatile memory device (500) in the first horizontal direction (X direction). Thus, a structure advantageous for high integration of the three-dimensional non-volatile memory device (500) can be provided.

[0063] FIGS. 7A and 7B are drawings for explaining a three-dimensional non-volatile memory element (600) according to other embodiments of the technical concept of the present invention. More specifically, FIG. 7A is a partial enlarged plan view of the portion corresponding to the part labeled "EX1" in FIG. 1B of the three-dimensional non-volatile memory element (600). FIG. 7B is a partial enlarged cross-sectional view of the portion corresponding to the part labeled "EX2" in FIG. 1A, and is a cross-sectional view along the line X6 - X6' of FIG. 7A.

[0064] Referring to FIGS. 7a and 7b, the three-dimensional non-volatile memory device (600) has a configuration generally identical to that of the three-dimensional non-volatile memory device (100) described with reference to FIGS. 1a to 1f and FIG. 2. However, the three-dimensional non-volatile memory device (600) may include a memory cell (MC6) instead of a memory cell (MC). The memory cell (MC6) may include a metal-containing pattern (650) interposed between an interface dielectric layer (140) and a ferroelectric layer (160).

[0065] The metal-containing pattern (650) may be placed at the same vertical level as the interface dielectric layer (140) and the horizontal channel region (130). In the three-dimensional non-volatile memory device (600), the horizontal channel region (130), the interface dielectric layer (140), and the metal-containing pattern (650) each penetrate the local hole (130H) of the horizontal channel region (130) in the vertical direction (Z direction), but may not penetrate the local hole (122H) of the inter-cell insulation pattern (122P).

[0066] A horizontal channel region (130), an interface dielectric layer (140), and a metal-containing pattern (650) may be disposed within a space defined by two adjacent inter-cell insulation patterns (122P) in the vertical direction (Z direction) among a plurality of inter-cell insulation patterns (122P) surrounding the perimeter of a vertical word line (WL) and a ferroelectric layer (160). The horizontal channel region (130), the interface dielectric layer (140), and the metal-containing pattern (650) may each have a maximum vertical length (VL6) defined by two adjacent inter-cell insulation patterns (122P) in the vertical direction (Z direction).

[0067] The metal-containing pattern (650) may have a ring shape when viewed in a plane (e.g., an XY plane). The bottom and top surfaces of the metal-containing pattern (650) may each be covered with an inter-cell insulation pattern (122P). The constituent material of the metal-containing pattern (650) is generally the same as that described for the constituent material of the vertical word line (WL) with reference to FIGS. 1a through 1e and FIG. 2.

[0068] In the three-dimensional non-volatile memory device (600) illustrated in FIGS. 7a and 7b, the ferroelectric layer (160) can penetrate the horizontal channel region (130) in the vertical direction (Z direction) between the vertical word line (WL) and the metal-containing pattern (650). The inner surface of the ferroelectric layer (160) is in contact with the vertical word line (WL), and the local surface of the outer surface of the ferroelectric layer (160) facing the horizontal channel region (130) can be in contact with the metal-containing pattern (650).

[0069] In the memory cell (MC6) of the three-dimensional non-volatile memory device (600) illustrated in FIGS. 7a and 7b, a metal-containing pattern (650) is interposed between the interface dielectric layer (140) and the ferroelectric layer (160), thereby more effectively preventing the concentration of the electric field in the interface dielectric layer (140) when the electric field is applied from the vertical word line (WL) to the horizontal channel region (130) during the operation of the three-dimensional non-volatile memory device (600). Additionally, the inner surface of the ferroelectric layer (160) may be in contact with the vertical word line (WL), and the local surface of the outer surface of the ferroelectric layer (160) facing the horizontal channel region (130) may be in contact with the metal-containing pattern (650). Accordingly, when the vertical word line (WL) is made of a metal film or a metal-containing film, the ferroelectric properties of the ferroelectric layer (160) may be further enhanced. For example, if the ferroelectric layer (160) is made of a ferroelectric material based on materials such as HfO2, ZrO2, etc., and includes a TiN film in which a vertical word line (WL) and a metal-containing pattern (650) each contact the ferroelectric layer (160), the strain exerted by the vertical word line (WL) and the metal-containing pattern (650) on the ferroelectric layer (160) acts favorably to maintain an orthorhombic phase (o-phase) in the ferroelectric layer (160), thereby optimizing the ferroelectric properties. Accordingly, the reliability of the three-dimensional non-volatile memory device (600) can be further improved. For example, the vertical word line (WL) includes a W plug and a TiN barrier film that surrounds the W plug and contacts the ferroelectric layer (160), the metal-containing pattern (650) is made of a TiN film, and the ferroelectric layer (160) may be made of a thin film based on a material such as hafnium oxide, zirconium oxide, etc., but is not limited to these.

[0070] FIG. 8a is a plan view for explaining a three-dimensional non-volatile memory device (700) according to another embodiment of the technical concept of the present invention. FIG. 8a illustrates an enlarged planar configuration of a portion of the three-dimensional non-volatile memory device (700) corresponding to the part labeled "EX1" in FIG. 1b.

[0071] Referring to FIG. 8a, the three-dimensional non-volatile memory device (700) has a configuration generally identical to that of the three-dimensional non-volatile memory device (100) described with reference to FIG. 1a to 1f and FIG. 2. However, the three-dimensional non-volatile memory device (700) may include a memory cell (MC7) instead of a memory cell (MC). The memory cell (MC7) may include a gate dielectric structure (740) interposed between a vertical word line (WL) and a horizontal channel region (130).

[0072] The gate dielectric structure (740) may include a tunneling dielectric (742), a charge storage film (744), and a blocking dielectric (746) arranged sequentially from the inner surface of the horizontal channel region (130) toward the vertical word line (WL). The tunneling dielectric (742), the charge storage film (744), and the blocking dielectric (746) may penetrate the horizontal channel region (130) in the vertical direction (Z direction) through a local hole (130H) of the horizontal channel region (130).

[0073] In exemplary embodiments, the tunneling dielectric film (742) may comprise silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film (744) may comprise silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric film (746) may be made of silicon oxide, silicon nitride, or a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. In exemplary embodiments, the blocking dielectric film (746) may be made of an anti-ferroelectric (AFE) material such as ZrO2. When the blocking dielectric film (746) is made of an AFE material, it may provide the effect of lowering the operating voltage of the three-dimensional non-volatile memory device (700).

[0074] FIGS. 8B and FIGS. 8C are drawings for explaining three-dimensional non-volatile memory elements (700A, 700B) according to other embodiments of the technical concept of the present invention, respectively, and are cross-sectional views illustrating various structures along the X7 - X7' line of FIG. 8A. FIGS. 8B and FIGS. 8C illustrate, respectively, an enlarged cross-sectional configuration of a portion corresponding to the part labeled "EX2" in FIG. 1A among the three-dimensional non-volatile memory elements (700A, 700B).

[0075] Referring to FIG. 8b, the three-dimensional non-volatile memory device (700A) may have a configuration generally identical to that of the three-dimensional non-volatile memory device (700) described with reference to FIG. 8a. However, the three-dimensional non-volatile memory device (700A) may include a memory cell (MC7A) comprising a gate dielectric structure (740A) interposed between a vertical word line (WL) and a horizontal channel region (130). In the memory cell (MC7A), the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) may penetrate the horizontal channel region (130) and the cell insulation pattern (122P) in the vertical direction (Z direction) through the local hole (130H) of the horizontal channel region (130) and the local hole (122H) of the cell insulation pattern (122P), respectively.

[0076] FIG. 8b illustrates an example in which the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) are all configured to penetrate the channel region (130) and the inter-cell insulation pattern (122P) in a vertical direction (Z direction), but the technical concept of the present invention is not limited to that illustrated in FIG. 8b. In a three-dimensional non-volatile memory device (700A), at least one of the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) may have a configuration in which it penetrates the channel region (130) and the inter-cell insulation pattern (122P) in a vertical direction (Z direction). At least one of the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) may be configured to surround the outer surface of the vertical word line (WL) along the perimeter of the vertical word line (WL) over the entire length of the vertical direction (Z direction) of the vertical word line (WL).

[0077] Referring to FIG. 8c, the three-dimensional non-volatile memory device (700B) may have a configuration generally identical to that of the three-dimensional non-volatile memory device (700) described with reference to FIG. 8a. However, in the three-dimensional non-volatile memory device (700B), the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) included in the gate dielectric film structure (740B) may each penetrate the local hole (130H) of the horizontal channel region (130) in the vertical direction (Z direction), but may not penetrate the local hole (122H) of the inter-cell insulation pattern (122P). The tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) may each have a maximum vertical length (VL7) limited by two inter-cell insulation patterns (122P) adjacent to each other in the vertical direction (Z direction).

[0078] In FIG. 8c, an example is illustrated in which the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) are all configured to penetrate the channel region (130) in the vertical direction (Z direction) but not the inter-cell insulation pattern (122P); however, the technical concept of the present invention is not limited to that illustrated in FIG. 8c. In a three-dimensional non-volatile memory device (700B), at least one of the tunneling dielectric film (742), the charge storage film (744), and the blocking dielectric film (746) may have a configuration in which it penetrates the channel region (130) in the vertical direction (Z direction) but does not penetrate the inter-cell insulation pattern (122P).

[0079] The three-dimensional non-volatile memory devices (300, 400, 500, 600, 700) illustrated in FIGS. 3 to 8 each include a plurality of horizontal channel regions that overlap each other at spaced-apart positions and a plurality of vertical word lines that penetrate the plurality of horizontal channel regions in the vertical direction, and may have a channel all-around structure in which the horizontal channel regions wrap around the perimeter of the vertical word lines in transistors sharing the plurality of vertical word lines. Accordingly, when an electric field is applied from the vertical word lines to the horizontal channel regions during the operation of the three-dimensional non-volatile memory devices (300, 400, 500, 600, 700), a structure is implemented that prevents the electric field from concentrating on the interface dielectric layer interposed between the vertical word lines and the horizontal channel regions, thereby improving the reliability of the three-dimensional non-volatile memory devices (300, 400, 500, 600, 700). In addition, when a gate insulating film having a structure including a ferroelectric layer is adopted, a relatively large memory window can be secured, and even if the number of stacked memory cells increases along the vertical direction in a three-dimensional non-volatile memory device (300, 400, 500, 600, 700), problems such as WOC (worst on cell current) degradation can be prevented and excellent operating characteristics can be provided.

[0080] FIG. 9 is a cross-sectional view illustrating a three-dimensional non-volatile memory device (800) according to other embodiments of the technical concept of the present invention.

[0081] Referring to FIG. 9, a three-dimensional non-volatile memory device (800) may include a substrate (812), a peripheral circuit region (PE1) disposed on the substrate (812), and a cell region (CE1) disposed on the peripheral circuit region (PE1).

[0082] A peripheral circuit structure (PCS1) may be disposed in the peripheral circuit region (PE1). The cell region (CE1) may include a memory cell array (MCA8) disposed to overlap the peripheral circuit region (PE1) in a vertical direction (Z direction). The memory cell array (MCA8) may have a configuration generally identical to that described for the memory cell array (MCA) of the three-dimensional non-volatile memory device (100) with reference to FIGS. 1a to 1f and FIG. 2. However, in the memory cell array (MCA8), a plurality of vertical word lines (WL) and a plurality of ferroelectric layers (160) may extend to the peripheral circuit region (PE1) by penetrating the etching stop layer (114). Each of the plurality of ferroelectric layers (160) may cover the outer sidewall of the vertical word line (WL) but not the bottom surface of the vertical word line (WL).

[0083] The peripheral circuit area (PE1) may include a substrate (812) and a plurality of circuits (CT1) formed on the substrate (812). The plurality of circuits (CT1) may be disposed between the substrate (812) and the cell area (CE1).

[0084] The substrate (812) may include a semiconductor material, such as a group IV semiconductor material, a group III-V compound semiconductor material, or a group II-VI compound material. In exemplary embodiments, a plurality of circuits (CT1) may include a row decoder, a page buffer, a data input / output circuit, control logic, a common source line driver, etc. In exemplary embodiments, a plurality of circuits (CT1) may further include unit elements such as a resistor, a capacitor, etc.

[0085] A device isolation film (814) defining a plurality of active regions (AC1) may be formed on the substrate (812). A plurality of transistors (TR1) may be formed on the plurality of active regions (AC1), and a plurality of conductive plugs (816) and a plurality of conductive lines (818) may be disposed on the substrate (812) and the plurality of transistors (TR1). The plurality of conductive plugs (816) and the plurality of conductive lines (818) may constitute a wiring structure of a peripheral circuit region (PE1).

[0086] A plurality of transistors (TR1) may each include a gate dielectric film (PD1), a gate electrode (PG1), and a pair of source / drain regions (PSD1). A plurality of conductive plugs (816) may each be configured to connect a selected portion of a plurality of transistors (TR1) and a plurality of conductive lines (818) in a vertical direction (Z direction). An interlayer insulating film (819) may cover a plurality of transistors (TR1), a plurality of conductive plugs (816), and a plurality of conductive lines (818).

[0087] In exemplary embodiments, a plurality of conductive plugs (816) and a plurality of conductive lines (818) in the peripheral circuit region (PE1) may each comprise tungsten, aluminum, copper, or a combination thereof, but are not limited thereto. The device isolation film (814) may be made of silicon oxide, silicon nitride, or a combination thereof. The interlayer insulating film (819) may be made of silicon oxide, silicon nitride, or a combination thereof.

[0088] Each of the plurality of transistors (TR1), the plurality of conductive plugs (816), and the plurality of conductive lines (818) can constitute part of the plurality of circuits (CT1) formed in the peripheral circuit area (PE1). Each of the plurality of transistors (TR1) can be configured to be electrically connected to the cell area (CE1) through the wiring structure of the peripheral circuit area (PE1).

[0089] A plurality of vertical word lines (WL) included in the memory cell array (MCA8) can penetrate a portion of the etching stop layer (114) and the interlayer insulating film (819) in the vertical direction (Z direction) and be connected to a plurality of conductive lines (818) at the top layer among the plurality of conductive lines (818). In exemplary embodiments, the bottom surface of each of the plurality of vertical word lines (WL) included in the memory cell array (MCA8) can be in contact with the top surface of any one of the conductive lines (818) selected among the plurality of conductive lines (818).

[0090] FIG. 9 illustrates a configuration in which a portion of an interlayer insulating film (819) is interposed between the upper surface of each of the plurality of conductive lines (818) in the uppermost layer and the etching stop layer (114), but the technical concept of the present invention is not limited to that illustrated in FIG. 9. For example, the interlayer insulating film (819) may not be interposed between the upper surface of each of the plurality of conductive lines (818) in the uppermost layer and the etching stop layer (114), and the upper surface of the plurality of conductive lines (818) in the uppermost layer may be in contact with the lower surface of the etching stop layer (114).

[0091] FIG. 10 is a cross-sectional view illustrating a three-dimensional non-volatile memory device (900) according to other embodiments of the technical concept of the present invention.

[0092] Referring to FIG. 10, a three-dimensional non-volatile memory device (900) may include a substrate (922), a peripheral circuit region (PE2) disposed on the substrate (922), and a cell region (CE2) spaced vertically from the substrate (922) with the peripheral circuit region (PE2) in between. A peripheral circuit structure (PCS2) may be disposed in the peripheral circuit region (PE2). The cell region (CE2) may include a memory cell array (MCA9) disposed to overlap the peripheral circuit region (PE1) in a vertical direction (Z direction). The memory cell array (MCA9) may have a configuration generally identical to that described for the memory cell array (MCA) of the three-dimensional non-volatile memory device (100) with reference to FIG. 1a to 1f and FIG. 2.

[0093] The peripheral circuit area (PE2) may include a substrate (922) and a plurality of circuits (CT2) formed on the substrate (922). The plurality of circuits (CT2) may be disposed between the substrate (922) and the cell area (CE2). The substrate (922) and the plurality of circuits (CT2) may have a configuration generally identical to that described with respect to the substrate (812) and the plurality of circuits (CT1) with reference to FIG. 8. However, a device isolation film (924) defining a plurality of active areas (AC2) may be formed on the substrate (922). A plurality of transistors (TR2) may be formed on the plurality of active areas (AC2), and a plurality of conductive plugs (926) and a plurality of conductive lines (928) may be disposed on the substrate (922) and the plurality of transistors (TR2). The plurality of conductive plugs (926) and the plurality of conductive lines (928) may constitute a wiring structure of the peripheral circuit area (PE2).

[0094] A plurality of transistors (TR2) may each include a gate dielectric film (PD2), a gate electrode (PG2), and a pair of source / drain regions (PSD2). A plurality of conductive plugs (926) may each be configured to connect a selected portion of a plurality of transistors (TR2) and a plurality of conductive lines (928) in a vertical direction (Z direction). An interlayer insulating film (929) may cover a plurality of transistors (TR2), a plurality of conductive plugs (926), and a plurality of conductive lines (928). The interlayer insulating film (929) may be made of silicon oxide, SiON, SiOCN, or a combination thereof.

[0095] Each of the plurality of transistors (TR2), the plurality of conductive plugs (926), and the plurality of conductive lines (928) can constitute part of the plurality of circuits (CT2) formed in the peripheral circuit area (PE2). Each of the plurality of transistors (TR2) can be configured to be electrically connected to the cell area (CE2) through the wiring structure of the peripheral circuit area (PE2).

[0096] The three-dimensional non-volatile memory device (900) may have a C2C (chip-to-chip) structure. The C2C structure may be obtained by fabricating a first chip including a cell region (CE2) formed on a first wafer, fabricating a second chip including a peripheral circuit region (PE2) formed on a second wafer different from the first wafer, and then connecting the first chip and the second chip to each other by a bonding method. For example, the bonding method may refer to a method of bonding a first bonding metal pad (982) formed on the uppermost metal layer of the first chip including the cell region (CE2) and a second bonding metal pad (984) formed on the uppermost metal layer of the second chip including the peripheral circuit region (PE2) so that they can be electrically connected to each other. In exemplary embodiments, when the first bonding metal pad (982) and the second bonding metal pad (984) are made of copper (Cu), the bonding method may be a Cu-Cu bonding method. In other exemplary embodiments, the first bonding metal pad (982) and the second bonding metal pad (984) may each be made of aluminum (Al) or tungsten (W).

[0097] A cell region (CE2) may include a wiring structure (MS9) formed on the upper part of a memory cell array (MCA9) and a plurality of first bonding metal pads (982) disposed on the wiring structure (MS9). The wiring structure (MS9) may include a first upper wiring layer (974) and a second upper wiring layer (976) connected to one end of each of a plurality of vertical word lines (WL) and a common source line (CSL). In the cell region (CE2), the wiring structure (MS9) and the plurality of first bonding metal pads (982) may be covered with an interlayer insulating film (950). The interlayer insulating film (950) may be made of a silicon oxide film, a silicon nitride film, or a combination thereof.

[0098] The peripheral circuit area (PE2) may include a plurality of second bonding metal pads (984) disposed on a wiring structure comprising a plurality of conductive plugs (926) and a plurality of conductive lines (928). Each of the plurality of second bonding metal pads (984) may be configured to be electrically connected to the first bonding metal pad (178) by being bonded to one of the first bonding metal pads (982) selected from among the plurality of first bonding metal pads (982) included in the cell area (CE2). The plurality of first bonding metal pads (178) and the plurality of second bonding metal pads (278) may form a plurality of bonding structures (BS). An interlayer insulating film (929) may cover a plurality of transistors (TR2), a plurality of conductive plugs (926), a plurality of conductive lines (928), and a plurality of second bonding metal pads (984).

[0099] In exemplary embodiments, a plurality of conductive plugs (926) and a plurality of conductive lines (928) in the peripheral circuit region (PE2) may each comprise tungsten, aluminum, copper, or a combination thereof, but are not limited thereto. The device isolation film (924) may be made of silicon oxide, silicon nitride, or a combination thereof. The interlayer insulating film (929) may be made of silicon oxide, silicon nitride, or a combination thereof. A plurality of first bonding metal pads (982) and a plurality of second bonding metal pads (984) constituting the bonding structure (BS) may each be made of copper, aluminum, or tungsten.

[0100] A plurality of vertical word lines (WL), common source lines (CSL), and bit lines (BL) in the cell region (CE2) can be configured to be connected to a circuit (CT2) in the peripheral circuit region (PE2) through a wiring structure (MS9) and a first bonding metal pad (982). FIG. 10 illustrates a case where the wiring structure (MS9) is composed of a two-layer wiring structure including a plurality of first upper wiring layers (974) and a plurality of second upper wiring layers (976), but the technical concept of the present invention is not limited thereto. For example, the wiring structure (MS9) may be composed of a single-layer wiring structure consisting of a plurality of first upper wiring layers (974) or a plurality of second upper wiring layers (976), or a multi-layer wiring structure of at least three layers.

[0101] The peripheral circuit area (PE2) can be spaced apart from the substrate (110) in a vertical direction (Z direction) with the cell area (CE2) in between.

[0102] The three-dimensional non-volatile memory device (800, 900) described with reference to FIGS. 9 and 10 may have conductive lines included in cell regions (CE1, CE2), such as a plurality of vertical word lines (WL), connected to a plurality of circuits (CT1, CT2) included in peripheral circuit regions (PE1, PE2) that overlap with the cell regions (CE1, CE2) in a vertical direction (Z direction). Accordingly, to improve the integration density in the three-dimensional non-volatile memory device (800, 900), even if the number of vertical stacking (Z direction) of a plurality of horizontal channel regions (130) in the cell regions (CE1, CE2) is increased and the number of transistors to be formed in peripheral circuit regions (PE1, PE2) increases accordingly, the degree of freedom in wiring design in the three-dimensional non-volatile memory device (800, 900) can be improved, and a structure advantageous for high integration and planar size reduction can be provided.

[0103] Next, an exemplary method for manufacturing a three-dimensional non-volatile memory device according to embodiments based on the technical concept of the present invention will be described in detail.

[0104] FIGS. 11a to 21b are drawings illustrated in the order of process to explain a method for manufacturing a three-dimensional non-volatile memory device according to embodiments of the technical concept of the present invention. In particular, FIGS. 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, 19a, 20a, and 21a are cross-sectional views illustrated in the order of process to explain a method for manufacturing a three-dimensional non-volatile memory device according to embodiments according to the technical concept of the present invention, and FIGS. 11b, 12b, 13b, 14b, 15b, 16b, 17b, 18b, 19b, 20b, and 21b are respectively a first on a substrate (110) in FIGS. 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, 19a, 20a, and 21a This is a plan view illustrating the configuration at a vertical level (LV1). Referring to FIGS. 11a to 21b, a method for manufacturing a three-dimensional non-volatile memory device (100) exemplified in FIGS. 1a to 1f will be explained as an example. In FIGS. 11a to 21b, the same reference numerals as in FIGS. 1a to 1f indicate the same components, and redundant descriptions of these are omitted here.

[0105] Referring to FIG. 11a and FIG. 11b, a lower insulating film (112) and an etching stop layer (114) are formed sequentially on a substrate (110), and then a stacked structure can be formed in which a plurality of first insulating films (122) and a plurality of second insulating films (124) are alternately stacked one by one on the etching stop layer (114). After that, a protective film (126) can be formed on the stacked structure.

[0106] A plurality of first insulating films (122) and a plurality of second insulating films (124) may be made of materials having different etching selectivity ratios. In exemplary embodiments, a plurality of first insulating films (122) may be made of silicon oxide films, and a plurality of second insulating films (124) may be made of silicon nitride films. In exemplary embodiments, the protective film (126) may be made of aluminum oxide films or titanium nitride films, but is not limited thereto.

[0107] Referring to FIGS. 12a and 12b, some regions in the results of FIGS. 11a and 11b can be etched to form a plurality of through holes (HL), a first cut space (CS1), and a second cut space (CS2). The first horizontal direction (X direction) width of the memory cell array to be formed on the substrate (110) can be determined by the first cut space (CS1) and the second cut space (CS2).

[0108] By forming a plurality of through holes (HL), a first cut space (CS1), and a second cut space (CS2), a plurality of inter-cell insulation patterns (122P) can be formed from a plurality of first insulating films (122).

[0109] A plurality of through holes (HL), a first cut space (CS1), and a second cut space (CS2) may be formed so as not to be connected to each other. The first cut space (CS1) and the second cut space (CS2) may be formed to extend along a second horizontal direction (Y direction) on the substrate (110). An etch stop layer (114) may be exposed at the bottom of each of the plurality of through holes (HL), the first cut space (CS1), and the second cut space (CS2). While the etching process for forming the plurality of through holes (HL), the first cut space (CS1), and the second cut space (CS2) is being performed, the protective film (126) may serve to protect the underlying structure.

[0110] Referring to FIGS. 13a and FIGS. 13b, the first cut space (CS1) and the second cut space (CS2) in the results of FIGS. 12a and FIGS. 12b can be filled with sacrificial membranes (S1, S2), respectively.

[0111] In exemplary embodiments, the sacrificial layers (S1, S2) may each be made of a silicon nitride film. In other exemplary embodiments, the sacrificial layers (S1, S2) may each have a multilayer structure comprising a sacrificial liner made of silicon oxide and a sacrificial pattern filling a first cut space (CS1) and a second cut space (CS2) on the sacrificial liner. The sacrificial pattern may be made of silicon nitride or polysilicon.

[0112] Referring to FIGS. 14a and 14b, a portion of each of the multiple second insulating films (124) exposed through the multiple through holes (HL) in the result of FIGS. 13a and 13b can be selectively removed to form multiple expansion spaces (EA) around the multiple through holes (HL).

[0113] At a predetermined vertical level on the substrate (110), for example, at a first vertical level (LV1), groups of through holes (HL) aligned along a first horizontal direction (X direction) among a plurality of through holes (HL) can be enclosed in one expansion space (EA).

[0114] Referring to FIGS. 15a and 15b, a plurality of horizontal channel regions (130) and a plurality of interface dielectric layers (140) can be formed sequentially in a plurality of expansion spaces (EA) in the results of FIGS. 14a and 14b.

[0115] In exemplary embodiments, to form a plurality of horizontal channel regions (130) in a plurality of expansion spaces (EA), a channel liner covering the front surface of the result of FIG. 14a and FIG. 14b may be formed by an atomic layer deposition (ALD) process, and an unnecessary portion of the channel liner may be removed so that a plurality of horizontal channel regions (130) remain in the plurality of expansion spaces (EA). In exemplary embodiments, to form a plurality of interface dielectric layers (140) in a plurality of expansion spaces (EA), a dielectric liner covering the front surface of the result in which a plurality of horizontal channel regions (130) are formed may be formed by an ALD process, and an unnecessary portion of the dielectric liner may be removed so that a plurality of interface dielectric layers (140) remain in the plurality of expansion spaces (EA).

[0116] After a plurality of interface dielectric layers (140) are formed, a plurality of sacrificial plugs (S3) that fill a plurality of through holes (HL) can be formed. In exemplary embodiments, the plurality of sacrificial plugs (S3) may each be made of a silicon nitride film. In other exemplary embodiments, the plurality of sacrificial plugs (S3) may each have a multilayer structure comprising a sacrificial liner made of silicon nitride and a sacrificial plug that fills a plurality of through holes (HL) on the sacrificial liner. The sacrificial plug may be made of polysilicon.

[0117] Referring to FIGS. 16a and 16b, the sacrificial film (S1) can be removed from the first cut space (CS1) in the result of FIGS. 15a and 15b to expose an etching stop layer (114) at the bottom of the first cut space (CS1) and to expose a plurality of inter-cell insulation patterns (122P) and a plurality of second insulation films (124) at the sidewalls of the first cut space (CS1).

[0118] Referring to FIGS. 17a and 17b, a portion of each of the plurality of second insulating films (124) exposed through the first cut space (CS1) in the result of FIGS. 16a and 16b can be selectively removed to form a plurality of bit line spaces (BLS) connected to the first cut space (CS1). A plurality of horizontal channel regions (130) can be exposed through the plurality of bit line spaces (BLS).

[0119] Referring to FIGS. 18a and 18b, in the result of FIGS. 17a and 17b, an ohmic contact portion (130A) can be formed in a portion of each of the plurality of horizontal channel regions (130) exposed through the plurality of bit line spaces (BLS), and a plurality of bit lines (BL) can be formed to fill the plurality of bit line spaces (BLS). After that, the first cut space (CS1) can be filled with a separating insulating film (152).

[0120] In exemplary embodiments, dopant ions may be implanted into a portion of each of the plurality of horizontal channel regions (130) through the first cut space (CS1) to form an ohmic contact portion (130A). In exemplary embodiments, the process of forming the ohmic contact portion (130A) may be omitted.

[0121] Referring to FIGS. 19a and 19b, in the result of FIGS. 18a and 18b, the sacrificial film (S2) can be removed from the second cut space (CS2) to expose an etching stop layer (114) at the bottom of the second cut space (CS2) and to expose a plurality of inter-cell insulation patterns (122P) and a plurality of second insulation films (124) at the sidewalls of the second cut space (CS2). Then, the plurality of second insulation films (124) exposed through the second cut space (CS2) can be selectively removed to form a plurality of source line spaces (SLS) connected to the second cut space (CS2). A plurality of horizontal channel regions (130) and inter-cell insulation patterns (122P) can be exposed through the plurality of source line spaces (SLS).

[0122] In the result of selectively removing a plurality of second insulating films (124) exposed through a second cut space (CS2) to form a plurality of source line spaces (SLS), the remaining portions of the plurality of second insulating films (124) can form an inter-string insulating pattern (124P).

[0123] Referring to FIGS. 20a and FIGS. 20b, in the result of FIGS. 19a and FIGS. 19b, an ohmic contact portion (130B) is formed in a portion of each of the multiple horizontal channel regions (130) exposed through the multiple source line spaces (SLS), and the multiple source line spaces (SLS) and the second cut space (CS2) can be filled with a common source line (CSL).

[0124] In exemplary embodiments, dopant ions may be implanted into a portion of each of the plurality of horizontal channel regions (130) through the second cut space (CS2) to form an ohmic contact portion (130B). In exemplary embodiments, the process of forming the ohmic contact portion (130B) may be omitted.

[0125] Referring to FIGS. 21a and FIGS. 21b, after removing a plurality of sacrificial plugs (S3) from a plurality of through holes (HL) in the result of FIGS. 20a and FIGS. 20b, a plurality of ferroelectric layers (160) conformally covering the inner walls of a plurality of through holes (HL) and a plurality of vertical word lines (WL) filling the plurality of through holes (HL) on the plurality of ferroelectric layers (160) can be formed.

[0126] In exemplary embodiments, to form a plurality of ferroelectric layers (160) and a plurality of vertical word lines (WL), a ferroelectric material liner is formed conformally to the inner wall of each of a plurality of through holes (HL) on the result from which a plurality of sacrificial plugs (S3) have been removed, a conductive layer having a thickness sufficient to fill the plurality of through holes (HL) is formed on the ferroelectric material liner, and the upper portion of the conductive layer and the ferroelectric material liner can be removed by a chemical mechanical polishing (CMP) process or an etchback process so that the plurality of ferroelectric layers (160) and a plurality of vertical word lines (WL) remain.

[0127] In other exemplary embodiments, instead of forming a plurality of ferroelectric layers (160), a ferroelectric material liner conformally covers the inner wall of each of the plurality of through holes (HL) on the result from which a plurality of sacrificial plugs (S3) have been removed, and then the ferroelectric material liner is etched back to form a plurality of ferroelectric layers having a shape that covers the side wall of each of the plurality of through holes (HL) but does not cover the bottom of each of the plurality of through holes (HL). After that, a plurality of vertical word lines (WL) that fill the plurality of through holes (HL) can be formed. In this case, the bottom surface of each of the plurality of vertical word lines (WL) may not be covered by the ferroelectric layer.

[0128] While forming a plurality of ferroelectric layers (160) and a plurality of vertical word lines (WL), the protective film (126) is removed so that the upper surface of the uppermost cell insulation pattern (122P) among the plurality of cell insulation patterns (122P) can be exposed.

[0129] According to the method for manufacturing a three-dimensional non-volatile memory device (100) described with reference to FIGS. 11a to 21b, a plurality of horizontal channel regions (130), a plurality of bit lines (BL), and a common source line (CSL) that overlap each other in the vertical direction (Z direction) are first formed, and then a plurality of ferroelectric layers (160) and a plurality of vertical word lines (WL) that penetrate the plurality of horizontal channel regions (130) in the vertical direction (Z direction) can be formed. Accordingly, in the manufacturing process of the three-dimensional non-volatile memory device (100), the thermal burden of the ferroelectric layer (160), which may be made of a material that is relatively vulnerable to thermal burden (thermal budget), can be reduced. Accordingly, the possibility of degradation of the ferroelectric layer (160) during the manufacturing process of the three-dimensional non-volatile memory device (100), and / or the possibility of defects such as oxygen vacancy caused by unwanted intermixing between the ferroelectric layer (160) and the adjacent metal-containing film can be significantly reduced, and the reliability of the three-dimensional non-volatile memory device (100) can be improved.

[0130] Although an exemplary method for manufacturing a three-dimensional non-volatile memory device (100) has been described with reference to FIGS. 11a to 21b, those skilled in the art will understand that the three-dimensional non-volatile memory devices (200, 300, 400, 500, 600, 700, 700A, 700B, 800, 900) exemplified in FIGS. 2 to 10 can be formed by making various modifications and changes within the scope of the technical concept of the present invention as described with reference to FIGS. 11a to 21b.

[0131] For example, to manufacture a three-dimensional non-volatile memory device (200) exemplified in FIG. 3, in the process described with reference to FIG. 12a and FIG. 12b, after making the first horizontal direction (X direction) separation distance between the second cut space (CS2) and the plurality of through holes (HL) larger than in FIG. 12a and FIG. 12b, and then forming an ohmic contact portion (130B) in a portion of each of the plurality of horizontal channel regions (130) in the process of FIG. 20a and FIG. 20b, a plurality of source lines (SL) that fill a plurality of source line spaces (SLS) (see FIG. 19a and FIG. 19b) through the second cut space (CS2) can be formed. After that, the second cut space (CS2) can be filled with an insulating film.

[0132] In exemplary embodiments, to manufacture the three-dimensional non-volatile memory device (300) illustrated in FIG. 4, a process of removing at least a portion of a plurality of second insulating films (124) through a plurality of bit line spaces (BLS) before forming a plurality of bit lines (BL) in the process described with reference to FIG. 18a and FIG. 18b, and / or a process of removing at least a portion of a plurality of second insulating films (124) through a second cut space (CS2) before forming a common source line (CSL) in the process of FIG. 20a and FIG. 20b may be performed to form a plurality of air gaps (AG). In this case, in the process of forming a plurality of bit lines (BL) and / or the process of forming a common source line (CSL), a first deposition process may be performed to deposit a conductive material with a deposition process that provides relatively degraded step coverage so that the plurality of air gaps (AG) are closed, and then a second deposition process may be performed to provide relatively good step coverage.

[0133] In exemplary embodiments, to manufacture the three-dimensional non-volatile memory device (400, 500) illustrated in FIGS. 5 and 6, the first horizontal (X-direction) separation distance between the first cut space (CS1) and the second cut space (CS2), and the number and arrangement of the plurality of through holes (HL) can be designed in various ways as desired in the process described with reference to FIGS. 12a and 12b.

[0134] Although exemplary embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0135] 110: Substrate, 130: Horizontal channel area, 140: Interface dielectric layer, 160: Ferroelectric layer, BL: Bit line, CSL: Common source line, WL: Word line.

Claims

Claim 1 A memory cell array comprising a plurality of memory cells repeatedly arranged along a first horizontal direction and a second horizontal direction parallel to and mutually orthogonal to the main surface of the substrate, and a vertical direction perpendicular to the main surface, wherein the memory cell array comprises a plurality of horizontal channel regions that extend longitudinally in the first horizontal direction on the substrate and overlap each other at positions spaced apart along the vertical direction, a plurality of vertical word lines that penetrate the plurality of horizontal channel regions in the vertical direction and are spaced apart from each other in the first horizontal direction, a plurality of bit lines disposed on one side of the plurality of memory cells, and a common source line disposed on the other side of the plurality of memory cells, wherein a first bit line selected among the plurality of bit lines is connected to one side of the first horizontal channel region selected among the plurality of horizontal channel regions, and the common source line is connected to the other side furthest from the one side of the first horizontal channel region in the first horizontal direction, wherein the plurality of bit lines and the common source line are spaced apart in the first horizontal direction with the plurality of memory cells in between, and the plurality of bit lines and the common source line are each extended parallel to each other along the second horizontal direction 3D non-volatile memory device. Claim 2 A three-dimensional non-volatile memory device according to claim 1, wherein the memory cell array further comprises a plurality of inter-cell insulation patterns interposed between each of the plurality of horizontal channel regions and overlapping the plurality of horizontal channel regions in the vertical direction, and the plurality of vertical word lines each comprise a plurality of first local regions surrounded by the plurality of horizontal channel regions and a plurality of second local regions surrounded by the inter-cell insulation patterns in the string insulation pattern. Claim 3 In claim 1, the memory cell array further comprises a ferroelectric layer interposed between a first vertical word line selected among the plurality of vertical word lines and the plurality of horizontal channel regions and penetrating the plurality of horizontal channel regions in the vertical direction, and a plurality of interface dielectric layers interposed between the ferroelectric layer and the plurality of horizontal channel regions and disposed at the same vertical level as the plurality of horizontal channel regions, wherein the ferroelectric layer surrounds the outer surface of the first vertical word line and contacts the outer surface of the first vertical word line, a three-dimensional non-volatile memory device. Claim 4 A three-dimensional non-volatile memory device according to claim 1, wherein the memory cell array further comprises a plurality of interface dielectric layers interposed between a first vertical word line selected among the plurality of vertical word lines and the plurality of horizontal channel regions and disposed at the same vertical level as the plurality of horizontal channel regions, a plurality of metal-containing patterns interposed between the first vertical word line and the plurality of interface dielectric layers and disposed at the same vertical level as the plurality of horizontal channel regions, and a ferroelectric layer interposed between the first vertical word line and the plurality of metal-containing patterns and penetrating the plurality of horizontal channel regions in the vertical direction, wherein the inner surface of the ferroelectric layer contacts the first vertical word line, and a local surface among the outer surfaces of the ferroelectric layer facing the horizontal channel region contacts the metal-containing pattern. Claim 5 The memory cell array further comprises a plurality of inter-cell insulation patterns interposed between each of the plurality of horizontal channel regions and overlapping with the plurality of horizontal channel regions in the vertical direction, and a gate dielectric structure interposed between a first vertical word line selected among the plurality of vertical word lines and the plurality of horizontal channel regions, wherein the gate dielectric structure comprises a tunneling dielectric, a charge storage film, and a blocking dielectric, which are sequentially arranged from the inner surface of each of the plurality of horizontal channel regions in a direction approaching the first vertical word line, and at least one of the tunneling dielectric, the charge storage film, and the blocking dielectric is a three-dimensional non-volatile memory device that penetrates the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction. Claim 6 The memory cell array further comprises a plurality of inter-cell insulation patterns interposed one by one between each of the plurality of horizontal channel regions and overlapping with the plurality of horizontal channel regions in the vertical direction, and a plurality of gate dielectric film structures interposed between a first vertical word line selected among the plurality of vertical word lines and the plurality of horizontal channel regions, wherein the plurality of gate dielectric film structures each comprise a tunneling dielectric film, a charge storage film, and a blocking dielectric film sequentially arranged from the inner surface of each of the plurality of horizontal channel regions in a direction approaching the first vertical word line, and at least one of the tunneling dielectric film, the charge storage film, and the blocking dielectric film has a maximum vertical length defined by two inter-cell insulation patterns adjacent to each other in the vertical direction among the plurality of inter-cell insulation patterns. Claim 7 In claim 1, the plurality of horizontal channel regions each comprise a first ohmic contact portion adjacent to one bit line selected among the plurality of bit lines and a second ohmic contact portion adjacent to the common source line, forming a three-dimensional non-volatile memory device. Claim 8 A memory cell array comprising a substrate having a main surface and a plurality of memory cells repeatedly arranged on the substrate along a first horizontal direction and a second horizontal direction parallel to and mutually orthogonal to the main surface of the substrate and a vertical direction perpendicular to the main surface, wherein the memory cell array comprises a plurality of horizontal channel regions that overlap each other at positions spaced apart along the vertical direction on the substrate and each extend parallel to the main surface, a plurality of inter-cell insulation patterns interposed one by one between each of the plurality of horizontal channel regions, a plurality of vertical word lines penetrating the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction, a plurality of bit lines arranged on one side of the plurality of memory cells, and a common source line arranged on the other side of the plurality of memory cells, wherein a first bit line selected among the plurality of bit lines is connected to one side of a first horizontal channel region selected among the plurality of horizontal channel regions, and the common source line is connected to the other side furthest from the one side of the first horizontal channel region in the first horizontal direction, and the plurality of bit lines and the common source line are spaced apart in the first horizontal direction with the plurality of memory cells in between. A three-dimensional non-volatile memory device wherein the plurality of bit lines and the common source line each extend in mutually parallel along the second horizontal direction, and each of the plurality of horizontal channel regions includes a plurality of ring channel portions that define a plurality of first local holes spaced apart from each other and are regularly arranged along the first horizontal direction, and a plurality of connection portions arranged between each of the plurality of ring channel portions, and the plurality of inter-cell insulation patterns include a plurality of second local holes aligned with the plurality of first local holes and the vertical direction, and the plurality of vertical word lines penetrate the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction through the plurality of first local holes and the plurality of second local holes. Claim 9 In claim 8, the plurality of vertical word lines are arranged in a straight line along the first horizontal direction, and the plurality of horizontal channel regions each include a first ohmic contact portion that contacts one bit line selected among the plurality of bit lines and a second ohmic contact portion that contacts the common source line, a three-dimensional non-volatile memory device. Claim 10 In claim 8, the plurality of vertical word lines are arranged in a zigzag manner in the first horizontal direction, and the plurality of horizontal channel regions each include a first ohmic contact portion that contacts one bit line selected among the plurality of bit lines and a second ohmic contact portion that contacts the common source line, a three-dimensional non-volatile memory device. Claim 11 A three-dimensional non-volatile memory device according to claim 8, further comprising a plurality of ferroelectric layers penetrating the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction through the plurality of first local holes and the plurality of second local holes, and a plurality of interface dielectric layers surrounding the outer sidewalls of the plurality of ferroelectric layers within the plurality of first local holes, wherein each of the plurality of ferroelectric layers contacts the outer sidewall of one vertical word line selected among the plurality of vertical word lines. Claim 12 A three-dimensional non-volatile memory device according to claim 8, comprising a plurality of ferroelectric layers penetrating the plurality of horizontal channel regions and the plurality of inter-cell insulation patterns in the vertical direction within the plurality of first local holes and the plurality of second local holes, and a plurality of metal-containing patterns surrounding the outer sidewalls of the plurality of ferroelectric layers within the plurality of first local holes, wherein each of the plurality of metal-containing patterns has a maximum vertical length defined by two inter-cell insulation patterns adjacent to each other in the vertical direction among the plurality of inter-cell insulation patterns. Claim 13 In claim 8, the three-dimensional non-volatile memory device further comprises a plurality of gate dielectric structures surrounding the outer surface of the plurality of vertical word lines within the plurality of first local holes, wherein each of the plurality of gate dielectric structures comprises a tunneling dielectric, a charge storage film, and a blocking dielectric, each arranged sequentially in a direction approaching one of the vertical word lines from the inner surface of the ring channel portion of each of the plurality of horizontal channel regions, and at least one of the tunneling dielectric, the charge storage film, and the blocking dielectric penetrates the plurality of horizontal channel regions and the plurality of cell-to-cell insulation patterns in the vertical direction through the plurality of first local holes and the plurality of second local holes. Claim 14 A three-dimensional non-volatile memory device according to claim 8, further comprising a plurality of gate dielectric structures surrounding the outer surface of the plurality of vertical word lines within the plurality of first local holes, wherein each of the plurality of gate dielectric structures comprises a tunneling dielectric, a charge storage film, and a blocking dielectric, each arranged sequentially in a direction approaching one of the vertical word lines from the inner surface of the ring channel portion of each of the plurality of horizontal channel regions, and at least one of the tunneling dielectric, the charge storage film, and the blocking dielectric has a maximum vertical length defined by two inter-cell insulation patterns adjacent to each other in the vertical direction among the plurality of inter-cell insulation patterns. Claim 15 A memory cell array comprising a substrate having a main surface, and a plurality of memory cell strings each extending longitudinally along a first horizontal direction parallel to the main surface on the substrate, and repeatingly arranged along a second horizontal direction parallel to the main surface and orthogonal to the first horizontal direction, and a vertical direction perpendicular to the main surface; a plurality of bit lines connected to one side of each of the plurality of memory cell strings and overlapping each other at positions spaced apart along the vertical direction; and at least one source line spaced apart from the plurality of bit lines in the first horizontal direction with the plurality of memory cell strings in between and connected to the other side of each of the plurality of memory cell strings, wherein each of the plurality of memory cell strings includes a plurality of ring channel portions defining a plurality of local holes spaced apart from each other and regularly arranged along the first horizontal direction, a horizontal channel region including a plurality of connection portions arranged between each of the plurality of ring channel portions, and a plurality of vertical word lines penetrating the horizontal channel region in the vertical direction through the plurality of local holes, wherein a first bit line selected among the plurality of bit lines is connected to one side of the horizontal channel region, and the at least one A three-dimensional non-volatile memory element in which a first source line selected from among the source lines is connected to the other side furthest from the first horizontal direction from the one side of the horizontal channel region, the plurality of bit lines and the at least one source line are spaced apart in the first horizontal direction with the plurality of memory cell strings in between, and the plurality of bit lines and the at least one source line are each extended mutually parallel to each other along the second horizontal direction. Claim 16 In claim 15, each of the plurality of bit lines is shared by a first group of memory cell strings disposed at the same vertical level on the main surface of the substrate, and each of the plurality of memory cell strings further comprises a plurality of ferroelectric layers penetrating the horizontal channel region of each of the plurality of memory cell strings in the vertical direction through the plurality of local holes, and each of the plurality of ferroelectric layers contacts the outer sidewall of one vertical word line selected among the plurality of vertical word lines, a three-dimensional non-volatile memory device. Claim 17 In claim 15, the plurality of vertical word lines are a three-dimensional non-volatile memory element shared by a second group of memory cell strings that overlap each other along the vertical direction among the plurality of memory cell strings. Claim 18 In claim 15, the at least one source line is composed of a common source line connected to the other side of each of the plurality of memory cell strings, and each of the horizontal channel regions of each of the plurality of memory cell strings includes a first ohmic contact portion in contact with one bit line selected among the plurality of bit lines and a second ohmic contact portion in contact with the common source line, thereby forming a three-dimensional non-volatile memory device. Claim 19 In claim 15, the at least one source line comprises a plurality of source lines that overlap each other at positions spaced apart along the vertical direction, and each of the plurality of source lines is shared by a first group of memory cell strings arranged at the same vertical level on the main surface of the substrate, forming a three-dimensional non-volatile memory device. Claim 20 A three-dimensional non-volatile memory device according to claim 15, further comprising a peripheral circuit structure interposed between the substrate and the memory cell array, the peripheral circuit structure comprising a plurality of transistors and a plurality of wiring structures connected to the plurality of transistors, wherein the plurality of wiring structures comprises at least one conductive line configured to be connected to at least one vertical word line among the plurality of vertical word lines.

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