Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package comprises a package substrate having wirings provided in each of a plurality of layers and insertion holes that extend in the thickness direction from the upper surface and expose portions of the wirings of different layers, a semiconductor chip disposed such that a first surface having chip pads formed on the package substrate faces the upper surface of the package substrate, a plurality of connection pins provided on the chip pads and extending into the corresponding insertion holes to electrically connect with the exposed portions of the wirings, and a sealing member provided on the package substrate to cover the semiconductor chip.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a semiconductor package comprising a semiconductor chip mounted by a flip-chip bonding method and a method for manufacturing the same. Background Technology

[0002] A semiconductor package structure utilizing a flip chip has the advantage of achieving improved electrical characteristics and a relatively lower package height compared to a conventional wire bonding structure. However, due to the characteristics of the flip chip bonding process, tilting of the semiconductor chip occurs, and in the case of a package product with a dolmen structure, there is a problem in that a sealing member penetrates into the space between the semiconductor chip and the upper semiconductor chip due to the tilting of the semiconductor chip. The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor package having structural stability and improved electrical characteristics.

[0004] Another objective of the present invention is to provide a method for manufacturing the semiconductor package described above. means of solving the problem

[0005] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises: a package substrate having wirings provided in each of a plurality of layers and insertion holes that extend in the thickness direction from the upper surface and expose portions of the wirings of different layers; a semiconductor chip disposed such that a first surface having chip pads formed on the package substrate faces the upper surface of the package substrate; a plurality of connection pins provided on the chip pads and extending into the corresponding insertion holes to electrically connect with the exposed portions of the wirings; and a sealing member provided on the package substrate to cover the semiconductor chip.

[0006] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises: a package substrate having first to third wires sequentially stacked from an upper surface and first to third insertion holes that extend from the upper surface to different depths in the thickness direction and expose portions of the first to third wires, respectively; a semiconductor chip disposed such that a first surface on the package substrate having chip pads formed thereon faces the upper surface of the package substrate; a plurality of connection pins each having first to third connection pins that extend into the corresponding first to third insertion holes and electrically connect to the exposed portions of the first to third wires, respectively, provided on the chip pads; and a sealing member provided on the package substrate to cover the semiconductor chip. The first to third insertion holes have a diameter within the range of 15 μm to 150 μm, and the first to third connection pins have a diameter within the range of 5 μm to 95 μm.

[0007] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises a package substrate, a first semiconductor chip disposed such that a first surface having chip pads formed on an upper surface of the package substrate faces the package substrate, a plurality of connection pins each provided on the chip pads of the first semiconductor chip, at least one support structure spaced apart from the first semiconductor chip on an upper surface of the package substrate, a plurality of second semiconductor chips mounted on the package substrate to be supported on the support structure, and a sealing member covering the support structure, the first semiconductor chip, and the second semiconductor chips on an upper surface of the package substrate. The package substrate includes wirings each provided on a plurality of layers and has insertion holes each extending in the thickness direction from the upper surface and each exposing a portion of the wirings of different layers. The connection pins extend into the corresponding insertion holes and electrically connect with the portions of the wirings. Effects of the invention

[0008] According to exemplary embodiments, a semiconductor package may include a package substrate having insertion holes that extend in the thickness direction from the top surface and expose portions of wiring of different layers, a semiconductor chip disposed such that a first surface having chip pads formed thereon faces the top surface of the package substrate, and a plurality of connection pins that are each provided on the chip pads and extend into the corresponding insertion holes to electrically connect to the exposed portions of the wiring.

[0009] Accordingly, the semiconductor chip can be mounted on the package substrate via the connection pins inserted into the insertion holes formed in the package substrate without using existing bumps.

[0010] Accordingly, since the connection pins are inserted into the insertion holes, the overall package thickness can be reduced. In addition, since the chip pads of the semiconductor chip are directly connected to the wiring inside the package substrate by the connection pins, the routing space can be reduced and electrical characteristics can be improved.

[0011] However, the effects of the present invention are not limited to the effects mentioned above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0012] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 2 is an enlarged cross-sectional view showing part A of Figure 1. Figure 3 is a plan view showing the semiconductor package of Figure 1. FIGS. 4 to 18 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 19 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 20 is an enlarged cross-sectional view showing part D of FIG. 19. FIGS. 21 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Specific details for implementing the invention

[0013] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

[0014] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 2 is an enlarged cross-sectional view showing portion A of FIG. 1. FIG. 3 is a top view showing the semiconductor package of FIG. 1. FIG. 1 is a cross-sectional view cut along line II' of FIG. 3.

[0015] Referring to FIGS. 1 to 3, a semiconductor package (10) may include a package substrate (100), a semiconductor chip (200), a plurality of connection pins (300), and a molding member (400). Additionally, the semiconductor package (10) may further include external connection members (500).

[0016] In exemplary embodiments, the package substrate (100) may be a multilayer circuit board having an upper surface (102) and a lower surface (104) facing each other. For example, the package substrate (100) may be a printed circuit board (PCB) comprising wirings provided in each of the plurality of layers and vias for connecting them.

[0017] Specifically, the package substrate (100) may include a plurality of stacked insulating layers (110) and wirings (120a, 120b, 120c, 120d) respectively provided on the insulating layers.

[0018] The package substrate (100) may include first to fifth insulating layers (110a, 110b, 110c, 110d, 110e) stacked sequentially. The first insulating layer (110a) may be an upper cover insulating layer, the second insulating layer (110b) may be an upper insulating layer, the third insulating layer (110c) may be a core layer, the fourth insulating layer (110d) may be a lower insulating layer, and the fifth insulating layer (110e) may be a lower cover insulating layer.

[0019] For example, the insulating layer may include an insulating material such as a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulating layer may include a resin impregnated in a core material such as an organic fiber (glass fiber), for example, prepreg, FR-4, BT (Bismaleimide Triazine), etc.

[0020] The first wiring (120a) may be formed on the upper surface of the second insulating layer (110b), and the second wiring (120b) may be formed on the upper surface of the third insulating layer (110c). The third wiring (120c) may be formed on the lower surface of the third insulating layer (110c), and the fourth wiring (120d) may be formed on the lower surface of the fourth insulating layer (110d). The first to fourth wirings (120a, 120b, 120c, 120d) may be first to fourth circuit layers stacked in the thickness direction from the upper surface (102) of the package substrate (100). For example, the wiring may include a metallic material such as copper, aluminum, etc. It will be understood that the arrangement and number of the insulating layers and the conductive patterns are exemplary and are not limited thereto.

[0021] The package substrate (100) may have a plurality of insertion holes (112a, 112b, 112c, 112d) of different depths extending in the thickness direction from the upper surface (102). For example, the insertion holes (112a, 112b, 112c, 112d) may have a diameter within the range of 15 μm to 150 μm.

[0022] The first insertion hole (112a) can extend the first insulating layer (110a) in the thickness direction from the upper surface (102) to expose a portion of the first wiring (120a). The first insertion hole (112a) can expose a portion of the first circuit layer by having a first depth (D1) from the upper surface (102). The portion of the first wiring (120a) exposed by the first insertion hole (112a) can serve as a first connection pad to which the first connection pin (300a) is connected.

[0023] The second insertion hole (112b) can extend the first and second insulating layers (110a, 110b) in the thickness direction from the upper surface (102) to expose a portion of the second wiring (120b). The second insertion hole (112b) can expose a portion of the second circuit layer by having a second depth (D2) greater than the first depth (D1) from the upper surface (102). The portion of the second wiring (120b) exposed by the second insertion hole (112b) can serve as a second connection pad to which the second connection pin (300b) is connected.

[0024] The third insertion hole (112c) can extend the first, second, and third insulating layers (110a, 110b, 110c) in the thickness direction from the upper surface (102) to expose a portion of the third wiring (120c). The third insertion hole (112c) can expose a portion of the third circuit layer by having a third depth (D3) greater than the second depth (D2) from the upper surface (102). The portion of the third wiring (120c) exposed by the third insertion hole (112c) can serve as a third connection pad to which the third connection pin (300c) is connected.

[0025] The fourth insertion hole (112d) can extend the first, second, third, and fourth insulating layers (110a, 110b, 110c, 110d) in the thickness direction from the upper surface (102) to expose a portion of the fourth wiring (120d). The fourth insertion hole (112d) can expose a portion of the fourth circuit layer by having a fourth depth (D4) greater than the third depth (D3) from the upper surface (102). The portion of the fourth wiring (120d) exposed by the fourth insertion hole (112d) can serve as a fourth connection pad to which the fourth connection pin (300d) is connected.

[0026] A semiconductor chip (200) can be placed on a package substrate (100). The semiconductor chip (200) can be mounted on the package substrate (100) through connection pins (300). The planar area of ​​the semiconductor chip (200) may be smaller than the planar area of ​​the package substrate (100). When viewed in a planar view, the semiconductor chip (200) can be placed within an area of ​​the package substrate (100).

[0027] A semiconductor chip (200) may include a plurality of chip pads (230) provided on a first surface (212). Connection pins (300) having different heights may be provided on the plurality of chip pads (230). The connection pins (300) may have a diameter within the range of 5 μm to 95 μm.

[0028] A first connection pin (300a) having a first height (H1) may be provided on the first chip pad (230a). A second connection pin (300b) having a second height (H2) may be provided on the second chip pad (230b). The second height (H2) may be greater than the first height (H1). A third connection pin (300c) having a third height (H3) may be provided on the third chip pad (230c). The third height (H3) may be greater than the second height (H2). A fourth connection pin (300d) having a fourth height (H4) may be provided on the fourth chip pad (230d). The fourth height (H4) may be greater than the third height (H3). For example, the first to fourth heights may be within the range of 15 μm to 300 μm. The difference between each height, for example, the difference between the second height and the first height may be within the range of 15㎛ to 180㎛.

[0029] In exemplary embodiments, the semiconductor chip (200) may be mounted on the package substrate (100) by a flip chip bonding method. In this case, the semiconductor chip (200) may be mounted on the package substrate (100) such that the active surface, i.e., the first surface (212), on which the chip pads (230) are formed, faces the package substrate (100). An underfill member (350) may be provided between the first surface (212) of the semiconductor chip (200) and the upper surface (102) of the package substrate (100).

[0030] When a semiconductor chip (200) is mounted on a package substrate (100), the connection pins (300) on the chip pads (230) are inserted into the insertion holes formed in the package substrate (100), and the connection pins (300) can be joined to parts of the wiring exposed by the insertion holes by a heat pressing process. The connection pins (300) can partially penetrate the insulating layers (110) of the package substrate (100) and serve as vias to electrically connect the wiring.

[0031] The first connection pin (300a) can be inserted into the first insertion hole (112a) and electrically connected to a part of the first wiring (120a) exposed by the first insertion hole (112a), i.e., the first connection pad. The second connection pin (300b) can be inserted into the second insertion hole (112b) and electrically connected to a part of the second wiring (120b) exposed by the second insertion hole (112b), i.e., the second connection pad. The third connection pin (300c) can be inserted into the third insertion hole (112c) and electrically connected to a part of the third wiring (120c) exposed by the third insertion hole (112c), i.e., the third connection pad. The fourth connection pin (300d) can be inserted into the fourth insertion hole (112d) and electrically connected to a part of the fourth wiring (120d) exposed by the fourth insertion hole (112d), i.e., the fourth connection pad.

[0032] As illustrated in FIG. 2, the second connection pin (300b) may include a connection post (30) and a metal bonding layer (32) formed on the surface of the connection post (30). The second connection pin (300b) may be connected to a portion of the second wiring (120b) exposed by the second insertion hole (112b) by a heat pressing process. At this time, the metal bonding layer (32) may be melted at a high temperature to at least partially fill the space between the surface of the connection post (30) and the inner surface of the second insertion hole (112b).

[0033] As illustrated in FIG. 3, chip pads (230) of a semiconductor chip (200) are arranged in an array form in a pad area (R), and connection pins (300) may be provided on each of the chip pads (230) within the pad area (R). Dummy connection pillars (310) may be provided on each of the four corner areas outside the pad area (R). Dummy connection pillars (310) may be provided on each of the dummy pads provided on the first surface (212) of the semiconductor chip (200).

[0034] The dummy connection pillars (310) may have a height smaller than the height (H1) of the first connection pin (300a). The dummy connection pillars (310) may have a diameter larger than the diameter of the first connection pin (300a). The dummy connection pillars (310) may extend from the first surface (212) of the semiconductor chip (200) to contact the upper surface (102) of the package substrate (100). The dummy connection pillars (310) may be positioned between the first surface (212) of the semiconductor chip (200) and the upper surface (102) of the package substrate (100). The dummy connection pillars (310) may support the semiconductor chip (200) so that the semiconductor chip (200) is stably attached to the package substrate (100) when the semiconductor chip (200) is mounted via the connection pins (300).

[0035] In exemplary embodiments, a sealing member (400) may be formed on a package substrate (100) to protect a semiconductor chip (200) from the outside. The sealing member may include an epoxy mold compound (EMC).

[0036] On the lower surface (104) of the package substrate (100), external connection pads for providing electrical signals, namely, parts of the fourth wiring (120d) exposed by the fifth insulating layer (110e), may be provided. On the external connection pads of the package substrate (100), an external connection member (500) may be disposed for electrical connection with an external device. For example, the external connection member (500) may be a solder ball. The semiconductor package (10) may be mounted on a module substrate (not shown) via the solder balls to form a memory module.

[0037] As described above, the semiconductor package (10) may include a package substrate (100) having insertion holes that extend in the thickness direction from the upper surface (102) and expose portions of the wiring of different layers, a semiconductor chip (200) arranged such that a first surface (212) on which chip pads (230) are formed faces the upper surface (102) of the package substrate (100), and a plurality of connection pins (300) that are respectively provided on the chip pads (230) and extend into the corresponding insertion holes to electrically connect with portions of the wiring.

[0038] Accordingly, the semiconductor chip (200) can be mounted on the package substrate (100) by means of connection pins (300) inserted into the insertion holes formed in the package substrate (100) without using existing bumps.

[0039] Accordingly, the connection pins (300) are inserted into the insertion holes, thereby reducing the overall package thickness. Additionally, since the chip pads (230) of the semiconductor chip (200) are directly connected to the internal wiring of the package substrate (100) by the connection pins (300), the routing space can be reduced and electrical characteristics can be improved.

[0040] Below, a method for manufacturing the semiconductor package of FIG. 1 will be described.

[0041] FIGS. 4 through 18 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 5 through 10 are enlarged cross-sectional views showing portion B of FIG. 4. FIG. 17 is an enlarged cross-sectional view showing portion C of FIG. 16.

[0042] Referring to FIGS. 4 to 14, a plurality of connection pins (300) can be formed on the chip pads (230) of a semiconductor chip.

[0043] First, connection pins (300) can be formed on chip pads (230) of a wafer (W) containing a wafer-level semiconductor chip.

[0044] In exemplary embodiments, the wafer (W) may include a substrate (210) and chip pads (230) provided on a first surface (212) of the substrate (210). Although not illustrated in the drawings, the wafer (W) may include an interlayer insulating film on the active surface of the substrate (210). For example, the chip pads (230) may be provided on the outermost insulating layer of the interlayer insulating film. The substrate (210) may include a die region (DA) in which circuit patterns and cells are formed, and a scribe region (SA) surrounding the die region (DA). As described below, the substrate (210) may be cut and individualized along the scribe region (SA) separating a plurality of die regions (DA) of the wafer (W).

[0045] For example, the substrate (210) may include semiconductor materials such as silicon, germanium, silicon-germanium, etc., or group III-V compound semiconductors such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. According to some embodiments, the substrate (210) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0046] Circuit patterns (not shown) may be provided on the active surface of the substrate (210). The circuit patterns may include transistors, diodes, etc. The circuit patterns may constitute circuit elements. The chip pad (230) may be electrically connected to the circuit elements by wiring within the interlayer insulating film.

[0047] In exemplary embodiments, first connection pins (300a) can be formed on first chip pads (230a) among a plurality of chip pads (230).

[0048] First, as shown in FIG. 5, an insulating film pattern (20) can be formed on the front surface (212) of the wafer (W) (hereinafter referred to as the first surface of the substrate (210) for convenience of explanation) to expose a plurality of the chip pads, and a seed layer (22) can be formed on the chip pads.

[0049] For example, the insulating film pattern (20) may include oxides, nitrides, etc. These may be used alone or in combination. Additionally, the insulating film pattern (20) may be formed using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer stacking (ALD) process, a low-pressure chemical vapor deposition (LPCVD) process, a sputtering process, etc. Alternatively, the insulating film pattern (20) may be a polymer film formed by a spin coating method or a spray method. If a protective film pattern that exposes chip pads (230) is already formed on the first surface (212) of the substrate (210), the process of forming the insulating film pattern may be omitted.

[0050] The seed layer (22) may include an alloy layer composed of titanium / copper (Ti / Cu), titanium / palladium (Ti / Pd), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), or a combination thereof. The seed layer (22) may be formed by a sputtering process.

[0051] Next, as illustrated in FIG. 6, a photoresist pattern (24) having a first opening (26) that exposes a seed layer (22) region above a first chip pad (230a) among a plurality of chip pads can be formed on a first surface (212) of a substrate (210).

[0052] After forming a photoresist film covering a plurality of chip pads on the first surface of the substrate (210), an exposure process is performed on the photoresist film to form a photoresist pattern (24) having a first opening (26) that exposes a seed layer (22) region on the first chip pad (230a) among the plurality of chip pads. The thickness of the photoresist pattern (24) can determine the first height of the first connection pin formed in a subsequent step. The diameter of the first opening (26) can determine the diameter of the first connection pin.

[0053] As shown in FIG. 7, a metal material can be filled into the first opening (26) of the photoresist pattern (24) to form a connection pillar (30) as a first connection pin. The metal material may include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), etc.

[0054] As illustrated in FIGS. 8 and 9, a metal bonding layer (32) can be formed on a connection column (30). A second opening (28) that exposes the connection column (30) can be formed by performing an exposure process on a photoresist pattern (24). The outer surface of the connection column (30) can be completely exposed by the second opening (28). Subsequently, a plating process can be performed to form a metal bonding layer (32) on the surface of the connection column (30) exposed within the second opening (28) and on the surface of the seed layer (22). The metal bonding layer may include a metal material that has a melting point lower than that of the metal material of the connection column and is in a solid state at room temperature. For example, the metal bonding layer may include a solder material.

[0055] Alternatively, the process of forming the metal bonding layer on the connection pillars may be omitted. In this case, after filling the insertion holes formed in the package substrate with the metal material of the metal bonding layer, the connection pins are inserted into the insertion holes and bonded with the connection pins at a high temperature to mount the semiconductor chip on the package substrate.

[0056] As illustrated in FIGS. 10 and 11, after removing the photoresist pattern (24), a seed layer pattern (23) can be formed by etching a portion of the seed layer (22) exposed to the outside using a metal bonding layer (32) as a mask. Accordingly, a first connection pin (300a) having a first height (H1) can be formed on a first chip pad (230a) among a plurality of the chip pads. The first connection pin (300a) may include a connection pillar (30) formed on the first chip pad (230a) and a metal bonding layer (32) formed on the surface of the connection pillar (30). The first connection pin (300a) may have a diameter within the range of 5 μm to 95 μm.

[0057] Referring to FIG. 12, a second connection pin (300b) having a second height (H2) can be formed on a second chip pad (230b) among a plurality of chip pads (230).

[0058] A second connection pin (300b) having a second height (H2) can be formed on a second chip pad (230b) by performing processes identical or similar to those described with reference to FIGS. 5 to 10. The second height (H2) may be greater than the first height (H1).

[0059] Referring to FIG. 13, third and fourth connection pins (300c, 300d) can be formed respectively on the third and fourth chip pads (230c, 230d) among the plurality of chip pads (230).

[0060] A third connection pin (300c) having a third height (H3) can be formed on a third chip pad (230c) by performing processes identical or similar to those described with reference to FIGS. 5 to 10. The third height (H3) may be greater than the second height (H2).

[0061] Next, a fourth connection pin (300d) having a fourth height (H4) can be formed on a fourth chip pad (230d) by performing processes identical or similar to those described with reference to FIGS. 5 to 10. The fourth height (H4) may be greater than the third height (H3).

[0062] For example, the first to fourth heights may be within the range of 15 µm to 300 µm. The difference between each height, for example, the difference between the second height and the first height, may be within the range of 15 µm to 180 µm.

[0063] Accordingly, connection pins (300) having different heights can be formed on a plurality of chip pads (230). First to fourth connection pins (300a, 300b, 300d, 300d) having different heights (H1, H2, H3, H4) can be formed on the first to fourth chip pads (300a, 300b, 300c, 300d). The first to fourth connection pins (300a, 300b, 300c, 300d) may have a diameter within the range of 5㎛ to 95㎛.

[0064] In exemplary embodiments, dummy connection pillars (310, see FIG. 16) may be formed in four corner regions of the semiconductor chip (200) before or after forming the first to fourth connection pins (300a, 300b, 300c, 300d). The dummy connection pillars may have a diameter larger than the diameter of the connection pins. The dummy connection pillars may have a height smaller than the height (H1) of the first connection pin (300a). The dummy connection pillars (310) may support the semiconductor chip (200) to be stably attached to the package substrate (100) via the connection pins (300) during a subsequent mounting process.

[0065] Referring to FIG. 14, a wafer (W) can be cut along a scribe area (SA) to form an individualized semiconductor chip (200).

[0066] Before performing the above cutting process, the second surface (214) of the substrate (210) can be polished.

[0067] Referring to FIG. 15, a package substrate (100) having insertion holes (112a, 112b, 112c, 112d) of different depths can be provided.

[0068] In exemplary embodiments, the package substrate (100) may be a multilayer circuit board having upper surfaces (102) and lower surfaces (104) facing each other. For example, the package substrate (100) may be a printed circuit board (PCB) comprising wirings provided in each of the plurality of layers and vias for connecting them.

[0069] As illustrated in FIG. 15, the package substrate (100) may include a plurality of stacked insulating layers (110) and wirings (120a, 120b, 120c, 120d) respectively provided in the insulating layers.

[0070] Specifically, the first to fifth insulating layers (110a, 110b, 110c, 110d, 110e) may be stacked sequentially. The first insulating layer (110a) may be an upper cover insulating layer, the second insulating layer (110b) may be an upper insulating layer, the third insulating layer (110c) may be a core layer, the fourth insulating layer (110d) may be a lower insulating layer, and the fifth insulating layer (110e) may be a lower cover insulating layer.

[0071] For example, the insulating layer may include an insulating material such as a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulating layer may include a resin impregnated in a core material such as an organic fiber (glass fiber), for example, prepreg, FR-4, BT (Bismaleimide Triazine), etc.

[0072] The first wiring (120a) may be formed on the upper surface of the second insulating layer (110b), and the second wiring (120b) may be formed on the upper surface of the third insulating layer (110c). The third wiring (120c) may be formed on the lower surface of the third insulating layer (110c), and the fourth wiring (120d) may be formed on the lower surface of the fourth insulating layer (110d). The first to fourth wirings (120a, 120b, 120c, 120d) may be first to fourth circuit layers stacked in the thickness direction from the upper surface (102) of the package substrate (100). For example, the wiring may include a metallic material such as copper, aluminum, etc. It will be understood that the arrangement and number of the insulating layers and the conductive patterns are exemplary and are not limited thereto.

[0073] In the insulating layer (110) of the package substrate (100), a plurality of insertion holes (112a, 112b, 112c, 112d) of different depths extending from the upper surface (102) can be formed. The insertion holes can be formed by an etching process or a laser drilling process.

[0074] The first insertion hole (112a) may be formed to extend the first insulating layer (110a) in the thickness direction from the upper surface (102). The first insertion hole (112a) may expose a portion of the first wiring (120a). The first insertion hole (112a) may expose a portion of the first circuit layer by having a first depth (D1) from the upper surface (102). The portion of the first wiring (120a) exposed by the first insertion hole (112a) may serve as a first connection pad to which the first connection pin (300a) is connected by a subsequent mounting process.

[0075] The second insertion hole (112b) may be formed to extend the first and second insulating layers (110a, 110b) in the thickness direction from the upper surface (102). The second insertion hole (112b) may expose a portion of the second wiring (120b). The second insertion hole (112b) may expose a portion of the second circuit layer by having a second depth (D2) greater than the first depth (D1) from the upper surface (102). The portion of the second wiring (120b) exposed by the second insertion hole (112b) may serve as a second connection pad to which the second connection pin (300b) is connected by a subsequent mounting process.

[0076] The third insertion hole (112c) may be formed to extend the first, second, and third insulating layers (110a, 110b, 110c) in the thickness direction from the upper surface (102). The third insertion hole (112c) may expose a portion of the third wiring (120c). The third insertion hole (112c) may expose a portion of the third circuit layer by having a third depth (D3) greater than the second depth (D2) from the upper surface (102). The portion of the third wiring (120c) exposed by the third insertion hole (112c) may serve as a third connection pad to which the third connection pin (300c) is connected by a subsequent mounting process.

[0077] The fourth insertion hole (112d) may be formed to extend the first, second, third, and fifth insulating layers (110a, 110b, 110c, 110d) in the thickness direction from the upper surface (102). The fourth insertion hole (112d) may expose a portion of the fourth wiring (120d). The fourth insertion hole (112d) may expose a portion of the fourth circuit layer by having a fourth depth (D4) greater than the third depth (D3) from the upper surface (102). The portion of the fourth wiring (120d) exposed by the fourth insertion hole (112d) may serve as a fourth connection pad to which the fourth connection pin (300d) is connected by a subsequent mounting process.

[0078] Referring to FIGS. 16 and 17, a semiconductor chip (200) can be mounted on a package substrate (100).

[0079] In exemplary embodiments, the semiconductor chip (200) may be mounted on the package substrate (100) by a flip chip bonding method. In this case, the semiconductor chip (200) may be mounted on the package substrate (100) such that the active surface, i.e., the first surface (212), on which the chip pads (230) are formed, faces the package substrate (100). An underfill member (350) may be provided between the first surface (212) of the semiconductor chip (200) and the upper surface (102) of the package substrate (100).

[0080] When a semiconductor chip (200) is placed on a package substrate (100), the connection pins (300) on the chip pads (230) are inserted into the insertion holes formed in the package substrate (100), and the connection pins (300) can be joined to parts of the wiring exposed by the insertion holes by a heat pressing process.

[0081] The first connection pin (300a) can be inserted into the first insertion hole (112a) and electrically connected to a part of the first wiring (120a) exposed by the first insertion hole (112a), i.e., the first connection pad. The second connection pin (300b) can be inserted into the second insertion hole (112b) and electrically connected to a part of the second wiring (120b) exposed by the second insertion hole (112b), i.e., the second connection pad. The third connection pin (300c) can be inserted into the third insertion hole (112c) and electrically connected to a part of the third wiring (120c) exposed by the third insertion hole (112c), i.e., the third connection pad. The fourth connection pin (300d) can be inserted into the fourth insertion hole (112d) and electrically connected to a part of the fourth wiring (120d) exposed by the fourth insertion hole (112d), i.e., the fourth connection pad.

[0082] As illustrated in FIG. 17, the second connection pin (300b) may include a connection post (30) and a metal bonding layer (32) formed on the surface of the connection post (30). The second connection pin (300b) may be connected to a portion of the second wiring (120b) exposed by the second insertion hole (112b) by a heat pressing process. At this time, the metal bonding layer (32) may be melted at a high temperature to at least partially fill the space between the surface of the connection post (30) and the inner surface of the second insertion hole (112b).

[0083] Alternatively, if the metal bonding layer (32) is not formed, the metal material of the metal bonding layer can be filled into the insertion holes formed in the package substrate (100), and then the connection pins (300) can be inserted into the insertion holes and then the connection pins (300) can be bonded to parts of the wiring at a high temperature. Or, for example, the connection pins (300) can be directly bonded to parts of the wiring by copper-copper bonding (Cu-Cu Bonding).

[0084] Referring to FIG. 18, a molding member (400) covering a semiconductor chip (200) can be formed on a package substrate (100). For example, the molding member (400) may include an insulating material such as an epoxy molding compound.

[0085] Next, the semiconductor package (10) of FIG. 1 can be completed by forming external connection members, such as solder balls, on the external connection pads on the lower surface (104) of the package substrate (100), that is, on parts of the fourth wiring (120d) exposed by the fifth insulating layer (110e).

[0086] FIG. 19 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 20 is an enlarged cross-sectional view showing portion D of FIG. 19. The semiconductor package is substantially identical or similar to the semiconductor package described with reference to FIG. 1 through 3, except for the configuration of additional support structures and second semiconductor chips. Accordingly, identical or similar components are indicated by identical or similar reference numerals, and a repeated description of identical components is omitted.

[0087] Referring to FIGS. 19 and 20, the semiconductor package (11) may include a package substrate (100), a first semiconductor chip (200), a plurality of connection pins (300), a support structure (600), a plurality of second semiconductor chips (700), and a sealing member (800). Additionally, the semiconductor package (11) may further include conductive connection members (730) that electrically connect the second semiconductor chips (700) to the package substrate (100). Additionally, the semiconductor package (11) may further include external connection members (900).

[0088] In exemplary embodiments, the package substrate (100) may be a multilayer circuit board having an upper surface (102) and a lower surface (104) facing each other. For example, the package substrate (100) may be a printed circuit board (PCB) comprising wirings provided in each of the plurality of layers and vias for connecting them.

[0089] The package substrate (100) may include first to fourth wirings (120a, 120b, 120c, 120d) stacked sequentially.

[0090] The package substrate (100) may have a plurality of insertion holes (112a, 112b, 112c, 112d) of different depths extending in the thickness direction from the upper surface (102). For example, the insertion holes (112a, 112b, 112c, 112d) may have a diameter within the range of 15 μm to 150 μm.

[0091] The first insertion hole (112a) can extend the first insulating layer (110a) in the thickness direction from the upper surface (102) to expose a portion of the first wiring (120a). The first insertion hole (112a) can expose a portion of the first circuit layer by having a first depth (D1) from the upper surface (102). The portion of the first wiring (120a) exposed by the first insertion hole (112a) can serve as a first connection pad to which the first connection pin (300a) is connected.

[0092] The second insertion hole (112b) can extend the first and second insulating layers (110a, 110b) in the thickness direction from the upper surface (102) to expose a portion of the second wiring (120b). The second insertion hole (112b) can expose a portion of the second circuit layer by having a second depth (D2) greater than the first depth (D1) from the upper surface (102). The portion of the second wiring (120b) exposed by the second insertion hole (112b) can serve as a second connection pad to which the second connection pin (300b) is connected.

[0093] The third insertion hole (112c) can extend the first, second, and third insulating layers (110a, 110b, 110c) in the thickness direction from the upper surface (102) to expose a portion of the third wiring (120c). The third insertion hole (112c) can expose a portion of the third circuit layer by having a third depth (D3) greater than the second depth (D2) from the upper surface (102). The portion of the third wiring (120c) exposed by the third insertion hole (112c) can serve as a third connection pad to which the third connection pin (300c) is connected.

[0094] The fourth insertion hole (112d) can extend the first, second, third, and fourth insulating layers (110a, 110b, 110c, 110d) in the thickness direction from the upper surface (102) to expose a portion of the fourth wiring (120d). The fourth insertion hole (112d) can expose a portion of the fourth circuit layer by having a fourth depth (D4) greater than the third depth (D3) from the upper surface (102). The portion of the fourth wiring (120d) exposed by the fourth insertion hole (112d) can serve as a fourth connection pad to which the fourth connection pin (300d) is connected.

[0095] A semiconductor chip (200) may be placed on a package substrate (100). The semiconductor chip (200) may be mounted on the package substrate (100) through connection pins (300). The first semiconductor chip (200) may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory chips.

[0096] A semiconductor chip (200) may include a plurality of chip pads (230) provided on a first surface (212). Connection pins (300) having different heights may be provided on the plurality of chip pads (230).

[0097] A first connection pin (300a) having a first height (H1) may be provided on the first chip pad (230a). A second connection pin (300b) having a second height (H2) may be provided on the second chip pad (230b). The second height (H2) may be greater than the first height (H1). A third connection pin (300c) having a third height (H3) may be provided on the third chip pad (230c). The third height (H3) may be greater than the second height (H2). A fourth connection pin (300d) having a fourth height (H4) may be provided on the fourth chip pad (230d). The fourth height (H4) may be greater than the third height (H3).

[0098] In exemplary embodiments, the semiconductor chip (200) may be mounted on the package substrate (100) by a flip chip bonding method. In this case, the semiconductor chip (200) may be mounted on the package substrate (100) such that the active surface on which the chip pads (230) are formed, i.e., the first surface (212), faces the package substrate (100).

[0099] When a semiconductor chip (200) is mounted on a package substrate (100), the connection pins (300) on the chip pads (230) are inserted into the insertion holes formed in the package substrate (100), and the connection pins (300) can be joined to parts of the wiring exposed by the insertion holes by a heat pressing process. The connection pins (300) can partially penetrate the insulating layers (110) of the package substrate (100) and serve as vias to electrically connect the wiring.

[0100] The first connection pin (300a) can be inserted into the first insertion hole (112a) and electrically connected to a part of the first wiring (120a) exposed by the first insertion hole (112a), i.e., the first connection pad. The second connection pin (300b) can be inserted into the second insertion hole (112b) and electrically connected to a part of the second wiring (120b) exposed by the second insertion hole (112b), i.e., the second connection pad. The third connection pin (300c) can be inserted into the third insertion hole (112c) and electrically connected to a part of the third wiring (120c) exposed by the third insertion hole (112c), i.e., the third connection pad. The fourth connection pin (300d) can be inserted into the fourth insertion hole (112d) and electrically connected to a part of the fourth wiring (120d) exposed by the fourth insertion hole (112d), i.e., the fourth connection pad.

[0101] As illustrated in FIG. 20, the second connection pin (300b) may include a connection post (30) and a metal bonding layer (32) formed on the surface of the connection post (30). The second connection pin (300b) may be connected to a portion of the second wiring (120b) exposed by the second insertion hole (112b) by a heat pressing process. At this time, the metal bonding layer (32) may be melted at a high temperature to at least partially fill the space between the surface of the connection post (30) and the inner surface of the second insertion hole (112b).

[0102] In exemplary embodiments, the support structure (600) may be spaced apart from the first semiconductor chip (200) on the package substrate (100). The support structure (600) may be attached to the upper surface (102) of the package substrate (100) using an adhesive member (610). The support structure (600) may be positioned between the package substrate (100) and other electronic components to support the other electronic components.

[0103] The support structure (600) may include a support spacer and an adhesive film (610) attached to the lower surface of the support spacer. For example, the adhesive film (610) may include a die adhesive film (DAF). The support spacer may be attached to the upper surface (102) of the package substrate (100) using the adhesive film (610) by a die attach process.

[0104] Two support structures (600) may be placed on both sides of the first semiconductor chip (200). The height of the support structures from the package substrate (100) may be substantially the same as the height of the first semiconductor chip (200).

[0105] In exemplary embodiments, a plurality of second semiconductor chips (700) may be stacked on a first semiconductor chip (200) and a support structure (600). The second semiconductor chips (700a, 700b) may be attached to the support structure (600) using adhesive members (710a, 710b). For example, the adhesive members may include an adhesive film such as a direct adhesive film (DAF). The planar area of ​​the second semiconductor chips may be larger than the planar area of ​​the first semiconductor chip or the support structure. Accordingly, the second semiconductor chips (700a, 700b) may be supported and mounted on a package substrate (100) by a support structure (300).

[0106] The second semiconductor chip (700) can be electrically connected to the package substrate (100) by conductive connecting members (730). Specifically, the conductive connecting member (730) can electrically connect the chip pad of the second semiconductor chip (700) to the substrate pad of the package substrate (100), that is, to a portion of the first wiring (120d) exposed by the first insulating layer (110a). For example, the conductive connecting member (730) may include a bonding wire. Thus, the second semiconductor chips (700) can be stacked on the support structure (600) by the adhesive member and electrically connected to the package substrate (100) by a plurality of conductive connecting members (730).

[0107] The second semiconductor chips (700) may include a memory chip comprising a memory circuit. For example, the second semiconductor chips (700) may include a non-volatile memory device such as a NAND flash memory. It will be understood that the number, size, arrangement, etc. of the second semiconductor chips are provided as examples and that the present invention is not limited thereto.

[0108] In exemplary embodiments, a sealing member (800) is formed on a package substrate (100) to protect a first semiconductor chip (200), a support structure (600), and second semiconductor chips (700) from the outside. The sealing member may include an epoxy mold compound (EMC).

[0109] On the lower surface (104) of the package substrate (100), external connection pads for providing electrical signals, namely, parts of the fourth wiring (120d) exposed by the fifth insulating layer (110e), may be provided. On the external connection pads of the package substrate (100), an external connection member (900) may be disposed for electrical connection with an external device. For example, the external connection member (900) may be a solder ball. The semiconductor package (11) may be mounted on a module substrate (not shown) via the solder balls to form a memory module.

[0110] As described above, the semiconductor package (11) may include a package substrate (100), a first semiconductor chip (200) mounted on the package substrate (100) and a support structure (600), a plurality of second semiconductor chips (700) supported on the first semiconductor chip (200) and the support structure (600), and a sealing member (800) covering the first semiconductor chip (200), the support structure (600), and the second semiconductor chips (700) on the package substrate (100).

[0111] The first semiconductor chip (200) can be mounted on the package substrate (100) via connection pins (300). When the semiconductor chip (200) is mounted on the package substrate (100), the connection pins (300) on the chip pads (230) are inserted into the insertion holes formed in the package substrate (100), and the connection pins (300) can be joined to parts of the wiring exposed by the insertion holes through a thermal compression process. The connection pins (300) can partially penetrate the insulating layers (110) of the package substrate (100) and serve as vias to electrically connect the wiring.

[0112] Therefore, the overall package thickness can be reduced and structural stability improved. Accordingly, it is possible to prevent the sealing member from penetrating into the space between the first semiconductor chip (200) and the second semiconductor chip (700) due to the tilting of the first semiconductor chip (200) mounted by the conventional flip-chip method.

[0113] Below, a method for manufacturing the semiconductor package of FIG. 19 will be described.

[0114] FIGS. 21 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

[0115] Referring to FIG. 21, a plurality of connection pins (300) can be formed on the chip pads (230) of the first semiconductor chip (200).

[0116] Connection pins (300) having different heights can be formed on chip pads (230) by performing processes identical or similar to those described with reference to FIGS. 4 to 14.

[0117] A first connection pin (300a) having a first height (H1) may be provided on the first chip pad (230a). A second connection pin (300b) having a second height (H2) may be provided on the second chip pad (230b). The second height (H2) may be greater than the first height (H1). A third connection pin (300c) having a third height (H3) may be provided on the third chip pad (230c). The third height (H3) may be greater than the second height (H2). A fourth connection pin (300d) having a fourth height (H4) may be provided on the fourth chip pad (230d). The fourth height (H4) may be greater than the third height (H3). For example, the first to fourth heights may be within the range of 15 μm to 300 μm. The difference between each height, for example, the difference between the second height and the first height, may be within the range of 15 µm to 180 µm. The first to third connecting pins (300) may have a diameter within the range of 5 µm to 95 µm.

[0118] Referring to FIG. 22, insertion holes (112a, 112b, 112c, 112d) of different depths can be formed in the package substrate (100).

[0119] For example, the above insertion holes can be formed by an etching process or a laser drilling process.

[0120] The first insertion hole (112a) may be formed to extend the first insulating layer (110a) in the thickness direction from the upper surface (102). The first insertion hole (112a) may expose a portion of the first wiring (120a). The first insertion hole (112a) may expose a portion of the first circuit layer by having a first depth (D1) from the upper surface (102). The portion of the first wiring (120a) exposed by the first insertion hole (112a) may serve as a first connection pad to which the first connection pin (300a) is connected by a subsequent mounting process.

[0121] The second insertion hole (112b) may be formed to extend the first and second insulating layers (110a, 110b) in the thickness direction from the upper surface (102). The second insertion hole (112b) may expose a portion of the second wiring (120b). The second insertion hole (112b) may expose a portion of the second circuit layer by having a second depth (D2) greater than the first depth (D1) from the upper surface (102). The portion of the second wiring (120b) exposed by the second insertion hole (112b) may serve as a second connection pad to which the second connection pin (300b) is connected by a subsequent mounting process.

[0122] The third insertion hole (112c) may be formed to extend the first, second, and third insulating layers (110a, 110b, 110c) in the thickness direction from the upper surface (102). The third insertion hole (112c) may expose a portion of the third wiring (120c). The third insertion hole (112c) may expose a portion of the third circuit layer by having a third depth (D3) greater than the second depth (D2) from the upper surface (102). The portion of the third wiring (120c) exposed by the third insertion hole (112c) may serve as a third connection pad to which the third connection pin (300c) is connected by a subsequent mounting process.

[0123] The fourth insertion hole (112d) may be formed to extend the first, second, third, and fifth insulating layers (110a, 110b, 110c, 110d) in the thickness direction from the upper surface (102). The fourth insertion hole (112d) may expose a portion of the fourth wiring (120d). The fourth insertion hole (112d) may expose a portion of the fourth circuit layer by having a fourth depth (D4) greater than the third depth (D3) from the upper surface (102). The portion of the fourth wiring (120d) exposed by the fourth insertion hole (112d) may serve as a fourth connection pad to which the fourth connection pin (300d) is connected by a subsequent mounting process.

[0124] Referring to FIG. 23, a first semiconductor chip (200) can be mounted on a package substrate (100).

[0125] In exemplary embodiments, the first semiconductor chip (200) may be mounted on the package substrate (100) by a flip chip bonding method. In this case, the first semiconductor chip (200) may be mounted on the package substrate (100) such that the active surface on which the chip pads (230) are formed, i.e., the first surface (212), faces the package substrate (100).

[0126] When the first semiconductor chip (200) is placed on the package substrate (100), the connection pins (300) on the chip pads (230) are inserted into the insertion holes formed in the package substrate (100), and the connection pins (300) can be joined to parts of the wiring exposed by the insertion holes by a heat pressing process.

[0127] The first connection pin (300a) can be inserted into the first insertion hole (112a) and electrically connected to a part of the first wiring (120a) exposed by the first insertion hole (112a), i.e., the first connection pad. The second connection pin (300b) can be inserted into the second insertion hole (112b) and electrically connected to a part of the second wiring (120b) exposed by the second insertion hole (112b), i.e., the second connection pad. The third connection pin (300c) can be inserted into the third insertion hole (112c) and electrically connected to a part of the third wiring (120c) exposed by the third insertion hole (112c), i.e., the third connection pad. The fourth connection pin (300d) can be inserted into the fourth insertion hole (112d) and electrically connected to a part of the fourth wiring (120d) exposed by the fourth insertion hole (112d), i.e., the fourth connection pad.

[0128] Referring to FIG. 24, at least one support structure (600) can be laminated on a package substrate (100).

[0129] In exemplary embodiments, a support structure (60) can be attached to the upper surface (102) of a package substrate (100) using an adhesive film (610) so as to be spaced apart from the first semiconductor chip (200). Two support structures (600) may be placed on both sides of the first semiconductor chip (200). For example, the adhesive film (610) may include a die adhesive film (DAF). The support structure (600) may be attached to the upper surface (102) of the package substrate (100) using the adhesive film (610) by a die attach process.

[0130] The height of the support structure from the package substrate (100) may be substantially the same as the height of the first semiconductor chip (200).

[0131] Referring to FIG. 25, a plurality of second semiconductor chips (700) can be stacked on a first semiconductor chip (200) and a support structure (300).

[0132] Second semiconductor chips (700a, 700b) can be attached to a support structure (600) using adhesive members (710a, 710b). The planar area of ​​the second semiconductor chip may be larger than the planar area of ​​the first semiconductor chip or the support structure. Accordingly, the second semiconductor chips (700a, 700b) can be supported and mounted by the support structure (600) on a package substrate (100).

[0133] The second semiconductor chips may be offset aligned sequentially or in a zigzag direction. For example, the second semiconductor chips (700a, 700b) may be stacked in a cascade structure. The second semiconductor chips (700a, 700b) may be offset aligned sequentially in the first side direction (right direction) of the package substrate (100). The second semiconductor chips (700a, 700b) may be attached to the first semiconductor chip (200) and the support structure (300) using an adhesive film (710) such as DAF.

[0134] Next, a wire bonding process can be performed to connect the chip pads of the second semiconductor chips (700a, 700b) to the substrate pads on the upper surface (102) of the package substrate (100), i.e., to parts of the first wiring (120a) exposed by the first insulating layer (110a). The chip pads of the second semiconductor chips (700a, 700b) can be connected to the substrate pads by conductive connecting members (730), i.e., bonding wires.

[0135] Referring to FIG. 26, a sealing member (800) covering a first semiconductor chip (200), a support structure (300), and second semiconductor chips (700) can be formed on the upper surface (102) of a package substrate (100). The sealing member may include an epoxy mold compound (EMC).

[0136] Next, the semiconductor package (11) of FIG. 19 can be completed by forming external connection members (900), such as solder balls, on the external connection pads on the lower surface (104) of the package substrate (100), that is, on parts of the fourth wiring (120d) exposed by the fifth insulating layer (110e).

[0137] The aforementioned semiconductor package may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include, for example, logic devices such as a central processing unit (CPU, MPU), an application processor (AP), volatile memory devices such as an SRAM device, a DRAM device, and non-volatile memory devices such as a flash memory device, a PRAM device, an MRAM device, or an RRAM device.

[0138] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0139] 10, 11: Semiconductor package 30: Connection post 32: Metal joint layer 100: Package substrate 110a, 110b, 110c, 110d, 110e: Insulating layer 112a, 112b, 112c, 112d: Insertion holes 120a, 120b, 120c, 120d: Wiring 200: Semiconductor chip, the first semiconductor chip 230, 230a, 230b, 230c, 230d: Chip pad 300, 300a, 300b, 300c, 300d: Connection pins 310: Dummy connection post 400, 800: Sealing member 500, 900: External connection members 600: Supporting structure 700: Second semiconductor chip 710a, 710b: Adhesive member 730: Conductive connection absence

Claims

Claim 1 A semiconductor package comprising: a package substrate having wirings provided in each of a plurality of layers, and insertion holes that extend in the thickness direction from the upper surface and expose portions of the wirings of different layers; a semiconductor chip disposed on the package substrate such that a first surface having chip pads formed thereon faces the upper surface of the package substrate; a plurality of connection pins provided on the chip pads and extending into the corresponding insertion holes to electrically connect with the exposed portions of the wirings; and a sealing member provided on the package substrate to cover the semiconductor chip, wherein each of the plurality of connection pins includes a connection pillar extending from the first surface on the chip pad of the semiconductor chip and a metal bonding layer covering the entire outer surface of the connection pillar, wherein the insertion holes have different depths from the upper surface of the package substrate, and the connection pillars of the connection pins have different heights from the first surface of the semiconductor chip to correspond to the different depths of the corresponding insertion holes. Claim 2 A semiconductor package according to claim 1, wherein the wiring comprises first to third wirings sequentially stacked from the upper surface of the package substrate, and the insertion holes comprise a first insertion hole exposing a portion of the first wiring, a second insertion hole exposing a portion of the second wiring, and a third insertion hole exposing a portion of the third wiring. Claim 3 A semiconductor package according to claim 2, wherein the connection pins include: a first connection pin inserted into the first insertion hole and electrically connected to an exposed portion of the first wiring; a second connection pin inserted into the second insertion hole and electrically connected to an exposed portion of the second wiring; and a third connection pin inserted into the third insertion hole and electrically connected to an exposed portion of the third wiring. Claim 4 A semiconductor package according to claim 3, wherein the first connection pin has a first height from the first surface of the semiconductor chip, the second connection pin has a second height greater than the first height from the first surface of the semiconductor chip, and the third connection pin has a third height greater than the second height from the first surface of the semiconductor chip. Claim 5 delete Claim 6 A semiconductor package according to claim 1, wherein the metal bonding layer is configured to at least partially fill the space between the surface of the connection column and the inner surface of the insertion hole. Claim 7 A semiconductor package according to claim 1, wherein the metal junction layer comprises a metal material having a lower melting point than the metal material of the connection pillar and being in a solid state at room temperature. Claim 8 A semiconductor package according to claim 1, wherein the insertion hole has a diameter within the range of 15㎛ to 150㎛ and the connection pin has a diameter within the range of 5㎛ to 95㎛. Claim 9 In claim 1, the connection pin is a semiconductor package having a height within the range of 15㎛ to 300㎛ from the first surface of the semiconductor chip. Claim 10 A semiconductor package according to claim 1, further comprising a plurality of dummy connection pillars each provided in corner regions on the first surface of the semiconductor chip and in contact with the upper surface of the package substrate.

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