Electronic circuit for detecting an ultra-wideband pulse

Abstract

An electronic circuit (1) for detecting ultra-wideband pulses, wherein the electronic circuit (1) comprises an analog input terminal (11, 11A, 11B) configured for connection to an ultra-wideband antenna (2, 2A, 2B), a low-noise amplifier (12, 12A, 12B) connected to the analog input terminal (11, 11A, 11B) and configured to amplify one or more ultra-wideband pulses received through the ultra-wideband antenna (2, 2A, 2B), and a comparator (13, 13A, 13B) connected to the low-noise amplifier (12, 12A, 12B) and configured to generate a wake-up trigger signal for ultra-wideband pulses exceeding a predefined pulse amplitude threshold.

Description

Technology Field

[0001] The present disclosure relates to an electronic circuit for detecting ultra-wideband pulses. Background Technology

[0002] Ultra-wideband (UWB) readers communicate using ultra-wideband transmitters. UWB transmitters have advantages over other wireless transmission technologies that allow the exact distance between two UWB devices, for example, a mobile communication device and an authentication device, to be determined. The distance can be calculated, for example, by evaluating the time of flight (ToF) using the principle of two-way ranging (TWR).

[0003] In addition, using multiple antennas connected to a single UWB reader or using multiple UWB anchors allows determining the distance between the UWB reader and the UWB transmitter, as well as the relative position, relative angle, and / or relative orientation, using principles such as the time difference of arrival (TDoA) or the angle of arrival (AoA).

[0004] Furthermore, UWB transmitters enable low-power applications. However, for UWB readers that rely on battery power without a permanently wired power supply, reducing power consumption is always a design goal. The problem to be solved

[0005] The object of the present invention is to provide an electronic circuit for detecting ultra-wideband pulses that overcomes one or more of the disadvantages of the prior art.

[0006] In particular, the object of the present invention is to provide an electronic circuit for detecting one or more ultra-wideband pulse(s) in a more energy-efficient manner, with a combination of high resistance to interference and spurious signals compared to known prior art electronic circuits. Additionally, the object of the embodiments disclosed herein is to provide an ultra-wideband reader having an electronic circuit for energy-efficient wake-up based on the detection of one or more ultra-wideband pulses. means of solving the problem

[0007] According to embodiments of the present disclosure, the above-mentioned objectives are achieved by an electronic circuit for detecting ultra-wideband pulses. The electronic circuit includes an analog input terminal configured for connection to an ultra-wideband antenna. The electronic circuit includes a low-noise amplifier connected to the analog input terminal and configured to amplify one or more ultra-wideband pulses received through the ultra-wideband antenna, and a comparator connected to the low-noise amplifier and configured to generate a wake-up trigger signal for ultra-wideband pulses that exceed a predefined pulse amplitude threshold.

[0008] In an embodiment, the electronic circuit further comprises an integrator arranged between a low-noise amplifier and a comparator and configured to integrate one or more ultra-wideband pulses over a predefined integration time period, and the comparator is further configured to generate a wake-up trigger signal for integrated ultra-wideband pulses that exceed a predefined integration threshold.

[0009] In an embodiment, the electronic circuit further includes a correlator arranged upstream from a comparator, configured to multiply one or more received ultra-wideband pulses by a template ultra-wideband waveform and integrate one or more multiplied ultra-wideband pulses over a predefined correlation integration time period.

[0010] In an embodiment, the correlation integral time period is a continuous correlation integral time period.

[0011] In an embodiment, the electronic circuit further includes a quadrature demodulator arranged downstream from a low-noise amplifier, configured to determine the in-phase and quadrature components of one or more ultra-wideband pulses.

[0012] In an embodiment, the demodulated in-phase components of one or more ultra-wideband pulses are added to the demodulated orthogonal components of one or more ultra-wideband pulses.

[0013] In an embodiment, one or more demodulated in-phase components of an ultra-wideband pulse and one or more demodulated orthogonal components of an ultra-wideband pulse are each transmitted to a comparator, either directly or through an integrator and / or correlator, and the comparators are connected to downstream logic gates configured to generate a wake-up trigger signal depending on the output signal of the comparators.

[0014] In an embodiment, the analog input terminal is connected to a directional ultra-wideband antenna. For example, the directional ultra-wideband antenna is configured to receive ultra-wideband transmissions only within a specific horizontal and / or vertical angle range. In particular, the antenna is configured so that the main lobe of sensitivity is oriented in a specific direction, and the direction depends on the application. For example, in an access control application in which electronic circuitry is included in an access control terminal arranged at or near an access control gate, the antenna is configured so that ultra-wideband transmissions are received only from a specific direction and / or a predefined pulse amplitude threshold is configured so that ultra-wideband transmissions from the main lobe generate a wake-up trigger signal.

[0015] In an embodiment, the electronic circuit includes a timing circuit connected to a low-noise amplifier configured to receive one or more ultra-wideband pulses in response to a beacon pulse transmitted by the electronic circuit, determine a distance using the time difference between the reception of a specific ultra-wideband pulse and the transmission of the beacon pulse, and, in particular, forward a specific ultra-wideband pulse to generate a wake-up trigger signal only when the distance is smaller than a predefined proximity distance.

[0016] In an embodiment, the electronic circuit is configured to receive one or more ultra-wideband pulses in response to a beacon pulse transmitted by the electronic circuit, a transmitting electronic circuit connected in parallel to the electronic circuit, or a relative ranging device.

[0017] In an embodiment, the electronic circuit comprises two analog input terminals configured to be connected to each of two ultra-wideband antennas, and the timing circuit is configured to determine, for a specific ultra-wideband pulse received from the two analog input terminals, the time difference in receiving the specific ultra-wideband pulse from the two analog input terminals and / or the phase difference of the specific ultra-wideband pulse received from the two analog input terminals. The timing circuit is configured to forward the specific ultra-wideband pulse, in particular to generate a wake-up trigger signal, only when the time difference corresponds to a predetermined time difference range and / or the phase difference corresponds to a predetermined phase difference range.

[0018] In an embodiment, the electronic circuit includes a plurality of analog input terminals configured to be connected to a plurality of ultra-wideband antennas, and the electronic circuit further includes a direction component configured to determine the transmission direction of one or more ultra-wideband pulses depending on the reception time and / or phase of one or more ultra-wideband pulses, and the direction component is further configured to forward one or more ultra-wideband pulses only when the determined transmission direction matches a predetermined transmission direction.

[0019] The present disclosure also relates to an ultra-wideband reader comprising an electronic circuit as described herein, wherein the ultra-wideband reader comprises a digital processing unit connected to the electronic circuit, and the digital processing unit is configured to wake up upon receiving a wake-up trigger signal.

[0020] In an embodiment, the ultra-wideband reader further includes a battery. The digital processing unit is initially powered off, and a wake-up trigger signal is received by a switch configured to wake up the digital processing unit by connecting the battery to the digital processing unit.

[0021] In an embodiment, the digital processing unit is initially in a low-power state, and a wake-up trigger signal is configured to switch the digital processing unit to a high-power state, and the digital processing unit has relatively higher power consumption in the high-power state than in the low-power state.

[0022] In an embodiment, the ultra-wideband reader further comprises an analog-to-digital converter arranged downstream from a low-noise amplifier, the analog-to-digital converter is connected to a digital processing unit and configured to generate a digital signal from one or more ultra-wideband pulses, and the digital processing unit is configured to use the digital signal to authenticate and / or identify an ultra-wideband device that has transmitted one or more ultra-wideband pulses. Brief explanation of the drawing

[0023] The disclosures described in this specification will be more fully understood from the accompanying drawings and the detailed description given in the following specification, which should not be construed as limiting the disclosures described in the appended claims. Figure 1 shows a block diagram schematically illustrating an electronic circuit for detecting ultra-wideband pulses. Figure 2 shows a block diagram schematically illustrating an electronic circuit including an integrator. Figure 3 shows a block diagram schematically illustrating an electronic circuit including a correlator. FIGS. 4 to 6 show block diagrams schematically illustrating an electronic circuit further including an orthogonal demodulator. Figures 7 and 8 show block diagrams schematically illustrating electronic circuits that further include timing circuits. FIGS. 9 to 11 are block diagrams illustrating ultra-wideband readers including a digital processing unit and electronic circuits for detecting ultra-wideband pulses. Figure 12 shows a chart illustrating the super-wideband pulse amplitude and the corresponding response of the electronic circuit as a function of time. Figure 13 shows a timing diagram illustrating single-sided two-way ranging between an electronic circuit and a mobile ultra-wideband device. Figure 14 shows a timing diagram illustrating double-sided bidirectional ranging between an electronic circuit and a mobile ultra-wideband device. FIG. 15 shows a circuit diagram schematically illustrating a comparator according to an embodiment. Figure 16 shows a chart illustrating the corresponding response of an electronic circuit including a super-wideband pulse amplitude and a comparator as a function of time. FIG. 17 shows a circuit diagram schematically illustrating a comparator having hysteresis according to an embodiment. Figure 18 shows a chart illustrating the corresponding response of an electronic circuit including a comparator having super-wideband pulse amplitude and hysteresis as a function of time. FIG. 19 shows a circuit diagram schematically illustrating a comparator having rectified input and hysteresis according to an embodiment. FIG. 20 shows a chart illustrating the corresponding response of an electronic circuit including a comparator having a super-wideband pulse amplitude, a rectified input, and hysteresis as a function of time. FIG. 21 shows a circuit diagram schematically illustrating a comparator having positive and negative thresholds and hysteresis according to an embodiment. Figure 22 shows a chart illustrating the corresponding response of an electronic circuit with super-wideband pulse amplitude, positive and negative thresholds, and hysteresis as a function of time. FIG. 23 shows a circuit diagram schematically illustrating a comparator having positive and negative thresholds and hysteresis according to an embodiment. FIG. 24 shows a chart illustrating the corresponding response of an electronic circuit having positive and negative thresholds and hysteresis, for example, when occurring in FIG. 5, with respect to time, demodulation and correlated ultra-wideband pulse amplitudes and especially in addition outputs. Specific details for implementing the invention

[0024] Now, reference to certain embodiments will be made in detail, examples of which are illustrated in the accompanying drawings, in which only some, not all, of the features are shown. In fact, the embodiments disclosed herein may be implemented in many different forms and should not be interpreted as being limited to the embodiments presented herein; rather, these embodiments are provided to satisfy the applicable legal requirements of this disclosure. Where possible, similar reference numbers will be used to refer to similar components or parts.

[0025] FIG. 1 illustrates an electronic circuit (1). An analog input terminal (11) of the electronic circuit (1) is connected to an ultra-wideband antenna (2). Preferably, the ultra-wideband antenna (2) is directly connected to the analog input terminal (11) by a wire or circuit board trace without any intermediate active or passive electronic components. The electronic circuit (1) includes various electronic components connected to one another using wires or conductive traces. Preferably, the electronic components of the electronic circuit (1) are arranged on a single printed circuit board (PCB). Each electronic component has one or more input signals and one or more output signals. A low-noise amplifier (LNA) (12) is connected to the analog input terminal (11) to amplify one or more ultra-wideband pulses received by the ultra-wideband antenna (2). The LNA (12) is an electronic amplifier configured to amplify very low power signals without significantly degrading the signal-to-noise ratio. LNAs (12) are suitable for use in radio antenna receivers, particularly because, for example, their high gain of 10-20 dB and low noise floor enable the reception of low-power radio signals, especially low-power ultra-wideband pulses. The LNA (12) is connected to a comparator (13). The comparator (13) is configured to compare the pulse amplitude of the received (and amplified) ultra-wideband pulse with a defined threshold pulse amplitude. The comparator (13) is configured such that if the pulse amplitude of the ultra-wideband pulse exceeds the defined threshold pulse amplitude, a wake-up trigger signal is generated by the comparator (13) and output from the wake-up trigger signal output (14) of the electronic circuit (1). The comparator (13) includes, for example, a high-gain differential amplifier. Specific characteristics of the wake-up trigger signal depend on the embodiment.Examples of wake-up trigger signals include analog signals and digital trigger signals, such as analog voltages within a specific voltage range or binary digital trigger signals.

[0026] As described below with reference to FIGS. 1 to 11, FIGS. 15, FIGS. 17, FIGS. 19, FIGS. 21 and FIGS. 23, the wake-up trigger signal output (14) of the electronic circuit (1) corresponds to the output of the comparator (13) in at least some embodiments, particularly because the output of the comparator (13) is directly connected to the wake-up trigger signal output (14) of the electronic circuit (1).

[0027] In other embodiments, intermediate components, e.g., logic gates, are configured to take outputs from two comparators (13A and 13B) as inputs as described below with reference to FIG. 6, and to generate a wake-up trigger signal output (14) using outputs from one or more of the comparators (13).

[0028] In additional embodiments, as described with reference to FIG. 11, intermediate components such as an ADC (7) convert ultra-wideband pulse(s) into digital data output (14'), which itself may be used as a wake-up trigger signal.

[0029] Depending on the embodiment, the wake-up trigger signal is configured to wake up one or more additional electronic components of a device connected to the electronic circuit (1) and / or to wake up one or more additional electronic components of a device in which the electronic circuit (1) is integrated, in particular the ultra-wideband reader (3) as described with reference to FIGS. 9 through 11. “Wake-up” is understood to mean moving from an electronic component in a “sleep” state, which consumes a small amount of power, to an “awake” state, which consumes a large amount of power (compared to the “sleep” state). Depending on the specifics of the electronic component, the sleep state has reduced functionality compared to the awake state.

[0030] Accordingly, the electronic circuit (1) is configured to detect whether one or more ultra-wideband pulses are received at the antenna (2), wherein at least one of the ultra-wideband pulses exceeds a specific signal strength as determined by a predefined pulse amplitude threshold of the comparator (13). By detecting whether one or more ultra-wideband pulses are received at the antenna (2), the electronic circuit (1) can detect an ultra-wideband transmitter.

[0031] In an embodiment, the electronic circuit (1) is an analog electronic circuit (1). Specifically, the analog electronic circuit (1) consists only of analog components arranged between a signal path, i.e., an input terminal (11) and a wake-up trigger signal output (14). In other words, one or more ultra-wideband pulses are not digitized in the electronic circuit (1) for the purpose of generating a wake-up trigger signal (i.e., the electronic circuit (1) does not include an analog-to-digital converter for generating a wake-up trigger signal).

[0032] In some embodiments, one or more ultra-wideband pulses are not processed using digital components or techniques in the electronic circuit (1).

[0033] In particular, in the signal chain, the advantage of omitting digital components is that it reduces the cost and complexity of the electronic circuit (1). It also increases the power efficiency of the electronic circuit (1).

[0034] In an embodiment, the electronic circuit (1) is implemented using a plurality of discrete electronic components. In particular, the discrete electronic components are arranged on a printed circuit board (PCB) and are connected to each other directly or indirectly through PCB traces and / or wires. The discrete electronic components include various elements and components of the electronic circuit (1) as described herein, for example, the LNA (12) and comparator (13) described with reference to FIG. 1, as well as one or more of additional elements and components described with reference to the rest of the drawings.

[0035] In an embodiment, the electronic circuit (1) is implemented as an integrated circuit (IC). The IC preferably includes analog components along a signal chain, that is, the direct signal chain between the analog input terminal (11) and the wake-up trigger signal output (14) includes only analog components.

[0036] Depending on the embodiment, one or more ultra-wideband pulses digitally encode data using a specific encoding scheme. In one example, phase shift keying, such as binary-phase shift keying (BPSK), transmits data by modulating the phase of one or more ultra-wideband pulses to encode digital bits.

[0037] In an embodiment, the pulse amplitude threshold includes a plurality of pulse amplitude thresholds. In an example where ultra-wideband pulses encode data using BPSK, the pulse amplitude threshold includes a positive pulse amplitude threshold and a negative pulse amplitude threshold. The comparator (13) is configured to generate a wake-up trigger signal when one or both of the positive pulse amplitude threshold and the negative pulse amplitude threshold are exceeded, that is, when one or more ultra-wideband pulses have a pulse amplitude greater than the positive pulse amplitude threshold and / or a pulse amplitude smaller than the negative pulse amplitude threshold. Depending on the embodiment, the comparator (13) is configured to generate a wake-up trigger signal based on the absolute value of the ultra-wideband pulse amplitude of one or more ultra-wideband pulses.

[0038] Depending on the embodiment, the electronic circuit (1) is configured to receive, in particular, low rate pulse (LRP) ultra-wideband pulses and / or high rate pulse (HRP) ultra-wideband pulses. Because the amplitudes of the ultra-wideband pulses differ between the LRP and HRP ultra-wideband pulses, a pulse amplitude threshold defined accordingly is adjusted. Specifically, LRP ultra-wideband pulses typically have higher amplitude pulses than HRP ultra-wideband pulses, and thus the pulse amplitude threshold is higher when the electronic circuit (1) is configured for LRP ultra-wideband pulses than when the electronic circuit (1) is configured for LRP ultra-wideband pulses.

[0039] Depending on the embodiment, the electronic circuit (1) includes two comparators (13) in parallel, configured such that the first comparator (13) has a pulse amplitude threshold designed to detect LRP ultra-wideband pulses and the second comparator (13) has a pulse amplitude threshold designed to detect HRP ultra-wideband pulses.

[0040] In an embodiment, the comparator (13) is implemented as an analog comparator (13) using, for example, one or more operational amplifiers (op-amps), as described in more detail with reference to FIGS. 15, 17, 19, and 21.

[0041] FIG. 2 shows a block diagram of an electronic circuit (1) as described with reference to FIG. 1, further comprising an integrator (15). The integrator (15) is arranged downstream of the LNA (12) and upstream of the comparator (13) and is configured to integrate a plurality of ultra-wideband pulses so that the output signal of the integrator (15) increases as the number of ultra-wideband pulses increases. The integrator (15) is configured to have a relaxation time so that if no additional ultra-wideband pulses are received, the output signal of the integrator (15), specifically the voltage level of the output signal, gradually returns to a baseline value. The integrator (15) is connected to a comparator (13) configured to generate a wake-up trigger signal when the output signal of the integrator (15) exceeds a predefined integration threshold.

[0042] For example, the integration threshold is defined such that at least 10 super-wideband pulses, preferably 20, are received within a short time period defined by the electronic circuit (1) so that the integrator (15) generates an output signal exceeding the integration threshold of the comparator (13).

[0043] Accordingly, the electronic circuit (1) is configured to generate a wake-up trigger signal only when a predetermined number of ultra-wideband pulses are received within a short time period. This has the technical benefit that a single and / or a few spurious ultra-wideband pulses received by the electronic circuit (1) do not result in the generation of a wake-up trigger signal.

[0044] In an embodiment, the integrator (15) is implemented as an analog integrator (15). Specifically, the analog integrator (15) exclusively includes an analog circuit section.

[0045] In an embodiment, the electronic circuit (1) further comprises a rectifier arranged downstream of the LNA (12), particularly between the LNA (12) and the integrator (15). Additionally or alternatively, the electronic circuit (1) comprises an envelope detector and / or filter (e.g., a low-pass or band-pass filter) arranged downstream of the LNA (12), particularly between the LNA (12) and the integrator (15).

[0046] FIG. 3 shows a block diagram of an electronic circuit (1) as described with reference to FIG. 1, further comprising a correlator (16) arranged downstream of a low-noise amplifier (12) and upstream of a comparator (13). The correlator (16) is configured to multiply one or more (amplified) ultra-wideband pulses received by the antenna (2) at a mixer (162) by a template ultra-wideband pulse (161). The multiplication has the effect of increasing the amplitude of the received ultra-wideband pulses having a waveform that is correlated (i.e., similar) to the template pulse (161), while suppressing the received ultra-wideband pulses having a waveform that is not similar to the template pulse (161). An integrator (163) integrates the ultra-wideband pulses downstream and forwards the output signal of the integrator (163) to the comparator (13). The integrator (163) integrates super-wideband pulses over a predefined correlation integration time period.

[0047] By multiplying one or more received ultra-wideband pulses by a template waveform (161), the electronic circuit (1) has a higher selectivity for detecting an ultra-wideband signal, and the ultra-wideband signal may consist of multiple ultra-wideband pulses. For example, the electronic circuit (1) generates a wake-up trigger signal only when a predetermined number of ultra-wideband pulses have a waveform corresponding to the stored template waveform (161).

[0048] In an embodiment, the correlation integration time period is a continuous correlation integration time period.

[0049] Depending on the embodiment, the template ultra-wideband pulse (161) is provided by an analog component and / or a digital component. For example, the template ultra-wideband pulse (161) is stored in digital memory, for example, in the form of a lookup table.

[0050] Depending on the embodiment, the template super-wideband pulse (161) includes the entire waveform of the template super-wideband pulse (161) and / or the envelope of the template super-wideband pulse.

[0051] In fact, the correlator (16) performs convolution of the template pulse (161) and each of one or more ultra-wideband pulses.

[0052] Depending on the embodiment, the correlator (16) performs cross-correlation between the template pulse (161) and each of one or more ultra-wideband pulses.

[0053] In an embodiment, the correlator (16) is an analog correlator (16) including, for example, a Gilbert cell.

[0054] In an embodiment, the correlator (16) is configured to use the envelope of a stored template ultra-wideband pulse (161) as a basis for comparison. In particular, the correlator (16) is configured to multiply one or more (amplified) ultra-wideband pulses received by the antenna (2) by the envelope of the template ultra-wideband pulse (161).

[0055] In an embodiment, a rectifier, envelope detector and / or filter (e.g., a low-pass or band-pass filter) is arranged downstream of the LNA (12), particularly between the LNA (12) and the integrator (16).

[0056] FIG. 4 shows a block diagram of an electronic circuit (1) as described with reference to FIG. 1, further comprising a quadrature demodulator (17). The quadrature demodulator (17) is configured to receive one or more amplified ultra-wideband pulses and to demodulate the ultra-wideband pulses into an in-phase component and a quadrature component. The quadrature demodulator (17) is arranged downstream from low-noise amplifiers (12, 12A, 12B). The electronic circuit (1) is configured to provide the in-phase component and the quadrature component to analog outputs (171 and 172), respectively.

[0057] Depending on the embodiment, the quadrature demodulator (17) has a local oscillator or is connected to a local oscillator of the electronic circuit (1). The quadrature demodulator (17) is configured to mix the in-phase output signal of the local oscillator with the received ultra-wideband pulses to generate an in-phase component, and includes mixers configured to mix the output signal that is 90° out of phase with the local oscillator with the received ultra-wideband pulses to generate a quadrature component.

[0058] Depending on the embodiment, the in-phase components and the quadrature components are each provided to an analog-to-digital converter (ADC) arranged downstream of the quadrature demodulator (17) so that a digital representation of the in-phase and quadrature components of the ultra-wideband signal is provided to the analog outputs (171 and 172), respectively.

[0059] In an embodiment, the quadrature demodulator (17) demodulates ultra-wideband pulses into in-phase and quadrature components and then includes a filter block.

[0060] FIG. 5 shows a block diagram of an electronic circuit (1) as described with reference to FIG. 3, further comprising a quadrature demodulator (17) arranged downstream from the LNA (12) and upstream from the comparator (16). The quadrature demodulator (17) is configured such that the output signals of both, namely the in-phase component and the quadrature component, are added together. The combined (i.e., added) output signal of the quadrature demodulator (17) is then forwarded to the correlator (16) (i.e., provided as an input signal).

[0061] In an embodiment, the orthogonal demodulator (17) is an analog orthogonal demodulator (17). Specifically, the orthogonal demodulator (17) is implemented using an analog circuit section exclusively.

[0062] The in-phase component and the orthogonal component are added, and as illustrated by the addition symbol, the summed signal is provided to the correlator (16).

[0063] In an embodiment, the electronic circuit (1) includes a rectifier, an envelope detector, and / or a filter arranged downstream of the quadrature demodulator (17), particularly between the quadrature demodulator (17) and the correlator (16).

[0064] In an embodiment, the electronic circuit (1) includes a feedback connection, as shown by the dotted line connection in FIG. 5. The feedback connection connects the output of the correlator (16) to the demodulator (17). The feedback connection provides phase control and / or frequency control of the local oscillator of the demodulator (17) to maximize the amplitude of the correlator (16).

[0065] FIG. 6 shows a block diagram of an electronic circuit (1) having many of the components previously described with reference to FIGS. 1 through 5, but in-phase and quadrature components are correlated and compared separately in separate correlators (16A, 16B) and comparators (13A, 13B), respectively. Specifically, the in-phase component output signal of the quadrature demodulator (17) is provided to the first correlator (16A), which is then connected to the first comparator (13A). Similarly, the quadrature component output signal of the quadrature demodulator (17) is connected to the second correlator (16B), which is then connected to the second comparator (13B). The comparators (13A, 13B) are connected to a logic gate (18), the output signal of which depends on the output signals of the comparators (13A, 13B).

[0066] For example, since the logic gate (18) is an OR gate, the logic gate (18) forwards the wake-up trigger signal only when one or both of the comparators (13A, 13B) detect an ultra-wideband pulse (i.e., the input signal of either of the comparators (13A, 13B) exceeds the pulse amplitude threshold). In another example, since the logic gate (18) is an AND gate, the wake-up trigger signal is forwarded by the logic gate (18) only when both of the comparators (13A, 13B) detect an ultra-wideband pulse.

[0067] In an embodiment, the electronic circuit (1) includes a rectifier, an envelope detector, and / or a filter arranged downstream of each output of the quadrature demodulator (17), particularly between each output of the quadrature demodulator (17) and each correlator (16A, 16B).

[0068] In an embodiment, analog outputs (171 and 172) are each provided to directly output signals from comparators (13A, 13B).

[0069] FIG. 7 shows a block diagram of an electronic circuit (1) as described with reference to FIG. 1. A timing circuit (19) is arranged downstream of the LNA (12) and upstream of a comparator (13) (optional). The timing circuit (19) is configured to transmit beacon super-wideband pulses at regular intervals, preferably once per second. The beacon super-wideband pulses are transmitted using an antenna (2).

[0070] In an embodiment, the transmitter circuit is arranged in parallel with an electronic circuit (1) configured to transmit a beacon ultra-wideband pulse using an antenna (2).

[0071] Depending on the embodiment, the timing circuit (19) or the electronic circuit (1) has a separate amplifier configured to amplify the beacon ultra-wideband pulse.

[0072] In an embodiment, the electronic circuit (1) has a separate connection for connecting the timing circuit (19) to the antenna (2) in particular to transmit a beacon ultra-wideband pulse.

[0073] The beacon ultra-wideband pulse is configured to be received by a mobile ultra-wideband device (9), particularly a mobile ultra-wideband device (9) that is returned by a user (see FIG. 13 and FIG. 14). The timing circuit (19) is configured to receive one or more ultra-wideband pulses in response to the transmitted beacon ultra-wideband pulse. The timing circuit (19) is configured to determine the distance using the time difference between the reception of a specific ultra-wideband pulse and the transmission of the beacon pulse. In particular, the distance between the electronic circuit (1) and the mobile ultra-wideband device (9) uses time-of-flight (ToF) calculations, taking into account the response time of the mobile ultra-wideband device (9) in addition.

[0074] Depending on the embodiment, the timing circuit (19) is configured to forward a specific ultra-wideband pulse, for example in the form of a wake-up trigger signal, only when the distance is smaller than a predefined proximity distance. Alternatively, the timing circuit (19) is configured to forward an ultra-wideband pulse to the comparator (13) only when the distance is smaller than a predefined proximity distance.

[0075] In this way, the electronic circuit (1) forwards the wake-up trigger signal only when the ultra-wideband transmitter, for example, the aforementioned mobile ultra-wideband device (9), is within close proximity.

[0076] The above-described timing circuit (19) is also combined with a correlator (16) as described with reference to FIGS. 3, FIGS. 5, and FIGS. 6, depending on the embodiment. For example, the correlator (16) is arranged upstream or downstream from the timing circuit (19).

[0077] Additionally, depending on the embodiment, as described with reference to FIG. 2, the integrator (15) is arranged upstream or downstream from the timing circuit (19).

[0078] In an embodiment, the timing circuit (19) is an analog timing circuit (19). Specifically, the analog timing circuit (19) is implemented exclusively using an analog circuit section.

[0079] FIG. 8 shows a block diagram of an electronic circuit (1) having two analog input terminals (11A, 11B), each connected to a separate LNA (12A, 12B). Each analog input terminal (11A, 11B) is connected to a separate antenna (2A, 2B). A timing circuit (19) is connected to the LNAs (12A, 12B) and configured to determine the time difference and / or phase difference between a specific ultra-wideband pulse received at both of the analog input terminals (11A, 11B). By determining the time difference and / or phase difference, the timing component (19) is enabled to determine the direction in which the specific ultra-wideband pulse was received, in addition to the distance.

[0080] In an embodiment, the antennas (2A, 2B) are directional antennas (2A, 2B) facing different directions, and the timing circuit (19) is configured to determine which directional antenna (2A, 2B) has received an ultra-wideband pulse. The timing circuit (19) is further configured to forward the ultra-wideband pulse only when the direction of reception corresponds to one or more predetermined directions, using the signal characteristics of the ultra-wideband pulse received from the directional antennas (2A, 2B), in particular the amplitude of the ultra-wideband pulse.

[0081] In an embodiment, the timing component (19) is configured to forward an ultra-wideband pulse to a (optional) comparator (13) only when the direction of reception corresponds to one or more predetermined directions.

[0082] The predetermined direction is defined, for example, by one or more vertical and / or horizontal angle ranges.

[0083] In an embodiment, the timing circuit (19) forwards the ultra-wideband pulse to a comparator (13) (optional) that generates a wake-up trigger signal depending on the amplitude of the ultra-wideband pulse.

[0084] Depending on the embodiment, the comparator (13) is arranged as part of the timing circuit (19) and / or the timing circuit (19) is configured to possess the functionality of the comparator (13) as described herein.

[0085] FIG. 9 shows a block diagram of an ultra-wideband reader (3) including an electronic circuit (1), an antenna (2), and a digital processing unit (DPU) (4). The digital processing unit (4) is a digital microprocessor, such as an ultra-wideband modem, for example. The DPU (4) optionally includes an ultra-wideband receiver, a transmitter, and / or an analog-to-digital converter. The DPU (4) is connected to the antenna via the electronic circuit (1).

[0086] The DPU (4) is connected to the wake-up trigger signal output (14) of the electronic circuit (1). Depending on the embodiment, the DPU (4) is alternatively or additionally connected to the antenna (2) via a wire (41). The DPU (4) is configured to be in a sleep state that initially consumes little or no power compared to the awake state.

[0087] The DPU (4) is connected to the electronic circuit (1) and is configured to receive a wake-up signal trigger from the electronic circuit (1) and, in response to the wake-up, transition from a sleep state to an awake state. In particular, the sleep state is defined by the DPU (4) not receiving and / or processing any ultra-wideband pulses received from the antenna (2) through the electronic circuit (1) or through other connections such as the wire (41). The awake state is defined by the electronic circuit (1) receiving and processing ultra-wideband pulses received from the antenna (2).

[0088] Depending on the embodiment, the DPU (4) is configured to perform one or more of a number of functions in an awake state. For example, the DPU (4) is configured to perform ranging using the signal characteristics of one or more received ultra-wideband pulses. For example, the DPU (4) is additionally configured to transmit ultra-wideband pulses. In another example, the DPU (4) is configured to perform access control using an identification and / or secret key contained in one or more ultra-wideband pulses received by the antenna (2).

[0089] Depending on the embodiment, the DPU (4) is configured to return to a sleep state after a defined period of inactivity, for example, after a defined period of not receiving any ultra-wideband pulses.

[0090] In an embodiment, one or more ultra-wideband pulses received by the antenna (2) include a sequence of one or more LRP ultra-wideband pulses followed by one or more ultra-wideband HRP pulses. The electronic circuit (1) is configured to receive one or more LRP ultra-wideband pulses and generate a wake-up trigger signal as described herein. In particular, the pulse amplitude threshold is defined with respect to the higher instantaneous peak power of the LRP ultra-wideband pulse.

[0091] The DPU (4) is configured to process one or more HRP ultra-wideband pulses by digitizing the HRP ultra-wideband pulses to extract encoded digital bits, particularly to execute one or more functions. This configuration of the ultra-wideband reader (3) enables both high selectivity due to the higher instantaneous peak power of the LRP pulses and the consequently higher pulse amplitude threshold, while simultaneously allowing a higher data transmission rate enabled by the HRP ultra-wideband pulses.

[0092] In an embodiment, both the electronic circuit (1) and the DPU (4) are implemented as integrated circuits (ICs) on a PCB that are connected to each other directly or indirectly through PCB traces. An antenna (2) may additionally be arranged on the same PCB or connected to the PCB, and thus connected to the electronic circuit (1) and optionally also to the DPU (4).

[0093] In an embodiment, the electronic circuit (1) and the DPU (4) are integrated into the same IC. Preferably, the electronic circuit (1) exclusively includes analog components along at least the signal chain between the input terminal (11) and the wake-up trigger signal output (14).

[0094] FIG. 10 shows a block diagram of an ultra-wideband reader (3) as described with reference to FIG. 9, additionally including a switch (6) configured to electrically connect the DPU (4) to the battery (5) upon receiving a wake-up trigger signal from the electronic circuit (1). By doing so, the switch (6) supplies power to the DPU (4) by connecting the battery (5) to the DPU (4).

[0095] Depending on the embodiment, the switch (6) is arranged as part of the electronic circuit (1) or DPU (4), or as a separate circuit arranged between the electronic circuit (1) and DPU (4).

[0096] In an embodiment, the switch (6) is configured to maintain an electrical connection between the battery (5) and the DPU (4) for a predetermined time period after receiving a wake-up trigger signal, and after that time period, the switch (6) disconnects the battery (5) from the DPU (4).

[0097] In an embodiment, the switch (6) is configured to receive a shutdown trigger signal from the DPU (4), and upon receiving the signal, the switch (6) disconnects the DPU (4) from the battery (5).

[0098] FIG. 11 shows a block diagram of an ultra-wideband reader (3) as described with reference to FIG. 9 and FIG. 10, wherein the electronic circuit (1) further includes an analog-to-digital converter (ADC) (7) arranged downstream of an LNA (12). The ADC (7) is configured to digitize an (amplified) analog input signal and provide the digitized output signal to a DPU (4). Reference numeral 8 refers to various components of the electronic circuit (1) that are not shown in FIG. 11 but are shown in FIG. 1 through 9.

[0099] The digitized output signal (14') may be used as a wake-up trigger signal, allowing the omission of block (8) in the embodiment. In the embodiment, an orthogonal demodulator (as described with reference to the preceding drawings) is arranged upstream of the ADC (7), particularly between the LNA (12) and the ADC (7).

[0100] FIG. 12 is a chart illustrating the ideal waveform of a received ultra-wideband pulse using binary phase-shift keying (BPSK) encoding logic '0' and logic '1'. Both ultra-wideband pulses encoding '0' and '1' are shown. The amplitude is the normalized amplitude. Time is given in nanoseconds, and it can be seen that the illustrated ultra-wideband pulse has a total duration of about 0.3 nanoseconds. In particular, the chart shows the output signal of the comparator (13) as well as the ultra-wideband pulse amplitudes after amplification by the LNA (12). It can be seen that the output signal of the comparator (13) is '0', while the ultra-wideband pulse amplitude is below a predefined pulse amplitude threshold for the BPSK '0' signal. Similarly, the output signal of the comparator (13) is maintained at '0', while the ultra-wideband pulse amplitude is greater than the predefined pulse amplitude threshold for the BPSK '1' signal.

[0101] Depending on the embodiment, as described particularly with reference to FIGS. 1 to 8, the electronic circuit (1) is designed to generate an output signal at the comparator (13) as illustrated.

[0102] The wake-up trigger signal generated by the comparator (13) is defined by the change in the comparator output signal from a normalized amplitude of 0 to 1.

[0103] The wake-up trigger signal is forwarded to an ultra-wideband reader (13) as described with reference to FIGS. 9 through 11 in an embodiment.

[0104] The embodiments described above in this disclosure are exemplary, and those skilled in the art know that at least some of the components described in the embodiments may be rearranged, omitted, or introduced in other embodiments without departing from the scope of this disclosure.

[0105] FIG. 13 shows a timing diagram illustrating cross-sectional bidirectional ranging between an electronic circuit (1) and a mobile ultra-wideband device (9). In particular, the timing diagram applies to the embodiment described above with reference to FIG. 7, in which the electronic circuit (1) transmits an ultra-wideband pulse, particularly a beacon pulse.

[0106] In step (S1), the electronic circuit (1) transmits an ultra-wideband pulse, specifically a beacon pulse. After a propagation time (T1), the mobile ultra-wideband device (9) receives the ultra-wideband pulse in step (S2). The propagation time (T1) depends on the distance between the electronic circuit (1) and the mobile ultra-wideband device (9). The ultra-wideband device (9) processes the received ultra-wideband pulse in processing time (T2). In step (S3), the ultra-wideband device (9) transmits one or more ultra-wideband pulses, specifically one or more response pulses. After a propagation time (T3) approximately equal to T1, the electronic circuit (1) receives one or more ultra-wideband pulses in step (S4). The round-trip time is defined as the sum of T1, T2, and T3.

[0107] In an embodiment in which a processing time (T2) is predefined, for example, a mobile ultra-wideband device (9) has a known consistent processing time (T2), the electronic device (1), in particular the timing circuit (19), is configured to forward one or more ultra-wideband pulses received in step (S4) to generate a wake-up trigger signal only when the round-trip time is less than a predefined threshold time. The predefined threshold time is defined in consideration of the processing time (T2) and a predefined proximity distance, and the predefined proximity distance is related to the propagation time (T1, T2) in consideration of the propagation speed of the ultra-wideband signals. In particular, the predefined threshold time is defined such that the ultra-wideband device (9) must be at or within a predefined proximity distance from the electronic circuit (1) in order to satisfy the predefined threshold time or fall within that time.

[0108] In an embodiment, the electronic device (1) is configured to decode an encoded processing time (T2) from one or more response pulses. The electronic device (1), in particular the timing circuit (19), is further configured to forward one or more ultra-wideband pulses received in step (S4) to generate a wake-up trigger signal only when the round-trip time is less than a threshold time, the threshold time being determined by taking into account the processing time (T2) and a predefined proximity distance. In particular, the threshold time is defined such that the ultra-wideband device (9) must be at or within a predefined proximity distance from the electronic circuit (1) in order to satisfy or fall within the predefined threshold time.

[0109] FIG. 14 shows a timing diagram illustrating bidirectional ranging between an electronic circuit (1) and a mobile ultra-wideband device (9). The timing diagram corresponds to some embodiments of the electronic circuits (1) described herein, in particular the embodiment described above with reference to FIG. 7, in which the electronic circuit (1) transmits an ultra-wideband pulse, in particular a beacon pulse. The timing diagram illustrates an embodiment in which a beacon pulse of the electronic circuit (1) is transmitted in response to one or more ultra-wideband pulses transmitted by the mobile ultra-wideband device (9).

[0110] In step (S5), the mobile ultra-wideband device (9) transmits these pulses to an electronic circuit (1) that receives one or more ultra-wideband pulses in step (S6) after a propagation time (T4). After a processing time (T5), the electronic circuit (1) transmits a beacon pulse in step (S1). Subsequently, steps (S1-S4) occur as described above with reference to FIG. 13.

[0111] In an embodiment, the electronic circuit (1), particularly the timing circuit (19), is configured to forward one or more ultra-wideband pulses received in step (S4) to generate a wake-up trigger signal as described above with reference to FIG. 13.

[0112] In an embodiment, the electronic circuit (1) is configured to forward one or more ultra-wideband pulses received in step (S4) to generate a wake-up trigger signal by also considering one or more ultra-wideband pulses received in step (S6). In particular, the first round-trip time is defined as the sum of T4, T5, and T1. The second round-trip time is defined as the sum of T1, T2, and T3. The electronic circuit (1) is configured to generate a wake-up trigger only when the following conditions are satisfied:

[0113]

[0114] Here is the critical time corresponding to a predefined proximity distance.

[0115] FIGS. 15, 17, 19, 21 and 23 illustrate embodiments of a comparator (13), and FIGS. 16, 18, 20, 22 and 24 illustrate charts illustrating the output of the comparator (13), respectively. A comparator (13) as described below with reference to FIGS. 15, 17, 19, 21 and 23 is implemented in an electronic circuit (1) according to the present disclosure, depending on the embodiment.

[0116] The electronic circuit (1) in which a specific comparator (13) is implemented is one of the electronic circuits (1) described above, particularly with reference to FIGS. 1 to 11.

[0117] Fig. 15 shows the input voltage (V IN ) to a predefined voltage threshold (V THOLD POS It represents a comparator (13) implemented using an op-amp (131) configured to compare with ). The op-amp (131) has a positive terminal (132) and a negative terminal (133), a positive supply terminal (134) and a negative supply terminal (135), and an output terminal (136). The positive terminal (132) is the input voltage (V IN It is connected to ), and the negative terminal (133) is connected to a predefined voltage threshold (V THOLD POS It is connected to ), and the positive supply terminal (134) is connected to the positive supply rail (V CC + It is connected to ), and the negative supply terminal (135) is connected to the negative supply rail (V CC- It is connected to ), and the output terminal (136) is connected to .

[0118] Input voltage (V IN) and predefined voltage threshold (V THOLD POS Both are defined for analog ground (AGND). The input terminal (132) is connected to, for example, an LNA (12) or an integrator (15), input voltage (V IN ) is defined by the output from the LNA (12) or integrator (15), respectively. The comparator output of the comparator (13) is connected, for example, to the wake-up trigger signal output (14) of the electronic circuit (1).

[0119] Input voltage (V IN ) is a predefined voltage threshold (V THOLD POS If it is higher than ), the comparator output is positive supply rail (V CC + It is defined by the input voltage (V). IN ) is a predefined voltage threshold (V THOLD POS If it is smaller than ), the comparator output is the negative supply rail (V CC - It is defined by ) or 0V ground.

[0120] FIG. 16 shows a chart illustrating the amplitude of the super-wideband pulse over time and the corresponding comparator output of the comparator (13) according to FIG. 15 as a function of time.

[0121] In particular, as shown in FIG. 16, the chart illustrates the output (14) of the comparator (13) for a single received ultra-wideband pulse. The ultra-wideband pulse, input as a voltage of Vin received by the comparator (13), results in an output as shown in the chart.

[0122] V for ultra-wideband pulse IN In this case, the comparator input is represented on the chart by the curve BPSK '0', where the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0123] VTHOLDPOS The threshold value as defined by is represented on the chart by the curves THOLD POS.

[0124] The comparator output (14) is represented on a chart by the curve comparator output (COMPARATOR OUT), in which the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0125] As shown in the chart, the comparator output (COMPARATOR OUT) corresponding to the output (14) in FIG. 15 changes from 0 to 1 when the ultra-wideband pulse satisfies the thresholds, generating a wake-up trigger signal.

[0126] FIG. 17 shows a comparator (13) implemented similarly to the comparator (13) shown in FIG. 15, but the first hysteresis resistor (137) is arranged between the input voltage (V IN) and the positive terminal (132) of the op-amp, and the second hysteresis resistor (138) is arranged between the output terminal (136) of the op-amp and the positive terminal (132). These hysteresis resistors (137, 138) cause a comparator (13) with hysteresis, which switches between different output levels (i.e., the positive supply rail (V CC + ) and negative supply rail (V CC - The threshold value for switching between ) is the amplitude (i.e., the input voltage (V IN It differs depending on whether it increases or decreases. This is shown in Fig. 18, where the voltage threshold is higher when the amplitude increases than when the amplitude decreases.

[0127] In particular, as shown in FIG. 18, the chart illustrates the output (14) of the comparator (13) for a single received ultra-wideband pulse. The ultra-wideband pulse received by the comparator (13) produces an output as shown in the chart.

[0128] V for ultra-wideband pulse IN In this case, the comparator input is represented on the chart by the curve BPSK '0', where the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0129] V along with the values ​​of the hysteresis resistors (137, 138) THOLD POS The thresholds defined by are represented on the chart by the curves THOLD POS HYST+ and THOLD POS HYST-.

[0130] The comparator output (14) is represented on a chart by the curve comparator output (COMPARATOR OUT), in which the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0131] As shown in the chart, the comparator output (COMPARATOR OUT) corresponding to the output (14) in FIG. 17 changes from 0 to 1 when the ultra-wideband pulse satisfies the thresholds, generating a wake-up trigger signal.

[0132] FIG. 19 shows a comparator (13) implemented similarly to the comparator (13) shown in FIG. 17, but the rectifier (139) is an input voltage (V IN It is arranged between the input terminal (132) of the op-amp and the input voltage (V). Additionally or alternatively, an envelope detector and / or filter (e.g., a low-pass or band-pass filter) is used to detect the input voltage (V). INIt is arranged between the input terminal (132) of the op-amp and the rectifier (139). As can be seen in the chart of FIG. 20, the comparator (13), implemented including the rectifier (139), outputs three wake-up trigger signals, specifically from the point where the rectified amplitude of the ultra-wideband pulse exceeds the positive hysteresis threshold to the point where the rectified amplitude falls below the negative hysteresis threshold.

[0133] In particular, the chart shows the output (14) of the comparator (13) for a single received ultra-wideband pulse. The ultra-wideband pulse received by the comparator (13) produces an output as shown in the chart.

[0134] V for ultra-wideband pulse IN In this case, the comparator input is represented on the chart by a rectified curve BPSK '0', where the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0135] V along with the values ​​of the hysteresis resistors (137, 138) THOLD POS The thresholds defined by are represented on the chart by the curves THOLD POS HYST+ and THOLD POS HYST-.

[0136] The comparator output (14) is represented on a chart by the curve comparator output (COMPARATOR OUT), in which the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0137] As shown in the chart, the comparator output (COMPARATOR OUT) corresponding to the output (14) in FIG. 19 changes from 0 to 1 when the ultra-wideband pulse satisfies the thresholds, generating a wake-up trigger signal.

[0138] FIG. 21 shows a comparator (13) comprising two op-amps (131A, 131B), wherein the first op-amp (131A) is configured to a positive threshold (i.e., to generate a wake-up trigger signal when the amplitude of an ultra-wideband pulse exceeds a predefined threshold), and the second op-amp (131B) is configured to a negative threshold (i.e., to generate a wake-up trigger signal when the amplitude of an ultra-wideband pulse falls below a predefined threshold).

[0139] To avoid confusion, not all reference numerals are shown. In particular, while the complete reference numerals related to the second op-amp (131B) are shown, the reference numerals for the first op-amp (131A) are partially omitted. References are made to FIGS. 15, FIGS. 17, and FIGS. 19, which show the reference numerals for the first op-amp (131A).

[0140] The first op-amp (131A) is connected as described with reference to FIGS. 15, 17, and 19. The second op-amp (131B) is connected to the input terminal (V IN When the amplitude of the ultra-wideband pulse, as is present in the (first) positive threshold, falls below a second threshold, for example, a negative threshold, the output terminal (136B) of the second op-amp (131B) is connected in reverse to generate a wake-up trigger signal.

[0141] In particular, the second op-amp (131B) has a negative threshold voltage (V THOLD NEG Negative terminal (132B) connected to ), input voltage (V INIt has a positive terminal (133B) connected to the positive rail (VCC+), a positive supply terminal (134B) connected to the positive rail (VCC+), and a negative supply terminal (135B) connected to the negative supply rail (VCC-). The output (136B) of the second op-amp (131B) is connected to a logic gate (1310). The output of the first op-amp (131A) is also connected to a logic gate (1310). Preferably, the logic gate (1310) is configured as a logic 'OR' gate.

[0142] In an embodiment, the input voltage (V IN ) is differentially defined between the first hysteresis resistor (137A) of the first op-amp (131A) and the first hysteresis resistor (137B) of the second op-amp (131B).

[0143] As illustrated by the chart shown in FIG. 22, the comparator (13) shown in FIG. 21 is configured to generate a wake-up trigger signal when the amplitude of the super-wideband pulse falls below a predefined negative threshold voltage or when the amplitude of the super-wideband pulse exceeds a predefined positive threshold voltage. Additionally, the negative threshold voltage includes a positive hysteresis voltage and a negative hysteresis voltage, and similarly, the positive threshold voltage also includes a positive hysteresis voltage and a negative hysteresis voltage, so that a larger amplitude (magnitude) of the super-wideband pulse is required to cause the comparator (13) to start generating a wake-up trigger signal rather than stop generating a wake-up trigger signal.

[0144] In particular, the chart shows the output (14) of the comparator (13) for a single received ultra-wideband pulse. The ultra-wideband pulse received by the comparator (13) produces an output as shown in the chart.

[0145] Input voltage (V) for ultra-wideband pulse IN In ), the comparator input is represented on the chart by the curve BPSK '0', where the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0146] V as well as the values ​​of the hysteresis resistors (137A, 138A, 137B, 138B) THOLD POS The thresholds defined by are represented on the chart by the curves THOLD POS HYST+, THOLD POS HYST-, THOLD NEG HYST+, and THOLD NEG HYST-.

[0147] The comparator output (14) is represented on a chart by the curve comparator output (COMPARATOR OUT), in which the amplitude (i.e., voltage) appears on a normalized scale as a function of time.

[0148] As shown in the chart, the comparator output (COMPARATOR OUT) corresponding to the output (14) in FIG. 21 changes from 0 to 1 when the ultra-wideband pulse satisfies the thresholds, generating a wake-up trigger signal.

[0149] FIG. 23 shows a comparator (13) of FIG. 21 comprising additional outputs (171, 172) from a first op-amp (131A) and a second op-amp (131B), respectively. By doing so, additional outputs (171, 172) are provided to an electronic circuit (1) comprising the comparator (13), as described above with reference to, for example, FIG. 3, FIG. 5, or FIG. 6.

[0150] In an embodiment in which one or more ultra-wideband pulses encode data digitally using phase-shift keying BPSK as described above, the positive output (171) of the comparator (13) provides a '0' bit and the negative output (172) of the comparator (13) provides a '1' bit.

[0151] Input voltage (V IN ) is preferably provided by a correlator (16) as described above with reference to FIG. 3, FIG. 5, or FIG. 6. Specifically, in an embodiment, the input voltage (V IN) ) is connected to the output of the correlator (16).

[0152] The output of the comparator (13) is connected to the wake-up trigger signal output (14) of the electronic circuit (1), as described above with reference to the previous drawings.

[0153] FIG. 24 shows a chart illustrating the outputs of the comparator (13) described with reference to FIG. 23. In particular, these are the outputs of the comparator (13) when an ultra-wideband pulse received at the input terminal (11) of the electronic circuit (1) passes through the correlator (16) before being input to the comparator (13), as described above with reference to FIG. 3, FIG. 5 and FIG. 6.

[0154] In particular, the chart illustrates the outputs (14, 171, 172) of a comparator (13) for two correlated ultra-wideband pulses, a first correlated ultra-wideband pulse encoding a '0' bit according to BPSK, and a second correlated ultra-wideband pulse encoding a '1' bit according to BPSK. As shown in the chart, the first and second correlated ultra-wideband pulses used to generate the outputs have slightly different amplitudes to have minimum shifted trigger times to better illustrate the outputs (14, 171, 172).

[0155] V for the first and second correlated ultra-broadband pulses IN In this case, the comparator inputs are represented on the chart by the curves CORR I+Q (BPSK '0') and CORR I+Q (BPSK '1'), where the amplitudes (i.e., voltages) as a function of time appear on a normalized scale.

[0156] V as well as the values ​​of the hysteresis resistors (137A, 138A, 137B, 138B) THOLD POS The thresholds defined by are represented on the chart by the curves THOLD POS HYST+, THOLD POS HYST-, THOLD NEG HYST+, and THOLD NEG HYST-.

[0157] Comparator outputs (14, 171, 172) are represented on a chart by curves comparator output (COMPARATOR OUT), comparator POS (COMPARATOR POS), and comparator NEG (COMPARATOR NEG), where amplitudes (i.e., voltages) appear on a normalized scale as a function of time.

[0158] As shown in the chart, the comparator output (COMPARATOR OUT) corresponding to output (171) in FIG. 23 changes from 0 to 1 when a super-wideband pulse representing a '0' bit satisfies the threshold THOLD POS HYST+. The comparator NEG output corresponding to output (172) in FIG. 23 changes from 0 to 1 when a second super-wideband pulse representing a '1' bit satisfies the threshold THOLD NEG HYST- (shown as changing from 0 to -1 for illustrative purposes only). In FIG. 23, the comparator output (COMPARATOR OUT) corresponding to the output (14) is generated by changing from 0 to 1 when the gate (1310) is an OR gate, or when the comparator POS (COMPARATOR POS) or comparator NEG (COMPARATOR NEG) output changes from 0 to 1, thereby generating a wake-up trigger signal.

Claims

Claim 1 An electronic circuit (1) for detecting ultra-wideband pulses, comprising: an analog input terminal (11, 11A, 11B) configured for connection to an ultra-wideband antenna (2, 2A, 2B); a low-noise amplifier (12, 12A, 12B) connected to the analog input terminal (11, 11A, 11B) and configured to amplify one or more ultra-wideband pulses received through the ultra-wideband antenna (2, 2A, 2B); and a comparator (13, 13A, 13B) connected to the low-noise amplifier (12, 12A, 12B) and configured to generate a wake-up trigger signal for ultra-wideband pulses exceeding a predefined pulse amplitude threshold. Claim 2 An electronic circuit (1) for detecting ultra-wideband pulses, wherein, in claim 1, it further comprises an integrator (15) arranged between the low-noise amplifier (12, 12A, 12B) and the comparator (13, 13A, 13B) and configured to integrate the one or more ultra-wideband pulses over a predetermined integration time period, and the comparator (13, 13A, 13B) is further configured to generate a wake-up trigger signal for the integrated ultra-wideband pulses that exceed a predetermined integration threshold. Claim 3 An electronic circuit (1) for detecting an ultra-wideband pulse, further comprising a correlator (16, 16A, 16B) arranged upstream from the comparator (13, 13A, 13B) and configured to multiply one or more received ultra-wideband pulses by a template ultra-wideband waveform (161) and integrate one or more multiplied ultra-wideband pulses over a predefined correlation integration time period. Claim 4 An electronic circuit (1) for detecting an ultra-wideband pulse, further comprising an orthogonal demodulator (17) arranged downstream from the low-noise amplifier (12, 12A, 12B) and configured to determine the in-phase component and the orthogonal component of the one or more ultra-wideband pulses. Claim 5 In claim 4, the demodulated in-phase components of one or more ultra-wideband pulses are added to the demodulated orthogonal components of one or more ultra-wideband pulses, an electronic circuit (1) for detecting an ultra-wideband pulse. Claim 6 An electronic circuit (1) for detecting an ultra-wideband pulse, wherein the demodulated in-phase components of one or more ultra-wideband pulses and the demodulated orthogonal components of one or more ultra-wideband pulses are each transmitted to separate comparators (13, 13A, 13B), and all of the comparators (13, 13A, 13B) are connected to a single downstream logic gate (18) configured to generate the wake-up trigger signal depending on the output signal of the comparators (13, 13A, 13B). Claim 7 In claim 1, the analog input terminals (11, 11A, 11B) are connected to a directional ultra-wideband antenna (2, 2A, 2B), and the electronic circuit (1) for detecting an ultra-wideband pulse. Claim 8 An electronic circuit (1) for detecting an ultra-wideband pulse, wherein the electronic circuit (1) receives the one or more ultra-wideband pulses in response to a beacon pulse transmitted by the electronic circuit (1); determines a distance using the time difference between the reception of a specific ultra-wideband pulse and the transmission of the beacon pulse; and comprises a timing circuit (19) connected to the low-noise amplifier (12, 12A, 12B), configured to forward the specific ultra-wideband pulse specifically to generate a wake-up trigger signal only when the distance is smaller than a predefined proximity distance. Claim 9 In claim 8, the electronic circuit (1) comprises two analog input terminals (11, 11A, 11B) configured to be connected to each of two ultra-wideband antennas (2, 2A, 2B), and the timing circuit (19) determines, for a specific ultra-wideband pulse received from the two analog input terminals (11, 11A, 11B): at least one of the time difference of receiving the specific ultra-wideband pulse from the two analog input terminals (11, 11A, 11B) or the phase difference of the specific ultra-wideband pulse received from the two analog input terminals (11, 11A, 11B); An electronic circuit (1) for detecting an ultra-wideband pulse, configured to forward the specific ultra-wideband pulse to generate the wake-up trigger signal, specifically only when the above time difference corresponds to a predetermined time difference range or the above phase difference corresponds to a predetermined phase difference range. Claim 10 In claim 1, the electronic circuit (1) comprises a plurality of analog input terminals (11, 11A, 11B) configured to be connected to a plurality of ultra-wideband antennas (2, 2A, 2B), respectively, and the electronic circuit (1) further comprises a direction component configured to determine the transmission direction of the one or more ultra-wideband pulses depending on one or more of the reception time or phase of the one or more ultra-wideband pulses, and the direction component further comprises an electronic circuit (1) for detecting ultra-wideband pulses, wherein the direction component is further configured to forward the one or more ultra-wideband pulses only when the determined transmission direction matches a predetermined transmission direction. Claim 11 An ultra-wideband reader (3) comprising an electronic circuit (1) described in any one of claims 1 to 10, and a digital processing unit (4) connected to the electronic circuit (1) and configured to wake up when receiving the wake-up trigger signal. Claim 12 In claim 11, an ultra-wideband reader (3) further comprising a battery (5), wherein the digital processing unit (4) is initially powered off, and the wake-up trigger signal is received by a switch (6) configured to wake up the digital processing unit (4) by connecting the battery (5) to the digital processing unit. Claim 13 In claim 11, the digital processing unit (4) is initially in a low-power state, and the wake-up trigger signal is configured to switch the digital processing unit (4) to a high-power state, and the digital processing unit (4) has a relatively higher power consumption in the high-power state than in the low-power state, an ultra-wideband reader (3). Claim 14 In claim 11, the ultra-wideband reader (3) further comprises an analog-to-digital converter (7) arranged downstream from the low-noise amplifier (12, 12A, 12B), wherein the analog-to-digital converter (7) is connected to the digital processing unit and configured to generate a digital signal from the one or more ultra-wideband pulses; and the digital processing unit (4) is configured to use the digital signal to authenticate the ultra-wideband device that transmitted the one or more ultra-wideband pulses.

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