Electrostatic discharge protection circuit

Abstract

An electrostatic discharge (ESD) protection circuit comprising a main transistor, a resistor element, and a control circuit is disclosed. A first voltage terminal is coupled to a second terminal of the main transistor and a first terminal of the resistor element. A second voltage terminal is coupled to a first terminal of the main transistor. A control circuit is coupled between the second terminal of the resistor element and a control terminal of the main transistor. When an ESD event occurs, the product of the capacitance value of the parasitic capacitance of the control circuit and the resistance value of the resistor element is greater than the duration of the ESD event, and the control circuit turns on the main transistor so that an ESD current flows through the main transistor.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of priority of Taiwan application No. 112144579 filed on November 17, 2023. The entirety of the aforementioned patent application is hereby incorporated by reference into this specification and becomes part of this application.

[0003] The present disclosure relates to an integrated circuit, in particular, to an electrostatic discharge (ESD) protection circuit. Background Technology

[0004] Electrostatic discharge (ESD) is one of the major factors causing electrical overstress (EOS) that damages integrated circuits. ESD can permanently damage semiconductor elements within integrated circuits and affect the functionality of the integrated circuit (or even cause it to fail to operate properly). How to prevent ESD from damaging integrated circuits is one of the many technical issues that need to be resolved in this field.

[0005] The present disclosure provides an electrostatic discharge protection circuit for preventing electrostatic discharge (ESD) from damaging an integrated circuit.

[0006] In an embodiment of the disclosure, an ESD protection circuit is coupled between a first voltage terminal and a second voltage terminal. The ESD protection circuit includes a main transistor, a first resistor element, and a control circuit. A first terminal of the main transistor is coupled to the second voltage terminal. A second terminal of the main transistor is coupled to the first voltage terminal. A first terminal of the first resistor element is coupled to the first voltage terminal. A first terminal of the control circuit is coupled to the first voltage terminal. A second terminal of the control circuit is coupled to the second voltage terminal. An input terminal of the control circuit is coupled to the second terminal of the first resistor element. An output terminal of the control circuit is coupled to the control terminal of the main transistor. The control circuit includes a first control transistor and a second control transistor. A first terminal of the first control transistor is coupled to the first terminal of the control circuit. A control terminal of the first control transistor is coupled to the input terminal of the control circuit. A first terminal of the second control transistor is coupled to the second terminal of the control circuit. The second terminal of the second control transistor is connected to the second terminal of the first control transistor. The control terminal of the second control transistor is connected to the input terminal of the control circuit. When an ESD event occurs, the product of the capacitance value of the parasitic capacitance of the second control transistor and the resistance value of the first resistor element exceeds the duration of the ESD event, and the control circuit is configured to turn on the main transistor so that the ESD current flows through the main transistor.

[0007] Based on the above, in an embodiment of the disclosure, the product of the capacitance value of the parasitic capacitance of the second control transistor and the resistance value of the first resistor element exceeds the duration of the ESD event. Therefore, the parasitic capacitance and the first resistor element can act as ESD detectors. When an ESD event occurs, the parasitic capacitance and the first resistor element can trigger a control circuit to turn on the main transistor, thereby allowing the ESD current to flow through the main transistor. In this way, the above ESD protection circuit can prevent ESD from damaging the integrated circuit.

[0008] In order to make the aforementioned features and advantages of the present disclosure more obvious and easier to understand, embodiments are given below and described in detail below with reference to the accompanying drawings. Brief explanation of the drawing

[0009] FIG. 1 is a circuit block diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment. FIG. 2 is a circuit block diagram of an ESD protection circuit according to an embodiment of the disclosed content. FIG. 3 is a circuit block diagram of an ESD protection circuit according to another embodiment of the disclosure. FIG. 4 is a circuit block diagram of an ESD protection circuit according to another embodiment of the disclosure. FIG. 5 is a circuit block diagram of an ESD protection circuit according to another embodiment of the disclosure. FIG. 6 is a circuit block diagram of an ESD protection circuit according to another embodiment of the disclosure. FIG. 7 is a circuit block diagram of an ESD protection circuit according to another embodiment of the disclosure. FIG. 8 is a circuit block diagram of an ESD protection circuit (800) according to another embodiment of the disclosure. FIG. 9 is a circuit block diagram of a pull-down circuit according to an embodiment of the disclosed content. Specific details for implementing the invention

[0010] Throughout the specification of the disclosure (including the claims of the disclosure), the term “combination (or connection)” may refer to any direct or indirect means of connection. For example, where a first device is combined (or connected) to a second device, it should be interpreted that the first device may be directly connected to the second device, or that the first device may be indirectly connected to the second device through another device or through some means of connection. Throughout the specification of the disclosure (including the claims), the terms “first” and “second” are used to name elements or to distinguish different elements or ranges, and are not used to limit the upper or lower limit of the number of elements or to limit the order of components. Additionally, whenever possible, elements / components / steps having the same reference number are used in the drawings and examples to indicate identical or similar parts. Elements / components / steps using the same number or the same term in different examples may serve as cross-references to one another.

[0011] FIG. 1 is a circuit block diagram of an electrostatic discharge (ESD) protection circuit (100) according to an embodiment. The ESD protection circuit (100) may be configured within an integrated circuit. The ESD protection circuit (100) illustrated in FIG. 1 is coupled between a voltage terminal (PAD11) and a voltage terminal (PAD12). The voltage terminals (PAD11 and PAD12) may be bonding pads or other types of connection pads. In some applications, the voltage terminal (PAD11) is configured to transmit a system voltage (such as VDD), and the voltage terminal (PAD12) is configured to transmit a reference voltage (such as VSS). In other applications, the voltage terminal (PAD11) is configured to transmit input / output data (or input / output signals) of the integrated circuit.

[0012] The ESD protection circuit (100) illustrated in FIG. 1 includes a resistor (R11), a capacitor (C11), a transistor (M11), a transistor (M12), and a main transistor (B11). A voltage terminal (PAD12) is coupled to a first terminal of the capacitor (C11), a first terminal (e.g., source) of the transistor (M12), and a first terminal (e.g., source) of the main transistor (B11). A voltage terminal (PAD11) is coupled to a first terminal of the resistor (R11), a first terminal (such as source) of the transistor (M11), and a second terminal (such as drain) of the main transistor (B11). The second terminal of the resistor (R11) and the second terminal of the capacitor (C11) are coupled to a control terminal (such as gate) of the transistor (M11) and a control terminal (such as gate) of the transistor (M12). The second terminal (e.g., drain) of transistor (M11) and the second terminal (e.g., drain) of transistor (M12) are connected to the control terminal (e.g., gate) of the main transistor (B11).

[0013] In the normal operation mode of the integrated circuit, the resistor (R11) and capacitor (C11) can provide a high logic voltage to the control terminals of the transistors (M11 and M12), thereby turning on the transistor (M12) and turning off the transistor (M11) and the main transistor (B11). Therefore, the ESD protection circuit (100) will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal (PAD11), the resistor (R11) and capacitor (C11) can provide a low voltage to the control terminals of the transistors (M11 and M12), thereby turning off the transistor (M12) and turning on the transistor (M11) and the main transistor (B11). Under these conditions, the main transistor (B11) can transmit the ESD current from the voltage terminal (PAD11) to the voltage terminal (PAD12). Therefore, the ESD protection circuit (100) can prevent ESD from damaging the integrated circuit. Generally speaking, the capacitor (C11) occupies a large area of ​​the integrated circuit.

[0014] FIG. 2 is a circuit block diagram of an ESD protection circuit (200) according to an embodiment of the present disclosure. The ESD protection circuit (200) may be configured within an integrated circuit. The ESD protection circuit (200) is coupled between a voltage terminal (PAD21) and a voltage terminal (PAD22). The voltage terminals (PAD21 and PAD22) may be bonding pads or other types of connection pads. In some applications, the voltage terminal (PAD21) is configured to transmit a system voltage (such as VDD), and the voltage terminal (PAD22) is configured to transmit a reference voltage (such as VSS). In other applications, the voltage terminal (PAD21) is configured to transmit input / output data (or input / output signals) of the integrated circuit.

[0015] The ESD protection circuit (200) illustrated in FIG. 2 includes a resistor element (R21), a control circuit (210), and a main transistor (B21). The main transistor (B21) illustrated in FIG. 2 is, for example, an N-type transistor, i.e., an N-channel Metal-Oxide-Semiconductor (NMOS) transistor, but this should not be interpreted as a limitation to other embodiments. The resistor element (R21) is, for example, an actual resistor, or another element equivalent to a resistor, such as an active element or an inductor, where the active element is, for example, a metal-oxide-semiconductor (MOS) (which may be N-channel or P-channel type), a field-effect transistor (FET), a bipolar junction transistor (BJT), a heterojunction bipolar transistor (HBT), or a diode. The voltage terminal (PAD22) is coupled to the second terminal of the control circuit (210) and the first terminal (e.g., source) of the main transistor (B21). The voltage terminal (PAD21) is coupled to the first terminal of the resistor element (R21), the first terminal of the control circuit (210), and the second terminal (e.g., drain) of the main transistor (B21). The input terminal of the control circuit (210) is connected to the second terminal of the resistor element (R21). The output terminal of the control circuit (210) is connected to the control terminal (e.g., gate) of the main transistor (B21). When an ESD event occurs, the control circuit (210) can turn on the main transistor (B21) so that the ESD current flows through the main transistor (B21). In this embodiment, the ESD event is, for example, a positive pulse.The ESD current flows, for example, from the voltage terminal (PAD21) through the main transistor (B21) and is conducted to the voltage terminal (PAD22). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD22) through the main transistor (B21) and be conducted to the voltage terminal (PAD21).

[0016] In the embodiment illustrated in FIG. 2, the control circuit (210) includes a control transistor (M21) and a control transistor (M22). The control transistor (M21) illustrated in FIG. 2 is, for example, a P-type transistor, i.e., a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, and the control transistor (M22) is, for example, an N-type transistor, i.e., an N-channel Metal-Oxide-Semiconductor (NMOS) transistor, but this should not be interpreted as a limitation to other embodiments. The sizes of the main transistor (B21), the control transistor (M21), and the control transistor (M22) may be determined according to the actual design. For example, in some applications, the size of the main transistor (B21) is larger than the size of the control transistor (M22). The first terminal (e.g., source) of the control transistor (M21) is coupled to the first terminal of the control circuit (210). The control terminal (e.g., gate) of the control transistor (M21) is connected to the input terminal of the control circuit (210). The first terminal (e.g., source) of the control transistor (M22) is connected to the second terminal of the control circuit (210). The second terminal (e.g., drain) of the control transistor (M22) is connected to the second terminal (e.g., drain) of the control transistor (M21). The control terminal (e.g., gate) of the control transistor (M22) is connected to the input terminal of the control circuit (210). The second terminals of the control transistors (M22 and M21) are connected to the output terminal of the control circuit (210).

[0017] In the normal operating mode of the integrated circuit, the resistor element (R21) can provide a high logic voltage to the control terminals of the control transistors (M22 and M21), thereby turning on the control transistor (M22) and turning off the control transistor (M21) and the main transistor (B21). Therefore, the ESD protection circuit (200) will not affect the normal operation of the integrated circuit. When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal (PAD21), the product of the capacitance value of the parasitic capacitance (Cgs) of the control transistor (M22) (effective capacitance between the gate and source) and the resistance value of the resistor element (R21) exceeds the duration of the ESD event, and the parasitic capacitance (Cgs) of the resistor element (R21) and the control transistor (M22) can provide a low voltage to the control terminals of the control transistors (M22 and M21), thereby turning off the control transistor (M22) and turning on the control transistor (M21) and the main transistor (B21) (the potential at the output terminal of the control circuit (210) is a high potential). Under this condition, the main transistor (B21) can transmit the ESD current of the voltage terminal (PAD21) to the voltage terminal (PAD22). Therefore, the ESD protection circuit (200) can prevent ESD from damaging the integrated circuit. Compared to the embodiment shown in FIG. 1, the capacitor (C11) can be omitted to save the area of ​​the integrated circuit. Additionally, the resistance value of the resistor element (R21) may be the equivalent resistance value of the resistor element (R21) when an ESD event occurs.

[0018] FIG. 3 is a circuit block diagram of an ESD protection circuit (300) according to another embodiment of the present disclosure. References to the voltage terminal (PAD31), voltage terminal (PAD32), and ESD protection circuit (300) shown in FIG. 3 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (300) shown in FIG. 3 includes a resistor element (R31), a control circuit (310), and a main transistor (B31). The main transistor (B31) shown in FIG. 3 is, for example, a P-type transistor, i.e., a PMOS transistor, but this should not be interpreted as a limitation to other embodiments. References to the resistor element (R31), control circuit (310), and main transistor (B31) illustrated in FIG. 3 may be derived from the related description of the resistor element (R21), control circuit (210), and main transistor (B21) illustrated in FIG. 2 and derived by analogy. When an ESD event occurs, the control circuit (310) may turn on the main transistor (B31) so that the ESD current flows through the main transistor (B31). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows from the voltage terminal (PAD31) through the main transistor (B31) and is conducted to the voltage terminal (PAD32). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current may also flow from the voltage terminal (PAD32) through the main transistor (B31) and be conducted to the voltage terminal (PAD31).

[0019] In the embodiment illustrated in FIG. 3, the control circuit (310) includes a control transistor (M31) and a control transistor (M32). The control transistor (M32) illustrated in FIG. 3 is a P-type transistor, for example, a PMOS transistor. The control transistor (M31) is an N-type transistor, for example, an NMOS transistor, but this should not be interpreted as a limitation to other embodiments. The sizes of the main transistor (B31), the control transistor (M32), and the control transistor (M31) can be determined according to the actual design. For example, in some applications, the size of the main transistor (B31) is larger than the size of the control transistor (M32). The first terminal (e.g., drain) of the control transistor (M31) is coupled to the first terminal of the control circuit (310). The control terminal (e.g., gate) of the control transistor (M31) is coupled to the input terminal of the control circuit (310). The first terminal (e.g., drain) of the control transistor (M32) is connected to the second terminal of the control circuit (310). The second terminal (e.g., source) of the control transistor (M32) is connected to the second terminal (e.g., source) of the control transistor (M31). The control terminal (e.g., gate) of the control transistor (M32) is connected to the input terminal of the control circuit (310). The second terminals of the control transistors (M32 and M31) are connected to the output terminal of the control circuit (310).

[0020] In the normal operating mode of the integrated circuit, the resistor element (R31) can provide a high logic voltage to the control terminals of the control transistors (M31 and M32), thereby turning on the control transistor (M31) and turning off the control transistor (M32) and the main transistor (B31). Therefore, the ESD protection circuit (300) will not affect the normal operation of the integrated circuit. When an ESD event (e.g., a positive pulse) occurs at the voltage terminal (PAD31), the product of the capacitance value of the parasitic capacitance (Cgd) of the control transistor (M32) (effective capacitance between the gate and source) and the resistance value of the resistor element (R31) exceeds the duration of the ESD event, and the parasitic capacitance (Cgd) of the resistor element (R31) and the control transistor (M32) can provide a low voltage to the control terminals of the control transistors (M31 and M32), thereby turning off the control transistor (M31) and turning on the control transistor (M32) and the main transistor (B31) (the potential at the output terminal of the control circuit (310) is a low potential). Under this condition, the main transistor (B31) can transmit the ESD current of the voltage terminal (PAD31) to the voltage terminal (PAD32). Therefore, the ESD protection circuit (300) can prevent ESD from damaging the integrated circuit, and the capacitor (C11) can also be omitted to save the area of ​​the integrated circuit. Additionally, the resistance value of the resistor element (R31) may be the equivalent resistance value of the resistor element (R31) when an ESD event occurs.

[0021] FIG. 4 is a circuit block diagram of an ESD protection circuit (400) according to another embodiment of the present disclosure. References to the voltage terminal (PAD41), voltage terminal (PAD42), and ESD protection circuit (400) shown in FIG. 4 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (400) shown in FIG. 4 includes a resistor element (R41), a control circuit (410), and a main transistor (B41). References to the resistor element (R41), control circuit (410), and main transistor (B41) shown in FIG. 4 may be derived from the related description of the resistor element (R21), control circuit (210), and main transistor (B21) shown in FIG. 2 and derived by analogy. When an ESD event occurs, the control circuit (410) can turn on the main transistor (B41) so that the ESD current flows through the main transistor (B41). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows, for example, from the voltage terminal (PAD41) through the main transistor (B41) and is conducted to the voltage terminal (PAD42). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD42) through the main transistor (B41) and be conducted to the voltage terminal (PAD41).

[0022] In the embodiment illustrated in FIG. 4, the control circuit (410) includes a control transistor (M41), a control transistor (M42), a control transistor (M45), and a control transistor (M46). The main transistor (B41) illustrated in FIG. 4 is a P-type transistor, for example, a PMOS transistor. The control transistors (M41 and M45) are P-type transistors, for example, PMOS transistors. The control transistors (M42 and M46) are N-type transistors, for example, NMOS transistors, but this should not be interpreted as a limitation to other embodiments. The sizes of the main transistor (B41), the control transistor (M41), the control transistor (M42), the control transistor (M45), and the control transistor (M46) may be determined according to the actual design. For example, in some applications, the size of the main transistor (B41) is larger than the size of the control transistor (M45). The first terminal (e.g., source) of the control transistor (M41) and the first terminal (e.g., source) of the control transistor (M45) are connected to the first terminal of the control circuit (410). The control terminal (e.g., gate) of the control transistor (M41) and the control terminal (e.g., gate) of the control transistor (M42) are connected to the input terminal of the control circuit (410). The first terminal (e.g., source) of the control transistor (M42) and the first terminal (e.g., source) of the control transistor (M46) are connected to the second terminal of the control circuit (410). The second terminal (e.g., drain) of the control transistor (M42) and the second terminal (e.g., drain) of the control transistor (M41) are connected to the control terminal (e.g., gate) of the control transistor (M46) and the control terminal (e.g., gate) of the control transistor (M45). The second terminal of the control transistor (M45 and M46) is connected to the output terminal of the control circuit (410).

[0023] In the normal operating mode of the integrated circuit, the resistor element (R41) can provide a high logic voltage to the control terminals of the control transistors (M42 and M41), thereby turning on the control transistors (M42 and M45) and turning off the control transistor (M41), the control transistor (M46), and the main transistor (B41). In this way, the ESD protection circuit (400) will not affect the normal operation of the integrated circuit. When an ESD event (e.g., a positive pulse) occurs at the voltage terminal (PAD41), the product of the capacitance value of the parasitic capacitance (Cgs) (effective capacitance between the gate and source) of the control transistor (M42) and the resistance value of the resistor element (R41) exceeds the duration of the ESD event, and the resistor element (R41) and the parasitic capacitance (Cgs) of the control transistor (M42) can provide a low voltage to the control terminals of the control transistors (M42 and M41), thereby turning off the control transistors (M42 and M45) and turning on the control transistor (M41), the control transistor (M46), and the main transistor (B41) (so that the potential at the second terminal of the control transistors (M41 and M42) is a high potential, so that the potential at the output terminal of the control circuit (410) becomes a low potential). Under these conditions, the main transistor (B41) can transmit the ESD current from the voltage terminal (PAD41) to the voltage terminal (PAD42). Therefore, the ESD protection circuit (400) can prevent ESD from damaging the integrated circuit, and the capacitor (C11) can be omitted to save the area of ​​the integrated circuit. Additionally, the resistance value of the resistor element (R41) may be the equivalent resistance value of the resistor element (R41) when an ESD event occurs.

[0024] FIG. 5 is a circuit block diagram of an ESD protection circuit (500) according to another embodiment of the present disclosure. References to the voltage terminal (PAD51), voltage terminal (PAD52), and ESD protection circuit (500) shown in FIG. 5 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (500) shown in FIG. 5 includes a resistor element (R51), a control circuit (510), and a main transistor (B51). The control circuit (510) includes a control transistor (M51) and a control transistor (M52). References to the resistor element (R51), control circuit (510), control transistor (M51), control transistor (M52), and main transistor (B51) illustrated in FIG. 5 may be derived from the related description of the resistor element (R21), control circuit (210), control transistor (M21), control transistor (M22), and main transistor (B21) illustrated in FIG. 2 and derived by analogy, and thus, details will not be described again. When an ESD event occurs, the control circuit (510) can turn on the main transistor (B51) so that the ESD current flows through the main transistor (B51). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows from the voltage terminal (PAD51) through the main transistor (B51) and is conducted to the voltage terminal (PAD52). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD52) through the main transistor (B51) and be conducted to the voltage terminal (PAD51).

[0025] Unlike the embodiment illustrated in FIG. 2, the ESD protection circuit (500) illustrated in FIG. 5 further includes a resistor element (R52). The first terminal of the resistor element (R52) is connected to the control terminal of the main transistor (B51). The second terminal of the resistor element (R52) is connected to the voltage terminal (PAD52). In normal operation mode, during the initialization phase of the integrated circuit, the system voltage from the voltage terminal (PAD51) gradually rises but may not reach the voltage required to turn on the control transistor (M52), so the control transistor (M52) cannot be turned on, thereby allowing the potential at the output terminal of the control circuit (510) to become a high potential. Under these conditions, there is a very high probability that the main transistor (B51) will be accidentally turned on (corresponding to the embodiment of FIG. 2, in normal operating mode, the output terminal of the control circuit (210) must be at a low potential to turn off the main transistor (B21); adding a resistor element (R52) may allow the output terminal of the control circuit (510) to be maintained at a low potential in normal operating mode, thereby preventing the main transistor (B51) from being accidentally turned on. The resistance value of the resistor element (R52) may be set according to the actual design. For example, in some applications, the resistance value of the resistor element (R52) is 10 KΩ or more and 10 MΩ or less. In a preferred embodiment, the resistor element (R52) is 5 MΩ or less. Furthermore, when an ESD event occurs, if the resistance value of the resistor element (R52) is less than 10 KΩ, the potential at the output terminal of the control circuit (510) may be zero, and the main transistor (B51) cannot be turned on (correspondingly, referring to the embodiment of FIG. 2, when an ESD event occurs, the output terminal of the control circuit (210) must be at a high potential to turn on the main transistor (B21)).In normal operating mode, when the resistance value of the resistor element (R52) exceeds 10 MΩ, the output terminal of the control circuit (510) may be floating, that is, the resistor element (R52) may not function. Based on the related description of the resistor element (R52) shown in FIG. 5, the resistor element (R52) may be similarly configured in the ESD protection circuit shown in FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 6, FIG. 7, FIG. 8, or FIG. 9.

[0026] FIG. 6 is a circuit block diagram of an ESD protection circuit (600) according to another embodiment of the present disclosure. References to the voltage terminal (PAD61), voltage terminal (PAD62), and ESD protection circuit (600) shown in FIG. 6 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (600) shown in FIG. 6 includes a resistor element (R61), a control circuit (610), and a main transistor (B61). The control circuit (610) includes a control transistor (M61) and a control transistor (M62). References to the resistor element (R61), control circuit (610), control transistor (M61), control transistor (M62), and main transistor (B61) illustrated in FIG. 6 may be derived from the related description of the resistor element (R21), control circuit (210), control transistor (M21), control transistor (M22), and main transistor (B21) illustrated in FIG. 2 and derived by analogy, and thus, details will not be described again. When an ESD event occurs, the control circuit (610) may turn on the main transistor (B51) so that the ESD current flows through the main transistor (B61). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows from the voltage terminal (PAD61) through the main transistor (B61) and is conducted to the voltage terminal (PAD62). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD62) through the main transistor (B61) and be conducted to the voltage terminal (PAD61).

[0027] Unlike the embodiment illustrated in FIG. 2, the ESD protection circuit (600) illustrated in FIG. 6 further includes a pull-down circuit (620). The pull-down circuit (620) is coupled between the input terminal (A6), the voltage terminal (PAD61), and the voltage terminal (PAD62) of the control circuit (610). That is, the pull-down circuit (620) is coupled between the first terminal and the second terminal of the resistor element (R61). When an ESD event occurs, the pull-down circuit (620) can pull down the potential at the input terminal (A6) of the control circuit (610) and maintain that potential at a low potential. The ESD energy from the voltage terminal (PAD61) is gradually discharged, and when the potential difference between the input terminal (A6) of the control circuit (610) and the voltage terminal (PAD61) is lower than the threshold voltage, it means that the ESD event has ended and the normal operating mode can be restored. The pull-down circuit (620) can change the potential at the input terminal (A6) of the control circuit (610) from a low potential to a high potential in order to turn off the main transistor (B61). Thus, in this embodiment, the ESD protection circuit (600) uses the pull-down circuit (620) to assist in pulling down the current during an ESD event, so that the potential at the input terminal (A6) of the control circuit (610) is pulled down and maintained at a low potential, thereby successfully turning on the main transistor (B61) during an ESD event, making it possible to more effectively prevent ESD from damaging the integrated circuit.

[0028] FIG. 7 is a circuit block diagram of an ESD protection circuit (700) according to another embodiment of the present disclosure. References to the voltage terminal (PAD71), voltage terminal (PAD72), and ESD protection circuit (700) shown in FIG. 7 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (700) shown in FIG. 7 includes a resistor element (R71), a control circuit (710), and a main transistor (B71). The control circuit (710) includes a control transistor (M71) and a control transistor (M72). References to the resistor element (R71), control circuit (710), control transistor (M71), control transistor (M72), and main transistor (B71) illustrated in FIG. 7 may be derived from the description of the resistor element (R31), control circuit (310), control transistor (M31), control transistor (M32), and main transistor (B31) illustrated in FIG. 3 and derived by analogy, and no further description will be given. When an ESD event occurs, the control circuit (710) can turn on the main transistor (B71) so that the ESD current flows through the main transistor (B71). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows from the voltage terminal (PAD71) through the main transistor (B71) and is conducted to the voltage terminal (PAD72). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD72) through the main transistor (B71) and be conducted to the voltage terminal (PAD71).

[0029] Unlike the embodiment illustrated in FIG. 3, the ESD protection circuit (700) illustrated in FIG. 7 further includes a pull-down circuit (720). The pull-down circuit (720) is coupled between the input terminal (A7), the voltage terminal (PAD71), and the voltage terminal (PAD72) of the control circuit (710). That is, the pull-down circuit (720) is coupled between the first terminal and the second terminal of the resistor element (R71). When an ESD event occurs, the pull-down circuit (720) can pull down the potential at the input terminal (A7) of the control circuit (710) and maintain that potential at a low potential. The ESD energy from the voltage terminal (PAD71) is gradually discharged, and when the potential difference between the input terminal (A7) of the control circuit (710) and the voltage terminal (PAD71) is lower than the threshold voltage, it means that the ESD event has ended and the normal operating mode can be restored. The pull-down circuit (720) can change the potential at the input terminal (A7) of the control circuit (710) from a low potential to a high potential in order to turn off the main transistor (B71). Thus, in this embodiment, the ESD protection circuit (700) uses the pull-down circuit (720) to assist in pulling down the current during an ESD event, so that the potential at the input terminal (A7) of the control circuit (710) is pulled down and maintained at a low potential, thereby successfully turning on the main transistor (B71) during an ESD event, making it possible to more effectively prevent ESD from damaging the integrated circuit.

[0030] FIG. 8 is a circuit block diagram of an ESD protection circuit (800) according to another embodiment of the disclosure. References to the voltage terminal (PAD81), voltage terminal (PAD82), and ESD protection circuit (800) shown in FIG. 8 may be derived from the related description of the voltage terminal (PAD21), voltage terminal (PAD22), and ESD protection circuit (200) shown in FIG. 2 and derived by analogy. The ESD protection circuit (800) shown in FIG. 8 includes a resistor element (R81), a control circuit (810), and a main transistor (B81). The control circuit (810) includes a control transistor (M81), a control transistor (M82), a control transistor (M85), and a control transistor (M86). References to the resistor element (R81), control circuit (810), control transistor (M81), control transistor (M82), control transistor (M85), control transistor (M86), and main transistor (B81) illustrated in FIG. 8 may be derived from the description of the resistor element (R41), control circuit (410), control transistor (M41), control transistor (M42), control transistor (M45), control transistor (M46), and main transistor (B41) illustrated in FIG. 4 and derived by analogy, and no further description will be given. When an ESD event occurs, the control circuit (810) can turn on the main transistor (B81) so that the ESD current flows through the main transistor (B71). In this embodiment, the ESD event is, for example, a positive pulse. The ESD current flows, for example, from the voltage terminal (PAD81) through the main transistor (B81) and is conducted to the voltage terminal (PAD82). In another embodiment, the ESD event is, for example, a negative pulse. The ESD current can also flow from the voltage terminal (PAD82) through the main transistor (B81) and be conducted to the voltage terminal (PAD81).

[0031] Unlike the embodiment illustrated in FIG. 4, the ESD protection circuit (800) illustrated in FIG. 8 further includes a pull-down circuit (820). The pull-down circuit (820) is coupled between the input terminal (A8), the voltage terminal (PAD81), and the voltage terminal (PAD82) of the control circuit (810). That is, the pull-down circuit (820) is coupled between the first terminal and the second terminal of the resistor element (R81). When an ESD event occurs, the pull-down circuit (820) can pull down the potential at the input terminal (A8) of the control circuit (810) and maintain that potential at a low potential. The ESD energy from the voltage terminal (PAD81) is gradually discharged, and when the potential difference between the input terminal (A8) of the control circuit (810) and the voltage terminal (PAD81) is lower than the threshold voltage, it means that the ESD event has ended and the normal operating mode can be restored. The pull-down circuit (820) can change the potential at the input terminal (A8) of the control circuit (810) from a low potential to a high potential in order to turn off the main transistor (B81). Thus, in this embodiment, the ESD protection circuit (800) uses the pull-down circuit (820) to assist in pulling down the current during an ESD event, so that the potential at the input terminal (A8) of the control circuit (810) is pulled down and maintained at a low potential, thereby successfully turning on the main transistor (B81) during an ESD event, making it possible to more effectively prevent ESD from damaging the integrated circuit.

[0032] FIG. 9 is a circuit block diagram of a pull-down circuit (920) according to an embodiment of the disclosed content. For further explanation, FIG. 9 illustrates a voltage terminal (PAD91), a voltage terminal (PAD92), a resistor element (R91), a control circuit (910), a pull-down circuit (920), and a main transistor (B91). References to the voltage terminal (PAD91), voltage terminal (PAD92), resistor element (R91), control circuit (910) (including control transistor (M91) and control transistor (M92)), pull-down circuit (920), and main transistor (B91) illustrated in FIG. 9 may be derived from the related description of the voltage terminal (PAD61), voltage terminal (PAD62), resistor element (R61), control circuit (610), pull-down circuit (620), and main transistor (B61) illustrated in FIG. 6 and derived by analogy, or from the related description of the voltage terminal (PAD71), voltage terminal (PAD72), resistor element (R71), control circuit (710), pull-down circuit (720), and main transistor (B71) illustrated in FIG. 7 and derived by analogy, or from the voltage terminal (PAD81), voltage element (R71), control circuit (710), pull-down circuit (720), and main transistor (B71) illustrated in FIG. 8 and derived by analogy. It can be derived from the related description of the terminal (PAD82), resistor element (R81), control circuit (810), pull-down circuit (820), and main transistor (B81). The pull-down circuit (920) shown in FIG. 9 can serve as one of a plurality of embodiments of the pull-down circuit (620) shown in FIG. 6, or one of a plurality of embodiments of the pull-down circuit (720) shown in FIG. 7, or one of a plurality of embodiments of the pull-down circuit (820) shown in FIG. 8.

[0033] In the embodiment illustrated in FIG. 9, the pull-down circuit (920) comprises a control transistor (M93), a control transistor (M94), and a resistor element (R92). The resistor element (R92) may be, for example, an actual resistor, or other elements equivalent to a resistor, such as an active element or an inductor, wherein the active element is, for example, a metal-oxide-semiconductor (which may be N-channel or P-channel type) transistor, a field-effect transistor, a bipolar junction transistor, a heterojunction bipolar transistor, or a diode. The control transistor (M93) illustrated in FIG. 9 is a P-type transistor, which is a PMOS transistor, and the control transistor (M94) is an N-type transistor, which is an NMOS transistor, but this should not be interpreted as a limitation to the disclosure. The first terminal (e.g., source) of the control transistor (M93) is coupled to the first terminal of the resistor element (R91). The control terminal (e.g., gate) of the control transistor (M93) is connected to the input terminal (A9) of the control circuit (910). The first terminal (e.g., source) of the control transistor (M94) is connected to the voltage terminal (PAD92). The second terminal (e.g., drain) of the control transistor (M94) is connected to the input terminal (A9) of the control circuit (910). The control terminal (e.g., gate) of the control transistor (M94) is connected to the second terminal (e.g., drain) of the control transistor (M93). The first terminal of the resistor element (R92) is connected to the second terminal of the control transistor (M93) and the control terminal of the control transistor (M94). The second terminal of the resistor element (R92) is connected to the voltage terminal (PAD92).Additionally, the pull-down circuits (620, 720, and 820) illustrated in FIGS. 6, 7, and 8 are each coupled to voltage terminals (PAD62, PAD72, and PAD82) through nodes, but it should be noted that this example merely illustrates that the pull-down circuits (620, 720, and 820) each have a coupling relationship with the voltage terminals (PAD62, PAD72, and PAD82), and the coupling method is not limited to only one node. FIG. 9 further illustrates an amplifying element of the pull-down circuit (920), and an exemplary coupling relationship between the pull-down circuit (920) and the voltage terminal (PAD92). In the exemplary coupling relationship, the resistor element (R92) and the control transistor (M94) are each coupled to the voltage terminal (PAD92) through two nodes. This combination method can be applied to the embodiments of FIGS. 6, FIGS. 7, and FIGS. 8.

[0034] In the normal operating mode of the integrated circuit, the potential difference between the input terminal (A9) and the voltage terminal (PAD91) of the control circuit (910) is significantly small (lower than the threshold voltage or even zero), so the control transistor (M93) is turned off. When the control transistor (M93) is turned off, the resistor element (R92) can pull down the control terminal voltage of the control transistor (M94) to a low logic level, so the control transistor (M94) is turned off. Under this condition, the pull-down circuit (920) will not affect the input terminal (A9) of the control circuit (910).

[0035] When an ESD event (taking a positive pulse as an example) occurs at the voltage terminal (PAD91), the parasitic capacitance (Cgs) of the resistor element (R21) and the control transistor (M92) can provide a low voltage to the input terminal (A9) of the control circuit (910), thereby turning on the control transistor (M93), that is, under this condition, the potential difference between the first terminal of the control transistor (M93) and the input terminal (A9) of the control circuit (910) exceeds the voltage required to turn on the control transistor (M93). When the control transistor (M93) is turned on, the control transistor (M93) can pull up the control terminal voltage of the control transistor (M94) to a high logic level, so that the control transistor (M94) is turned on. The turned-on control transistor (M94) can pull down and maintain the potential at the input terminal (A9) of the control circuit (910) to a low potential, for example, the potential is pulled down to zero. Under these conditions, the main transistor (B91) can act as a small resistor when turned on. When an ESD current flows, the ESD voltage generated at the voltage terminal (PAD91) can be pulled down and fixed at a clamping voltage. When the potential difference between the input terminal (A9) of the control circuit (910) and the voltage terminal (PAD91) is lower than the threshold voltage of the control transistor (M93), it means that the ESD event has ended and the normal operating mode can be restored. Since the control transistors (M93 and M94) are turned off, the pull-down circuit (920) can change the potential at the input terminal (A9) of the control circuit (910) from a low potential to a high potential in order to turn off the main transistor (B91).

[0036] The resistance value of the resistor element (R92) can be set according to the actual design. For example, in some application examples, the resistance value of the resistor element (R92) is 10 Ω or more and 10 MΩ or less. In a preferred embodiment, the resistance value of the resistor element (R92) is 5 MΩ or less. Furthermore, when an ESD event occurs, if the resistance value of the resistor element (R92) is less than 10 Ω, the potential at the node (N9) between the first terminal of the resistor element (R92), the second terminal of the control transistor (M93), and the control terminal of the control transistor (M94) may be zero, and as a result, the control transistor (M94) cannot be turned on, and the potential at the input terminal (A9) of the control circuit (910) cannot be pulled down and maintained at a low potential. In normal operating mode, when the resistance value of the resistor element (R92) exceeds 10 MΩ, the node (N9) may be floating. As a result, the resistor element (R92) may be coupled with other nearby traces, and therefore, the pull-down circuit (920) is highly likely to be affected by signals on other traces, which is undesirable. Additionally, the resistance value of the resistor element (R92) may be the equivalent resistance value of the resistor element (R92).

[0037] According to the above, in this embodiment, the control transistor (M93), control transistor (M94), and resistor element (R92) of the pull-down circuit (920) are configured to assist in pulling the current during an ESD event, so that the potential at the input terminal (A9) of the control circuit (910) is pulled down and maintained at a low potential, allowing the main transistor (B81) to be successfully turned on during an ESD event, thereby making it more effective to prevent the ESD from damaging the integrated circuit. The control transistor (M93) and the control transistor (M94) are active elements and can be controlled by voltage. Compared to the capacitor (C11) used in the embodiment of FIG. 1, the control transistor (M93) and the control transistor (M94) pull down the potential at the input terminal (A9) of the control circuit (910) more quickly. Additionally, in some embodiments, the resistor element (R92) may also be an active element, and the speed of pulling down the potential at the input terminal (A9) of the control circuit (910) may be further accelerated through voltage control. Therefore, when the pull-down circuit (920) is adopted in the embodiments of FIGS. 6, 7, and 8, the ESD protection circuits (600, 700, and 800) can be operated more quickly and effectively.

[0038] In summary, in the above-described embodiment, since the product of the capacitance value of the parasitic capacitance (such as Cgs or Cgd) and the resistance value of the resistor element (such as R21, R31, R41, R51, R61, R71, R81, or R91) exceeds the duration of the ESD event, the parasitic capacitance and the resistor element can function as ESD detectors. When an ESD event occurs, the parasitic capacitance and resistor elements can trigger a control circuit (such as 210, 310, 410, 510, 610, 710, 810, or 910) to turn on the main transistor (such as B21, B31, B41, B51, B61, B71, B81, or B91), so that the ESD current is transmitted between a first voltage terminal (such as PAD21, PAD31, PAD41, PAD51, PAD61, PAD71, PAD81, or PAD91) and a second voltage terminal (such as PAD22, PAD32, PAD42, PAD52, PAD62, PAD72, PAD82, or PAD92). Therefore, the ESD protection circuit of the above embodiment can prevent ESD from damaging the integrated circuit. In addition, since the above embodiment utilizes parasitic capacitance to replace large capacitance, it is possible to save the area of ​​the integrated circuit.

[0039] Although the present disclosure is disclosed above through embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope to be protected by the present disclosure will be determined by the appended claims.

Claims

Claim 1 An electrostatic discharge protection circuit coupled between a first voltage terminal and a second voltage terminal, comprising: a main transistor having a first terminal, a second terminal, and a control terminal—the first terminal of the main transistor is coupled to the second voltage terminal, and the second terminal of the main transistor is coupled to the first voltage terminal—; a first resistor element having a first terminal and a second terminal—the first terminal of the first resistor element is coupled to the first voltage terminal—; a control circuit having a first terminal, a second terminal, an input terminal, and an output terminal—the first terminal of the control circuit is coupled to the first voltage terminal, the second terminal of the control circuit is coupled to the second voltage terminal, the input terminal of the control circuit is coupled to the second terminal of the first resistor element, and the output terminal of the control circuit is coupled to the control terminal of the main transistor—; and a pull-down circuit coupled between the input terminal, the first voltage terminal, and the second voltage terminal of the control circuit, wherein the control circuit comprises a first control transistor having a first terminal, a second terminal, and a control terminal - the first terminal of the first control transistor is coupled to the first terminal of the control circuit, and the control terminal of the first control transistor is coupled to the input terminal of the control circuit -;An electrostatic discharge protection circuit comprising: a second control transistor having a first terminal, a second terminal, and a control terminal— wherein the first terminal of the second control transistor is coupled to the second terminal of the control circuit, the second terminal of the second control transistor is coupled to the second terminal of the first control transistor, and the control terminal of the second control transistor is coupled to the input terminal of the control circuit—and, when an electrostatic discharge event occurs, the product of the capacitance value of the parasitic capacitance of the second control transistor and the resistance value of the first resistor element exceeds the duration of the electrostatic discharge event, and the control circuit is configured to turn on the main transistor so that an electrostatic discharge current flows through the main transistor, and when the electrostatic discharge event occurs, the potential at the input terminal of the control circuit is low. Claim 2 In claim 1, the electrostatic discharge protection circuit, wherein the main transistor is an N-type transistor and the size of the main transistor is larger than the size of the second control transistor. Claim 3 An electrostatic discharge protection circuit according to paragraph 2, wherein when the electrostatic discharge event occurs, the first control transistor is turned on and the second control transistor is turned off, and the potential at the output terminal of the control circuit is high to turn on the main transistor. Claim 4 In paragraph 3, the electrostatic discharge protection circuit, wherein the first control transistor is a P-type transistor and the second control transistor is an N-type transistor. Claim 5 In claim 1, the electrostatic discharge protection circuit, wherein the main transistor is a P-type transistor and the size of the main transistor is larger than the size of the second control transistor. Claim 6 An electrostatic discharge protection circuit according to claim 5, wherein when the electrostatic discharge event occurs, the first control transistor is turned off, the second control transistor is turned on, and the potential at the output terminal of the control circuit is low to turn on the main transistor. Claim 7 In claim 6, the electrostatic discharge protection circuit, wherein the first control transistor is an N-type transistor and the second control transistor is a P-type transistor. Claim 8 An electrostatic discharge protection circuit according to claim 1, wherein when the potential difference between the input terminal of the control circuit and the first voltage terminal is lower than the threshold voltage, the potential at the input terminal of the control circuit changes from low to high to turn off the main transistor. Claim 9 In claim 1, the pull-down circuit is an electrostatic discharge protection circuit coupled to the first terminal and the second terminal of the first resistor element. Claim 10 In claim 1, the pull-down circuit comprises: a third control transistor - the first terminal of the third control transistor is coupled to the first terminal of the first resistor element, and the control terminal of the third control transistor is coupled to the input terminal of the control circuit -; and a fourth control transistor - the first terminal of the fourth control transistor is coupled to the second voltage terminal, the second terminal of the fourth control transistor is coupled to the input terminal of the control circuit, and the control terminal of the fourth control transistor is coupled to the second terminal of the third control transistor - an electrostatic discharge protection circuit. Claim 11 In claim 10, the pull-down circuit further comprises a second resistor element, wherein the first terminal of the second resistor element is coupled to the second terminal of the third control transistor and the control terminal of the fourth control transistor, and the second terminal of the second resistor element is coupled to the second voltage terminal, an electrostatic discharge protection circuit. Claim 12 An electrostatic discharge protection circuit according to claim 11, wherein the resistance value of the second resistor element is 10 Ω or more and 10 MΩ or less. Claim 13 An electrostatic discharge protection circuit according to claim 10, wherein when the electrostatic discharge event occurs, the third control transistor is turned on and the fourth control transistor is turned on so that the potential at the input terminal of the control circuit is maintained at low. Claim 14 In paragraph 13, the electrostatic discharge protection circuit, wherein the third control transistor is a P-type transistor and the fourth control transistor is an N-type transistor. Claim 15 In claim 1, the electrostatic discharge protection circuit further comprises a third resistor element, wherein the first terminal of the third resistor element is coupled to the control terminal of the main transistor and the second terminal of the third resistor element is coupled to the second voltage terminal. Claim 16 An electrostatic discharge protection circuit according to claim 15, wherein the resistance value of the third resistor element is 10 KΩ or more and 10 MΩ or less. Claim 17 The electrostatic discharge protection circuit according to claim 1, wherein the control circuit further comprises: a fifth control transistor having a first terminal, a second terminal, and a control terminal—the first terminal of the fifth control transistor is coupled to the first terminal of the control circuit, the second terminal of the fifth control transistor is coupled to the output terminal of the control circuit, and the control terminal of the fifth control transistor is coupled to the second terminal of the first control transistor—; and a sixth control transistor having a first terminal, a second terminal, and a control terminal—the first terminal of the sixth control transistor is coupled to the second terminal of the control circuit, the second terminal of the sixth control transistor is coupled to the second terminal of the fifth control transistor, and the control terminal of the sixth control transistor is coupled to the second terminal of the second control transistor. Claim 18 In claim 17, when the electrostatic discharge event occurs, the first control transistor is turned on, the second control transistor is turned off, the fifth control transistor is turned off, the sixth control transistor is turned on, the potential at the second terminal of the first control transistor and the potential at the second terminal of the second control transistor are high potential, and the potential at the output terminal of the control circuit is low to turn on the main transistor, an electrostatic discharge protection circuit. Claim 19 An electrostatic discharge protection circuit according to claim 18, wherein the main transistor is a P-type transistor, the size of the main transistor is larger than the size of the first control transistor, the first control transistor and the fifth control transistor are P-type transistors, and the second control transistor and the sixth control transistor are N-type transistors. Claim 20 delete

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