Address decoding method, and memory controller and semiconductor memory system using the same

Abstract

A semiconductor memory system may include a memory controller that generates and provides an offset address for the first address based on a second address when the first address in the first bank corresponding to a first request scheduled in the first bank is within an offset range based on a second address corresponding to a second request scheduled in the first bank immediately before the first request, and a memory device that receives the first address from the memory controller and generates the first address by adding the offset address to the second address. The memory device may include a plurality of banks, and the first bank may be one of the plurality of banks.

Description

Technology Field

[0001] The disclosed content relates to an address decoding method, and a memory controller and a semiconductor memory system using the same. Background Technology

[0002] The bandwidth and operating frequency of semiconductor memory devices are continuously increasing. As the operating frequency increases, standby power, which is proportional to the frequency, is also increasing. Therefore, technology for semiconductor memory devices is required to reduce standby power. The problem to be solved

[0003] We aim to provide technology regarding a semiconductor memory device capable of low-power operation by reducing standby power. means of solving the problem

[0004] A semiconductor memory system according to one feature of the invention may include a memory controller that generates and provides an offset address for a first bank and a command indicating said offset address in response to a first request, and a plurality of banks, and for the first bank among the plurality of banks, a memory device that generates a first address by adding said offset address and a base address for the first bank according to said command, and performs a memory operation according to said command at the first address of the first bank.

[0005] The memory controller generates an offset address for the first address based on the second address when the first address in the first bank corresponding to the first request scheduled in the first bank is within an offset range based on the second address corresponding to the second request scheduled in the first bank immediately before the first request, and the base address may be the second address.

[0006] The above command may include at least one of: an Offset-Activate command that directs an activation operation using the offset address and includes a command separator, a bank address, and an offset; an Offset-Read command that directs a read operation using the offset address and includes a command separator, a bank address, and an offset; and an Offset-Write command that directs a write operation using the offset address and includes a command separator, a bank address, and an offset.

[0007] The offset of the above Offset-Activate command is an offset row address, and the offsets of the above Offset-Read command and the above Offset-Write command, respectively, may be offset column addresses.

[0008] The above command may include at least one of an Offset-Activate command that directs an activation operation using the offset address and includes a command separator and a bank address, an Offset-Read command that directs a read operation using the offset address and includes a command separator and , an Offset-Write command that directs a write operation using the offset address and includes a command separator and a bank address, and a Set-Offset command that includes a command separator, a bank address, and an offset.

[0009] The offset of the above Set-Offset command may be a fixed value corresponding to the offset address.

[0010] The memory device may include an address decoder that decodes the command to identify the offset address for the first bank and adds the second address and the offset address to generate the first address.

[0011] The address decoder may include an address table storing a base row address and a base column address for the last driven memory row and memory column for each of the plurality of banks, a row / column selector providing one of a base row address or a base column address corresponding to the first bank from the address table, and an address summer that generates the first address by adding the offset address and one of the base row address and the base column address provided from the row / column selector.

[0012] If the above command indicates an offset row address, the row / column selector provides the base row address to the address summerator, and the address summerator can generate the first address by adding the base row address and the offset address.

[0013] If the above command indicates an offset column address, the row / column selector provides the base column address to the address summerator, and the address summerator can generate the first address by adding the base column address and the offset address.

[0014] The above address decoder may further include an address demultiplexer that updates the first address to one of the base row address and base column address corresponding to the first bank in the address table.

[0015] The above address decoder may further include an address multiplexer that outputs the first address provided by the address summerator when the first address is within an offset range based on the second address, and outputs the first address provided by the memory controller when the first address is not within an offset range based on the second address.

[0016] The memory controller generates the offset address and generates a command that directs memory operation according to the offset address, and a plurality of signals constituting the command include a chip select signal, and can provide the chip select signal to the memory device in a DDR manner.

[0017] According to another feature of the invention, a memory controller may include a plurality of bank queues corresponding to a plurality of banks of a memory device, a plurality of bank queues in which a plurality of requests are queued, and a plurality of bank schedulers corresponding to each of the plurality of bank queues and scheduling the processing order for a plurality of requests of each bank queue. Each of the plurality of bank schedulers may generate an offset address according to the difference between the address corresponding to the current request and the last address when the address difference between the last address of the memory region last operated in the corresponding bank and the address corresponding to the current request is within an offset range.

[0018] Each of the above multiple bank schedulers can generate a command indicating the offset address when the address corresponding to the current request is generated as the offset address.

[0019] Each of the above multiple bank schedulers can determine the priority of a request corresponding to an offset address over a request corresponding to a pool address among multiple requests queued in a corresponding bank queue.

[0020] Each of the above plurality of bank schedulers may include a register that stores the address corresponding to the current request in the corresponding bank as the last address.

[0021] Each of the above multiple bank schedulers can generate the difference between the first address and the second address as an offset address when there is no memory row in an active state in the corresponding bank, and the difference between the first address of the memory row that was last in an active state in the corresponding bank and the second address corresponding to this request is within the offset range.

[0022] A method for decoding a command and an address provided from a memory controller according to another feature of the invention comprises: a step of decoding the command to determine whether the address is an offset row address or an offset column address; and, if the determination result indicates that the address includes an offset row address, a base row address for the last executed memory row in the bank corresponding to the address and the offset row address cast The method may include the step of generating a row address by adding, and, if the address includes an offset column address, the step of generating a column address by adding the base column address for the last driven memory column in the bank corresponding to the address and the offset column address.

[0023] The above address decoding method further includes the step of updating the row address or the column address in an address table, and the address table may store the base row address and base column address for the last driven memory row and memory column per bank. Brief explanation of the drawing

[0024] FIG. 1 is an example block diagram of a semiconductor memory system according to one embodiment. FIG. 2 is a block diagram showing a semiconductor memory device according to one embodiment. FIG. 3 is a block diagram showing a memory controller according to one embodiment. FIG. 4 is a block diagram showing an address decoder according to one embodiment. FIG. 5 is a flowchart illustrating an address decoding method of a memory device according to one embodiment. FIG. 6 is a diagram schematically showing a part of a memory cell array of one of a plurality of banks according to one embodiment. FIG. 7 is a diagram showing a plurality of pins of a memory device according to one embodiment. FIG. 8 is a waveform diagram showing a command separator for a variable offset-based command according to one embodiment. FIG. 9 is a waveform diagram showing a command separator for a fixed offset-based command according to one embodiment. FIG. 10 is a waveform diagram showing the command transmission according to an offset addressing method according to one embodiment compared with a full addressing method. FIG. 11 is an exemplary block diagram showing a computer system according to one embodiment. Specific details for implementing the invention

[0025] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0026] In addition, to clearly explain the invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals. In the flowcharts described with reference to the drawings, the order of operations may be changed, multiple operations may be merged or divided, and certain operations may not be performed.

[0027] Additionally, expressions written in the singular form may be interpreted as singular or plural unless explicit expressions such as "one" or "singular" are used. Terms including ordinal numbers, such as the first, the second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0028] FIG. 1 is an example block diagram of a semiconductor memory system according to one embodiment.

[0029] Referring to FIG. 1, the semiconductor memory system (100) includes a semiconductor memory device (hereinafter, memory device) (110) and a memory controller (120).

[0030] The memory controller (120) can access the memory device (110) in response to a request transmitted via the memory system (100) bus. Data signals (DQ) and data strobe signals (DQS) are transmitted and received between the memory device (110) and the memory controller (120) via a bus between the two configurations, and commands (CMD), addresses (ADDR), and clocks (CLK) can be transmitted from the memory controller (120) to the memory device (110).

[0031] The memory device (110) includes a control logic circuit (111), an address decoder (112), and a plurality of banks (113). Each of the plurality of banks (111) may include a memory cell array (114). The memory cell array (114) may include a plurality of memory cells connected to a plurality of rows and a plurality of columns. In some embodiments, the rows may be defined by word lines and the columns may be defined by bit lines.

[0032] The address decoder (112) can generate a full address based on the last address and the offset address when the address received from the memory controller (120) is an offset address. The address (ADDR) may include one of a row address and a column address along with a bank address. The offset address may represent the difference between the address (row or column) of the memory region to be driven this time and the base address for the bank indicated by the address (ADDR). The base address may be set to the address (row or column) of the memory region last driven in the corresponding bank. The offset address may be any one of an offset row address, an offset column address, and an offset row address and an offset column address. The full address generated by the address decoder (112) may be any one of a row address, a column address, and a row address and a column address in the bank indicated by the address (ADDR). The memory region may include at least one memory cell.

[0033] The address decoder (112) can decode a command (CMD) to obtain information on whether the address (ADDR) is an offset address or a full address. The address decoder (112) may include an address table that stores information about the last driven row and column for each of the multiple banks (113) as a base address.

[0034] In FIG. 1, the control logic circuit (111) and the address decoder (112) are shown separately, but the address decoder (112) can be implemented as a component of the control logic circuit (111). For example, the memory device (110) further includes an address buffer, and the control logic circuit (111) can generate a full address by adding the address received in the address buffer and the last address when the address received in the address buffer is an offset address.

[0035] The memory controller (120) receives multiple requests from one or more processors and I / O devices via a bus, and in response to each of the multiple requests, writes data to the memory device (110) or transmits data read from the memory device (110) via the bus. The memory controller (120) converts each of the multiple requests into a first address according to an address mapping policy, schedules each of the multiple requests to a corresponding bank among multiple banks according to a set rule, and can generate each of the multiple commands (CMD) for each of the multiple requests. The memory controller (120) can generate an offset address for the first address based on the second address when the first address corresponding to the current request is within an offset range based on the second address corresponding to the last request immediately preceding the current request (off-set addressing method). Otherwise, the memory controller (120) can use the first address as is (full addressing method).

[0036] A memory controller (120) can generate an offset address for a request and generate a command (CMD) that directs memory operations according to the offset address. The memory controller (120) can schedule multiple commands (CMDs) corresponding to multiple banks and provide each of the multiple commands (CMDs) and their corresponding addresses (ADDRs) to the memory device (110) according to the scheduling. At this time, the command (CMD) can indicate whether the address (ADDR) is a full address or an offset address. In the following description, “address” and “full address” indicate an address for a memory area in a bank defined according to the full address method, “full row address” and “row address” indicate an address of a memory row according to the full address method, and “full column address” and “column address” indicate an address of a memory column according to the full address method. “Offset address” indicates an address for a memory area in a bank defined according to the offset addressing method, “offset row address” indicates an address for a memory row according to the offset addressing method, and “offset column address” indicates an address for a memory column according to the offset addressing method.

[0037] A memory device (110) can perform memory operations such as reading or writing by accessing a memory cell array (114) of a corresponding bank among a plurality of banks (113) according to a command (CMD) and an address (ADDR). The memory device (110) can generate clock signals based on a clock signal (CLK) and control read and write operations using the generated clock signals. According to a read operation, data read from the memory cell array (114) of a plurality of banks (113) is implemented as a data signal (DQ) and transmitted to a memory controller (120), and according to a write operation, the data signal (DQ) transmitted from the memory controller (120) can be written as data to the memory cell array (114). A data strobe signal (DQS) for controlling read and write operations can be provided from the memory controller (120) to the memory device (110).

[0038] The command (CMD) may include an activate command, a read / write command, a refresh command, etc. In some embodiments, the activate command may be a command to switch a target row of a memory cell array (114) to an active state in order to write data to a memory cell array (114) of a specific bank among a plurality of banks (113) or to read data from a memory cell array (114) of a specific bank among a plurality of banks (113). In response to the activate command, the memory cell of the target row may be activated (e.g., driven). The read / write command may be a command to perform a read or write operation on the target memory cell of the row that has been switched to an active state.

[0039] The memory device (110) may be a storage device based on a semiconductor device. In some embodiments, the memory device (110) may include dynamic random access memory (DRAM), double data rate 4 (DDR4), synchronous DRAM (SDRAM), low power DDR4 SDRAM, or LPDDR5 SDRAM. In some embodiments, the memory device (110) may include a non-volatile memory device such as NAND, 3D Vertical NAND, etc.

[0040] FIG. 2 is a block diagram showing a semiconductor memory device according to one embodiment.

[0041] Referring to FIG. 2, the memory device (200) includes a plurality of memory cell arrays (210), a plurality of sense amplifiers (211), a control logic circuit (220), an address decoder (230), an address buffer (235), a bank control logic (240), a plurality of row decoders (250), a plurality of column decoders (260), an I / O gating circuit (270), and a data I / O circuit (280).

[0042] Each of the plurality of memory cell arrays (210) includes a plurality of memory cells (MC). Each of the plurality of memory cell arrays (210) may include a plurality of rows, a plurality of columns, and a plurality of memory regions where the plurality of rows and the plurality of columns intersect. Each of the plurality of memory regions may include at least one memory cell (MC). In a memory cell array (210) according to some embodiment, each of the plurality of rows may be defined by each of the plurality of word lines (WL), and each of the plurality of columns may be defined by at least one corresponding bit line (BL).

[0043] The control logic circuit (220) controls the operation of the memory device (200). For example, the control logic circuit (220) can generate a control signal to cause the memory device (200) to perform a read operation, a write operation, a ZQ calibration operation, etc. In some embodiments, the control logic circuit (220) can generate a control signal by decoding a command (CMD).

[0044] The address buffer (235) can receive and store an address (ADDR) provided by the memory controller (120). In FIG. 2, the address buffer (235) is shown as being separate from the address decoder (230), but the invention is not limited thereto. The address buffer (2350) may be implemented within the address decoder (230). The address (ADDR) may be a row address indicating a row in the memory cell array (210), or a column address indicating at least two columns. A column address may be defined in units of bit lines (BL) corresponding to multiple columns in a data bus unit. For example, in a semiconductor memory system having a 4-bit data bus, a column address may correspond to units of 4 bit lines. Hereinafter, a memory row is defined as a word line, and a memory column may be defined in units of bit lines corresponding to the number of bits in the data bus.

[0045] The address decoder (230) can receive a command (CMD) from the memory controller (120). The address decoder (230) can decode the command (CMD) to determine whether the address (ADDR) provided from the memory controller (120) to the memory device (110) is an offset address or a pool address for a certain bank. Specifically, the address decoder (230) can decode the command (CMD) to identify whether the address (ADDR) is a pool row address, a pool column address, an offset row address, and an offset column address for a certain bank. Alternatively, the control logic circuit (220) can decode the command (CMD) to identify whether the address (ADDR) received from the memory controller (120) is a pool row address, a pool column address, an offset row address, and an offset column address for a certain bank, and provide information indicating the identification result to the address decoder (230). In the following disclosure, the address decoder (230) is described as decoding a command (CMD) to identify the type of address (ADDR).

[0046] When a command (CMD) indicates an offset row address, the address (ADDR) is an offset row address for a bank and may indicate the difference between the last memory row driven in that bank and the memory row to be driven this time. The address decoder (230) may generate a row address (RA), which is a full address, based on the offset row address stored in the address buffer (235) and the last row address of that bank.

[0047] When the command (CMD) indicates an offset column address, the address (ADDR) is an offset column address for a bank and may indicate the difference between the memory column last driven in that bank and the memory column to be driven this time. The address decoder (230) may generate a column address (CA), which is a full address, based on the offset row address and the last column address of the bank stored in the address buffer (235). When the command (CMD) indicates a full address, the address decoder (230) may output the row address (RA) or column address (CA), which is the address (ADDR) stored in the address buffer (235), as is.

[0048] The address decoder (230) can provide the row address (RA) to the row address multiplexer (251) and the column address (CA) to the column decoder (260).

[0049] In some embodiments, the memory controller (120) provides a bank address indicating a bank corresponding to an address (ADDR) among a plurality of banks to the memory device (200), and the address decoder (230) may provide the bank address (BA) to the bank control logic (240).

[0050] The bank control logic (240) can activate a row decoder (250) corresponding to the bank address (BA) among a plurality of row decoders (250) according to the bank address (BA), and activate a column decoder (260) corresponding to the bank address (BA) among a plurality of column decoders (260). In some embodiments, a plurality of row decoders (250a~250h) and a plurality of column decoders (260a~260h) corresponding to a plurality of memory cell arrays (210a~210h) may be provided. In some embodiments, the bank may include a memory cell array and a row decoder and a column decoder that drive the memory cell array. A plurality of banks (300) includes eight banks (300a~300h), and bank (300a) includes a memory cell array (210a), a row decoder (250a), and a column decoder (260a), and … The bank (300h) may include a memory cell array (210h), a row decoder (250h), and a column decoder (260h).

[0051] In some embodiments, the memory device (200) further includes a row address multiplexer (251), and the refresh control circuit (290) can sequentially output row addresses (REF_RA) to be refreshed under the control of the control logic circuit (220). The row address multiplexer (251) can receive row addresses (RA) from an address decoder (230) and row addresses (REF_RA) to be refreshed from the refresh control circuit (290). The row address multiplexer (251) can selectively output the row address (RA) received from the address decoder (230) and the row address (REF_RA) received from the refresh control circuit (290) to the row decoder (250).

[0052] The row decoder (250) selects a row to be activated from among a plurality of rows of the memory cell array (210) based on a row address in a bank indicated by a bank address (BA). To do this, the row decoder (250) may apply a driving voltage to a word line corresponding to the row to be activated.

[0053] The column decoder (260) selects a column to be activated from among a plurality of columns of the memory cell array (210) based on a column address in a bank indicated by a bank address (BA). To do this, the column decoder (260) can activate a sense amplifier (211) corresponding to a column address (CA) through an I / O gating circuit (270).

[0054] In some embodiments, the I / O gating circuit (270) gates input / output data and may include a data latch for storing data read from the memory cell array (210) and a write driver for writing data to the memory cell array (210). Data read from the memory cell array (210) is detected by a sense amplifier (211) and may be stored in the I / O gating circuit (270) (e.g., the data latch). In some embodiments, a plurality of sense amplifiers (211a to 211h) corresponding to a plurality of memory banks (300a to 300h) may be provided.

[0055] In some embodiments, data read from the memory cell array (210) (e.g., data stored in a data latch) may be provided to the memory controller (120) through the data I / O circuit (280). Data to be written to the memory cell array (210) is provided from the memory controller (120) to the data I / O circuit (280), and the data provided to the data I / O circuit (280) may be provided to the I / O gating circuit (270).

[0056] The data I / O circuit (280) can generate a clock signal using a data strobe signal (DQS) received from the memory controller (120) via a bus, and can convert data input to the data I / O circuit (280) among the data stored in the memory cell array (210) according to the clock signal into a data signal (DQ) and provide it to the memory controller (120). The data I / O circuit (280) can generate a clock signal using a data strobe signal (DQS) received from the memory controller (120) via a bus, and can generate data to be written to the memory cell array (210) by sampling and amplifying the data signal (DQ) provided from the memory controller (120).

[0057] In the following description, the offset address indicates at least one of the offset row address and the offset column address, and the pool address may indicate at least one of the pool row address and the pool column address.

[0058] FIG. 3 is a block diagram showing a memory controller according to one embodiment.

[0059] The memory controller (120) may include address mapping logic (121), a plurality of bank queues (122_1 to 122_n), a plurality of bank schedulers (123_1 to 123_n), a plurality of command registers (124_1 to 124_n), and a channel scheduler (125).

[0060] The address mapping logic (121) can convert each of multiple requests into an address according to an address mapping policy. The address mapping policy may be implemented as a known address mapping policy, such as Interleaved Banks or Private Banks, or as a combination of two or more of the known address mapping policies. The address mapping logic (121) may assign each of multiple requests to one of the multiple bank schedulers (123_1 to 123_n) according to a set rule, taking into account timing constraints defined in a specific protocol such as JEDEC and efficiency in processing requests, and may queue the requests to a bank queue (one of 122_1 to 122_n) corresponding to the bank defined by the address corresponding to each request. Each of the multiple bank queues (122_1 to 122_n) may be equal to the number of multiple banks (BANK1 to BNAKn) constituting the memory device (110).

[0061] Each of the multiple bank schedulers (123_1 to 123_n) schedules the processing order for multiple requests stored in a corresponding bank queue (one of 122_1 to 122_n) and can generate multiple requests as multiple commands according to the scheduling order. Each of the multiple bank schedulers (123_1 to 123_n) compares the last address of the memory area last operated in the corresponding bank with the address corresponding to the current request according to the scheduling order, and if the difference between the two addresses is within a set offset range, can generate an offset address according to the difference between the address corresponding to the current request and the last address. Each of the multiple bank schedulers (123_1 to 123_n) can update the address corresponding to the current request to the last address. If each of the multiple bank schedulers (123_1 to 123_n) generates an offset address for an address corresponding to a request, they can generate a command that indicates the offset address for that request. Instructions using a full address and instructions using an offset address can be distinguished by a command separator. If the difference between the two addresses is not within the set offset range, each of the multiple bank schedulers (123_1 to 123_n) can generate a full address corresponding to this request. Each of the multiple bank schedulers (123_1 to 123_n) can provide the address and instruction generated in this way to each of the multiple command registers (124_1 to 124_n).

[0062] Each of the multiple bank schedulers (123_1 to 123_n) can determine the processing order for multiple requests according to a set policy. The set policy may include an open page method that considers row hits. In one embodiment, in addition to the existing policy, each of the multiple bank schedulers (123_1 to 123_n) can determine the processing order for multiple requests queued in the corresponding bank queue based on whether the address of each request can be generated as an offset address. For example, each of the multiple bank schedulers (123_1 to 123_n) can determine a request that can provide an address (ADDR) to the memory device (110) as an offset address with higher priority than a request that must provide an address (ADDR) to the memory device (110) as a full address. Then, a request corresponding to a full address can be changed to a request corresponding to an offset address. Additionally, each of the multiple bank schedulers (123_1 to 123_n) may determine that there is a buffer miss in which there is no active memory row in the bank corresponding to this request, and that the difference between the address of the last active memory row in each bank and the address of this request is within a predetermined offset range, and may determine that this request has priority over other requests in the bank queue corresponding to this request, and generate the difference between the address of this request and the address of the last active memory row as the offset address.

[0063] The channel scheduler (125) can monitor multiple commands for multiple banks stored in multiple command registers (124_1 to 124_n) and select the highest priority command (CMD) among all commands satisfying the required channel real-time constraints and transmit it to the memory device (110) along with an address (ADDR). The channel scheduler (125) can select the highest priority command (CMD) among the multiple commands stored in multiple command registers (124_1 to 124_n) and transmit it to the memory device (110) along with an address (ADDR). At this time, the address (ADDR) may include an offset address along with the bank address, or may include a full address along with the bank address.

[0064] In this way, the memory controller (120) can determine access sequences through bank scheduling and channel scheduling for multiple received requests, and provide a command (CMD) and an address (ADDR) to the memory device (200) according to the determined access sequences.

[0065] Each of the plurality of bank schedulers (123_1 to 123_n) may include a register (126_1 to 126_n) that stores the last address of the memory region last executed in the corresponding bank. The channel scheduler (125) may transmit a command processing signal to the bank scheduler (123_1 to 123_n) corresponding to the command (CMD) and address (ADDR) transmitted to the memory device (110) to indicate that the corresponding command has been processed. For example, the channel scheduler (125) transmits a command processing signal to the bank scheduler (123_i, where i is one of an integer from 1 to n), and the bank scheduler (123_i) may record the address corresponding to the command processed by the channel scheduler (125) in the last address register (126_i). At this time, the address may be a full address. That is, among the multiple bank schedulers (123_1 to 123_n), the bank scheduler (123_i) that receives a command processing signal from the channel scheduler (125) may store the full address corresponding to the processed command in the last address register (126_i).

[0066] The memory controller (120) may further include a read data buffer (128) and a write data buffer (129). The read data buffer (128) stores read data provided from the memory device (110) and can provide the read data to the bus in response to an external request. The write data buffer (129) stores data to be written provided through the bus and can be provided to the memory device (110) in response to an external request.

[0067] Hereinafter, the address decoder will be described with reference to FIG. 4.

[0068] FIG. 4 is a block diagram showing an address decoder according to one embodiment.

[0069] As illustrated in FIG. 4, the address decoder (230) may include an address table (231), a row / column selector (232), an address summer (233), an address multiplexer (234), and decoding control logic (235).

[0070] The decoding control logic (235) receives an address (ADDR) and a command (CMD), decodes the command (CMD) to identify whether the address (ADDR) is an offset address or a full address, and can generate an address selection signal (ASS) to control the address multiplexer (234) based on the identified result. The decoding control logic (235) can derive a bank address (BA) from the address (ADDR). The decoding control logic (235) can provide the bank address (BA) to the bank control logic (240).

[0071] The decoding control logic (235) can derive address bits indicating a row address or a column address from the address (ADDR). Each of the offset row address and offset column address can be implemented with a set of Na consecutive bit data, and each of the full row address and full column address can also be implemented with a set of Nb consecutive bit data. Nb can be a natural number greater than Na.

[0072] The decoding control logic (235) can generate an address selection signal (ASS) that instructs the row address or column address indicated by the address (ADDR) to be output as is when the address (ADDR) is a full address. The decoding control logic (235) can generate an address selection signal (ASS) that instructs the row address or column address provided by the address summer (233) to be output when the address (ADDR) is an offset row address. The decoding control logic (235) can provide the address selection signal (ASS) to the address multiplexer (234). The multiplexer (234) can provide the row address or column address indicated by the address (ADDR) to the row address multiplexer (251) or the multiple column addresses (260) according to the address selection signal (ASS). Alternatively, it can provide the row address or column address provided by the address summerer (233) to the row address multiplexer (251) or the multiple column addresses (260).

[0073] The decoding control logic (235) can generate a bank selection signal (BSS) according to the bank address (BA) when the address (ADDR) is an offset row address, and can generate a row selection signal (RSS) to control the row address summing operation of the address summer (233). The decoding control logic (235) can generate a bank selection signal (BSS) according to the bank address (BA) when the address (ADDR) is an offset column address, and can generate a column selection signal (CSS) to control the column address summing operation of the address summer (233).

[0074] The offset row address and offset column address, or row address and column address, provided to the address summerator (233) and address multiplexer (234) in the decoding control logic (235) can be collectively defined as address bits.

[0075] The address table (231) can store row addresses (hereinafter referred to as base row addresses) and column addresses (hereinafter referred to as base column addresses) for the address of the last executed memory area (hereinafter referred to as base address) in each of the multiple banks (300a to 300h) on a bank-by-bank basis. As shown in FIG. 4, the address table (231) includes a “Bank” column, a “Row” column, and a “Col” column, and in each row of the address table (231), the bank address, base row address, and base column address are recorded on a column-by-column basis. One of the multiple banks (1, 2, … n) of the “Bank” column in the address table (231) can be selected by a bank selection signal (BSS) generated by the decoding control logic (235).

[0076] The row / column selector (232) can provide the base row address and base column address of the selected bank, respectively, to the address summerator (233) according to the row selection signal (RSS) and column selection signal (CSS) generated by the decoding control logic (235). The row / column selector (232) can provide the base row address to the address summerator (233) in synchronization with the row selection signal (RSS) and provide the base column address to the address summerator (233) in synchronization with the column selection signal (CSS).

[0077] In this way, the decoding control logic (235) can select a bank from the address table (231), control when the basic row address of the selected bank is provided to the address summer (233), and control when the basic column address of the selected bank is provided to the address summer (233).

[0078] When address bits are provided to the address summer (233), the row / column selector (232) can provide a base row address or base column address to the address summer (233) in accordance with the offset row address or offset column address indicated by the address bits.

[0079] The address summer (233) can generate a row address (RA) by adding the address bits and the base row address, or generate a column address (CA) by adding the address bits and the base column address.

[0080] The address multiplexer (234) may output a row address (RA) or a column address (CA) according to address bits according to an address selection signal (ASS), or output a row address (RA) or a column address (CA) generated by an address summerger (233). For example, when a command (CMD) indicates a full address, the address multiplexer (234) may output one of the row address (RA) and column address (CA) according to an address (ADDR) according to an address selection signal (ASS) provided by the decoding control logic (235), and when a command (CMD) indicates an offset address, it may output a row address or a column address generated by an address summerger (233) according to an address selection signal (ASS) provided by the decoding control logic (235).

[0081] The address demultiplexer (236) can update the row address or column address output through the address demultiplexer (234) to the row or column in the address table (231) in the bank indicated by the bank selection signal (BSS) and the bank indicated by the row selection signal (RSS) or column selection signal (CSS).

[0082] Hereinafter, a method for generating a full address by decoding a command (CMD) and an address (ADDR) by a semiconductor memory device according to one embodiment is described.

[0083] FIG. 5 is a flowchart illustrating an address decoding method of a memory device according to one embodiment.

[0084] The memory controller (120) can provide a command (CMD) and an address (ADDR) to the memory device (200) (S1, S2). Accordingly, the control logic circuit (220) and the address decoder (230) of the memory device (200) can acquire the command (CMD), and the address buffer (235) can acquire the address (ADDR).

[0085] The address buffer (235) can provide an address (ADDR) to the address decoder (230) (S3).

[0086] The address decoder (230) can decode the command (CMD) to determine whether the address (ADDR) is an offset address (S4).

[0087] S4. If the address (ADDR) is a full address rather than an offset address, the row address or column address indicated by the address (ADDR) can be provided to a row address multiplexer (251) or a plurality of column decoders (260) (S8).

[0088] Based on the result of S4, if the address (ADDR) is an offset address, the address decoder (230) can determine whether the address (ADDR) includes an offset row address (S5).

[0089] If the S5 judgment result indicates that the address (ADDR) includes an offset row address, the address decoder (230) selects a bank from the address table (231) according to the bank selection signal (BSS), reads out a base row address from the selected bank, and can generate a row address by adding address bits indicating the base row address and the offset row address (S6).

[0090] If the S5 judgment result indicates that the address (ADDR) includes an offset column address rather than an offset row address, the address decoder (230) selects a bank from the address table (231) according to the bank selection signal (BSS), reads out a base column address from the selected bank, and can generate a column address by adding address bits indicating the base column address and the offset column address (S7).

[0091] Step S8 may be performed following Step S6 or Step S7.

[0092] After step S8, the address decoder (230) can update the row address or column address generated in step S7 to the corresponding bank and row or column in the address table (231) (S9). The address table (231) can store the updated row address or column address.

[0093] In the case of multiple requests for read or write operations to a memory device (200), when multiple addresses corresponding to the multiple requests change according to a certain rule or are adjacent to each other, the memory controller (120) can generate an offset address. For example, when a chip implementing an artificial neural network reads data from a semiconductor memory system for vector processing and writes the processing result to the semiconductor memory system, multiple addresses corresponding to the multiple requests may follow a set rule. Additionally, when a video encoding chip reads an image source from a semiconductor memory system, multiple addresses corresponding to the multiple requests may follow a set rule. In this way, in an environment where predictable access to the semiconductor memory system is predominant, transmitting an offset address instead of transmitting a full address to the memory device may be efficient for operating the memory device.

[0094] FIG. 6 is a diagram schematically showing a part of a memory cell array of one of a plurality of banks according to one embodiment.

[0095] As illustrated in FIG. 6, let us assume a case where multiple read requests or multiple write requests for memory regions occur in order according to a stride pattern in a memory cell array (500). As illustrated in FIG. 6, multiple memory regions (501 to 516) are located in the memory cell array (500) at regular intervals. Specifically, in the memory cell array (500), multiple memory regions (501 to 516) are spaced apart in 2x2 units, and each of the multiple memory regions (501 to 516) can be defined by a row address and a column address and may include at least one memory cell.

[0096] Conventionally, a memory controller must transmit multiple addresses, implemented as full addresses for each of the multiple memory regions, to a memory device in a scheduling order. For example, when multiple memory regions (501 to 504) located at intervals of two columns in a row (ROW1) are driven in the right direction, the memory controller must transmit a column address with a fixed number of bits consecutively to memory device 3 after transmitting the full address for memory region (501). In the same manner, when multiple memory regions (505 to 508, 509 to 512, 513 to 516) located at intervals of two columns in each of the multiple rows (ROW2, ROW3, ​​ROW4) are driven in the right direction, the memory controller must transmit a column address with a fixed number of bits consecutively to memory device 3 after transmitting the full address for memory regions (505, 509, 513).

[0097] However, when using an offset address according to one embodiment, the memory controller (120) only needs to transmit to the memory device (110) the offset column address between the memory area (501) and the memory area (502), the offset column address between the memory area (502) and the memory area (503), and the offset column address between the memory area (503) and the memory area (504) after transmitting the full address for the memory area (501). At this time, the offset column addresses can be implemented with a number of bits smaller than the fixed number of bits of a conventional column address. Next, the memory controller (120) transmits the offset row address and offset column address between memory area (504) and memory area (505) to the memory device (110), and only transmits the offset column address between memory area (505) and memory area (506), the offset column address between memory area (506) and memory area (507), and the offset column address between memory area (507) and memory area (508) to the memory device (110). In this way, the memory controller (120) according to one embodiment can transmit an offset address containing a smaller number of bits compared to a full address to the memory device (110).

[0098] Since the memory controller (120) generates an offset address based on the difference between the last address and the current address, the generated offset address may be variable. Alternatively, the memory controller (120) may fix the offset address under specific conditions. Specific conditions may be defined according to the design. For example, if a host providing a video source to a display uses a semiconductor memory system as a frame buffer, the video source in one frame unit to be displayed on the screen for each frame may be located in a specific pattern in the memory device. In this case, the offset address may be a fixed value. According to one embodiment, the memory controller (120) may selectively provide one of a command containing the generated offset address and a command in which the offset address is fixed to the memory device (200).

[0099] Table 1 is a table showing variable offset-based instructions that can change whenever the offset address is generated.

[0100] Memory device operation component Offset-Activate Command separator, bank address, offset Offset-Read Command separator, bank address, offset, auto-precharge status Offset-Write Command separator, bank address, offset, auto-precharge status

[0101] In Table 1, the command “Offset-Activate” is a command that directs an Activate operation using an offset address and may include a Command identifier, a bank address, and an offset. “Activate operation” may refer to an operation of selecting one of a plurality of banks and activating one of a plurality of memory rows constituting the selected bank. The offset included in the command “Offset-Activate” may be an offset row address. The command “Offset-Read” is a command that directs a Read operation using an offset address and may include a Command identifier, a bank address, an offset, and whether or not to auto-precharge. “Read operation” may refer to an operation of selecting a specific memory column in the activated bank and memory row to read data. The command “Offset-Write” is a command that directs a Write operation using an offset address and may include a Command identifier, a bank address, an offset, and whether or not to auto-precharge. “Write operation” may refer to an operation of selecting a specific memory column in the activated bank and memory row to write data. The offsets for the “Offset-Read” and “Offset-Write” commands may be offset column addresses. Auto-precharge may refer to commands in which a precharge operation is performed after a read or write operation is performed for a fixed operation cycle. Table 2 is a table showing fixed offset-based commands in which the offset address is fixed.

[0102] Memory device operation component Offset-Activate Command separator, bank address Offset-Read Command separator, bank address, auto-precharge status Offset-Write Command separator, bank address, auto-precharge status Set-Offset Command separator, bank address, offset

[0103] In Table 2, the command “Offset-Activate” is a command that directs an Activate operation using an offset address and may include a Command identifier and a bank address. The command “Offset-Read” is a command that directs a Read operation using an offset address and may include a Command identifier, a bank address, and whether or not to auto-precharge. The command “Offset-write” is a command that directs a Write operation using an offset address and may include a Command identifier, a bank address, and whether or not to auto-precharge. The command “Set-Offset” may include a Command identifier, a bank address, and an offset having a fixed value. The offset of the command “Set-Offset” may be an offset address corresponding to the command, namely, an offset row address, an offset column address, or both an offset row address and an offset column address. As can be seen from Tables 1 and 2, to implement one embodiment, a plurality of Command identifiers for distinguishing each of the newly created plurality of commands were added to the existing plurality of Command identifiers. A pin may be added to the memory device (110) to combine multiple newly generated separators. Alternatively, information may be added to a signal transmitted to one of the pins provided in the memory device (110), and the memory device (110) may perform a decoding operation to obtain additional information.

[0104] FIG. 7 is a diagram showing a plurality of pins of a memory device according to one embodiment.

[0105] The memory device (600) illustrated in FIG. 7 is an example for explaining one embodiment, and only the pins involved in the Command identifier are illustrated. In addition to the pins illustrated in FIG. 7, the memory device (600) may further include a pin to which a clock enable signal ( / CKE) is input, a plurality of address pins to which an address (ADDR) is input, a plurality of DQ pins to which a data signal is input or output, a power pin, etc.

[0106] In FIG. 7, the memory controller (610) may provide a chip select signal ( / CS) to the first pin (601) of the memory device (600), a row address strobe command ( / RAS) to the second pin (602), a column address strobe command ( / CAS) to the third pin (603), and a write enable signal ( / WE) to the fourth pin (604). Multiple commands may be defined by a combination of the logic levels of the signals provided to the first to fourth pins (601 to 604). The memory controller (610) may provide a clock signal (CLK) to the fifth pin (605) to control the operating frequency of the memory device (600). The chip select signal ( / CS) is a signal that selects one of a plurality of memory chips constituting a semiconductor memory system, the row address strobe command ( / RAS) is a signal that controls the timing of reading a row address from an address line, the column address strobe command ( / CAS) is a signal that controls the timing of reading a column address from an address line, and the write enable signal ( / WE) is a signal that controls data writing.

[0107] A memory controller (610) according to one embodiment may provide a chip select signal ( / CS) of a first pin (601) in a DDR (Double Data Rate) manner to define a plurality of command separators for a plurality of offset commands. The memory device (600) may operate according to signals input through other pins when the chip select signal ( / CS) is at a low level at the rising edge of the clock signal (CLK). The memory controller (610) may set a logic level of the chip select signal ( / CS) for each specific edge of the clock signal (CLK) to define a command separator for an offset command. For example, the memory controller (610) may implement a command separator for an offset command by setting the chip select signal ( / CS) to a high level at the falling edge of the clock signal (CLK).

[0108] FIG. 8 is a waveform diagram showing a command separator for a variable offset-based command according to one embodiment.

[0109] As shown in FIG. 8, in each command directing the operation of the same memory device, the command separator between the full address and the offset address is different.

[0110] The clock signal (CLK), chip select signal ( / CS), row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) illustrated in FIG. 8 are generated by the memory controller (610) and provided to the memory device (600) through the first pin (601) to the fifth pin (605). In FIG. 8, the memory controller (610) provides a high-level clock enable signal ( / CKE) to the memory device (600) so that the memory device (600) can operate according to the clock signal (CLK).

[0111] FIG. 8 is an example illustrating a command separator for an offset command according to one embodiment, wherein a memory controller (610) can provide a chip select signal ( / CS) to a memory device (600) in a DDR manner. That is, the first pin (601) is driven in a DDR manner so that the chip select signal ( / CS) can have a specific value on the rising edge of the clock signal (CLK).

[0112] In FIG. 8, signals indicating the bank address, row address, column address, and whether auto-precharge is enabled, corresponding to the command (CMD), are omitted. It is obvious to those skilled in the art that signals can be implemented to indicate information corresponding to the command (CMD) in various known ways.

[0113] At the rising edge (T1) of the clock signal (CLK), the chip select signal ( / CS), the low address strobe command ( / RAS), the column address strobe command ( / CAS), and the write enable signal ( / WE) have values ​​of L, L, H, and H, and a combination thereof can implement a command identifier that directs the full address Activate operation. At the rising edge (T2) of the clock signal (CLK), the chip select signal ( / CS), the low address strobe command ( / RAS), the column address strobe command ( / CAS), and the write enable signal ( / WE) have values ​​of L, H, L, and H, and a combination thereof can implement a command identifier that directs the full address Read operation. At the rising edge (T3) of the clock signal (CLK), the chip select signal ( / CS), the low address strobe command ( / RAS), the column address strobe command ( / CAS), and the write enable signal ( / WE) have values ​​of L, H, L, L, and a combination thereof can implement a command identifier that directs a full address write operation.

[0114] At the falling edge (T4) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T5) of the clock signal (CLK) that follows the falling edge (T4), the low address strobe command ( / RAS), the column dress strobe command ( / CAS), and the write enable signal ( / WE) have values ​​of L, H, and H, and a combination of these (H, L, H, H) can implement a command identifier that indicates an Activate operation using a variable offset-based offset address. At the falling edge (T6) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T7) of the clock signal (CLK) that follows the falling edge (T6), the row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) have values ​​of H, L, and H, and a combination of these (H, H, L, H) can implement a command identifier that indicates a Read operation using a variable offset-based offset address. At the falling edge (T8) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T9) of the clock signal (CLK) that follows the falling edge (T8), the row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) have values ​​of H, L, L, and a combination of these (H, H, L, L) can implement a command identifier that directs a write operation using a variable offset-based offset address.

[0115] FIG. 9 is a waveform diagram showing a command separator for a fixed offset-based command according to one embodiment.

[0116] The waveforms of the chip select signal ( / CS), row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) shown in FIG. 9 are examples for explaining one embodiment, and the invention is not limited thereto.

[0117] At the falling edge (T10) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T11) of the clock signal (CLK) that follows the falling edge (T10), the row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) have values ​​of L, H, and L, and a combination of these (H, L, H, L) can implement a command identifier that indicates an Activate operation using an offset address based on a fixed offset. At the falling edge (T12) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T13) of the clock signal (CLK) that follows the falling edge (T12), the row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) have values ​​of L, L, and H, and a combination of these (H, L, L, H) can implement a command identifier that indicates a Read operation using a fixed offset-based offset address. At the falling edge (T14) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T15) of the clock signal (CLK) that follows the falling edge (T14), the row address strobe command ( / RAS), column address strobe command ( / CAS), and write enable signal ( / WE) have values ​​of H, H, and L, and a combination of these (H, H, H, L) can implement a command identifier that directs a write operation using a fixed offset-based offset address.At the falling edge (T16) of the clock signal (CLK), the chip select signal ( / CS) has a value of H, and at the rising edge (T17) of the clock signal (CLK) that follows the falling edge (T16), the low address strobe command ( / RAS), the column address strobe command ( / CAS), and the write enable signal ( / WE) have values ​​of L, L, L, and a combination of these (H, L, L, L) can implement a command identifier that indicates a fixed offset value.

[0118] In order to reduce standby power proportional to the operating frequency of the memory device, the clock frequency controlling the operating frequency of the memory device can be set lower by a predetermined ratio relative to the frequency of the data signal (DQ) by separating the clock domain. If the ratio increases, performance degradation may occur due to a reduction in the bandwidth of the command and address buses. Since the offset address according to one embodiment can reduce the amount of data transmitted through the command and address buses compared to the conventional full address, performance degradation caused by bandwidth reduction can be prevented. Furthermore, a command can be provided that allows the offset address to be used by utilizing existing pins without adding additional pins to the memory device. Even if additional pins are implemented in the memory device instead of using the CS pin that receives the chip select signal ( / CS), the amount of data transmitted by the memory controller to the memory device is reduced, so low-power operation may be possible even if the operating frequency is reduced.

[0119] FIG. 10 is a waveform diagram showing the command transmission according to an offset addressing method according to one embodiment compared with a full addressing method.

[0120] Figure 10 (A) is a waveform diagram schematically showing a command for transmitting a full address in a full addressing method.

[0121] Figure 10 (B) is a waveform diagram illustrating a command to transmit an offset address when an offset addressing method is applicable.

[0122] (C) of FIG. 10 is a waveform diagram schematically representing command transmission when the operating frequency is 0.5 compared to (A) and (B). The waveforms shown in FIG. 10 are for command transmission, and the frequency at which the memory controller (120) transmits a data signal to the memory device (200) may be different from the clock signal (CLK1) shown in FIG. 10. For example, the transmission frequency of the data signal may be higher than the frequency of the clock signal (CLK1).

[0123] When command 1 (CMD1) and command 2 (CMD2) are required for full address transmission, in (A) of FIG. 10, command 1 (CMD1) and command (CMD2) must be transmitted from the memory controller (120) to the memory device (200) at every rising edge of the clock signal (CLK1).

[0124] When driving the memory device (200) with the same clock signal (CLK1), in (B) of FIG. 10, command 1 (CMD1) and command 2 (CMD2) are required for the initial full address transmission, and when the memory device (200) can be driven using an offset addressing method, command 3 (CMD3) for transmitting the offset address can be transmitted to the memory device (200) at every rising edge (e.g., RE1) of the clock signal (CLK1) for two cycles. That is, there may be a period (BL) during which no command is transmitted during the period between command 3 (CMD3) and the subsequent command 3 (CMD3). Then, the memory device (200) can be driven at a frequency that is half that of the clock signal (CLK1), such as the clock signal (CLK2) shown in (C) of FIG. 10.

[0125] In (C) of FIG. 10, command 1 (CMD1) and command 2 (CMD2) for transmitting the initial full address are transmitted on the rising edge (RE2, RE3) of the clock signal (CLK2), and command 3 (CMD3) for transmitting the offset address can be transmitted on every rising edge of the clock signal (CLK2). In this way, the number of commands for transmitting the address according to offset addressing is reduced, thereby lowering the operating frequency and enabling low-power operation.

[0126] FIG. 11 is an exemplary block diagram showing a computer system according to one embodiment.

[0127] Referring to FIG. 11, the computing system (700) includes a processor (710), memory (720), memory controller (730), storage device (740), communication interface (750), and bus (760). The computing system (700) may further include other general-purpose components.

[0128] The processor (710) controls the overall operation of each component of the computing system (700). The processor (710) may be implemented as at least one of various processing units, such as a central processing unit (CPU), an application processor (AP), or a graphic processing unit (GPU). In some embodiments, the memory controller (730) may be provided as a separate chip from the processor (710). In some embodiments, the memory controller (730) may be provided as an internal component of the processor (710).

[0129] The memory (720) can store various data and commands. The memory (720) may be implemented as a memory device described with reference to FIGS. 1 to 10. The memory controller (730) controls the transfer of data or commands to and from the memory (720). The memory controller (730) may be implemented as a memory controller described with reference to FIGS. 1 to 10. Accordingly, the memory controller (730) can generate an offset addressing command for a plurality of requests from the processor (710) via the bus (760), transmit it to the memory (720), and store the requested address using the offset addressing method. The memory (720) receives a command indicating an offset address and, according to the command, can generate a full address by adding the offset address and the last address in the corresponding bank that has been stored.

[0130] The storage device (740) stores programs and data non-temporarily. In some embodiments, the storage device (740) may be implemented as non-volatile memory. The communication interface (750) supports wired and wireless internet communication of the computing system (700). Additionally, the communication interface (750) may support various communication methods other than internet communication. The bus (760) provides communication functions between components of the computing system (700). The bus (760) may include at least one type of bus according to the communication protocol between components.

[0131] In some embodiments, each component or combination of two or more components described with reference to FIGS. 1 to 11 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application-specific integrated circuit (ASIC), etc.

[0132] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

Claim 1 A semiconductor memory system comprising: a memory controller that generates and provides an offset address for a first bank and a command indicating said offset address in response to a first request; and a memory device that includes a plurality of banks, wherein, for the first bank among the plurality of banks, a first address is generated by adding said offset address and a base address for the first bank in accordance with said command, and performs a memory operation according to said command at said first address of the first bank, wherein the memory controller generates said offset address and generates a command indicating a memory operation according to said offset address, wherein a plurality of signals constituting said command include a chip select signal, and the chip select signal is provided to said memory device in a DDR manner. Claim 2 A semiconductor memory system according to claim 1, wherein the memory controller generates an offset address for the first address based on the second address when the first address in the first bank corresponding to the first request scheduled in the first bank is within an offset range based on the second address corresponding to the second request scheduled in the first bank immediately before the first request, and the base address is the second address. Claim 3 A semiconductor memory system according to claim 2, wherein the command comprises at least one of: an Offset-Activate command that directs an activation operation using the offset address and includes a command delimiter, a bank address, and an offset; an Offset-Read command that directs a read operation using the offset address and includes a command delimiter, a bank address, and an offset; and an Offset-Write command that directs a write operation using the offset address and includes a command delimiter, a bank address, and an offset. Claim 4 A semiconductor memory system in paragraph 3, wherein the offset of the Offset-Activate command is an offset row address, and the offsets of the Offset-Read command and the Offset-Write command, respectively, are offset column addresses. Claim 5 A semiconductor memory system according to paragraph 2, wherein the command comprises at least one of: an Offset-Activate command instructing an activation operation using the offset address and including a command separator and a bank address; an Offset-Read command instructing a read operation using the offset address and including a command separator and a bank address; an Offset-Write command instructing a write operation using the offset address and including a command separator and a bank address; and a Set-Offset command including a command separator, a bank address, and an offset. Claim 6 A semiconductor memory system according to claim 5, wherein the offset of the Set-Offset command is a fixed value corresponding to the offset address. Claim 7 In paragraph 2, the semiconductor memory system comprises an address decoder that decodes the command to identify the offset address for the first bank and adds the second address and the offset address to generate the first address. Claim 8 A semiconductor memory system according to claim 7, wherein the address decoder comprises: an address table storing a base row address and a base column address for a memory row and a memory column last driven for each of the plurality of banks; a row / column selector providing one of a base row address or a base column address corresponding to the first bank in the address table; and an address summer generating the first address by adding the offset address and one of the base row address and the base column address provided from the row / column selector. Claim 9 A semiconductor memory system according to claim 8, wherein when the above command indicates an offset row address, the row / column selector provides the base row address to the address summerator, and the address summerator adds the base row address and the offset address to generate the first address. Claim 10 A semiconductor memory system according to claim 8, wherein when the above command indicates an offset column address, the row / column selector provides the base column address to the address summerator, and the address summerator adds the base column address and the offset address to generate the first address. Claim 11 A semiconductor memory system according to claim 8, wherein the address decoder further comprises an address demultiplexer that updates the first address to one of a base row address and a base column address corresponding to the first bank in the address table. Claim 12 A semiconductor memory system according to claim 8, wherein the address decoder further comprises an address multiplexer that outputs the first address provided by the address summerator when the first address is within an offset range based on the second address, and outputs the first address provided by the memory controller when the first address is not within an offset range based on the second address. Claim 13 delete Claim 14 A memory controller comprising: a plurality of bank queues corresponding to a plurality of banks of a memory device and having a plurality of requests queued therein; and a plurality of bank schedulers corresponding to each of the plurality of bank queues and scheduling the processing order for a plurality of requests of each bank queue, wherein each of the plurality of bank schedulers generates an offset address according to the difference between the address corresponding to the current request and the last address when the address difference between the last address of the memory region last driven in the corresponding bank and the address corresponding to the current request is within an offset range, and generates a command instructing a memory operation according to the offset address, wherein a plurality of signals constituting the command include a chip select signal, and the chip select signal is provided to the memory device in a DDR manner. Claim 15 In claim 14, each of the plurality of bank schedulers generates a command indicating the offset address when the address corresponding to the current request is generated as the offset address, a memory controller. Claim 16 In claim 14, each of the plurality of bank schedulers determines the priority of a request corresponding to an offset address over a request corresponding to a pool address among a plurality of requests queued in a corresponding bank queue, as a memory controller. Claim 17 In claim 14, each of the plurality of bank schedulers comprises a memory controller including a register that stores the address corresponding to the current request in the corresponding bank as the last address. Claim 18 In claim 14, each of the plurality of bank schedulers generates the difference between the first address and the second address as an offset address when there is no memory row in an active state in the corresponding bank, and the difference between the first address of the memory row that was last in an active state in the corresponding bank and the second address corresponding to this request is within the offset range. Claim 19 A method for decoding a command and an address provided from a memory controller, comprising: a step of decoding the command to determine whether the address is an offset row address or an offset column address; a step of generating a row address by adding the offset row address to the base row address for the last driven memory row in the bank corresponding to the address, if the determination result indicates that the address includes an offset row address; and a step of generating a column address by adding the offset column address to the base column address for the last driven memory column in the bank corresponding to the address, if the determination result indicates that the address includes an offset column address, wherein a plurality of signals constituting the command include a chip select signal, and the chip select signal is provided in a DDR manner. Claim 20 An address decoding method according to claim 19, further comprising the step of updating the row address or the column address in an address table, wherein the address table stores the base row address and base column address for the last driven memory row and memory column per bank.

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