Semiconductor device and method for fabricating the same

Abstract

A semiconductor device comprising a ferroelectric field-effect transistor (FeFET) with improved characteristics is provided. The semiconductor device comprises a substrate, a gate electrode film comprising a metal element on the substrate, a gate insulating film comprising a ferroelectric between the substrate and the gate electrode film, and a buffer oxide film comprising an oxide of a semiconductor material in contact with the gate insulating film between the gate insulating film and the gate electrode film.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device comprising a ferroelectric field effect transistor (FeFET) and a method for manufacturing the same. Background Technology

[0002] Ferroelectrics are materials that possess ferroelectricity, maintaining spontaneous polarization through the alignment of internal electric dipole moments even without the application of an external electric field. Furthermore, the polarization of a ferroelectric can be altered by applying an external electric field exceeding the critical coercive field, and this state can be electrically read through changes within adjacent materials such as metals and semiconductors. Consequently, research is continuously being conducted to improve performance by applying these properties of ferroelectrics to semiconductor devices.

[0003] In particular, with the discovery of the ferroelectricity of hafnium oxides, ferroelectric field-effect transistors (FeFETs) utilizing hafnium oxides are being developed. Since hafnium oxides are compatible with semiconductor processes and can maintain ferroelectricity even in very thin films, they are expected to contribute to the miniaturization of semiconductor devices. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device including a ferroelectric field-effect transistor (FeFET) with improved characteristics.

[0005] Another technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device including a ferroelectric field-effect transistor (FeFET) with improved characteristics.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate, a gate electrode film comprising a metal element on the substrate, a gate insulating film comprising a ferroelectric material between the substrate and the gate electrode film, and a buffer oxide film comprising an oxide of a semiconductor material in contact with the gate insulating film between the gate insulating film and the gate electrode film.

[0008] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate having a first semiconductor material, a gate electrode film having a metal element on the substrate, a gate insulating film having a ferroelectric material between the substrate and the gate electrode film, an interface film having an oxide of the first semiconductor material between the gate insulating film and the substrate, and a buffer oxide film having an oxide of the second semiconductor material between the gate insulating film and the gate electrode film, wherein the thickness of the interface film is smaller than the thickness of the buffer oxide film.

[0009] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate having a first semiconductor material, a gate electrode film having a metal element on the substrate, a gate insulating film having a ferroelectric material between the substrate and the gate electrode film, a buffer film having a second semiconductor material between the gate insulating film and the gate electrode film, and a buffer oxide film having an oxide of the second semiconductor material between the gate insulating film and the buffer film.

[0010] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate comprising silicon (Si), a gate electrode film comprising a metal element on the substrate, a gate insulating film comprising a hafnium-based oxide having ferroelectricity between the substrate and the gate electrode film, a buffer film comprising silicon (Si) between the gate insulating film and the gate electrode film, and a buffer oxide film comprising a silicon oxide film between the gate insulating film and the buffer film.

[0011] A method for manufacturing a semiconductor device according to some embodiments for achieving the above other technical objectives comprises providing a substrate comprising a first semiconductor material, forming a gate insulating film comprising a hafnium-based oxide having ferroelectricity on the substrate, forming a buffer film comprising a second semiconductor material on the gate insulating film, forming a gate electrode film comprising a metal element on the buffer film, and performing an annealing process.

[0012] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0013] FIG. 1 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. Figure 2 is an enlarged view to explain the R1 region of Figure 1. FIG. 3 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. Figure 4 is an enlarged view to explain the R1 region of Figure 3. FIG. 5 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. FIG. 6 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figures 7 and 8 are various schematic cross-sectional views cut along AA of Figure 6. FIG. 9 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figure 10 is a schematic cross-sectional view taken along BB of Figure 9. FIG. 11 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is a schematic cross-sectional view taken along CC of FIG. 11. Figure 13 is an enlarged view to explain the R2 region of Figure 12. FIG. 14 is an exemplary perspective view for illustrating a semiconductor device according to some embodiments. Figure 15 is an enlarged view to explain the R3 region of Figure 14. FIGS. 16 to 20 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 21 and FIGS. 22 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0014] In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0015] Hereinafter, a semiconductor device according to exemplary embodiments is described with reference to FIGS. 1 to 15.

[0016] FIG. 1 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. FIG. 2 is an enlarged view for illustrating the R1 region of FIG. 1.

[0017] Referring to FIGS. 1 and 2, a semiconductor device according to some embodiments includes a substrate (100), a first source / drain region (102), a first gate structure (GS1), a first interlayer insulating film (180), a source / drain contact (192), and a gate contact (194).

[0018] The substrate (100) may include a first semiconductor material. The first semiconductor material may include, for example, an elemental semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the first semiconductor material may include a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound in which a group IV element is doped therein. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0019] For example, the substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a base substrate on which an epitaxial layer is formed. For convenience of explanation, the substrate (100) is described below as a silicon substrate.

[0020] In some embodiments, the substrate (100) may comprise the first semiconductor material doped with an impurity element of the first conductivity type. For example, in the case where the semiconductor device according to some embodiments is an NFET, the substrate (100) may comprise silicon (Si) doped with p-type impurities (e.g., boron (B), aluminum (Al), indium (In), or gallium (Ga), etc.). Or, for example, in the case where the semiconductor device according to some embodiments is a PFET, the substrate (100) may comprise silicon (Si) doped with n-type impurities (e.g., phosphorus (P) or arsenic (As), etc.).

[0021] A first gate structure (GS1) may be formed on a substrate (100). In some embodiments, the first gate structure (GS1) may include a gate insulating film (120), a buffer oxide film (135), a buffer film (130), and a gate electrode film (140) that are stacked sequentially on the substrate (100).

[0022] A gate insulating film (120) may be laminated on a substrate (100). Additionally, the gate insulating film (120) may be interposed between the substrate (100) and the gate electrode film (140). The gate insulating film (120) may include a ferroelectric having hysteresis characteristics. For example, the gate insulating film (120) may include at least one of hafnium oxide, zirconium oxide, yttrium-doped zirconium oxide, yttrium-doped hafnium oxide, magnesium-doped zirconium oxide, magnesium-doped hafnium oxide, silicon-doped hafnium oxide, silicon-doped zirconium oxide, barium-doped titanium oxide, and combinations thereof.

[0023] In some embodiments, the gate insulating film (120) may comprise a hafnium-based oxide having ferroelectricity. For example, the gate insulating film (120) may comprise hafnium oxide (HfO2) doped with at least one element selected from silicon (Si), zirconium (Zr), yttrium (Y), strontium (Sr), lanthanum (La), gadolinium (Gd), and aluminum (Al). Such hafnium oxide may exhibit ferroelectricity by having an orthorhombic phase (O-phase).

[0024] In some embodiments, as illustrated in FIG. 2, an interface film (105) may be formed between the substrate (100) and the gate insulating film (120). The interface film (105) may include an oxide of the first semiconductor material of the substrate (100). For example, the interface film (105) may be an oxide film formed by oxidizing the surface (e.g., top surface) of the substrate (100) adjacent to the gate insulating film (120). For example, if the substrate (100) includes silicon (Si), the interface film (105) may include a silicon oxide film.

[0025] In some embodiments, the interface film (105) may be in contact with the gate insulating film (120). That is, the interface film (105) may be formed directly below the gate insulating film (120), and the substrate (100) may be formed directly below the interface film (105).

[0026] In some other embodiments, the interface film (105) may not exist between the substrate (100) and the gate insulating film (120). Here, the absence of the interface film (105) means not only that there is no interface film (105) between the substrate (100) and the gate insulating film (120), but also that there is a case where it exists in a negligible amount with a thickness below the measurement limit by transmission electron microscope (TEM) image analysis, etc.

[0027] The thickness (T1) of the interface film (105) may be less than about 1 nm. Preferably, the thickness (T1) of the interface film (105) may be about 5 Å or less. Within this range, the characteristics of the ferroelectric field effect transistor (FeFET) including the gate insulating film (120) may be improved. For example, the thickness (T1) of the interface film (105) may be about 0.01 Å to about 5 Å. More preferably, the thickness (T1) of the interface film (105) may be about 1 Å or less.

[0028] A buffer film (130) may be laminated on a gate insulating film (120). Additionally, the buffer film (130) may be interposed between the gate insulating film (120) and the gate electrode film (140). The buffer film (130) may include a second semiconductor material. The second semiconductor material may include, for example, an elemental semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the first semiconductor material may include a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element. The above III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb). For example, the buffer film (130) may include polysilicon or amorphous silicon.

[0029] The thickness (T3) of the buffer film (130) may be less than about 10 nm. Within this range, the degradation of the characteristics of the semiconductor device due to the buffer film (130) can be prevented. Preferably, the thickness (T3) of the buffer film (130) may be about 5 nm or less. For example, the thickness (T3) of the buffer film (130) may be about 0.01 nm to about 5 nm. More preferably, the thickness (T3) of the buffer film (130) may be about 1 nm or less.

[0030] In some embodiments, the first semiconductor material and the second semiconductor material may be identical to each other. For example, the substrate (100) and the buffer film (130) may each comprise silicon (Si).

[0031] In some embodiments, the coefficient of thermal expansion (CTE) of the buffer film (130) may be smaller than the coefficient of thermal expansion (CTE) of the gate insulating film (120). For example, when the gate insulating film (120) contains hafnium-based oxide, the buffer film (130) may contain silicon (Si). Such a buffer film (130) can increase the ferroelectricity of the gate insulating film (120) by applying mechanical stress to the gate insulating film (120). For example, the buffer film (130) can induce the crystallographic structure of the gate insulating film (120) containing hafnium-based oxide to an orthorhombic phase during an annealing process for the gate insulating film (120).

[0032] A buffer oxide film (135) may be formed between the gate insulating film (120) and the buffer film (130). The buffer oxide film (135) may include an oxide of the second semiconductor material of the buffer film (130). For example, the buffer oxide film (135) may be an oxide film formed by oxidizing the surface (e.g., bottom surface) of the buffer film (130) adjacent to the gate insulating film (120). For example, if the buffer film (130) contains silicon (Si), the buffer oxide film (135) may include a silicon oxide film.

[0033] In some embodiments, the buffer oxide film (135) may be in contact with the gate insulating film (120). That is, the buffer oxide film (135) may be formed directly on the gate insulating film (120), and the buffer film (130) may be formed directly on the buffer oxide film (135).

[0034] In some embodiments, the thickness (T1) of the interface film (105) may be smaller than the thickness (T2) of the buffer oxide film (135). Preferably, the thickness (T2) of the buffer oxide film (135) may be about 5 Å or more. For example, the thickness (T2) of the buffer oxide film (135) may be about 5 Å to about 15 Å.

[0035] In some embodiments, the sum (T1+T2) of the thickness (T1) of the interface film (105) and the thickness (T2) of the buffer oxide film (135) may be about 5 Å to about 15 Å.

[0036] A gate electrode film (140) may be laminated on a buffer film (130). The gate electrode film (140) may include a metal element. For example, the gate electrode film (140) may include a metal film or a conductive metal nitride film. For example, the gate electrode film (140) may include at least one of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), and combinations thereof, but is not limited thereto.

[0037] In some embodiments, the coefficient of thermal expansion (CTE) of the gate electrode film (140) may be smaller than the coefficient of thermal expansion (CTE) of the gate insulating film (120). For example, when the gate insulating film (120) comprises a hafnium-based oxide, the gate electrode film (140) may comprise at least one of tungsten (W) and titanium nitride (TiN). Such a gate electrode film (140) can increase the ferroelectricity of the gate insulating film (120) by applying mechanical stress to the gate insulating film (120). For example, the gate electrode film (140) can induce the crystallographic structure of the gate insulating film (120) to be orthorhombic during an annealing process for the gate insulating film (120).

[0038] Although the gate electrode film (140) is illustrated as being a single film, this is merely exemplary. Unlike illustrated, the gate electrode film (140) may be formed by stacking multiple conductive materials. For example, the gate electrode film (140) may include a work function control film that controls the work function and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0039] In some embodiments, the first gate structure (GS1) may further include a gate spacer (160). The gate spacer (160) may cover the side of the gate electrode film (140). For example, the gate spacer (160) may extend along the side of the gate insulating film (120), the side of the buffer oxide film (135), the side of the buffer film (130), and the side of the gate electrode film (140). The gate spacer (160) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0040] The first source / drain region (102) may be formed within (or on the substrate (100) on the side of the first gate structure (GS1). The first source / drain region (102) may be an impurity region formed by injecting impurities into the substrate (100), or it may be an epitaxial layer formed on the substrate (100).

[0041] The first source / drain region (102) may have a second conductivity type different from the first conductivity type. For example, if the semiconductor device according to some embodiments is an NFET, the first source / drain region (102) may include n-type impurities or impurities to prevent the diffusion of n-type impurities. For example, the first source / drain region (102) may include at least one of P, Sb, As, or a combination thereof. Or, for example, if the semiconductor device according to some embodiments is a PFET, the first source / drain region (102) may include p-type impurities or impurities to prevent the diffusion of p-type impurities. For example, the first source / drain region (102) may include at least one of B, C, In, Ga, and Al, or a combination thereof.

[0042] The above-described substrate (100), first source / drain region (102), and first gate structure (GS1) can form a ferroelectric field-effect transistor (FeFET). In this specification, the region of the substrate (100) forming the ferroelectric field-effect transistor may also be referred to as an active region (or active pattern).

[0043] A first interlayer insulating film (180) may be formed on a substrate (100). The first interlayer insulating film (180) may cover a first gate structure (GS1) and a first source / drain region (102). The first interlayer insulating film (180) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide. The above low dielectric constant material may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof, but is not limited thereto.

[0044] The source / drain contact (192) can be connected to the first source / drain region (102). For example, the source / drain contact (192) can be connected to the first source / drain region (102) by penetrating the first interlayer insulating film (180).

[0045] The gate contact (194) can be connected to the gate electrode film (140). For example, the gate contact (194) can be connected to the gate electrode film (140) by penetrating the first interlayer insulating film (180).

[0046] The source / drain contact (192) and the gate contact (194) may each include at least one of a conductive material, for example, a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride and a conductive metal oxide and a two-dimensional (2D) material, but are not limited thereto.

[0047] FIG. 3 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. FIG. 4 is an enlarged view for illustrating the R1 region of FIG. 3. For convenience of explanation, parts that overlap with those described above using FIG. 1 and FIG. 2 are briefly described or omitted.

[0048] Referring to FIGS. 3 and 4, in a semiconductor device according to some embodiments, a first gate structure (GS1) may include a gate insulating film (120), a buffer oxide film (135), and a gate electrode film (140) that are stacked sequentially on a substrate (100).

[0049] For example, the buffer oxide film (135) may be in contact with the gate electrode film (140). That is, the buffer oxide film (135) may be formed directly on the gate insulating film (120), and the gate electrode film (140) may be formed directly on the buffer oxide film (135). Alternatively, for example, using FIGS. 1 and 2, the buffer film (130) described above may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0050] In some embodiments, as shown in FIG. 4, an interface film (105) may be formed between the substrate (100) and the gate insulating film (120). In some embodiments, the thickness (T1) of the interface film (105) may be smaller than the thickness (T2) of the buffer oxide film (135).

[0051] FIG. 5 is an exemplary cross-sectional view for illustrating a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 and FIG. 2 are briefly described or omitted.

[0052] Referring to FIG. 5, in a semiconductor device according to some embodiments, the gate insulating film (120), the buffer oxide film (135) and the buffer film (130) may each be further extended along the inner surface of the gate spacer (160).

[0053] For example, the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may each be conformally extended along the upper surface of the substrate (100) and the inner surface of the gate spacer (160). The first gate structure (GS1) comprising the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may be formed, for example, by a replacement process, but is not limited thereto.

[0054] FIG. 6 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 7 and FIG. 8 are various schematic cross-sectional views cut along AA of FIG. 6. For convenience of explanation, parts that overlap with those described above using FIG. 1 through 5 are briefly described or omitted.

[0055] Referring to FIGS. 6 to 8, a semiconductor device according to some embodiments includes a substrate (100), a first active pattern (AP1), a field insulating film (115), and a second gate structure (GS2).

[0056] A first active pattern (AP1) may be formed on a substrate (100). The first active pattern (AP1) may extend in a first direction (X1) parallel to the upper surface of the substrate (100). The first active pattern (AP1) may be part of the substrate (100) or may include an epitaxial layer grown from the substrate (100). The first active pattern (AP1) may include, for example, silicon or germanium, which are elemental semiconductor materials. Alternatively, the first active pattern (AP1) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0057] A field insulating film (115) may be formed on a substrate (100). The field insulating film (115) may cover at least a portion of the side of the first active pattern (AP1). The field insulating film (115) may comprise, for example, at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or a combination thereof, but is not limited thereto.

[0058] A second gate structure (GS2) can be formed on a first active pattern (AP1) and a field insulating film (115). Additionally, the second gate structure (GS2) may intersect with the first active pattern (AP1). For example, the second gate structure (GS2) may extend in a second direction (Y1) that intersects a first direction (X1) while being parallel to the upper surface of the substrate (100).

[0059] In some embodiments, the second gate structure (GS2) may include a gate insulating film (120), a buffer oxide film (135), a buffer film (130), and a gate electrode film (140) that are sequentially stacked on the first active pattern (AP1). By doing so, the first active pattern (AP1) and the second gate structure (GS2) can form a ferroelectric field-effect transistor (FeFET) that forms a channel along a first direction (X1).

[0060] Although not specifically illustrated, an interface film (105 in FIG. 2) may be formed between the first active pattern (AP1) and the gate insulating film (120). Alternatively, unlike illustrated, the buffer film (130) may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0061] Referring to FIGS. 6 and FIGS. 7, in a semiconductor device according to some embodiments, a first active pattern (AP1) may include a fin pattern.

[0062] For example, the first active pattern (AP1) may be extended in the first direction (X1) by protruding from the upper surface of the substrate (100) (e.g., protruding in a third direction (Z1) intersecting the first direction (X1) and the second direction (Y1). The second gate structure (GS2) may be extended along three sides (e.g., both sides and the upper surface) of the first active pattern (AP1) having a pin shape. For example, the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may each be extended conformally along both sides and the upper surface of the first active pattern (AP1).

[0063] In some embodiments, the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may be further extended along the upper surface of the field insulating film (115).

[0064] Referring to FIGS. 6 and FIGS. 8, in a semiconductor device according to some embodiments, a first active pattern (AP1) may include a plurality of sheet patterns.

[0065] For example, the first active pattern (AP1) may include first to third sheet patterns (SP1, SP2, SP3) that are spaced apart from each other and arranged along the third direction (Z1). The first to third sheet patterns (SP1, SP2, SP3) may each extend in the first direction (X1) and penetrate the second gate structure (GS2). For example, the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may each extend conformally along the perimeter of the first to third sheet patterns (SP1, SP2, SP3).

[0066] In some embodiments, the first active pattern (AP1) may further include a pin pattern (FP) that protrudes from the upper surface of the substrate (100) and extends in a first direction (X1). The first to third sheet patterns (SP1, SP2, SP3) may be arranged in sequence on the upper surface of the pin pattern (FP).

[0067] In some embodiments, the gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may be further extended along the upper surface of the pin pattern (FP) and the upper surface of the field insulating film (115).

[0068] FIG. 9 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 10 is a schematic cross-sectional view taken along BB of FIG. 9. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 5 are briefly described or omitted.

[0069] Referring to FIGS. 9 and 10, a semiconductor device according to some embodiments includes a substrate (100), a lower source / drain region (102B), a spacer pattern (116), a second active pattern (AP2), a third gate structure (GS3), and an upper source / drain region (102U).

[0070] The lower source / drain region (102B) may be formed on the substrate (100). The lower source / drain region (102B) may be an impurity region formed by injecting impurities into the substrate (100), or it may be an epitaxial layer formed on the substrate (100).

[0071] The lower source / drain region (102B) may have the second conductivity type. For example, if the semiconductor device according to some embodiment is an NFET, the lower source / drain region (102B) may contain n-type impurities or impurities to prevent the diffusion of n-type impurities. Or, for example, if the semiconductor device according to some embodiment is a PFET, the lower source / drain region (102B) may contain p-type impurities or impurities to prevent the diffusion of p-type impurities.

[0072] The spacer pattern (116) may cover a portion of the lower source / drain region (102B). Another portion of the lower source / drain region (102B) may be exposed by the spacer pattern (116). The lower source / drain region (102B) exposed by the spacer pattern (116) may include, for example, a long side extending in the fourth direction (X2) and a short side extending in the fifth direction (Y2), but is not limited thereto. Only the upper surface of the spacer pattern (116) is shown to be positioned in a co-plane with the upper surface of the lower source / drain region (102B), but this is merely exemplary. The spacer pattern (116) may include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0073] A second active pattern (AP2) may be formed on the lower source / drain region (102B). For example, the second active pattern (AP2) may be connected to the upper surface of the lower source / drain region (102B). The second active pattern (AP2) may extend from the lower source / drain region (102B) exposed from the spacer pattern (116) into a sixth direction (Z2) that intersects the fourth direction (X2) and the fifth direction (Y2).

[0074] A third gate structure (GS3) may be formed on a spacer pattern (116). Additionally, the third gate structure (GS3) may be formed on the side of the second active pattern (AP2). For example, the third gate structure (GS3) may surround the side of the second active pattern (AP2).

[0075] An upper source / drain region (102U) may be formed on the second active pattern (AP2). For example, the upper source / drain region (102U) may be connected to the upper surface of the second active pattern (AP2). That is, the second active pattern (AP2) may be interposed between the lower source / drain region (102B) and the upper source / drain region (102U).

[0076] The upper source / drain region (102U) may have the second conductivity type. For example, if the semiconductor device according to some embodiment is an NFET, the upper source / drain region (102U) may contain n-type impurities or impurities to prevent the diffusion of n-type impurities. Or, for example, if the semiconductor device according to some embodiment is a PFET, the upper source / drain region (102U) may contain p-type impurities or impurities to prevent the diffusion of p-type impurities.

[0077] In some embodiments, the third gate structure (GS3) may include a gate insulating film (120), a buffer oxide film (135), a buffer film (130), and a gate electrode film (140) that are sequentially stacked on the side of the second active pattern (AP2). Thus, the second active pattern (AP2), the second gate structure (GS2), the lower source / drain region (102B), and the upper source / drain region (102U) can form a ferroelectric field-effect transistor (FeFET) that forms a channel along the sixth direction (Z2). In some embodiments, the gate insulating film (120), the buffer film (130), the buffer oxide film (135), and the gate electrode film (140) may be further extended along the upper surface of the spacer pattern (116).

[0078] Although not specifically illustrated, an interface film (105 in FIG. 2) may be formed between the second active pattern (AP2) and the gate insulating film (120). Alternatively, unlike illustrated, the buffer film (130) may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0079] FIG. 11 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is a schematic cross-sectional view taken along CC of FIG. 11. FIG. 13 is an enlarged view for illustrating the R2 region of FIG. 12. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 5 are briefly described or omitted.

[0080] Referring to FIGS. 11 to 13, a semiconductor device according to some embodiments includes a substrate (100), a device isolation layer (117), a second source / drain region (104), a word line (WL), a bit line (BL), a bit line contact (DC), a capacitor structure (290), and a capacitor contact (CP).

[0081] The device isolation layer (117) can define a plurality of third active patterns (AP3) within the substrate (100). The device isolation layer (117) may include at least one of an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0082] The third active pattern (AP3) may extend in a seventh direction (W) within the substrate (100). The third active pattern (AP3) may be in the form of multiple bars extending in directions parallel to each other. In some embodiments, the center of one third active pattern (AP3) may be positioned adjacent to the end of another third active pattern (AP3).

[0083] The second source / drain region (104) may be formed within the third active pattern (AP3). The second source / drain region (104) may be an impurity region formed by injecting impurities into the substrate (100), or it may be an epitaxial layer formed on the substrate (100). The second source / drain region (104) may have the second conductivity type.

[0084] A word line (WL) can be formed on a substrate (100) and a device isolation layer (117). The word line (WL) can be extended in a seventh direction (W) and an eighth direction (X3) different from the seventh direction (W). Additionally, the word line (WL) can cross a third active pattern (AP3) between a bit line contact (DC) and a capacitor contact (CP). For example, the word line (WL) can cross the third active pattern (AP3) obliquely and cross the bit line (BL) vertically. A plurality of word lines (WL) can be extended parallel to each other and spaced apart from each other at equal intervals.

[0085] In some embodiments, the word line (WL) may correspond to the gate electrode film (140) described above using FIGS. 1 and FIGS. 2. For example, a gate insulating film (120), a buffer oxide film (135), and a buffer film (130) may be interposed between the third active pattern (AP3) and the word line (WL). The gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may be stacked sequentially on the third active pattern (AP3).

[0086] As illustrated in FIG. 13, an interface film (105 in FIG. 2) may be formed between the second active pattern (AP2) and the gate insulating film (120). Alternatively, unlike illustrated, the buffer film (130) may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0087] In some embodiments, the word line (WL) may be embedded within the substrate (100). For example, the substrate (100) may include a gate trench (100t) extending in the eighth direction (X3). The gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may extend along the profile of the gate trench (100t). The gate electrode film (140; or word line (WL)) may fill at least a portion of the gate trench (100t) on the buffer film (130; or buffer oxide film (135)). By doing so, the third active pattern (AP3), the word line (WL), and the second source / drain region (104) may form a ferroelectric field-effect transistor (FeFET) comprising a channel formed along the profile of the gate trench (100t).

[0088] In some embodiments, a capping pattern (145) may be formed on a gate electrode film (140; or word line (WL)). The capping pattern (145) may extend along the upper surface of the gate electrode film (140). For example, the capping pattern (145) may fill another portion of the gate trench (100t) on the gate electrode film (140). In this case, the upper surface of the gate electrode film (140) may be formed lower than the upper surface of the third active pattern (AP3). The capping pattern (145) may comprise an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0089] A bit line (BL) can be formed on a substrate (100) and a device isolation layer (117). For example, a second interlayer insulating layer (282) covering the substrate (100), the device isolation layer (117), and the capping pattern (145) can be formed. A bit line (BL) can be formed on the second interlayer insulating layer (282). The bit line (BL) can be extended in a tenth direction (Z3) different from the seventh direction (W) and the eighth direction (X3). For example, the bit line (BL) can cross the third active pattern (AP3) obliquely and cross the word line (WL) vertically. A plurality of bit lines (BL) can be extended parallel to each other and spaced apart from each other at equal intervals.

[0090] In some embodiments, the bit line (BL) may include a first conductive line (242), a second conductive line (244), and a third conductive line (246) that are sequentially stacked on a third active pattern (AP3). The first conductive line (242), the first conductive line (244), and the third conductive line (246) may each include a conductive material, for example, at least one of polysilicon, TiN, TiSiN, tungsten, tungsten silicide, and combinations thereof, but are not limited thereto. For example, the first conductive line (242) may include polysilicon, the first conductive line (244) may include TiSiN, and the third conductive line (246) may include tungsten.

[0091] A bit line contact (DC) can connect the third active pattern (AP3) and the bit line (BL). For example, the bit line contact (DC) can electrically connect the third active pattern (AP3) and the bit line (BL) by penetrating the second interlayer insulating film (282). In some embodiments, the bit line contact (DC) can be connected to the center of the third active pattern (AP3).

[0092] A capacitor structure (290) may be formed on a substrate (100) and a device isolation film (117). For example, a third interlayer insulating film (284) and a fourth interlayer insulating film (286) may be formed by sequentially stacking on a second interlayer insulating film (282). A capacitor structure (290) may be formed on the fourth interlayer insulating film (286).

[0093] The capacitor structure (290) can store data by being controlled by a word line (WL) and a bit line (BL). For example, the capacitor structure (290) may include a lower electrode (292), a capacitor dielectric film (294), and an upper electrode (296) that are stacked sequentially on a fourth interlayer insulating film (286). The capacitor structure (290) can store charge (i.e., data) within the capacitor dielectric film (294) by utilizing the potential difference generated between the lower electrode (292) and the upper electrode (296).

[0094] The lower electrode (292) and the upper electrode (296) may comprise, for example, doped polysilicon, a metal, or a metal nitride, but are not limited thereto. Additionally, the capacitor dielectric film (294) may comprise, for example, silicon oxide or a high dielectric constant material, but is not limited thereto.

[0095] A capacitor contact (CP) can connect the third active pattern (AP3) and the capacitor structure (290). For example, the capacitor contact (CP) can electrically connect the third active pattern (AP3) and the lower electrode (292) by penetrating the second interlayer insulating film (282), the third interlayer insulating film (284), and the fourth interlayer insulating film (286). In some embodiments, the capacitor contact (CP) can be connected to both ends of the third active pattern (AP3).

[0096] FIG. 14 is an exemplary perspective view for illustrating a semiconductor device according to some embodiments. FIG. 15 is an enlarged view for illustrating the R3 region of FIG. 14. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 5 are briefly described or omitted.

[0097] Referring to FIGS. 14 and 15, a semiconductor device according to some embodiments includes a substrate (100), a mold structure (MS), and a vertical structure (VC).

[0098] The mold structure (MS) may include a plurality of mold insulating films (310) and a plurality of gate electrode films (140) that are alternately stacked on a substrate (100). The mold insulating films (310) and the gate electrode films (140) may each be layered structures extending parallel to the upper surface of the substrate (100). The gate electrode films (140) may be stacked sequentially on the substrate (100) while being spaced apart from each other by the mold insulating films (310).

[0099] The mold insulating film (310) may include at least one of an insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, the mold insulating film (310) may include a silicon oxide film.

[0100] A vertical structure (VC) can be formed on a substrate (100). The vertical structure (VC) can extend in a direction intersecting the upper surface of the substrate (100) (e.g., vertical direction) and penetrate the mold structure (MS). For example, the vertical structure (VC) may be a pillar-shaped structure (e.g., cylindrical shape) extending in the vertical direction.

[0101] The vertical structure (VC) may include a fourth active pattern (AP4). The fourth active pattern (AP4) may extend in the vertical direction and intersect with a plurality of gate electrode films (140). For example, the fourth active pattern (AP4) may have various shapes, such as a cup shape, a cylinder shape, a rectangular shape, or a solid filler shape. The fourth active pattern (AP4) may include semiconductor materials such as, for example, single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0102] In some embodiments, a gate insulating film (120), a buffer oxide film (135), and a buffer film (130) may be interposed between the fourth active pattern (AP4) and the gate electrode film (140). The gate insulating film (120), the buffer oxide film (135), and the buffer film (130) may be stacked sequentially on the outer surface of the fourth active pattern (AP4). By doing so, the fourth active pattern (AP4) and the gate electrode film (140) can form a plurality of ferroelectric field-effect transistors (FeFETs) arranged along the vertical direction.

[0103] As illustrated in FIG. 15, an interface film (105 in FIG. 2) may be formed between the fourth active pattern (AP4) and the gate insulating film (120). Alternatively, unlike illustrated, the buffer film (130) may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0104] In some embodiments, the vertical structure (VC) may further include a filling pattern (315). The filling pattern (315) may be formed to fill the interior of, for example, a cup-shaped fourth active pattern (AP4). The filling pattern (315) may include an insulating material, for example, silicon oxide, but is not limited thereto.

[0105] Hereinafter, a method for manufacturing a semiconductor device according to exemplary embodiments is described with reference to FIGS. 16 to 22.

[0106] FIGS. 16 to 20 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 15 are briefly explained or omitted.

[0107] Referring to FIGS. 16 and 17, a gate insulating film (120) is formed on a substrate (100). For reference, FIG. 17 is an enlarged view to illustrate the R1 region of FIG. 16.

[0108] The substrate (100) may include a first semiconductor material. For example, the first semiconductor material may be silicon (Si). In some embodiments, the substrate (100) may include the first semiconductor material doped with an impurity element of the first conductivity type.

[0109] The gate insulating film (120) may be deposited, for example, by an atomic layer deposition (ALD) method, but is not limited thereto. The gate insulating film (120) may include ferroelectrics having hysteresis characteristics. In some embodiments, the gate insulating film (120) may include hafnium-based oxides having ferroelectricity.

[0110] As a gate insulating film (120) is formed on a substrate (100), an interface film (105) may be formed between the substrate (100) and the gate insulating film (120). The interface film (105) may be a natural oxide film formed by the oxidation of the surface (e.g., upper surface) of the substrate (100) adjacent to the gate insulating film (120). For example, the interface film (105) may be formed by oxygen atoms contained in the gate insulating film (120) diffusing into the substrate (100). The thickness (T4) of the interface film (105) may be, for example, about 5 Å to about 15 Å.

[0111] Referring to FIG. 18, a buffer film (130) and a gate electrode film (140) are formed sequentially on a gate insulating film (120).

[0112] A buffer film (130) may be laminated on a gate insulating film (120). In some embodiments, the buffer film (130) may be laminated directly on top of the gate insulating film (120). The buffer film (130) may include a second semiconductor material. For example, the second semiconductor material may be silicon (Si). In some embodiments, the first semiconductor material and the second semiconductor material may be the same.

[0113] The thickness (T5) of the buffer film (130) may be less than about 10 nm. Within this range, the degradation of the characteristics of the semiconductor device due to the buffer film (130) can be prevented. Preferably, the thickness (T5) of the buffer film (130) may be about 5 nm or less. For example, the thickness (T5) of the buffer film (130) may be about 0.01 nm to about 5 nm. More preferably, the thickness (T3) of the buffer film (130) may be about 1 nm or less.

[0114] A gate electrode film (140) may be laminated on a buffer film (130). In some embodiments, the gate electrode film (140) may be laminated directly on top of the buffer film (130). The gate electrode film (140) may contain a metal element. For example, the gate electrode film (140) may contain a metal film or a conductive metal nitride film.

[0115] Referring to FIGS. 19 and 20, an annealing process is performed. Through this, the semiconductor device described above can be manufactured using FIGS. 1 and 2.

[0116] The annealing process described above may include, for example, a Rapid Thermal Annealing (RTA) process, but is not limited thereto. As the annealing process is performed, the thickness of the interface film (105) may be reduced or removed. Specifically, oxygen atoms contained in the interface film (105) may move to the buffer film (130) through the gate insulating film (120) during the annealing process. The oxygen atoms moved to the buffer film (130) may form a buffer oxide film (135) between the gate insulating film (120) and the buffer film (130).

[0117] This can be understood as an equilibrium of oxygen atoms between the interface film (105) and the buffer film (130) through the gate insulating film (120). For example, since hafnium atoms included in the gate insulating film (120) have a higher coordination number compared to silicon atoms included in the interface film (105), hafnium atoms on the surface of the gate insulating film (120) adjacent to the interface film (105) can additionally bond with oxygen atoms. The additionally bonded oxygen atoms are in equilibrium with oxygen atoms forming a crystal structure within the gate insulating film (120) and can be transported toward the buffer film (130), which has a relatively lower oxygen atom concentration. That is, due to the presence of the buffer film (130), at least a portion of the interface film (105) can be lost during the annealing process.

[0118] The thickness (T1) of the decelerated interface film (105) may be less than about 1 nm. Preferably, the thickness (T1) of the interface film (105) may be about 5 Å or less. Within this range, the characteristics of the ferroelectric field-effect transistor (FeFET) including the gate insulating film (120) may be improved. For example, as the process variables of the annealing process are adjusted, the thickness (T1) of the interface film (105) may be controlled to about 0.01 Å to about 5 Å. More preferably, the thickness (T1) of the interface film (105) may be about 1 Å or less.

[0119] In some embodiments, the thickness (T1) of the reduced interface film (105) may be smaller than the thickness (T2) of the buffer oxide film (135). For example, as the substrate (100) contains impurity elements, the thickness (T1) of the reduced interface film (105) may be smaller than the thickness (T2) of the buffer oxide film (135) formed. In some embodiments, the sum (T1+T2) of the thickness (T1) of the interface film (105) and the thickness (T2) of the buffer oxide film (135) may be about 5 Å to about 15 Å.

[0120] In some other embodiments, the interface film (105) may not exist between the substrate (100) and the gate insulating film (120). Here, the absence of the interface film (105) means not only that there is no interface film (105) between the substrate (100) and the gate insulating film (120) at all, but also that there is a case where it exists only in a negligible amount with a thickness below the measurement limit by transmission electron microscope (TEM) image analysis, etc. For example, as the process variables of the annealing process are adjusted, the interface film (105) may be completely lost.

[0121] In some embodiments, as the annealing process is performed, the ferroelectricity of the gate insulating film (120) may be increased. For example, the buffer film (130) and the gate electrode film (140) may induce the crystallographic structure of the gate insulating film (120), which includes hafnium oxide, to an orthorhombic phase by applying mechanical stress to the gate insulating film (120) during the annealing process.

[0122] Research is ongoing to improve the performance of semiconductor devices by applying the properties of ferroelectrics. In particular, following the discovery of the ferroelectricity of hafnium oxides, ferroelectric field-effect transistors (FeFETs) utilizing hafnium oxides as gate insulators are being developed. Since hafnium oxides are compatible with semiconductor processes and can maintain ferroelectricity even in very thin films, they are expected to contribute to the miniaturization of semiconductor devices.

[0123] However, the interface film that naturally occurs during the process of forming the gate insulating film causes a degradation of the characteristics of the ferroelectric field effect transistor (FeFET). For example, during the process of depositing a gate insulating film (120) containing hafnium oxide, oxygen atoms contained in the gate insulating film (120) diffuse into the substrate (100) and form an interface film (105) of about 1 nm between the substrate (100) and the gate insulating film (120). This interface film (105) causes charge trapping and breakdown, etc., thereby degrading the characteristics of the semiconductor device including the ferroelectric field effect transistor (FeFET), such as durability (e.g., program / erase cycling endurance) and memory window.

[0124] In contrast, a semiconductor device according to some embodiments may have improved characteristics by eliminating at least a portion of the interface film (105). Specifically, as described above, due to the presence of a buffer film (130) formed on the gate insulating film (120), at least a portion of the interface film (105) formed between the substrate (100) and the gate insulating film (120) may be eliminated (e.g., controlled to a thickness of about 5 Å or less, or eliminated to a thickness below a measurement limit by transmission electron microscope (TEM) image analysis, etc.). Through this, a semiconductor device including a ferroelectric field-effect transistor (FeFET) with improved characteristics such as durability and memory window, and a method for manufacturing the same may be provided.

[0125] FIGS. 21 and 22 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 20 are briefly explained or omitted. For reference, FIG. 21 is an intermediate step drawing for explaining steps after FIG. 17.

[0126] Referring to FIG. 21, a buffer film (130) and a gate electrode film (140) are formed sequentially on a gate insulating film (120). Since forming the buffer film (130) and the gate electrode film (140) may be similar to that described above using FIG. 18, a detailed description is omitted below.

[0127] In some embodiments, the thickness (T6) of the buffer film (130) may be formed to be relatively thin, such as about 15 Å or less. For example, the thickness (T6) of the buffer film (130) may be about 1 Å to about 15 Å. Preferably, the thickness (T6) of the buffer film (130) may be about 1 Å to about 10 Å.

[0128] Referring to FIG. 22, an annealing process is performed. Through this, the semiconductor device described above using FIG. 3 and FIG. 4 can be manufactured. Since performing the annealing process may be similar to that described above using FIG. 19 and FIG. 20, a detailed description is omitted below.

[0129] As the above annealing process is performed, the thickness of the interface film (105) may be reduced or removed. Additionally, a buffer oxide film (135) may be formed between the gate insulating film (120) and the gate electrode film (140). For example, as the buffer film (130) of FIG. 21 is formed relatively thinly, the entire buffer film (130) may be oxidized to form a buffer oxide film (135). In this case, the buffer film (130) may not be interposed between the buffer oxide film (135) and the gate electrode film (140).

[0130] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0131] 100: Substrate 102: First source / drain region 105: Interface film 120: Gate insulating film 130: Buffer film 135: Buffer oxide film 140: Gate electrode film 160: Gate spacer 180: First interlayer insulating film 192: Source / drain contact 194: Gate Contact

Claims

Claim 1 A semiconductor device comprising: a substrate; a gate electrode film comprising a metal element on the substrate; a gate insulating film comprising a ferroelectric material between the substrate and the gate electrode film; a buffer oxide film comprising an oxide of a semiconductor material in contact with the gate insulating film between the gate insulating film and the gate electrode film; and a buffer film comprising silicon between the buffer oxide film and the gate electrode film. Claim 2 A semiconductor device according to claim 1, wherein the gate insulating film comprises a hafnium-based oxide having ferroelectricity. Claim 3 A semiconductor device according to claim 1, wherein the gate electrode film comprises at least one of tungsten and titanium nitride. Claim 4 A semiconductor device according to claim 1, wherein the substrate comprises silicon (Si) and the buffer oxide film comprises a silicon oxide film. Claim 5 A semiconductor device according to claim 4, further comprising a buffer film containing silicon (Si) between the buffer oxide film and the gate electrode film. Claim 6 A semiconductor device according to claim 1, further comprising an interface film between the substrate and the gate insulating film, wherein the interface film comprises an oxide of a semiconductor material included in the substrate. Claim 7 A semiconductor device according to claim 6, wherein the substrate comprises silicon (Si) and the interface film comprises a silicon oxide film. Claim 8 A semiconductor device according to claim 1, wherein the thickness of the buffer oxide film is 5 Å to 15 Å. Claim 9 A semiconductor device comprising: a substrate including a first semiconductor material; a gate electrode film including a metal element on the substrate; a gate insulating film including a ferroelectric between the substrate and the gate electrode film; an interface film including an oxide of the first semiconductor material between the gate insulating film and the substrate; a buffer oxide film including an oxide of a second semiconductor material between the gate insulating film and the gate electrode film; and a buffer film including a second semiconductor material between the buffer oxide film and the gate electrode film, wherein the thickness of the interface film is smaller than the thickness of the buffer oxide film. Claim 10 A semiconductor device according to claim 9, wherein the gate insulating film comprises a hafnium-based oxide having ferroelectricity. Claim 11 In claim 9, the first semiconductor material and the second semiconductor material are identical to each other, forming a semiconductor device. Claim 12 In claim 9, the semiconductor device wherein the buffer oxide film is in contact with the gate insulating film. Claim 13 A semiconductor device according to claim 9, wherein the thickness of the buffer oxide film is 5 Å to 1.5 Å. Claim 14 A semiconductor device according to claim 9, wherein the thickness of the interface film is 5 Å or less. Claim 15 In claim 9, the semiconductor device wherein the gate electrode film is in contact with the buffer oxide film. Claim 16 A semiconductor device comprising: a substrate comprising a first semiconductor material; a gate electrode film comprising a metal element on the substrate; a gate insulating film comprising a ferroelectric between the substrate and the gate electrode film; a buffer film comprising a second semiconductor material between the gate insulating film and the gate electrode film; and a buffer oxide film comprising an oxide of the second semiconductor material between the gate insulating film and the buffer film. Claim 17 A semiconductor device comprising: a substrate containing silicon (Si); a gate electrode film containing a metal element on the substrate; a gate insulating film containing a hafnium-based oxide having ferroelectricity between the substrate and the gate electrode film; a buffer film containing silicon (Si) between the gate insulating film and the gate electrode film; and a buffer oxide film containing a silicon oxide film between the gate insulating film and the buffer film. Claim 18 A semiconductor device according to claim 17, further comprising an interface film comprising a silicon oxide film between the substrate and the gate insulating film. Claim 19 A semiconductor device according to claim 18, wherein the thickness of the interface film is smaller than the thickness of the buffer oxide film. Claim 20 A method for manufacturing a semiconductor device comprising providing a substrate comprising a first semiconductor material, forming a gate insulating film comprising a hafnium-based oxide having ferroelectricity on the substrate, forming a buffer film comprising a second semiconductor material on the gate insulating film, forming a gate electrode film comprising a metal element on the buffer film, and performing an annealing process.

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