Semiconductor device having dummy pads and method for forming the same

Abstract

In a specific embodiment, the semiconductor device comprises a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure. The dielectric structure, the interconnect structure, and the dummy pad are overlaid.

Description

Background Technology

[0001] The present disclosure relates to a three-dimensional (3D) memory device and a method for manufacturing the same.

[0002] Electrostatic Discharge (ESD) refers to the sudden release of static electricity. ESD can occur when a charged body comes into contact with an electronic device. For example, if semiconductor devices are not protected against ESD during the manufacturing and packaging processes, the devices may be damaged. One way to prevent damage caused by ESD is to use ESD protection circuits (also known as ESD circuits) that divert the flow of ESD current by providing a low-impedance path.

[0003] In one embodiment, a semiconductor device comprises a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure. The dielectric structure, the interconnect structure, and the dummy pad are overlaid.

[0004] In some embodiments, the semiconductor device further includes a semiconductor layer between a dummy pad and an interconnect structure. In some embodiments, the dielectric structure includes an insulating structure within the semiconductor layer.

[0005] In some embodiments, the lateral dimensions of the insulating structure are larger than the lateral dimensions of the dummy pad.

[0006] In some embodiments, the semiconductor device further includes a first via contact that is in contact with an interconnect structure and separated from a dummy pad by an insulating structure.

[0007] In some embodiments, the first via contact comprises tungsten.

[0008] In some embodiments, the semiconductor device further includes a second via contact that contacts a dummy pad and extends in a vertical direction. In some embodiments, the dielectric structure includes a dielectric layer between the second via contact and the interconnect structure.

[0009] In some embodiments, the second via contact is separated from the interconnect structure by a dielectric layer.

[0010] In some embodiments, the second via contact comprises tungsten.

[0011] In some embodiments, the semiconductor device further includes a bonding interface between a dummy pad and a device layer. In some embodiments, the interconnect structure includes a bonding contact in the bonding interface.

[0012] In some embodiments, the interconnect structure further includes a device contact connecting the bonding interface and the device layer.

[0013] In some embodiments, the semiconductor device further includes a pad, another second via contact in contact with the pad, another first via contact in contact with the other second via contact, and another interconnect structure in contact with the other first via contact and the device layer.

[0014] In some embodiments, the pad and the dummy pad are in the same plane, and the interconnect structure and another interconnect structure are in the same plane.

[0015] In another embodiment, the semiconductor device comprises a device layer including an electrostatic discharge (ESD) circuit and a functional circuit, a dummy pad separated from the functional circuit, and an interconnection structure between the device layer and the dummy pad. The dummy pad is connected to the ESD circuit through at least the interconnection structure.

[0016] In some embodiments, the semiconductor device further includes a first via contact connected to an interconnection structure between a dummy pad and an interconnection structure.

[0017] In some embodiments, the semiconductor device further includes a semiconductor layer between a dummy pad and a first via contact, a spacer within the semiconductor layer, and a second via contact that contacts the dummy pad and extends through the spacer.

[0018] In some embodiments, the first and second via contacts comprise tungsten.

[0019] In some embodiments, the dummy pad is connected to the ESD circuit through at least the interconnect structure and the first and second via contacts.

[0020] In some embodiments, the semiconductor device further includes a bonding interface between a dummy pad and a device layer. In some embodiments, the interconnect structure includes a bonding contact in the bonding interface.

[0021] In some embodiments, the interconnect structure further includes a device contact connecting the bonding interface and the device layer.

[0022] In another embodiment, a method for forming a semiconductor device is provided. A device layer including a functional circuit is formed. An interconnection structure is formed on the device layer and separated from the functional circuit. A first via contact is formed on the interconnection structure and connected to the interconnection structure. An insulating structure is formed on the first via contact. A dummy pad is formed on the insulating structure and separated from the first via contact by the insulating structure.

[0023] In some embodiments, another interconnect structure is formed on a device layer and connected to a functional circuit, another first via contact is formed on another interconnect structure and connected to said other interconnect structure, a second via contact is formed on said other first via contact and contacts it and extends through an insulating structure, and a pad is formed on said second via contact and contacts it.

[0024] In some embodiments, a portion of the semiconductor layer is removed to form an insulating structure, thereby forming a trench to expose a first via contact and another first via contact, and a dielectric layer is deposited to fill the trench.

[0025] In some embodiments, to form a second via contact, a portion of the insulating structure is removed to form a hole that exposes the other first via contact, rather than the first via contact, and a metal layer is deposited to fill the hole.

[0026] In some embodiments, the metal layer contains tungsten. Brief explanation of the drawing

[0027] The attached drawings, incorporated into this specification and constituting part of the specification, illustrate aspects of the present disclosure, explain the principles of the present disclosure together with the specification, and serve to enable those skilled in the art of the relevant technology to manufacture and use the present disclosure. FIG. 1 illustrates a plan view of a semiconductor device having via contacts under a dummy pad according to some aspects of the present disclosure. FIG. 2 illustrates a plan view of a semiconductor device having no via contacts under a dummy pad according to some aspects of the present disclosure. FIG. 3a illustrates a side cross-sectional view of a semiconductor device having dummy pads according to some aspects of the present disclosure. FIG. 3b illustrates a side cross-sectional view of a three-dimensional (3D) memory device having a dummy pad and a pad according to some aspects of the present disclosure. FIG. 4 illustrates a side cross-sectional view of another semiconductor device having dummy pads according to some aspects of the present disclosure. FIG. 5 illustrates a side cross-sectional view of another semiconductor device having dummy pads according to some aspects of the present disclosure. FIGS. 6a and 6b illustrate circuit diagrams of an ESD circuit according to some aspects of the present disclosure. FIGS. 7a-7e illustrate a manufacturing process for forming a semiconductor device having dummy pads according to some aspects of the present disclosure. FIGS. 8a-8e illustrate a manufacturing process for forming another semiconductor device having dummy pads according to some aspects of the present disclosure. FIG. 9 is a flowchart of a method for forming a semiconductor device having dummy pads according to some aspects of the present disclosure. The present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0028] Specific configurations and arrangements are described, but it should be understood that they are for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be used for various other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with one another, and such combinations, adjustments, and modifications may be combined, adjusted, and modified in ways not specifically illustrated in the drawings as being within the scope of this disclosure.

[0029] Generally, terms can be understood, at least in part, through the terms used in the context. For example, the term "one or more" used here may, at least in part, be used to describe any function, structure, or characteristic in a singular sense or to describe a combination of functions, structures, or characteristics in a plural sense, depending on the context. Similarly, terms such as "a," "an," or "the" may be understood, at least in part, as conveying a singular usage or a plural usage depending on the context. Furthermore, the term "foundation" is not necessarily intended to convey an exclusive set of elements, but may, at least in part, be understood to allow for the existence of additional factors not explicitly described, depending on the context.

[0030] It will be easy to understand that in the present disclosure, the meanings of 'on,' 'on,' and 'on the upper side' should be interpreted in the broadest sense, so that 'on' includes not only the meaning of something 'directly on' but also the meaning of something 'on' which has an intermediate feature or layer in between, and 'on' or 'on the upper side' includes not only the meaning of something 'on' or 'on the upper side' but also the meaning of something being 'on' or 'on the upper side' without an intermediate feature or layer in between (i.e., directly on something).

[0031] Additionally, spatially relative terms such as 'below,' 'below,' 'under,' 'on top,' 'on the upper,' etc. may be used in this specification for convenience of explanation to describe the relationship between one element or feature and another element(s) or feature(s), as in the drawings. Spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawings. The device may be positioned in different directions (90-degree rotation or other orientations), and the relative spatial descriptions used herein may likewise be interpreted accordingly.

[0032] As used in this document, the term 'substrate' refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added to the top of the substrate may or may not be patterned. Additionally, the substrate may include various arrays of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of electrically nonconductive materials such as glass, plastic, or sapphire wafers.

[0033] As used in this document, the term "layer" refers to a portion of material comprising a region with thickness. A layer may extend across the entirety of a lower or upper structure, or it may have an extension range smaller than the extension range of the lower or upper structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes on the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or have one or more layers on top of, above, and / or below it. A layer may comprise a plurality of layers. For example, an interconnect layer may comprise one or more conductor and contact layers (in which interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0034] In a semiconductor device, dummy pads can be used for wire bonding during semiconductor device packaging, just like ordinary pads (referred to as "pads" herein). However, unlike ordinary pads, dummy pads are electrically isolated from the functional circuits of the semiconductor device (e.g., transistors or memory cells) and therefore do not facilitate the operation of the functional circuits.

[0035] Although dummy pads are designed to be electrically isolated from the corresponding functional circuit underneath, ESD from the dummy pad can still cause damage to the functional circuit, for example, during semiconductor device packaging, if the distance between the functional circuit and the underlying interconnect structure in contact with the dummy pad is not sufficiently far, and / or if the functional circuit is not ESD protected.

[0036] To address one or more of the aforementioned problems, the present disclosure introduces various solutions for preventing ESD-induced damage to a semiconductor device from a dummy pad. According to one aspect of the present disclosure, at least one via contact of an underlying interconnect structure overlaying the dummy pad is removed and replaced, for example, with a dielectric structure, so that ESD from the dummy pad does not propagate to a functional circuit. In some embodiments, the lateral dimensions of an insulating structure (e.g., buried shallow trench isolation (BSTI)) in the dielectric structure are larger than the lateral dimensions of the dummy pad, thereby further reducing the risk of burnout due to defects between the dummy pad and the semiconductor layer beneath the dummy pad. According to another aspect of the present disclosure, the dummy pad is electrically connected to an ESD circuit through at least an interconnect structure so that ESD from the dummy pad can be mitigated by the ESD circuit.

[0037] FIG. 1 illustrates a top view of a semiconductor device (100) having via contacts under a dummy pad (104) according to some aspects of the present disclosure. The semiconductor device (100) may include a logic device such as a microcontroller, a microprocessor, an application processor, etc., a memory device such as dynamic random access memory (DRAM), NAND or NOR flash memory, static random access (SRAM), etc., or an analog device such as an operational amplifier, a timer, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), etc. The semiconductor device (100) may include wire bonding pads used to electrically connect the semiconductor device (100) to an external device. For example, the wire bonding pads may be connected to a circuit board or a packaging board (e.g., a redistribution layer) or an interposer through soldering and the attachment of gold or aluminum wires. Thus, the wire bonding pads may function as bonding sites on the semiconductor device (100). The semiconductor device (100) may also include a functional circuit configured to perform the function of the semiconductor device (e.g., as part of the device layer), such as a transistor for a logic device, a memory cell for a memory device, or a resistor, capacitor, and inductor for an analog device.

[0038] In some embodiments, depending on whether the wire bonding pad is electrically connected to any functional circuit, that is, whether the wire bonding pad also facilitates the operation of the corresponding functional circuit (e.g., transmitting / receiving an electrical signal to / from a functional device), the wire bonding pad includes a general pad (also known as a pad) (102) and a dummy pad (104). For example, each pad (102) may be electrically connected to the corresponding functional circuit to facilitate the operation of the functional circuit, whereas each dummy pad (104) may not be electrically connected to any functional circuit and thus may not facilitate the operation of any functional circuit. As illustrated in FIG. 1, in some embodiments, the pad (102) or the dummy pad (104) is in contact with one or more lower via contacts that form part of an interconnect structure overlaying the pad (102) / dummy pad (104). It is understood that an interconnect structure overlaying a pad (102) can connect the pad (102) to a corresponding functional circuit, whereas an interconnect structure overlaying a dummy pad (104) may not connect the dummy pad (104) to any functional circuit. In some embodiments described in detail below, an interconnect structure overlaying a dummy pad (104) can connect the dummy pad (104) to an ESD circuit to mitigate the risk of ESD damage from the dummy pad (104) to a functional circuit close to the interconnect structure overlaying the dummy pad (104).

[0039] FIG. 2 illustrates a top view of a semiconductor device (200) without via contacts under a dummy pad (104) according to some aspects of the present disclosure. The semiconductor device (200) is similar to the semiconductor device (100) except that at least one of the via contacts under the dummy pad (104) is removed, for example, replaced by a dielectric structure. Consequently, according to some embodiments described in detail below, ESD from the dummy pad (104) can be insulated by the dielectric structure before reaching any functional circuit through an interconnect structure overlaying the dummy pad (104).

[0040] FIG. 3a illustrates a side cross-sectional view of a semiconductor device (300) having a dummy pad (330) according to some aspects of the present disclosure. The semiconductor device (300) may be an example of a semiconductor device (200). As shown in FIG. 3a, the semiconductor device (300) is, according to some embodiments, in a vertical direction (e.g., z It is a bonded chip comprising a first structure (302) and a second structure (304) stacked on each other in different planes in different directions. Depending on some embodiments, the first and second structures (302 and 304) are bonded at a bonding interface (306) between them.

[0041] As illustrated in FIG. 3a, the first structure (302) may comprise a substrate (308) which may comprise silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate (308) comprises single-crystal silicon which is a portion of a wafer of its intrinsic thickness or thin thickness on which the first structure (302) is manufactured. In some embodiments, the first substrate (302) comprises polysilicon which is a semiconductor layer replacing, for example, the portion of the wafer on which the first structure (302) is manufactured. To further explain the spatial relationships of the components of the semiconductor device (100, 200, 300), FIG. 1, FIG. 2, FIG. 3a x, y and z Note that an axis is included. The substrate (308) of the semiconductor device (300) is xy It includes two lateral surfaces extending laterally from the plane, namely the upper surface of the front of the wafer on which a device layer (310) can be formed and the lower surface of the rear opposite to the front of the wafer. z The axis x axis y All are perpendicular to the axis. As used herein, whether one component (e.g., a layer or device) is "on," "above," "below," or "below" another component (e.g., a layer or device) of the semiconductor device (300) is that the substrate (308) z Regarding the substrate (308) of the semiconductor device (300) when positioned at the lowest plane of the semiconductor device (300) in the direction z direction( xy It is determined by the vertical direction perpendicular to the plane. The same concept for describing spatial relationships applies throughout this disclosure.

[0042] As illustrated in FIG. 3a, the first structure may include a device layer (310) on a substrate (308). In some embodiments, the device layer (310) includes a functional circuit (312). In some embodiments, the semiconductor device (300) is a NAND flash memory device in which memory cells are formed as an array of NAND memory strings, and the functional circuit (312) is a peripheral circuit (also called a control and sensing circuit) that facilitates the operation of the NAND memory string and includes any suitable digital, analog and / or mixed-signal circuit. For example, the peripheral circuit may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sensing amplifier, a driver (e.g., word line driver), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the functional circuit mentioned above (e.g., a subcircuit), or an active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The functional circuit (312) can use complementary metal oxide semiconductor (CMOS) technology and can be implemented as a logic process at any suitable technology node, for example.

[0043] In some embodiments, the first structure (302) further includes an interconnect layer (311) on the device layer (310) to transmit electrical signals to and from the device layer (310). As illustrated in FIG. 3a, the interconnect layer (311) may be positioned vertically between the bonding interface (306) and the device layer (310) (including the functional circuit (312)). The interconnect layer (311) may include a plurality of interconnects (also referred to herein as “contacts”) including lateral lines and via contacts. As used herein, the term “interconnects” may broadly include any suitable type of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer (311) may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which lateral lines and via contacts may be formed. That is, the interconnect layer (311) may include lateral lines and via contacts of multiple ILD layers. Although not illustrated in FIG. 3a, it is understood that the functional circuit (312) of the device layer (310) may be electrically connected to any other suitable functional circuit through the interconnect portion of the interconnect layer (311). The interconnect portion of the interconnect layer (311) may include a conductive material comprising, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer of the interconnect layer (311) may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-dielectric constant (low-k) dielectric, or any combination thereof.In some embodiments, the interconnection portion of the interconnection layer (311) includes, for example, a device contact (316) of a metal 3-5 (M3-M5) layer. The device contact (316) may include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0044] As illustrated in FIG. 3a, the first structure (302) may further include a bonding layer (313) that is in contact with the bonding interface (306) and on the interconnection layer (311). The bonding layer (313) may include a plurality of bonding contacts (318) and a dielectric that electrically insulates the bonding contacts (318). The bonding contacts (318) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the bonding contacts (318) of the bonding layer (313) include Cu. The remaining portion of the bonding layer (313) may be formed of a dielectric comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The surrounding dielectric of the bonding contact (318) and the bonding layer (313) can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (forming a bond between surfaces without using an intermediate layer such as solder or adhesive, for example), and can simultaneously obtain metal-metal (e.g., Cu to Cu) bonding and dielectric-dielectric (e.g., SiO2 to SiO2) bonding.

[0045] As illustrated in FIG. 3a, the second structure (304) may include a bonding layer (315) at the bonding interface (306), for example, on the opposite side of the bonding interface (306) from the bonding layer (313) of the first structure (302). The bonding layer (315) may include a plurality of bonding contacts (320) and a dielectric that electrically insulates the bonding contacts (320). The bonding contacts (320) may include a conductive material such as Cu. The remaining area of ​​the bonding layer (315) may be formed of a dielectric material such as silicon oxide. The surrounding dielectric of the bonding contacts (320) and the bonding layer (315) may be used for hybrid bonding. In some embodiments, the bonding interface (306) is the place where the bonding layers (313 and 315) meet and are bonded. Actually, the bonding interface (306) may be a layer of a specific thickness including the upper surface of the bonding layer (313) of the first structure (302) and the lower surface of the bonding layer (315) of the second structure (304).

[0046] As illustrated in FIG. 3a, the second structure (304) may further include an interconnect layer (323) on top of the bonding layer (315) to transmit electrical signals. The interconnect layer (323) may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Although not illustrated in FIG. 3a, in some examples, the interconnects of the interconnect layer (323) may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer (323) may further include one or more ILD layers on which lateral lines and via contacts may be formed. The interconnects of the interconnect layer (323) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer of the interconnect layer (323) may include a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects of the interconnection layer (323) include W, which has a relatively high thermal budget (compatible with high-temperature processes) and excellent quality (e.g., reduction of defects such as voids) among conductive metal materials.

[0047] As illustrated in FIG. 3a, the second structure (304) may further include a semiconductor layer (326) on the interconnect layer (323). The semiconductor layer (326) may include a semiconductor material. In some embodiments, the semiconductor layer (326) is a thin silicon substrate having single-crystal silicon. In some embodiments, the semiconductor layer (326) is a deposited polysilicon layer replacing at least a portion of the silicon substrate having single-crystal silicon. In some examples, it is understood that trench insulation and doped regions (not shown) may also be formed in the semiconductor layer (326). Additionally, in some examples, it is understood that the semiconductor layer (326) may include a plurality of semiconductor layers in a vertical direction, and dielectric layers may be formed between them.

[0048] As illustrated in FIG. 3a, the second structure (304) may further include a pad-out layer (327) on top of the semiconductor layer (326). The pad-out layer (327) may include a dummy pad (330), one or more ILD layers (332) (e.g., a silicon oxide layer and a silicon nitride layer) and a protective layer (334) (e.g., a polyimide layer) on the top surface of the semiconductor device (300). The pad-out layer (327) and the interconnect layer (323) may be formed on opposite sides of the semiconductor layer (326). In some embodiments, an opening (336) is formed through the protective layer (334) and the ILD layer (332) of the pad-out layer (327) to expose the dummy pad (330), thereby allowing wire bonding to be performed on the top surface of the dummy pad (330).

[0049] According to the scope of the present disclosure, the semiconductor device (300) is in a vertical direction (e.g., in FIG. 3a). z A dielectric structure may be included between the device layer (310) and the dummy pad (330) in the direction) of the dielectric structure. The dielectric structure may be included laterally (e.g., of FIG. 3a). y Direction) and vertical direction (e.g., of Fig. 3a) zIt can be extended in the direction). In some embodiments as illustrated in FIG. 3a, the dielectric structure includes an insulating structure (328), such as BSTI, in the semiconductor layer (326). For example, the insulating structure (328) may include silicon oxide. The semiconductor device (300) can also be extended in the vertical direction (e.g., FIG. 3a). z An interconnection structure (314) may be included between the device layer (310) and the dielectric structure (e.g., the insulating structure (328) of FIG. 3a) in the direction) direction. The interconnection structure (314) may be included in the vertical direction (e.g., FIG. 3a z It may be extended in the direction. The semiconductor layer (326) may be positioned between the dummy pad (330) and the interconnect structure (314) in the vertical direction. As illustrated in FIG. 3a, the insulating structure (328), the interconnect structure (314), and the dummy pad (330) are overlaid according to some embodiments, which are considered to be the corresponding structures in the present disclosure. In other words, for each dummy pad (330), the semiconductor device (300) may include the corresponding overlaid insulating structure (328) and the interconnect structure (314).

[0050] As illustrated in FIG. 3a, the interconnect structure (314) may include bonding contacts (320 and 318) within the bonding layers (315 and 313) as well as device contacts (316) within the interconnect layer (311) of the first structure (302). According to some embodiments, the device contacts (316) are positioned vertically between the bonding interface (306) and the device layer (310), and the bonding interface (306) is positioned between the dummy pad (330) and the device layer (310). In some embodiments, it is understood that the interconnect structure (314) may further include an interconnect portion (322) in the interconnect layer (323) of the second structure (304).

[0051] As illustrated in FIG. 3a, the second structure (304) of the semiconductor device (300) may further include a via contact (324) extending vertically from the interconnect layer (323). The via contact (324) may include W. In some embodiments, the via contact (324) is in contact with the interconnect structure (314) but is separated from the dummy pad (330) by an insulating structure (328). Thus, to prevent ESD damage to the functional circuit (312) through the interconnect structure (314) and the via contact (324), even if the device contact (316) of the interconnect structure (314) is not sufficiently far from the functional circuit (312) of the device layer (310), the ESD propagating from the dummy pad (330) to the via contact (324) can still be prevented by the insulating structure (328) between the dummy pad (330) and the via contact (324). In some embodiments, the thickness of the insulating structure (328) (e.g., in the vertical direction) is between 500 nm and 1000 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range in which the bottom is bounded by any of these values ​​or any range defined by any two of these values).

[0052] In some embodiments, the insulating structure (328) (e.g., of FIG. 3a) y The lateral dimension (in the direction) of the dummy pad (330) (e.g., of FIG. 3a) y It is larger than the lateral dimension (in the direction). As a result, even if a defect is formed in the semiconductor layer (326), the risk of burnout between the dummy pad (330) and the semiconductor layer (326) can be reduced due to the large size of the insulating structure (328) (e.g., BSTI). In some embodiments, between the edges of the dummy pad (330) and the insulating structure (328) Lateral (e.g., of FIG. 3a) y Direction) Distance( d) is greater than 1μm, such as between 1μm and 5μm (e.g., 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, any range whose lower bound is set by any of these values, or any range defined by any two of these values).

[0053] FIG. 3b illustrates a side cross-sectional view of a 3D memory device (301) having a dummy pad (330) and a pad (346) according to some aspects of the present disclosure. The 3D memory device (301) may be a NAND flash memory device as an example of the semiconductor device (300) of FIG. 3a. For convenience of explanation, components identical to those described above in relation to FIG. 3a will not be repeated.

[0054] As illustrated in FIG. 3b, the 3D memory device (301) may further include a pad (346), a via contact (344) in contact with the pad (346) below the pad (346), a via contact (342) in contact with the via contact (344) below the via contact (344), and an interconnection structure (340) in contact with the via contact (342) below the via contact (342). The pad (346), the via contacts (344 and 342), and the interconnection structure (340) are overlaid according to some embodiments. As described in detail below regarding the manufacturing process, the pad (346) and the dummy pad (330) may be formed by the same process and are coplanar. Likewise, the interconnect structure (314) and the interconnect structure (340) can be formed by the same process and are coplanar, and the via contact (324) and the via contact (342) can be formed by the same process and are coplanar. According to some embodiments, the via contact (344) extends through an insulating structure (328) and connects the pad (346) and the via contact (342). Thus, unlike the dummy pad (330) and the interconnect structure (314) which are electrically insulated by the insulating structure (328), the pad (346) can be electrically connected to the interconnect structure (340) through the via contacts (344 and 342). Like the via contact (324), the via contacts (344 and 342) may include W.

[0055] As illustrated in FIG. 3b, the device layer (310) may further include a functional circuit (338) electrically connected to an interconnect structure (340), which is different from a functional circuit (312) electrically isolated from an interconnect structure (314). Consequently, the pad (346) may be electrically connected to the functional circuit (338) of the device layer (310) through via contacts (344 and 342) and the interconnect structure (340), thereby facilitating the operation of the functional circuit (338). Although not illustrated, it is understood that the device layer (310) may further include an ESD circuit electrically connected to the functional circuit (338) and the interconnect structure (340) to avoid ESD damage from the pad (346).

[0056] In some embodiments, the 3D memory device (301) further includes an array of memory cells, such as an array of NAND memory strings (350), on the bonding interface (306) in the second structure (304). In some embodiments, the NAND memory strings (350) are positioned vertically between the semiconductor layer (326) and the bonding interface (306). In some embodiments, the semiconductor layer (326) is positioned on the memory stack (348) and contacts the source of the NAND memory strings (350). In some embodiments, each NAND memory string (350) is a "charge trap" type NAND memory string containing any suitable channel structure. It is understood that the NAND memory strings (350) are not limited to "charge trap" type NAND memory strings and may be "floating gate" type NAND memory strings in other examples.

[0057] Each NAND memory string (350) extends vertically through a plurality of pairs, each comprising a conductive layer and a dielectric layer, according to some embodiments. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stack structure (e.g., memory stack) (348). The memory stack (348) and via contacts (324 and 342) may be coplanar. Thus, since the via contacts (324 and 342) are coplanar with the memory cell array within the memory stack (348), they may also be referred to as "array contacts." The interleaved conductive and dielectric layers within the memory stack (348) are arranged alternately in the vertical direction according to some embodiments. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material such as titanium nitride (TiN) that can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line and end at one or more stepped structures of the memory stack (348).

[0058] Compared to a pad (346) that is electrically connected to a corresponding interconnect structure (340) through two via contacts (344 and 342), a dummy pad (330) is separated from the via contact (324) by an insulating structure (328) according to some embodiments. In other words, one of the two via contacts overlaying the dummy pad (330) (i.e., the contact coplanar with the via contact (344)) is replaced by an insulating structure (328) according to some embodiments, thereby ensuring electrical insulation between the dummy pad (330) and the interconnect structure (314) without ESD circuit protection for the functional circuit (312), even if the distance between the interconnect structure (314) and the functional circuit (312) is too close, thus preventing ESD damage to the functional circuit (312).

[0059] To separate the dummy pad (330) from the interconnect structure (314), one or both of the two via contacts overlaying the dummy pad (330) may be replaced with a dielectric structure. Instead of removing the via contact in contact with the dummy pad (330) as shown in FIGS. 3a and 3b, the same result may be achieved by removing another via contact (e.g., 324) in contact with the interconnect structure (314) in other examples. FIG. 4 illustrates a side cross-sectional view of another semiconductor device (400) having a dummy pad (330) according to some aspects of the present disclosure. The semiconductor device (400) may be another example of the semiconductor device (200). The same components described above in relation to FIG. 3a will not be repeated for convenience of explanation.

[0060] According to the scope of the present disclosure, the semiconductor device (400) is in a vertical direction (e.g., of FIG. 4). z A dielectric structure may be included between the device layer (310) and the dummy pad (330) in the direction) direction. The dielectric structure may include a lateral direction (e.g., of FIG. 4). y direction) and perpendicular direction (e.g., of Fig. 4) z It can be extended in the direction). In some embodiments as illustrated in FIG. 4, the dielectric structure includes a dielectric layer (401) in an interconnect layer (323). For example, the dielectric layer (401) may include silicon oxide. The semiconductor device (400) can also be extended in the vertical direction (e.g., FIG. 4). z An interconnection structure (314) may be included between the device layer (310) and the dielectric structure (e.g., the dielectric layer (401) of FIG. 4) in the direction) direction. The interconnection structure (314) may be included in the vertical direction (e.g., FIG. 4). zIt can be extended in the direction. As illustrated in FIG. 4, the dielectric layer (401), interconnect structure (314), and dummy pad (330) are overlaid according to some embodiments, and these are considered as corresponding structures in the present disclosure. In other words, for each dummy pad (330), the semiconductor device (400) may include a corresponding overlaid dielectric layer (401) and interconnect structure (314).

[0061] Unlike the semiconductor device (300) of FIG. 3a, the semiconductor device (400) may further include a via contact (402) that contacts the dummy pad (330) below the dummy pad (330). In some embodiments, the via contact (402) extends vertically (e.g., in the z-direction of FIG. 4) through an insulating structure (328). The via contact (402) may include W. Since the via contact (402) also extends through the semiconductor layer (326), in some examples it may be referred to as a "TSV (through silicon via)." However, unlike the semiconductor device (300) of FIG. 3a which includes a via contact (324) in contact with the interconnect structure (314) on the interconnect structure (314), the semiconductor device (400) does not include the via contact (324), and instead, according to some embodiments, includes a dielectric layer (401) between the via contact (402) and the interconnect structure (314). That is, the via contact (402) can be separated from the interconnect structure (314) by the dielectric layer (401). Therefore, to prevent ESD damage to the functional circuit (312) through the interconnect structure (314), even if the device contact (316) of the interconnect structure (314) is not sufficiently far from the functional circuit (312) of the device layer (310), the dielectric layer (401) between the interconnect structure (314) and the via contact (402) can still prevent ESD propagation from the dummy pad (330) to the interconnect structure (314). In some embodiments, the thickness of the insulating structure (328) (e.g., in the vertical direction) is between 1000 nm and 2000 nm (e.g., 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, any range in which the bottom is bounded by any of these values ​​or any range defined by any two of these values).

[0062] In some embodiments, the insulating structure (328) (e.g., of FIG. 4) y The lateral dimension (in the direction) of the dummy pad (330) (e.g., of FIG. 4) y It is larger than the lateral dimension (in the direction). As a result, even if a defect is formed in the semiconductor layer (326), the risk of burnout between the dummy pad (330) and the semiconductor layer (326) can be reduced due to the large size of the insulating structure (328) (e.g., BSTI). In some embodiments, between the edges of the dummy pad (330) and the insulating structure (328) Lateral (e.g., of Fig. 4) y Direction) Distance( d ) is greater than 1μm, such as between 1μm and 5μm (e.g., 1μm, 1.5μm, 2μm, 2.5m, 3μm, 3.5m, 4μm, 4.5μm, 5μm, any range whose lower bound is set by any of these values, or any range defined by any two of these values).

[0063] Although not illustrated, in some examples, the two via contacts (324 and 402) overlaying the dummy pad (330) may be removed by, for example, being replaced by an insulating structure (328) and a dielectric layer (401), so that the dummy pad (330) may be separated from the interconnect structure (314) by the insulating structure (328) and the dielectric layer (401) to prevent ESD damage to the functional circuit (312) from the dummy pad (330).

[0064] FIG. 5 illustrates a side cross-sectional view of another semiconductor device (500) having a dummy pad (330) according to some aspects of the present disclosure. The semiconductor device (500) may be an example of the semiconductor device (100). As shown in FIG. 5, the semiconductor device (500) is in a vertical direction (e.g., according to some embodiments, zIt is a bonded chip comprising a first structure (302) and a second structure (304) stacked on each other in different planes in different directions. The first and second structures (302 and 304) are bonded at a bonding interface (306) between them according to some embodiments.

[0065] As illustrated in FIG. 5, the first structure (302) may include a substrate (308), which may include silicon (e.g., single-crystal silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, the substrate (308) includes single-crystal silicon which is a portion of a wafer of its intrinsic thickness or thinness on which the first structure (302) is manufactured. In some embodiments, the first substrate (302) includes polysilicon which is a semiconductor layer replacing, for example, a portion of the wafer on which the first structure (302) is manufactured.

[0066] As illustrated in FIG. 5, the first structure may include a device layer (310) on a substrate (308). In some embodiments, the device layer (310) includes a functional circuit (312) and an ESD circuit (502). In some embodiments, the semiconductor device (500) is a NAND flash memory device in which memory cells are formed as an array of NAND memory strings, and the functional circuit (312) is a peripheral circuit (also called a control and sensing circuit) that facilitates the operation of the NAND memory string and includes any suitable digital, analog and / or mixed-signal circuit. For example, the peripheral circuit may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sensing amplifier, a driver (e.g., word line driver), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the functional circuit mentioned above (e.g., a subcircuit), or an active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The functional circuit (312) can use CMOS technology that can be implemented as a logic process at any suitable technology node, for example.

[0067] The ESD circuit (502) can lower the ESD voltage below a specific limit using ESD suppression components. These components can be connected in parallel to vulnerable lines. When an ESD strike occurs, the ESD diode can fail to create a low-impedance path, thereby limiting peak voltage and current by diverting the current flow to ground. For example, as shown in FIG. 6a, the ESD circuit (502) may include a resistor (R), a capacitor (C), and a transistor (Q). The resistor (R) and the capacitor (C) may form a resistor-capacitor circuit (RC circuit), and the transistor (Q) may be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal (A), the output terminal of the resistor-capacitor circuit may be at a logic high level, which turns on the transistor (Q) and allows ESD to be performed through the transistor (Q). In another example, as illustrated in FIG. 6b, the ESD circuit (502) may include a resistor (R), a capacitor (C), a transistor (Qa), a transistor (Qb), and a transistor (Qc). The resistor (R) and the capacitor (C) may form an RC circuit, the transistor (Qa) and the transistor (Qb) may form an inverter, and the transistor (Qc) may be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal (A), the output terminal of the resistor-capacitor circuit may be at a logic low level, the output terminal of the inverter may be at a logic high level, the transistor (Qc) may be turned on, and ESD may be performed through the transistor (Qc).

[0068] As illustrated in FIG. 5, in some embodiments, the first structure (302) further comprises an interconnect layer (311) on the device layer (310) to transmit electrical signals to / from the device layer (310). The interconnect layer (311) may be positioned vertically between the bonding interface (306) and the device layer (310) (including the functional circuit (312) and the ESD circuit (502)). The interconnect layer (311) may include a plurality of interconnects and one or more ILD layers. That is, the interconnect layer (311) may include lateral lines and via contacts of multiple ILD layers. Although not illustrated in FIG. 5, it is understood that the functional circuit (312) of the device layer (310) may be electrically connected to any other suitable functional circuit through the interconnect of the interconnect layer (311). The interconnect portion of the interconnect layer (311) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layer of the interconnect layer (311) may include a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnect portion of the interconnect layer (311) includes, for example, a device contact (316) of a metal 3-5 (M3-M5) layer. The device contact (316) may include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0069] As illustrated in FIG. 5, the first structure (302) may further include a bonding layer (313) that is in the bonding interface (306) and contacts the interconnection layer (311) on the interconnection layer (311). The bonding layer (313) may include a plurality of bonding contacts (318) and a dielectric that electrically insulates the bonding contacts (318). The bonding contacts (318) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some embodiments, the bonding contacts (318) of the bonding layer (313) include Cu. The remaining portion of the bonding layer (313) may be formed of a dielectric comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact (318) of the bonding layer (313) and the surrounding dielectric can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (forming bonding between surfaces without using an intermediate layer such as solder or adhesive, for example), and can simultaneously obtain metal-metal (e.g., Cu to Cu) bonding and dielectric-dielectric (e.g., SiO2 to SiO2) bonding.

[0070] As illustrated in FIG. 5, the second structure (304) may include a bonding layer (315) on the bonding interface (306) opposite the bonding layer (313) of the first structure (302), for example. The bonding layer (315) may include a plurality of bonding contacts (320) and a dielectric that electrically insulates the bonding contacts (320). The bonding contacts (320) may include a conductive material such as Cu. The remaining area of ​​the bonding layer (315) may be formed of a dielectric material such as silicon oxide. The bonding contacts (320) and the surrounding dielectric of the bonding layer (315) may be used for hybrid bonding. In some embodiments, the bonding interface (306) is the place where the bonding layers (313 and 315) meet and are bonded. Actually, the bonding interface (306) may be a layer of a specific thickness including the upper surface of the bonding layer (313) of the first structure (302) and the lower surface of the bonding layer (315) of the second structure (304).

[0071] As illustrated in FIG. 5, the second structure (304) may further include an interconnect layer (323) on top of the bonding layer (315) to transmit electrical signals. The interconnect layer (323) may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. Although not illustrated in FIG. 5, in some examples, the interconnects of the interconnect layer (323) may also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer (323) may further include one or more ILD layers on which lateral lines and via contacts may be formed. The interconnects of the interconnect layer (323) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer of the interconnect layer (323) may include a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, the interconnects of the interconnection layer (323) include W, which has a relatively high thermal budget (compatible with high-temperature processes) and excellent quality (e.g., reduction of defects such as voids) among conductive metal materials.

[0072] As illustrated in FIG. 5, the second structure (304) may further include a semiconductor layer (326) on the interconnect layer (323). The semiconductor layer (326) may include a semiconductor material. In some embodiments, the semiconductor layer (326) is a thin silicon substrate having single-crystal silicon. In some embodiments, the semiconductor layer (326) is a deposited polysilicon layer replacing at least a portion of the silicon substrate having single-crystal silicon. In some examples, it is understood that trench insulation and doped regions (not shown) may also be formed in the semiconductor layer (326). Additionally, in some examples, it is understood that the semiconductor layer (326) may include a plurality of semiconductor layers in a vertical direction, and dielectric layers may be formed between them.

[0073] As illustrated in FIG. 5, the second structure (304) may further include a pad-out layer (327) on top of the semiconductor layer (326). The pad-out layer (327) may include a dummy pad (330), one or more ILD layers (332) (e.g., a silicon oxide layer and a silicon nitride layer) and a protective layer (334) (e.g., a polyimide layer) on the top surface of the semiconductor device (500). The pad-out layer (327) and the interconnect layer (323) may be formed on opposite sides of the semiconductor layer (326). In some embodiments, an opening (336) is formed through the protective layer (334) and the ILD layer (332) of the pad-out layer (327) to expose the dummy pad (330), thereby allowing wire bonding to be performed on the top surface of the dummy pad (330).

[0074] According to the scope of the present disclosure, the semiconductor device (500) is in a vertical direction (e.g., of FIG. 5). zAn interconnection structure (314) may be included between the device layer (310) and the dummy pad (330) in the direction (direction), thereby connecting the dummy pad (330) to the ESD circuit (502) within the device layer (310) at least through the interconnection structure (314). On the other hand, according to some embodiments, the dummy pad (330) is separated from the functional circuit (312) of the device layer (310). The interconnection structure (314) is in the vertical direction (e.g., of FIG. 5). z It may be extended in the direction. The semiconductor layer (326) may be positioned between the dummy pad (330) and the interconnect structure (314) in the vertical direction. As illustrated in FIG. 5, the interconnect structure (314) and the dummy pad (330) are overlaid according to some embodiments, and these are considered as corresponding structures in the present disclosure. In other words, for each dummy pad (330), the semiconductor device (500) may include a corresponding overlaid interconnect structure (314).

[0075] As illustrated in FIG. 5, the interconnect structure (314) may include bonding contacts (320 and 318) within the bonding layers (315 and 313) as well as device contacts (316) within the interconnect layer (311) of the first structure (302). According to some embodiments, the device contacts (316) are positioned vertically between the bonding interface (306) and the device layer (310), and the bonding interface (306) is positioned between the dummy pad (330) and the device layer (310). In some embodiments, it is understood that the interconnect structure (314) may further include an interconnect portion (322) in the interconnect layer (323) of the second structure (304).

[0076] As illustrated in FIG. 5, the second structure (304) of the semiconductor device (500) may further include a via contact (324) extending vertically from the interconnect layer (323). The via contact (324) may include W. In some embodiments, the via contact (324) is in contact with the interconnect structure (314). That is, the via contact (324) may be positioned between the dummy pad (330) and the interconnect structure (314) and connected to the interconnect structure (314). The second structure (304) of the semiconductor device (500) may further include a spacer (504) within the semiconductor layer (326) and a via contact (402) extending vertically through the spacer (504). The spacer (504) may include a dielectric material such as silicon oxide or silicon nitride. In some embodiments, the via contact (402) contacts the dummy pad (330) and the via contact (324) at opposite ends. That is, the via contact (402) can electrically connect the dummy pad (330) and the via contact (324). The via contact (402) may also include W. Consequently, the dummy pad (330) can be electrically connected to the ESD circuit (502) within the device layer (310) through at least the interconnect structure (314) and the via contacts (324 and 402). Thus, ESD from the dummy pad (330) can propagate to the ESD circuit (502) and be mitigated by the ESD circuit (502) to prevent damage to the functional circuit (312).

[0077] FIGS. 7a-7e illustrate a manufacturing process for forming a semiconductor device having dummy pads according to some aspects of the present disclosure. FIGS. 8a-8e illustrate a manufacturing process for forming another semiconductor device having dummy pads according to some aspects of the present disclosure. FIG. 9 illustrates a flowchart of method 900 for forming a semiconductor device having dummy pads according to some embodiments of the present disclosure. Examples of semiconductor devices illustrated in FIGS. 7a-7e, FIGS. 8a-8e and FIG. 9 include semiconductor devices (300, 301 and FIG. 400) illustrated in FIGS. 3a, FIG. 3b and FIG. 4. FIGS. 7a-7e, FIGS. 8a-8e and FIG. 9 are described together. It is understood that the operations illustrated in method 900 are not exhaustive and that other operations may be performed before, after, or in between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 9.

[0078] Referring to FIG. 9, method 900 begins with operation 902, in which a device layer containing functional circuits is formed. As illustrated in FIG. 7a and 8a, a device layer (710) containing functional circuits (712 and 738) is formed on a silicon substrate (708) having single-crystal silicon. The functional circuits (712 and 738) may be formed by a plurality of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed on the silicon substrate (708) by ion implantation and / or thermal diffusion, which function, for example, as well and source / drain regions of a transistor in the functional circuits (712 and 738). In some embodiments, an insulating region (e.g., STI) is also formed on a silicon substrate (708) by wet / dry etching and thin film deposition.

[0079] Method 900 proceeds to operation 904 as illustrated in FIG. 9, in which an interconnect structure is formed on a device layer and the interconnect structure is separated from the functional circuit. In some embodiments, another interconnect structure is formed on the device layer and the other interconnect structure is connected to the functional circuit. The interconnect structure and the other interconnect structure may be formed by the same process.

[0080] As illustrated in FIGS. 7a and 8a, an interconnect layer (711) is formed on the device layer (710). The interconnect layer (711) may include interconnects of MEOL and / or BEOL, such as device contacts (716), in a plurality of ILD layers to make an electrical connection with a functional circuit (738) other than a functional circuit (712). That is, the device contacts (716) may be connected to the functional circuit (738) but may be separated from the functional circuit (712). In some embodiments, the interconnect layer (711) includes a plurality of ILD layers formed by a plurality of processes and interconnects within them. For example, interconnects within the interconnect layer (711) may include a conductive material deposited by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects illustrated in FIGS. 7a and 7b may be collectively referred to as the interconnect layer (711). In some embodiments, the interconnects, such as device contacts (716) within the interconnect layer (711), comprise Cu, which has a relatively low resistivity among conductive metal materials.

[0081] As illustrated in FIGS. 7a and 8a, a bonding layer (713) is formed on an interconnect layer (711). The bonding layer (713) may include a plurality of bonding contacts (718) surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer (711) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, the bonding contacts (718) are formed through the dielectric layer by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material within the dielectric layer) and may contact the interconnects within the interconnect layer (711). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes involves depositing an adhesive (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor. For example, the adhesive layer improves the adhesion of the conductor to prevent defects, the barrier layer prevents metal ions (e.g., Cu ions) from diffusing from the conductor to other structures and causing contamination, and the seed layer promotes the deposition of the conductor (e.g., Cu) in the contact holes to improve the deposition quality and speed.

[0082] As illustrated in FIGS. 7a and 8a, a stack structure such as a memory stack (748) comprising interleaved conductive layers and dielectric layers is formed on a silicon substrate (726). To form the memory stack (748), in some embodiments, a dielectric stack (not shown) comprising interleaved sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate (726). In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The interleaved sacrificial layer and dielectric layers may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, the memory stack (748) may be formed by a gate replacement process, for example, by using wet / dry etching of an optional sacrificial layer on the dielectric layer to replace the sacrificial layer with a conductive layer, and filling the resulting recess with a conductive layer. In some embodiments, each conductive layer includes a metal layer such as a W layer. It is understood that the memory stack (748) can be formed in some examples by alternately depositing a conductive layer (e.g., a doped polysilicon layer) and a dielectric layer (e.g., a silicon oxide layer) without a gate replacement process. In some embodiments, a pad oxide layer containing silicon oxide (e.g., thermally grown local oxidation of silicon: LOCOS) is formed between the memory stack (748) and the silicon substrate (726).

[0083] As illustrated in FIGS. 7a and 8a, a NAND memory string (750) is formed, with each string extending vertically through a memory stack (748). In some embodiments, the manufacturing process for forming the NAND memory string (750) comprises forming channel holes within a silicon substrate (726) through the memory stack (748) (or dielectric stack) using dry etching and / or wet etching, such as deep reactive-ion etching (DRIE), and then filling the channel holes with multiple layers, such as a memory film (e.g., a tunneling layer, a storage layer, and a blocking layer) and a semiconductor layer, using thin film deposition processes such as ALD, CVD, PVD, or any combination thereof. It is understood that details for manufacturing the NAND memory string (750) may vary depending on the type of channel structure of the NAND memory string (750) and are therefore not described in detail for ease of explanation.

[0084] As illustrated in FIGS. 7a and 8a, a bonding layer (715) is formed on the memory stack (748). The bonding layer (715) may include a plurality of bonding contacts (720) surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the memory stack (748) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Then, the bonding contacts (720) may be formed through the dielectric layer by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material within the dielectric layer). The contact holes may be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes involves depositing an adhesive (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0085] As illustrated in FIGS. 7a and 8a, the silicon substrate (726) and the components formed thereon (e.g., memory stack (748) and the NAND memory string (750) formed thereon) are inverted. The downward-facing bonding layer (715) is bonded to the upward-facing bonding layer (713) in a face-to-face manner, i.e., in a facing manner, to form a bonding interface (706). That is, the silicon substrate (708) and the components formed thereon can be bonded to the silicon substrate (726) and the components formed thereon in a face-to-face manner, so that the bonding contact (718) in the bonding layer (713) can contact the bonding contact (720) in the bonding layer (715) at the bonding interface (706). In some embodiments, a processing process such as plasma treatment, wet treatment, and / or heat treatment is applied to the bonding surface before bonding. In some embodiments, the silicon substrate (726) is thinned after bonding to form a thinned silicon substrate, which is also referred to herein as a semiconductor layer (726).

[0086] As a result of bonding, for example, hybrid bonding, the bonding contacts (718 and 720) on opposite sides of the bonding interface (706) may be mixed with each other. After bonding, the bonding contact (718) of the bonding layer (713) and the bonding contact (720) of the bonding layer (715) may be aligned and come into contact with each other, so that two interconnected structures (714 and 740) may be formed. The interconnected structures (714 or 740) may include bonding contacts (718 and 720) and device contacts (716) across the bonding interface (706). As illustrated in FIGS. 7a and 8a, the interconnected structure (714) is formed on the device layer (710) and separated from the functional circuit (712), whereas the interconnected structure (740) is formed on the device layer (710) and connected to the functional circuit (738).

[0087] Method 900 proceeds to operation 906 as illustrated in FIG. 9, wherein a first via contact is formed on an interconnect structure and connected to the interconnect structure. In some embodiments, another via contact is formed on a different interconnect structure and connected to a different interconnect structure. The first via contact and the other via contact may be formed by the same process.

[0088] As illustrated in FIG. 7a, before bonding, via contacts (724 and 742) are formed by the same process as forming word line contacts through a memory stack (748), for example. Then, via contacts (724 and 742) can be formed through the dielectric layer by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material within the dielectric layer). The contact holes can be filled with a conductor (e.g., W). In some embodiments, filling the contact holes involves depositing an adhesive (glue) layer, a barrier layer, and / or a seed layer before depositing the conductor. After bonding, the via contacts (724) can be connected to and formed on the interconnect structure (714) as illustrated in FIG. 7a. Likewise, the via contact (742) can be connected to the interconnect structure (740) and formed on the interconnect structure (740).

[0089] Method 900 proceeds to operation 908 as exemplified in FIG. 9, wherein an insulating structure is formed on the first via contact. In some embodiments, a portion of the semiconductor layer is removed to form a trench to expose the first via contact and other first via contacts, and a dielectric layer is deposited to fill the trench.

[0090] As illustrated in FIG. 7a, the trench (727) is formed by removing a portion of the semiconductor layer (726) to expose one end of the via contacts (724 and 742). The trench (727) may be formed by etching the semiconductor layer (726) using, for example, dry etching and / or wet etching, and removing a portion of the semiconductor layer (726) covering the via contacts (724 and 742) until the via contacts (724 and 742) are exposed.

[0091] As illustrated in FIG. 7b, the trench (727) (illustrated in FIG. 7a) is filled with a dielectric layer. For example, a dielectric layer such as silicon oxide may be filled by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, as illustrated in FIG. 7b, an insulating structure (728) may be formed at the via contacts (724 and 742) as part of the deposited dielectric layer.

[0092] In some embodiments, a second via contact is formed on the other first via contact and contacts the other via contact and extends through an insulating structure. To form the second via contact, in some embodiments, a hole is formed by removing a portion of the insulating structure to expose a first via contact other than the first via contact, and the hole is filled by depositing a metal layer. The metal layer may include W.

[0093] As illustrated in FIG. 7c, the hole (746) is formed by removing a portion of the insulating structure (728) to expose one end of the via contact (742) other than the via contact (724). The hole (746) may be formed by etching the insulating structure (728) using, for example, dry etching and / or wet etching to selectively remove the portion of the insulating structure (728) covering the via contact (742) other than the via contact (724) until the via contact (742) is exposed. An etching mask may first be patterned using a photolithography process to expose only the portion of the insulating structure (728) covering the via contact (742) other than the via contact (724). The etching mask can then protect the portion of the insulating structure (728) covering the via contact (724) during the etching process. It is understood that in some examples, other holes (747) may be formed by the same process of forming holes (746) to expose components of memory stacks (748), such as the source end of a slit structure or a NAND memory string (750).

[0094] As illustrated in FIG. 7d, the hole (746) (illustrated in FIG. 7c) is filled with a metal layer such as W. For example, the hole (746) can be filled by depositing a metal layer such as W by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, as illustrated in FIG. 7d, a via contact (744) can be formed through an insulating structure (728) and land on and contact the via contact (742). Conversely, as illustrated in FIG. 7d, a via contact that contacts the via contact (724) cannot be formed on the via contact (724). It is understood that in some examples, for instance, another via contact (749) in contact with it on a component within a memory stack (748), such as a source end of a slit structure or a NAND memory string (750), can be formed by the same process as forming the via contact (744).

[0095] Method 900 proceeds to operation 910 as illustrated in FIG. 9, wherein a dummy pad is formed on an insulating structure and separated from the first via contact by the insulating structure. In some embodiments, the pad is formed on the second via contact in contact with it. The dummy pad and the pad can be formed by the same process.

[0096] As illustrated in FIG. 7d, a pad layer (729), such as aluminum, is deposited on the via contact (744). For example, a metal layer such as aluminum may be deposited on the via contact (744 and 749) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0097] As illustrated in FIG. 7e, the pad layer (729) (illustrated in FIG. 7d) is patterned to form a dummy pad (730) and a pad (745). The pad (745) can be formed on the via contact (744) in contact with it and thus electrically connected to the functional circuit (738) of the device layer (710) through the via contacts (744 and 742) and the interconnect structure (740). Conversely, the dummy pad (730) can be formed on the insulating structure (728) and separated from the via contact (724) by the insulating structure (728). Thus, the dummy pad (730) can be electrically separated from the interconnect structure (714). To form a dummy pad (730) and a pad (745), a patterning process (e.g., photolithography and dry / wet etching of the pad layer (729)) may be performed on the pad layer (729). A dielectric layer (732) (e.g., including silicon nitride) and a protective layer (734) (e.g., including polyimide) are subsequently formed on the dummy pad (730) and the pad (745), and then a patterning process follows to expose the dummy pad (730) and the pad (745) by forming openings (736 and 746) through the dielectric layer (732) and the protective layer (734).

[0098] In some examples, unlike the operation (906) in which a first via contact is formed on an interconnect structure and connected to an interconnect structure, it is understood that a dielectric layer is formed on an interconnect structure.

[0099] As illustrated in FIG. 8a, a dielectric layer (801) is formed on an interconnect structure (714). That is, according to some embodiments, via contacts (742) are formed and connected only to the interconnect structure (740) and not to the interconnect structure (714).

[0100] In some embodiments, an insulating structure is formed at another first via contact. In some embodiments, to form an insulating structure, a portion of the semiconductor layer is removed to form a trench, thereby exposing another first via contact, and a dielectric layer is deposited to fill the trench.

[0101] As illustrated in FIG. 8a, the trench (727) is formed by removing a portion of the semiconductor layer (726) to expose one end of the via contact (742). The trench (727) may be formed by etching the semiconductor layer (726) using, for example, dry etching and / or wet etching to remove a portion of the semiconductor layer (726) covering the via contact (742) until the via contact (742) is exposed.

[0102] As illustrated in FIG. 8b, the trench (727) (illustrated in FIG. 8a) is filled with a dielectric layer. For example, a dielectric layer such as silicon oxide may be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to fill the trench (727). Thus, as illustrated in FIG. 8b, an insulating structure (728) may be formed on the via contact (742) as part of the deposited dielectric layer.

[0103] In some embodiments, a second via contact extending through an insulating structure is formed. In some embodiments, another second via contact is formed that is connected to another first via contact and extends through an insulating structure. To form the second via contact and the other second via contact, in some embodiments, a portion of the insulating structure is removed to form a hole through the insulating structure, and a metal layer is deposited to fill the hole. The metal layer may include W.

[0104] As illustrated in FIG. 8c, holes (746 and 802) are formed by removing a portion of the insulating structure (728). Hole (746) may expose one end of the via contact (742) and hole (802) may be aligned with the interconnect structure (714). Holes (746 and 802) may be formed by etching the insulating structure, for example using dry etching and / or wet etching, to selectively remove the portion of the insulating structure (728) covering the via contact (742) and the portion of the insulating structure (728) aligned with the interconnect structure (714) until the via contact (742) is exposed. The etching mask may first be patterned using a photolithography process to expose a portion of the insulating structure (728) covering the via contact (742) and a portion of the insulating structure (728) aligned with the interconnect structure (714). It is understood that in some examples, other holes (747) may be formed by the same process of forming holes (746 and 802) to expose components of the memory stack (748), such as the source end of the slit structure or the NAND memory string (750).

[0105] As illustrated in FIG. 8d, the holes (746 and 802) (illustrated in FIG. 8c) are filled with a metal layer such as W. For example, a metal layer such as W may be deposited to fill the holes (746 and 802) by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Thus, a via contact (744) may be formed through an insulating structure (728) as illustrated in FIG. 8d, and may land on and contact the via contact (742). Another via contact (804) may be formed by landing on the dielectric layer (801) through an insulating structure (728) as illustrated in FIG. 8d and overlaying with an interconnect structure (714). It is understood that in some examples, other via contacts (749) may be formed by the same process that forms via contacts (744 and 804) in contact with, for example, on a component within a memory stack (748), such as a source end of a slit structure or a NAND memory string (750).

[0106] In some embodiments, a dummy pad is formed on it in contact with a second via contact. In some embodiments, a pad is formed on it in contact with another second via contact. The dummy pad and the pad can be formed by the same process.

[0107] As illustrated in FIG. 8d, a pad layer (729), such as aluminum, is deposited on the via contacts (744 and 804). For example, a metal layer, such as aluminum, may be deposited on the via contacts (744, 804 and 749) by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0108] As illustrated in FIG. 8e, a pad layer (729) (shown in FIG. 8d) is patterned to form a dummy pad (730) and a pad (745). The pad (745) can be formed on a via contact (744) in contact with it and thus electrically connected to the functional circuit (738) of the device layer (710) through the via contacts (744 and 742) and the interconnect structure (740). The dummy pad (730) can be formed on the via contact (804) in contact with it. However, the dummy pad (730) and the non-contact (804) can be separated from the interconnect structure (714) by a dielectric layer (801). Thus, the dummy pad (730) can be electrically separated from the interconnect structure (714). To form dummy pads (730) and pads (745), a patterning process (e.g., photolithography and dry / wet etching of the pad layer (729)) may be performed on the pad layer (729). A dielectric layer (732) (e.g., including silicon nitride) and a protective layer (734) (e.g., including polyimide) may subsequently be formed on the dummy pads (730) and pads (745), and a patterning process may follow to form openings (736 and 746) through the dielectric layer (732) and the protective layer (734) to expose the dummy pads (730) and pads (745), respectively.

[0109] The description of the specific embodiment described above can be easily modified and / or adjusted to suit various applications. Accordingly, such adaptations and modifications are intended to be within the equivalent meaning and scope of the disclosed embodiment based on the disclosures and guidance set forth in this specification.

[0110] The breadth and scope of the present disclosure should not be limited by the exemplary embodiments described above, but should be defined only by the following claims and corresponding claims.

Claims

Claim 1 A semiconductor device comprises: a device layer; a dummy pad; a dielectric structure extending vertically between the device layer and the dummy pad; and an interconnect structure extending vertically between the device layer and the dielectric structure, wherein the dummy pad is disposed on the top surface of the semiconductor device so as to be wire bonded, and the interconnect structure, the dielectric structure, and the dummy pad are vertically overlaid such that the dummy pad is electrically separated from the interconnect structure by the dielectric structure. Claim 2 A semiconductor device according to claim 1, further comprising a semiconductor layer between the dummy pad and the interconnect structure, wherein the dielectric structure comprises an insulating structure on the semiconductor layer. Claim 3 A semiconductor device according to paragraph 2, wherein the lateral dimension of the insulating structure is larger than the lateral dimension of the dummy pad. Claim 4 A semiconductor device according to paragraph 2, further comprising a first via contact that is in contact with an interconnecting structure and separated from a dummy pad by an insulating structure. Claim 5 In paragraph 4, the semiconductor device wherein the first via contact comprises tungsten. Claim 6 A semiconductor device according to claim 1, further comprising a second via contact that contacts a dummy pad and extends in a vertical direction, wherein the dielectric structure comprises a dielectric layer between the second via contact and an interconnection structure. Claim 7 A semiconductor device according to claim 6, wherein the second via contact is separated from the interconnect structure by the dielectric layer. Claim 8 In claim 6, the semiconductor device wherein the second via contact comprises tungsten. Claim 9 A semiconductor device according to claim 1, further comprising a bonding interface between a dummy pad and a device layer, wherein the interconnect structure comprises a bonding contact in the bonding interface. Claim 10 In claim 9, the semiconductor device wherein the interconnect structure further comprises a device contact between the bonding interface and the device layer. Claim 11 A semiconductor device according to claim 1, further comprising: a pad; another second via contact in contact with the pad; another first via contact in contact with the other second via contact; and another interconnect structure in contact with the other first via contact and the device layer. Claim 12 In paragraph 11, the pad and the dummy pad are in the same plane; and the interconnect structure and the other interconnect structure are in the same plane, semiconductor device. Claim 13 A semiconductor device comprising: a device layer including an electrostatic discharge (ESD) circuit and a functional circuit; a dummy pad separated from the functional circuit; and an interconnection structure between the device layer and the dummy pad in a vertical direction, wherein the dummy pad is disposed on the top surface of the semiconductor device so as to be wire bonded, and the dummy pad is connected to the ESD circuit through at least the interconnection structure. Claim 14 A semiconductor device according to claim 13, further comprising a first via contact between a dummy pad and an interconnection structure, wherein the first via contact is connected to the interconnection structure. Claim 15 A semiconductor device according to claim 14, further comprising: a semiconductor layer between a dummy pad and a first via contact; a spacer within the semiconductor layer; and a second via contact in contact with the dummy pad and extending through the spacer. Claim 16 A method for forming a semiconductor device comprising: forming a device layer including a functional circuit; forming an interconnect structure separated from the functional circuit on the device layer; forming a first via contact connected to the interconnect structure on the interconnect structure; forming an insulating structure on the first via contact; and forming a dummy pad separated from the first via contact by the insulating structure on the insulating structure, wherein the dummy pad is disposed on the top surface of the semiconductor device so as to be wire bonded, and the interconnect structure, the insulating structure, and the dummy pad are overlaid in a vertical direction such that the dummy pad is electrically separated from the interconnect structure by the insulating structure. Claim 17 A method for forming a semiconductor device according to claim 16, comprising: forming another interconnect structure connected to a functional circuit on the device layer; forming another first via contact connected to the other interconnect structure on the other interconnect structure; forming a second via contact extending through an insulating structure on the other first via contact in a state of contact with the other first via contact; and forming a pad on the second via contact in a state of contact with the second via contact. Claim 18 A method for forming a semiconductor device according to claim 17, wherein forming the insulating structure comprises: removing a portion of a semiconductor layer to form a trench to expose the first via contact and the other first via contact; and depositing a dielectric layer to fill the trench. Claim 19 A method for forming a semiconductor device according to claim 17, wherein forming the second via contact comprises: removing a portion of the insulating structure to form a hole to expose the other first via contact, which is not the first via contact; and depositing a metal layer to fill the hole. Claim 20 A method for forming a semiconductor device according to claim 19, wherein the metal layer comprises tungsten. Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete

Images