Semiconductor device

Abstract

The present invention provides a semiconductor device comprising a semiconductor layer, a trench gate structure, and a buffer layer, wherein the semiconductor layer comprises a first surface and a second surface facing each other, and at least a portion of the trench gate structure is located in a trench of the first surface of the semiconductor layer, wherein the semiconductor layer comprises a source region, a drift region, and a body region, and the buffer layer is a heterogeneous epitaxial layer of the semiconductor layer and covers the inner surface of the trench and the first surface of the semiconductor layer, and the buffer layer is located between the gate dielectric layer of the trench gate structure and the semiconductor layer, and by using a heterogeneous epitaxial layer of the conductor layer as the buffer layer, a more reliable gate dielectric layer is formed, thereby suppressing the formation of carbon clusters in the gate dielectric layer and improving the reliability of the device.

Description

Technology Field

[0001] The present invention relates to the field of semiconductor device technology, and specifically to a semiconductor device having a trench gate structure. Background Technology

[0002] Silicon carbide (SiC) semiconductor devices have advantages such as fast turn-on / off speeds and high power density. Compared to planar transistor structures, vertical transistor structures are advantageous for balancing blocking voltage and conduction resistance within the same area. However, the reliability of the gate dielectric layer is one of the important indicators of a vertical transistor structure. When forming a gate dielectric layer through an oxidation process on the semiconductor layer, the Si within the SiC oxidizes first, forming carbon clusters (C clusters) within the gate dielectric layer. This degrades the uniformity and film quality of the gate dielectric layer, thereby reducing the stability and reliability of the device.

[0003] Taking the above-mentioned problem into account, the objective of the present invention is to provide a semiconductor device capable of suppressing the formation of carbon clusters in the gate dielectric layer by forming a more reliable gate dielectric layer using a hetero-epitaxial layer as a buffer layer in the semiconductor layer.

[0004] A semiconductor device provided by an embodiment of the present invention comprises a semiconductor layer, a trench gate structure, and a buffer layer, wherein the semiconductor layer has a first surface and a second surface facing each other, and at least a portion of the trench gate structure is located in a trench of the first surface of the semiconductor layer.

[0005] Among them, the semiconductor layer includes a source region, a drift region and a body region, and

[0006] The source region extends from the first surface toward the second surface; and

[0007] At least a portion of the above drift region is located between the body region and the second surface of the semiconductor layer, and

[0008] The first portion of the body region is located between the source region and the drift region along the direction from the first surface to the second surface, and both the first portion of the body region and the source region are adjacent to the first side wall of the trench, and

[0009] Among them, the buffer layer is a heterogeneous epitaxial layer of the semiconductor layer, the buffer layer covers the inner surface of the trench and the first surface of the semiconductor layer, and the buffer layer is located between the gate dielectric layer of the trench gate structure and the semiconductor layer.

[0010] Among them, the source region and the drift region are of the first conduction type, and the body region is of the second conduction type, and the first conduction type and the second conduction type are opposite.

[0011] Optionally, the semiconductor layer comprises a silicon carbide semiconductor layer, and the buffer layer comprises one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer.

[0012] Optionally, the thickness of the buffer layer includes the thickness of one or more atomic layers.

[0013] Optionally, the first, second, and third portions of the body region are sequentially adjacent along the width direction of the trench gate structure, and

[0014] The first and second portions of the body region are located between two trench gate structures, the first portion and the first sidewall of the trench are adjacent, the second portion is close to the second sidewall of the trench, and the first sidewall and the second sidewall face each other.

[0015] The third part and the second part are adjacent to the same trench, and the third part is located between the bottom surface of the trench and the second surface, and the third part and the first part are separated by the drift area,

[0016] Among them, the second part and the second side wall are adjacent, or the second part and the second side wall are separated by the drift area.

[0017] Optionally, a third portion of the body region extends from the bottom surface of the trench toward the second surface, or

[0018] At least a portion of the bottom surface of the above trench and a third portion of the above body region are spaced apart from the first surface along the direction of the second surface by the drift region.

[0019] Optionally, the second portion of the body region includes an interconnected first sub-region and a second sub-region, and

[0020] Along the width direction of the trench gate structure, the first sub-region is adjacent to the first part of the body region and the second sub-region is adjacent to the third part of the body region, and

[0021] Among them, the distance from the edge of the first part of the body region in the direction toward the second surface to the first surface is the first distance, the distance from the edge of the first sub-region in the direction toward the second surface to the first surface is the second distance, and the distance from the edge of the second sub-region in the direction toward the second surface to the first surface is the third distance, and

[0022] The above third distance is greater than the above second distance, and the above second distance is greater than the above first distance.

[0023] Optionally, the distance from the bottom surface of the trench to the first surface is the fourth distance, and the second distance is not smaller than the fourth distance.

[0024] Optionally, along the direction from the second surface to the first surface, the distance between the third part of the body region and the bottom surface of the trench separated by the drift region is the fifth distance, and

[0025] The sum of the above 4th distance and 5th distance is equal to the above 2nd distance.

[0026] Optionally, the edges of the second and third parts of the body region facing the second surface are interconnected,

[0027] The edge of the third part in the direction toward the second surface is closer to the second surface than the edge of the second part in the direction toward the second surface.

[0028] Optionally, the semiconductor layer further includes a channel drain region located between a first portion of the body region and the drift region, thereby the source region, the first portion of the body region and the channel drain region are sequentially adjacent in a direction from the first surface toward the second surface, and all are adjacent to the first sidewall of the trench.

[0029] Each of the above channel drain regions is adjacent to the second part of the body region, and the channel drain region and the third part of the body region are separated by the drift region.

[0030] Among them, the above channel drain region is a first type of conduction.

[0031] Selectably, the doping concentration of the channel drain region is greater than the doping concentration of the drift region.

[0032] Optionally, the distance from the edge of the channel drain region in the direction toward the second surface to the first surface is not greater than the distance from the bottom of the trench to the first surface,

[0033] The distance from the edge of the channel drain area in the direction toward the second surface to the first surface is greater than the distance from the bottom of the trench to the first surface, and the channel drain area is adjacent to a part of the bottom of the trench.

[0034] Optionally, the semiconductor layer further includes a channel drain region located between a first portion of the body region and the drift region, so that the source region, the first portion of the body region and the channel drain region are sequentially adjacent from the first surface toward the second surface and all are adjacent to the first sidewall of the trench.

[0035] The channel drain region is also adjacent to the drift region and the second part of the body region, respectively, and the channel drain region and the third part of the body region are separated by the drift region.

[0036] Among them, the channel drain region is of the first conduction type, and

[0037] The distance from the edge facing the second surface of the channel drain region to the first surface is the sixth distance, and

[0038] The sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, so that the channel drain area and the second sub-area are separated by the drift area along the width direction of the trench gate structure.

[0039] Optionally, the semiconductor layer further includes a body contact region, the body contact region extends in a direction toward the second surface from the first surface, and the body contact region and the body region are adjacent.

[0040] The above body contact area is adjacent to the source area or spaced apart by the body area,

[0041] Among them, the above body contact area is a second type of conduction.

[0042] Optionally, along the extension direction of the trench gate structure, a portion of the body contact area is adjacent to the second side wall, and there is a gap between another portion of the body contact area and the second side wall, and the portion having a gap between the body contact area and the adjacent portion of the second side wall is alternately installed along the extension direction of the trench gate structure,

[0043] The body contact area and the second side wall are both separated by the body area.

[0044] Optionally, the trench gate structure comprises the gate dielectric layer and the gate conductor, and

[0045] The gate dielectric layer covers the buffer layer on the inner surface of the trench and also covers a portion of the buffer layer located on the first surface adjacent to the trench, and the trench extends in a direction from the first surface toward the second surface.

[0046] A portion of the gate conductor is located within the trench, and another portion extends out of the trench to cover the gate dielectric layer.

[0047] Among them, the gate dielectric layer is located between the gate conductor and the buffer layer, thereby separating the gate conductor and the buffer layer.

[0048] Optionally, the semiconductor device is a metal-oxide semiconductor, which is a field-effect transistor or an insulated gate bipolar transistor.

[0049] Optionally, between the two trench gate structures, the source region extends from the first sidewall of one of the trenches toward the second sidewall of the other trench and is also adjacent to the second portion of the body region.

[0050] One of the above technical solutions has the following beneficial effects:

[0051] By forming heterogeneous epitaxial layers on the inner surface of the trench of the semiconductor layer and the first surface of the semiconductor layer, and by using the heterogeneous epitaxial layers of the semiconductor layer as buffer layers, more reliable gate dielectric symmetry can be formed, thereby suppressing the formation of carbon clusters in the gate dielectric layer.

[0052] In some embodiments, a portion of the body region is installed below the bottom surface of the trench, and by causing a drift region to separate the bottom of the trench from the portion of the body region, the electric field distribution near the bottom and corner of the trench is controlled, thereby mitigating the problem of the gate dielectric layer being damaged due to excessive concentration of the electric field at the bottom and corner of the trench.

[0053] In some embodiments, by installing the channel drain region, the first part of the body region, and the source region sequentially adjacent to the first sidewall of the same trench in the vertical direction, the length of the channel is controlled using the position of the channel drain region, thereby improving the uniformity of the channel length, the uniformity of the overlapping portion of the channel and drain, and the uniformity of the drain concentration, and thus improving the overall function of the device.

[0054] In some embodiments, a second part of the body region in the horizontal direction is divided into a first sub-region and a second sub-region, and the first part of the body region, the first sub-region, and the second sub-region are sequentially adjacent so that the distance from the bottom edge of the first sub-region to the first surface is adjusted, and the distance from the first sidewall of the trench to the body region along the direction from the first surface to the second surface is gradually increased, so that the current path through which current flows to the second surface after passing through the source region and the channel in the turn-on state of the device is gradually widened, thereby lowering the conduction resistance and further improving the function of the device.

[0055] In some embodiments, the gate dielectric layer extends from the inner surface of the trench to the first surface of the semiconductor layer, protecting the buffer layer located on the first surface of the semiconductor layer and the portion adjacent to the trench.

[0056] The above description and the detailed description to be provided below are merely illustrative and should not be understood as a limitation to the present invention. Brief explanation of the drawing

[0057] To more clearly explain the technical methods of the embodiments of the present invention, the following is a brief introduction to the drawings of the embodiments. It is obvious that the drawings described below are merely some embodiments of the present invention and do not constitute a limitation on the invention. FIG. 1 is a schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a schematic diagram showing a cross-section cut along line AA of Figure 1. FIGS. 3 to 8 are schematic diagrams showing cross-sections of some steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 9 is a schematic diagram showing the structure of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a schematic diagram showing the structure of a semiconductor device according to a third embodiment of the present invention. FIG. 11 is a schematic diagram showing the structure of a semiconductor device according to a fourth embodiment of the present invention. FIG. 12 is a schematic diagram showing the structure of a semiconductor device according to the fifth embodiment of the present invention. FIG. 13 is a schematic diagram showing the structure of a semiconductor device according to the sixth embodiment of the present invention. FIG. 14 is a schematic diagram showing the structure of a semiconductor device according to the seventh embodiment of the present invention. FIG. 15 is a schematic diagram showing the structure of a semiconductor device according to the eighth embodiment of the present invention. FIG. 16 is a schematic diagram showing the structure of a semiconductor device according to the ninth embodiment of the present invention. FIGS. 17 to 19 are schematic diagrams showing cross-sections of some steps of a method for manufacturing a semiconductor device according to the ninth embodiment of the present invention. Specific details for implementing the invention

[0058] The present invention will be described in detail with reference to the drawings below. In each drawing, the same elements are indicated by similar reference numerals. For clarity, parts of the drawings are not drawn in proportion. Additionally, some known parts may not be shown. For simplicity and clarity, a semiconductor structure obtained through multiple steps can be explained in a single drawing.

[0059] It must be understood that when describing the structure of a device, if one layer or region is said to be located on the “top surface” or “top side” of another layer or region, it may be located directly on the top surface of the other layer or region, or it may include other layers or regions between it and the other layer or region. Furthermore, if the device is flipped over, the corresponding layer or region may be located on the “bottom surface” or “bottom side” of the other layer or region.

[0060] To describe cases where it is located directly on the upper surface of another layer or another area, this specification will use descriptive methods such as “directly located on the upper surface of …” or “adjacent to it on the upper surface of …”.

[0061] Power devices typically include an active device region, an edge termination region, and a crack-stop or shielding region. The active device region includes an active device array. The present invention relates to an active device structure. The size of the active devices may vary depending on product requirements, and a body region may exist between the active devices in the active device region.

[0062] To facilitate a better understanding of the present invention, the following description explains many specific details of the invention, such as the structure, material, size, processing steps, and techniques of the device. However, it is obvious to those skilled in the art that the present invention may be realized without adhering to these specific details.

[0063] FIG. 1 is a schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a schematic diagram showing a cross-section cut along line AA in FIG. 1. In FIG. 1, the structure on the upper side of the buffer layer and a part of the trench gate structure are omitted to more clearly express the positional relationship between each structure.

[0064] As shown in FIGS. 1 and 2, the semiconductor device of the first embodiment of the present invention comprises a semiconductor (100), a buffer layer (190), a plurality of trench gate structures (150), an interlayer dielectric layer (160), and a source metal layer (170). The semiconductor layer (100) comprises a first surface (10), a second surface (20), and a plurality of trenches (102) facing each other, and the trenches (102) extend to the semiconductor layer (100) in a direction from the first surface (10) toward the second surface (20). The trenches (102) have a first sidewall (102a), a second sidewall (102b), and a bottom surface (102c), wherein the first sidewall (102a) and the second sidewall (102b) face each other. Multiple trenches (102) extend along the Y-axis direction and are spaced apart along the X-axis direction (which can be understood as the width direction of the trenches (102)). Optionally, the X-axis, Y-axis, and Z-axis directions (along the direction of the first surface (10) from the second surface (20)) are mutually perpendicular. Optionally, the X-axis direction is the <11-20> direction or the <1-100> direction, and the plane of the first side wall (102a) and the plane of the second side wall (102b) are the (11-20) plane or the (1-100) plane. Multiple trench gate structures (150) are located within the corresponding trenches (102), and the extension direction of the trench gate structures (150) and the extension direction of the trenches (102) are the same. Among them, the semiconductor layer (100) is a stacked structure composed of, for example, a SiC substrate or a SiC substrate and an epitaxial layer. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings regarding the material and number of layers of the semiconductor layer (100) according to demand.

[0065] The semiconductor layer (100) includes a drift region (101), a body region (110), a source region (130), a body contact region (140), and a drain contact region (180). Among these, the source region (130) and the drift region (101) are of the first conduction type, and the body region (110) and the body contact region (140) are of the second conduction type, and the doping concentration of the body contact region (140) is greater than the doping concentration of the body region (110). The first conduction type and the second conduction type are opposite. The first conduction type is one of the P-type and the N-type, and the second conduction type is the other of the P-type and the N-type.

[0066] The semiconductor device of the present embodiment is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and may also be an Insulated Gate Bipolar Transistor (IGBT). For example, the conduction type of the drain contact region (180) may be installed as a corresponding first conduction type or second conduction type. However, the present invention is not limited thereto, and those skilled in the art may make other settings according to the conduction type of each region of the semiconductor layer (100) so that the semiconductor device may be a MOSFET or an IGBT.

[0067] The buffer layer (190) covers the inner surface of the trench (102) and the first surface (10) of the semiconductor layer (100). Among these, the buffer layer (190) is a heterogeneous epitaxial layer of the crystal form of the semiconductor layer (100), and optionally, the semiconductor layer (100) is a semiconductor layer containing C or Si elements, for example, a SiC semiconductor layer, or the semiconductor layer (100) may be a semiconductor layer containing other elements, and the buffer layer (190) may include one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heterogeneous epitaxial layer may be other semiconductor crystal materials or crystal materials with very little in situ impurity doping. The thickness of the buffer layer (190) is at the atomic layer level, for example, the thickness of the buffer layer (190) may be one atomic layer thick or two to three atomic layers thick, so as to avoid creating an energy barrier that is too large for the flow of carriers.

[0068] The trench gate structure (150) includes a gate dielectric layer (151) and a gate conductor (152). The gate dielectric layer (151) covers a buffer layer (190) located on the inner surface of the trench (102), and the gate conductor (152) is located in the trench (102). The gate dielectric layer (151) is located between the buffer layer (190) and the gate conductor (152) to separate the buffer layer (190) from the gate conductor (152).

[0069] In this embodiment, a buffer layer (190) is formed on the inner surface of the trench (102) of the semiconductor layer (100) and on the first surface (10) of the semiconductor layer (100), and the buffer layer (190) is a heterogeneous epitaxial layer of the semiconductor layer (100), and the buffer layer (190) prevents carbon clusters from forming on the gate dielectric layer (151) by separating the gate dielectric layer (151) and the semiconductor layer (100).

[0070] The body region (110) includes a first part (111), a second part (112), and a third part (113) that are sequentially interconnected along the X-axis direction. The first part (111) is adjacent to the first sidewall (102a) of the trench (102), the second part (112) is adjacent to the second sidewall (102b) of the trench (102), and the third part (113) is located between the bottom surface (102c) of the trench (102) and the second surface (20), and is adjacent to the bottom surface (102c). The edges of the second part (112) and the third part (113) in the direction toward the second surface (20) are generally uniform. Optionally, the doping concentrations of the first part (111), the second part (112), and the third part (113) are different.

[0071] The source region (130) extends in a direction toward the second surface (20) from the first surface (10) of the semiconductor layer (100). The source region (130) and the drift region (101) are separated along the Z-axis direction by the first part (111) of the body region (110). Between the two trench gate structures (150), the source region (130) and the first part (111) are adjacent to the first sidewall (102a) of the same trench (102).

[0072] Optionally, between two trench gate structures (150), the source region (130) extends from the first sidewall (102a) of one of the trenches (102) toward the second sidewall (102b) of the other trench (102) so that the source region (130) and the second part (112) of the body region (110) are adjacent. When the junction depth of the source region (130) is relatively deep, increasing the width of the source region (130) is advantageous for reducing the contact diffusion resistance of the source region (130).

[0073] The body contact region (140) extends in a direction toward the second surface (20) from the first surface (10) of the semiconductor layer (100) and is adjacent to the body region (110). Along the X-axis direction, between two adjacent trench gate structures (150), one end of the body contact region (140) is adjacent to the source region (130), and the other end is adjacent to the second sidewall (102b) of the trench (102), and is not connected to the second sidewall (102b), wherein the body contact region (140) and the second sidewall (102b) are separated by the body region (110). Optionally, the body contact region (140) and the source region (130) are separated by the body region (110).

[0074] Optionally, a portion of the body contact area (140) along the Y-axis direction is adjacent to the second side wall (102b), and a gap is formed between another portion of the body contact area (140) and the second side wall (102b) by being spaced apart by the body area (110), and the portions adjacent to the body contact area (140) and the portion having the gap are alternately installed along the Y-axis direction.

[0075] The capacitance from the gate to the source is composed of three parts, including the capacitance from the gate conductor (152) to the body region (110), the capacitance from the gate conductor (152) to the body contact region (140), and the capacitance from the gate conductor (152) to the source region (130). Among these, the source region (130) and the body region (110) are electrically connected. Since the doping concentration of the body contact region (140) is higher than that of the body region (110) and the capacitance per unit area is relatively high, the total capacitance from the gate to the source can be controlled by adjusting the area of ​​the body contact region (140) that is in direct contact with the second sidewall (150b). Depending on the requirements of different applications or systems, the requirements for the gate charge or the ratio of gate-to-drain capacitance / (gate-to-drain capacitance + gate-to-source capacitance) also differ. For example, during the transistor turn-off process of a hard switch, the drain voltage suddenly rises, causing self-turn-on behavior of the gate due to capacitance coupling. If there is no margin for the gate's self-turn-on, the margin can be improved by increasing the capacitance from the gate to the source.

[0076] The source metal layer (170) is located above the first surface (10) of the semiconductor layer (100) and is adjacent to the buffer layer (190), wherein the source metal layer (170) is electrically connected to the source region (130), the body region (110), and the body contact region (140), respectively, through the buffer layer (190). The interlayer dielectric layer (160) is located between the buffer layer (190) and the source metal layer (170), and the interlayer dielectric layer (160) and the trench gate structure (150) are installed in a corresponding manner to separate the source metal layer (170) and the trench gate structure (150). The source metal layer (170) and the interlayer dielectric layer (160) may be multilayer structures of different materials. As an example of a multilayer source metal layer (170), the source metal layer (170) comprises a tungsten (W) layer directly coated on the buffer layer (190) and an aluminum copper (AlCu) layer directly coated on the tungsten layer. The corresponding embodiment may optionally include parts not shown in the drawing, for example, a gate contact area opened immediately above the gate conductor (152) to connect the gate conductor (152) and the gate metal layer, the gate contact area being located directly on the gate conductor (152), and the gate conductor (152) being separated from the source metal layer (170) through the interlayer dielectric layer (160).

[0077] At least a portion of the drift region (101) is located between the body region (110) and the second surface (20), and is adjacent to the second part (112), the third part (113) of the body region (110), the bottom surface (102c) of the trench (102), and the drain contact region (180), respectively, wherein the drain contact region (180) extends from the second surface (20) of the semiconductor layer (100) toward the first surface (10).

[0078] Furthermore, the semiconductor device of the present embodiment further includes a drain metal layer (not shown) located on the second surface (20) of the semiconductor layer (100) and interconnected with the drain contact region (180).

[0079] FIGS. 3 to 8 are schematic diagrams showing cross-sections of a partial system of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

[0080] As shown in Figure 3, a buffer layer (201) is formed on the first surface (10) of the semiconductor layer (100), and after forming the first doping region (110-1) using an ion implantation process, the buffer layer (201) is removed.

[0081] Furthermore, a buffer layer (202) is formed on the first surface (10) of the semiconductor layer (100), a mask layer (203) is formed on the buffer layer (202), and a plurality of second doping regions (110-2) are formed using an ion implantation process, as shown in FIG. 4. Among these, the plurality of second doping regions (110-2) are adjacent to the first doping region (110-1) and are located between the first doping region (110-1) and the second surface (20), and are distributed spaced apart along the X-axis direction.

[0082] Furthermore, the buffer layer (202) and the mask layer (203) are removed, and the first doping region (110-1) and the second doping region (110-2) form a body region (110) as shown in FIG. 5.

[0083] Furthermore, a mask layer (204) is formed on the first surface (10) of the semiconductor layer (100), and a plurality of trenches (102) are formed using an etching process, as shown in Figure 6. Among them, the body region (110) includes a first part (111), a second part (112), and a third part (113) that are sequentially adjacent along the extension direction of the X-axis, and the first part (111) and the first side wall (102a) of the trench (102) are adjacent, the second part (112) and the second side wall (102b) of the trench (102) are adjacent, and the third part (113) and the bottom surface (102c) of the trench (102) are adjacent.

[0084] Furthermore, the mask layer (204) is removed, and a buffer layer (190) is formed on the inner surface of the trench (102) and the first surface (10) of the semiconductor layer (100) using an epitaxial process, as shown in FIG. 7. Among these, the buffer layer (190) is a heterogeneous epitaxial layer of the semiconductor layer (100) and includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heterogeneous epitaxial layer may be other semiconductor crystal materials or may be a material with very little in situ impurity doping. In this embodiment, since the body region (110) is formed before the buffer layer (190) is formed, the impurities injected when forming the body region (110) do not remain on the surface of the buffer layer (190), thereby improving the reliability of the device.

[0085] Furthermore, a gate dielectric layer (151) is formed on the buffer layer (190) as shown in FIG. 8. Among these, the gate dielectric layer (151) is formed using, for example, a thermal oxidation process, and in this process, a portion of the buffer layer (190) is consumed. After the gate dielectric layer (151) is formed, the thickness of the buffer layer (190) is at the atomic layer level, which not only suppresses the formation of a carbon cluster low-quality structure at the interface between the gate dielectric layer and the semiconductor layer, but also, the thickness of the buffer layer (190) is relatively thin so that it does not create an energy barrier too large for carrier flow. In a subsequent process step, the gate dielectric layer (151) on the upper side of the first surface (10) is removed.

[0086] FIG. 9 is a schematic diagram showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0087] As shown in FIG. 9, the description of the semiconductor device of the second embodiment of the present invention and the first embodiment may be shortened, and reference may be made to the description in FIG. 1 through 8. The difference is that in this embodiment, at least a portion of the bottom surface (102c) of the trench (102) and the third portion (113) of the body region (110) are separated by a drift region (101) along the Z-axis direction. Optionally, at a corner adjacent to the second side wall (102b) and the bottom surface (102c), the third portion (113) and the bottom surface (102c) are adjacent. Optionally, the third portion (113) and the bottom surface (102c) are completely separated by a drift region (101). Optionally, the second portion (112) of the body region (110) and the second side wall (102b) of the trench (102) are separated by a drift region (101).

[0088] In this embodiment, the drift region (101) separates the bottom surface (102c) of the trench (102) from the third part (113) of the body region (110), thereby controlling the electric field distribution near the bottom and corner of the trench (102), which mitigates the problem of damage caused by excessive concentration of the electric field at the bottom and corner of the trench (102) of the gate dielectric layer (151).

[0089] FIG. 10 is a schematic diagram showing the structure of a semiconductor device of the third embodiment of the present invention.

[0090] As shown in FIG. 10, the explanation regarding the similarities between the semiconductor device according to the third embodiment of the present invention and the first embodiment is shortened, and reference is made to the explanations in FIG. 1 to 8. The difference is that the semiconductor layer (100) of the present embodiment further includes a channel drain region (120), the channel drain region (120) is of the first conduction type, and the doping concentration of the channel drain region (120) is greater than the doping concentration of the drift region (101).

[0091] The channel drain region (120) is located between the first part (111) of the body region (110) and the drift region (101), and the source region (130), the first part (111) of the body region (110), and the channel drain region (120) are sequentially adjacent in the direction from the first surface (10) toward the second surface (20). Among these, between the two trench gate structures (150), the first part (111), the channel drain region (120), and the source region (130) are all adjacent to the first side wall (102a) of the same trench (102). The channel drain region (120) is adjacent to the bottom surface (102c) of the trench (102) and is also adjacent to the second part (112). The third part (113) of the channel drain area (120) and the body area (110) is separated by the drift area (101). Optionally, the distance from the edge in the direction toward the second surface (20) of the channel drain area (120) to the first surface (10) is not greater than the distance from the bottom surface (102c) of the trench (102) to the first surface (10). Optionally, the distance from the edge in the direction toward the second surface (20) of the channel drain area (120) to the first surface (10) is greater than the distance from the bottom surface (102c) of the trench (102) to the first surface (10), and the channel drain area (120) and the bottom surface (102c) of the trench (102) are adjacent.

[0092] In this embodiment, when the semiconductor device is in a turned-on state, the first part (111) of the body region (110) and the adjacent part of the first side wall (102a) of the trench (102) are opposite in shape, thereby forming a channel. By installing a channel drain region (120) on the bottom surface (102c) adjacent to the trench (102), the length of the channel is controlled more accurately, thereby improving the uniformity of the lengths of multiple channels in the semiconductor device. At the same time, installing the channel drain region (120) improves the uniformity of the overlapping portion of the channel and drain region and the uniformity of the drain region concentration, thereby improving the overall function of the device.

[0093] In some specific embodiments, the channel drain region (120) and the source region (130) are formed in the same process step to better control the length of the channel and further improve the uniformity of the channel length.

[0094] FIG. 11 is a schematic diagram showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

[0095] As shown in FIG. 11, the explanation regarding the similarities between the semiconductor device according to the fourth embodiment of the present invention and the third embodiment may be shortened, and reference may be made to the explanation in FIG. 10. The difference is that in this embodiment, at least a portion of the bottom surface (102c) of the trench (102) and the third portion (113) of the body region (110) are separated by the drift region (101) along the Z-axis direction. Optionally, at the corner adjacent to the second side wall (102b) and the bottom surface (102c), the third portion (113) is adjacent to the bottom surface (102c). Optionally, the third portion (113) and the bottom surface (102c) are completely separated by the drift region (101). Optionally, the second portion (112) of the body region (110) and the second side wall (102b) of the trench (102) are separated by the drift region (101).

[0096] In this embodiment, the drift region (101) is spaced apart from the bottom surface (102c) of the trench (102) and the third part (113) to control the electric field distribution near the bottom and corner of the trench (102), and the gate dielectric layer (151) can mitigate the problem of damage caused by excessive concentration of the electric field at the bottom and corner of the trench (102).

[0097] FIG. 12 is a schematic diagram showing the structure of a semiconductor device according to the fifth embodiment of the present invention.

[0098] As shown in FIG. 12, the explanation regarding the similarities between the semiconductor device according to the fifth embodiment of the present invention and the second embodiment may be shortened, and reference may be made to the explanation in FIG. 9. The difference is that in this embodiment, the second part (112) of the body region (110) includes an interconnected first sub-region (112a) and a second sub-region (112b). Along the X-axis direction, the first sub-region (112a) and the first part (111) of the body region (110) are adjacent, and the second sub-region (112b) and the third part (113) of the body region (110) are adjacent.

[0099] The distance from the edge of the direction toward the second surface (20) of the first part (111) to the first surface (10) is the first distance d1, the distance from the edge of the direction toward the second surface (20) of the first sub-region (112a) to the first surface (10) is the second distance d2, and the distance from the edge of the direction toward the second surface (20) of the second sub-region (112b) to the first surface (10) is the third distance d3, wherein the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1.

[0100] In this embodiment, by adjusting the distance d2 from the bottom edge of the first sub-region (112a) to the first surface, the edge approaching the first sidewall (102a) of the body region (110) has a stepped shape, and the distance from the first sidewall (102a) to the second part (112) of the body region (110) gradually increases in the direction from the first surface (10) to the second surface (20), so that when the device is turned on, the current path through which current flows to the second surface (20) after passing through the source region (130) and the channel becomes wider, thereby lowering the conduction resistance and further improving the function of the device.

[0101] Selectably, the distance from the bottom surface (102c) of the trench (102) to the first surface (10) is a fourth distance d4, wherein the second distance d2 is not greater than the fourth distance d4, thereby reducing the high electric field effect received by the bottom of the trench (102).

[0102] Optionally, depending on the Z-axis direction, the distance at which the third part (111) of the body area (110) and the bottom surface (102c) of the trench (102) are separated by the drift area (101) is a fifth distance d5, and the sum of the fourth distance d4 and the fifth distance d5 is equal to the second distance d2, so that the bottom surface (112-1) of the second sub-area (112b) and the separation surface (113-1) of the third part (113) of the body area (110) are generally aligned. Thus, the depth of the second sub-area (112b) is controlled to a relatively reasonable degree, so that the second distance d2 is not too large and the charge compensation is not limited in its help to lower the turn-on resistance.

[0103] FIG. 13 is a schematic diagram showing the structure of a semiconductor device according to the sixth embodiment of the present invention.

[0104] As shown in FIG. 13, the explanation regarding the similarities between the semiconductor device according to the sixth embodiment of the present invention and the third embodiment may be shortened and reference may be made to the explanation in FIG. 10. The difference is that in this embodiment, the second part (112) of the body region (110) includes an interconnected first sub-region (112a) and a second sub-region (112b). Along the X-axis direction, the first sub-region (112a) and the first part (111) of the body region (110) are adjacent, and the second sub-region (112b) and the third part (113) of the body region (110) are adjacent.

[0105] The distance from the edge of the direction toward the second surface (20) of the first part (111) to the first surface (10) is the first distance d1, the distance from the edge of the direction toward the second surface (20) of the first sub-region (112a) to the first surface (10) is the second distance d2, and the distance from the edge of the direction toward the second surface (20) of the second sub-region (112b) to the first surface (10) is the third distance d3, wherein the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1.

[0106] In this embodiment, the distance d2 from the bottom edge of the first sub-region (112a) to the first surface is adjusted so that the edge near the first sidewall (102a) of the body region (110) has a stepped shape, so that the distance from the first sidewall (102a) to the second part (112) of the body region (110) gradually increases along the direction from the first surface (10) to the second surface (20), and the current path through which current flows to the second surface (20) after passing through the source region (130) and the channel is gradually widened in the turn-on state of the device, thereby lowering the conduction resistance and further improving the function of the device.

[0107] Optionally, the distance from the edge toward the second surface (20) of the channel drain area (120) to the first surface (10) is a sixth distance d6, the sixth distance d6 is greater than the second distance d2, the third distance d3 is greater than the sixth distance d6, and a portion of the channel drain area (120) and the second sub-area (112b) are separated by a drift area (101) along the X-axis direction.

[0108] FIG. 14 is a schematic diagram showing the structure of a semiconductor device according to the seventh embodiment of the present invention.

[0109] As shown in FIG. 14, the description of the semiconductor device according to the 7th embodiment of the present invention and the 6th embodiment is shortened, and reference is made to the description in FIG. 13. The difference is that in the embodiment of the present invention, at least a portion of the bottom surface (102c) of the trench (102) and the third portion (113) of the body region (110) are separated by the drift region (101) along the Z-axis direction. Optionally, the third portion (113) and the bottom surface (102c) are adjacent at the corner adjacent to the second side wall (102b) and the bottom surface (102c). Optionally, the third portion (113) and the bottom surface (102c) are completely separated by the drift region (101). Optionally, the second portion (112) of the body region (110) and the second side wall (102b) of the trench (102) are separated by the drift region (101).

[0110] In this embodiment, the drift region (101) is spaced apart from the bottom surface (102c) of the trench (102) and the third part (113), thereby controlling the electric field distribution near the bottom and corner of the trench (102), which mitigates the problem of damage caused by excessive concentration of the electric field at the bottom and corner of the trench (102) of the gate dielectric layer (151).

[0111] FIG. 15 is a schematic diagram showing a semiconductor device structure according to the eighth embodiment of the present invention.

[0112] As shown in FIG. 15, the explanation regarding the similarities between the semiconductor device according to the eighth embodiment of the present invention and the first embodiment may be shortened and reference can be made to FIG. 1 to FIG. 8. The difference is that in this embodiment, a part of the trench gate structure (150) is located within the trench (102), and another part is located on the upper side of the first surface (10). Specifically, the gate dielectric layer (151) covers a buffer layer (190) located on the inner surface of the trench (102) and covers a part of the buffer layer (190) located on the first surface (10) adjacent to the trench (102), and a part of the gate conductor (152) is located in the trench (102), and another part extends out of the trench (102) and covers the gate dielectric layer (151) located on the upper side of the first surface (10).

[0113] The trench gate structure (150) of the present embodiment extends from inside the trench (102) to the upper side of the first surface (10), protecting the first surface (10), the buffer layer (190), and the adjacent portion of the trench (102), thereby reducing damage to the first surface (10), the buffer layer (190), and the adjacent portion of the trench (102) during the manufacturing process.

[0114] Optionally, in the semiconductor device of the eighth embodiment of the present invention, at least a portion of the bottom surface (102c) of the trench (102) and the third portion (113) may be separated by a drift region (101) along the Z-axis direction, as in the second, fourth, fifth, and seventh embodiments of the present invention.

[0115] Optionally, the semiconductor device of the 8th embodiment of the present invention may also have a channel drain region (120) installed, as in the 3rd, 4th, 6th, and 7th embodiments of the present invention.

[0116] Optionally, the semiconductor device of the eighth embodiment of the present invention may have a first sub-region (112a) and a second sub-region (112b) installed, as in the fifth, sixth, and seventh embodiments of the present invention.

[0117] FIG. 16 is a schematic diagram showing a semiconductor device structure according to the ninth embodiment of the present invention.

[0118] As shown in FIG. 16, the description of the semiconductor device of the ninth embodiment of the present invention and the first embodiment may be shortened and reference to FIG. 1 to FIG. 8 may be made. The difference is that in this embodiment, the distance from the edge in the direction toward the second surface (20) of the first part (111) of the body region (110) to the first surface (10) is d1, the distance from the edge in the direction toward the second surface (20) of the second part (112) of the body region (110) to the first surface (10) is d7, the distance from the edge in the direction toward the second surface (20) of the third part (113) of the body region (110) to the first surface (10) is d8, and the distance from the bottom surface (102c) of the trench (102) to the first surface (10) is d4, among which d8 > d7 > d4 > d1.

[0119] In this embodiment, the third part (113) has a charge compensation function, and increasing the depth of the third part (113) (increasing the distance d8) can improve the breakdown voltage of the device.

[0120] Optionally, the semiconductor device of the ninth embodiment of the present invention may be installed such that at least a portion of the bottom surface (102c) of the trench (102) and the third portion (113) are spaced apart along the Z-axis direction by the drift region (101), as in the second, fourth, fifth, and seventh embodiments of the present invention.

[0121] Optionally, the semiconductor device of the ninth embodiment of the present invention may have a channel drain region (120) installed, as in the third, fourth, sixth, and seventh embodiments of the present invention.

[0122] Optionally, the semiconductor device of the ninth embodiment of the present invention may have a trench gate structure (150) installed as in the eighth embodiment of the present invention.

[0123] FIGS. 17 to 19 are schematic diagrams showing cross-sections of a partial step of a method for manufacturing a semiconductor device according to the ninth embodiment of the present invention.

[0124] First, referring to the text description in FIG. 3, a first doping region (110-1) is formed using an injection process, then a mask layer (301) is formed on the first surface (10) of the semiconductor layer (100), and a plurality of trenches (102) are formed using an etching process, as shown in FIG. 17. Next, the mask layer (301) is removed.

[0125] Furthermore, a mask layer (302) is formed on the first surface (10) and trench (102) of the semiconductor layer (100), and then a second doping region (110-2) is formed using an injection process, as shown in FIG. 18. Then, the mask layer (302) is removed.

[0126] Furthermore, a buffer layer (190) is formed on the inner surface of the trench (102) and the first surface (10) of the semiconductor layer (100) using an epitaxial process, as shown in FIG. 19. Among these, the buffer layer (190) is a heterogeneous epitaxial layer of the semiconductor layer (100) and may include one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heterogeneous epitaxial layer may be other semiconductor crystal materials or may be a material with very little in situ impurity doping.

[0127] In this embodiment, the second doping region (110-2) is formed after the trench (102) is formed, so the structure of the trench (102) can relatively easily increase the depth of the third part (113) of the body region (110). Since the body region (110) is formed after the buffer layer (190) is formed, the impurities injected when forming the body region (110) do not remain on the surface of the buffer layer (190), thereby improving the reliability of the device.

[0128] Although embodiments of the present invention have been described above, such embodiments are provided merely for the purpose of explaining the invention and are not intended to limit the claims of the present invention. The claims of the present invention are limited by the appended claims and their equivalents. Those skilled in the art may make various substitutions and modifications without departing from the scope of the present invention, and it is obvious that all such substitutions and modifications are within the scope of the present invention.

Claims

Claim 1 A semiconductor device comprises a semiconductor layer, a trench gate structure, and a buffer layer, wherein the semiconductor layer has a first surface and a second surface facing each other, at least a portion of the trench gate structure is located in a trench of the first surface of the semiconductor layer, and the semiconductor layer has a source region extending from the first surface along the direction of the second surface; and includes a drift region and a body region, wherein at least a portion of the drift region is located between the body region and a second surface of the semiconductor layer, a first portion of the body region is located between the source region and the drift region along the direction of the second surface from the first surface, and both the first portion of the body region and the source region are adjacent to the first sidewall of the trench, the buffer layer is a heterogeneous epitaxial layer of the semiconductor layer, the buffer layer covers the inner surface of the trench and the first surface of the semiconductor layer, and the buffer layer is located between the gate dielectric layer of the trench gate structure and the semiconductor layer, the source region and the drift region are of a first conduction type, and the body region is of a second conduction type, wherein the first conduction type is opposite to the second conduction type, and the body region includes the first portion, the second portion and the third portion arranged sequentially, the first portion and the second portion are located between two adjacent trench gate structures, the first portion is adjacent to the first sidewall of one trench, and the second A semiconductor device characterized in that a portion is adjacent to a second side wall of another trench, and the third portion is located on the bottom surface of the other trench. Claim 2 A semiconductor device according to claim 1, wherein the semiconductor layer comprises a SiC semiconductor layer, and the buffer layer comprises one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. Claim 3 A semiconductor device according to claim 1, characterized in that the thickness of the buffer layer includes the thickness of one or more atomic layers. Claim 4 A semiconductor device according to claim 1, wherein the first part, the second part, and the third part of the body region are sequentially adjacent along the width direction of the trench gate structure, the first part and the second part of the body region are located between two trench gate structures, the first part is adjacent to the first sidewall of the trench, the second part is adjacent to the second sidewall of the trench, and the first sidewall and the second sidewall face each other, the third part and the second part are adjacent to the same trench, the third part is located between the bottom surface of the trench and the second surface, the third part and the first part are separated by the drift region, and the second part is adjacent to the second sidewall; or the second part and the second sidewall are separated by the drift region. Claim 5 A semiconductor device according to claim 4, wherein the third portion of the body region extends along the direction of the second surface from the bottom surface of the trench; or at least a portion of the bottom surface of the trench is spaced apart from the third portion of the body region and along the direction toward the second surface from the first surface by the drift region. Claim 6 A semiconductor device according to claim 5, wherein the second portion of the body region comprises an interconnected first sub-region and a second sub-region, and along the width direction of the trench gate structure, the first sub-region is adjacent to the first portion of the body region and the second sub-region is adjacent to the third portion of the body region, wherein the distance from the edge of the first portion of the body region toward the second surface direction to the first surface is a first distance, the distance from the edge of the first sub-region toward the second surface direction to the first surface is a second distance, the distance from the edge of the second sub-region toward the second surface direction to the first surface is a third distance, and the third distance is greater than the second distance and the second distance is greater than the first distance. Claim 7 A semiconductor device according to claim 6, characterized in that the distance from the bottom surface of the trench to the first surface is the fourth distance, and the second distance is not smaller than the fourth distance. Claim 8 A semiconductor device according to claim 7, wherein the distance between the bottom surface of the trench spaced apart by the drift region along the direction of the first surface from the second surface is a fifth distance, and the sum of the fourth distance and the fifth distance is equal to the second distance. Claim 9 A semiconductor device characterized in that, in any one of claims 4 to 8, the second portion of the body region is interconnected with the edge of the third portion facing the second surface direction; or the edge of the third portion facing the second surface direction is closer to the second surface than the edge of the second portion facing the second surface direction. Claim 10 A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer further comprises a channel drain region located between a first portion of the body region and a drift region, such that the source region, the first portion of the body region, and the channel drain region are sequentially adjacent along the direction of the second surface from the first surface and are all adjacent to the first sidewall of the trench, the channel drain region is adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region, and the channel drain region is of a first conduction type. Claim 11 A semiconductor device according to claim 10, characterized in that the doping concentration of the channel drain region is greater than the doping concentration of the drift region. Claim 12 A semiconductor device according to claim 10, wherein the distance from the edge of the channel drain region facing the second surface direction to the first surface is not greater than the distance from the bottom of the trench to the first surface; or the distance from the edge of the channel drain region facing the second surface direction to the first surface is greater than the distance from the bottom of the trench to the first surface, and the channel drain region is adjacent to a part of the bottom surface of the trench. Claim 13 A semiconductor device according to claim 6, wherein the semiconductor layer further comprises a channel drain region located between a first part of the body region and a drift region, so that the source region, the first part of the body region and the channel drain region are sequentially adjacent along the direction from the first surface toward the second surface and are all adjacent to the first sidewall of the trench, the channel drain region is adjacent to the drift region and the second part of the body region, respectively, and the channel drain region and the third part of the body region are separated by the drift region, the channel drain region is of a first conduction type, and the distance from the edge of the channel drain region toward the second surface to the first surface is a sixth distance, the sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, so that the channel drain region and the second sub-region are separated by the drift region in the width direction of the trench gate structure. Claim 14 A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer further comprises a body contact region, the body contact region extends along a direction from the first surface toward the second surface, the body contact region is adjacent to the body region, the body contact region is adjacent to the source region or spaced apart by the body region, and the body contact region is of a second conduction type. Claim 15 A semiconductor device according to claim 14, wherein, along the extension direction of the trench gate structure, a part of the body contact area is adjacent to the second sidewall and has a gap between another part of the body contact area and the second sidewall, and the part having a gap between the adjacent part of the body contact area and the second sidewall is alternately installed in the extension direction of the trench gate structure, or the body contact area and the second sidewall are both spaced apart by the body area. Claim 16 A semiconductor device according to any one of claims 1 to 8, wherein the trench gate structure comprises the gate dielectric layer and the gate conductor, the gate dielectric layer covers the buffer layer on the inner surface of the trench and also covers a portion of the buffer layer located on the first surface adjacent to the trench, the trench extends from the first surface toward the second surface, a portion of the gate conductor is located in the trench, and another portion extends out of the trench to cover the gate dielectric layer, and the gate dielectric layer is located between the gate conductor and the buffer layer to separate the gate conductor from the buffer layer. Claim 17 A semiconductor device characterized in that, in any one of claims 1 to 8, the semiconductor device is a metal-oxide semiconductor field-effect transistor or an insulated gate bipolar transistor. Claim 18 A semiconductor device according to any one of claims 4 to 8, wherein, between the two trench gate structures, the source region extends in a direction toward the second sidewall of the other trench from the first sidewall of one of the trenches and is adjacent to the second portion of the body region.

Images