Pixel array and method for operating the pixel array

Abstract

A pixel array (10) comprises a photodiode (20), a circuit node (35), a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35), an amplifier (60) coupled to the circuit node (35), a first transistor (90) coupled to the amplifier (60) and the first capacitor (70), a second transistor (100) coupled to the first transistor (90) and the second capacitor (80), a reset transistor (50) coupled to the supply terminal (17), a coupling transistor (105) coupled to the circuit node (35) and the reset transistor (50), and a third capacitor (85) coupled to the node between the reset transistor (50) and the coupling transistor (105). Furthermore, a method for operating the pixel array is described.

Description

Technology Field

[0001] The present application claims the benefit of U.S. provisional application No. 63 / 263,861 filed November 10, 2021, German patent application No. 10 2021 120 779.7 filed August 10, 2021, and German patent application No. 10 2022 107 660.1 filed March 31, 2022, which are thereby incorporated by reference.

[0002] A pixel array, an image sensor having a pixel array, and a method for operating the pixel array are provided. Background Technology

[0003] Image sensors typically comprise an array of pixel arrays. A high dynamic range is advantageous for converting electromagnetic radiation into electrical signals. However, the size of the pixel array must be kept small.

[0004] The objective is to provide a pixel array capable of reducing the gain of signal conversion, an image sensor having the pixel array, and a method for operating the pixel array.

[0005] These objectives are achieved by the subject matter of the independent claims. Additional embodiments and developments are given in the dependent claims.

[0006] In one embodiment, the pixel array comprises a photodiode, a circuit node, a transfer transistor coupled to the photodiode and the circuit node, an amplifier having an input coupled to the circuit node, a first capacitor and a second capacitor, a first transistor coupled to the output of the amplifier and the first capacitor, a second transistor coupled to the first transistor and the second capacitor, a supply terminal, a reset transistor coupled to the supply terminal, a coupling transistor coupled to the circuit node and the reset transistor, and a third capacitor having a first electrode coupled to a node between the reset transistor and the coupling transistor.

[0007] In one embodiment of the pixel array, the transfer transistor and the coupling transistor are set to a conductive state at the start of the first storage step. The first transistor and the second transistor, or the first transistor, are set to a conductive state before the end of the first storage step.

[0008] Advantageously, the circuit node has capacitive characteristics. The circuit node has a capacitance such as, for example, diffusion capacitance or floating diffusion capacitance. Thus, the charge provided by the photodiode can be applied to the capacitance of the circuit node and to the third capacitor through the transfer transistor and coupling transistor in the first storage stage. Therefore, the charge provided by the photodiode is detected with low sensitivity by storing this charge not only by the capacitance of the circuit node but also by the third capacitor. This reduces the capacitance voltage at the capacitance of the circuit node. This voltage is amplified and stored in the first capacitor and the second capacitor. The pixel array can be realized in a small area.

[0009] In one embodiment of the pixel array, the first transistor and the second transistor are set to a non-conducting state at the start of the first storage step. The transfer transistor and the coupling transistor are set to a non-conducting state at the end of the first storage step.

[0010] In one embodiment of the pixel array, the transfer transistor is set to a conductive state at the start of the second storage step. The first transistor is set to a conductive state before the end of the second storage step.

[0011] In one embodiment of the pixel array, the first transistor is set to a non-conducting state at the start of the second storage step. The transfer transistor is set to a non-conducting state at the end of the second storage step. The second transistor and the coupling transistor remain in a non-conducting state throughout the second storage step.

[0012] Advantageously, the charge in the capacitance of the circuit node is not supplied to the third capacitor through the coupling transistor in the second storage stage. Therefore, the charge supplied by the photodiode can be detected with high sensitivity by storing this charge solely in the capacitance of the circuit node, rather than in the third capacitor. This maintains a high voltage swing in the capacitance. This voltage is amplified and stored in the first capacitor.

[0013] In one embodiment, the pixel array further includes a reference voltage terminal coupled to the second electrode of the third capacitor. The reference voltage terminal is connected to or coupled to, for example, a supply terminal, an additional supply terminal, a reference potential terminal, an additional reference potential terminal, a ground terminal, or a voltage source.

[0014] In one embodiment, the pixel array further includes a reference potential terminal and a bias transistor coupled to the output of an amplifier and the reference potential terminal. The bias transistor is configured to discharge a first capacitor, or both the second capacitor and the first capacitor.

[0015] In one embodiment of the pixel array, the first capacitor includes a first electrode coupled to a node between the first transistor and the second transistor, and a second electrode coupled to an additional reference potential terminal. The second capacitor includes a first electrode coupled to the second transistor and a second electrode coupled to an additional reference potential terminal. The first transistor is configured to couple the first capacitor to the output of the amplifier. The second transistor is configured to couple the first capacitor to the second capacitor.

[0016] In one embodiment of the pixel array, the supply voltage is tapped at the supply terminal. The reference potential is tapped at the reference potential terminal. The additional reference potential is tapped at the additional reference potential terminal. The supply voltage is a positive voltage for the reference potential and the additional reference potential terminal.

[0017] In one embodiment, the pixel array further includes an additional photodiode and an additional transfer transistor coupled to the additional photodiode and the circuit node. In one example, different exposure times may be used for the photodiode and the additional photodiode.

[0018] In one embodiment of the pixel array, the amplifier includes an amplifier transistor having a control terminal coupled to the input of the amplifier, a first terminal coupled to an additional supply terminal, and a second terminal coupled to the output of the amplifier.

[0019] In one embodiment, the pixel array further includes an additional amplifier having an input coupled to a second capacitor. The pixel array further includes a column line and a select transistor coupled to the output of the column line and the additional amplifier. Advantageously, the second capacitor is coupled to the column line through the additional amplifier and the select transistor. Advantageously, when the select transistor is set to a conducting state, the output voltage at the second capacitor is amplified, and the amplified voltage is applied to the column line.

[0020] In one embodiment of the pixel array, the additional amplifier includes an additional amplifier transistor having a control terminal coupled to the input of the additional amplifier, a first terminal coupled to an additional supply terminal, and a second terminal coupled to the output of the additional amplifier.

[0021] In one embodiment, the pixel array further includes an additional amplifier having an input coupled to a first capacitor, and an additional select transistor coupled to a column line and the output of the additional amplifier. Advantageously, the first capacitor and the second capacitor may be individually coupled to the column line.

[0022] In one embodiment, the image sensor includes an array of pixel arrays, for example, an array of n × m pixel arrays.

[0023] In one embodiment, the image sensor further includes a row driver configured to provide a transfer signal to the control terminal of a transfer transistor, a coupling signal to the control terminal of a coupling transistor, a reset signal to the control terminal of a reset transistor, a first control signal to the control terminal of a first transistor, and a second control signal to the control terminal of a second transistor.

[0024] In one embodiment of the image sensor, the row driver is configured to perform an exposure step and a storage step for each of the pixel arrays in parallel and simultaneously. Thus, the exposure step is a global exposure step; and the storage step is a global storage step. The row driver is configured to perform a reading step in parallel and simultaneously for each of the pixel arrays of one row. The row driver is configured to perform reading steps for different rows in sequence (which is also referred to as row-by-row); thus, the rows are read sequentially. Alternatively, the row driver is configured to perform reading steps for every n-th row in parallel and simultaneously (in this case, the image sensor includes a plurality (n) of parallel column lines for each column of the image sensor). Thus, at one point in time, one row or more than one row (e.g., every n-th row) may be read. Reading of the pixel arrays (10) of one row or every n-th row of the image sensor is performed at one point in time. Typically, reading of the pixel arrays (10) of other rows of the image sensor is performed at different points in time.

[0025] In one embodiment of the image sensor, the row driver is configured to set the transfer transistor to a conductive state by a transfer signal and the coupling transistor to a conductive state by a coupling signal at the start of the first storage step. The row driver is configured to set the first transistor to a conductive state by a first control signal and the second transistor to a conductive state by a second control signal before the end of the first storage step.

[0026] In one embodiment of the image sensor, the row driver is configured to set the transfer transistor to a conductive state by a transfer signal at the start of the second storage step and to set the first transistor to a conductive state by a first control signal before the end of the second storage step.

[0027] In one example, the second storage step follows the first storage step.

[0028] In one embodiment of the image sensor, the first pulse of the transmission signal in the first storage step has a first voltage value, and the second pulse of the transmission signal in the second storage step has a second voltage value, and the first voltage value is different from the second voltage value.

[0029] In one embodiment, a method for operating a pixel array is:

[0030] - A step of converting electromagnetic radiation into electric charge by a photodiode,

[0031] - A step of providing a first pulse of a transfer signal to a transfer transistor and a pulse of a coupling signal to a coupling transistor to transfer charge from a photodiode to a circuit node capacitance and to a third capacitor at the start of the first storage step of the storage step,

[0032] - A step of providing a pulse of a first control signal to a first transistor and a pulse of a second control signal to a second transistor before the end of a first storage step to charge a first capacitor and a second capacitor as a function of the capacitance voltage at the capacitance of a circuit node — the second capacitor is coupled to the first capacitor through the second transistor, and the first capacitor is coupled to the circuit node through the first transistor — or a step of providing a pulse of a first control signal to a first transistor before the end of a first storage step to charge a first capacitor as a function of the capacitance voltage at the capacitance of a circuit node, wherein the second capacitor is coupled to the circuit node through the second transistor, and the first capacitor is coupled to the circuit node through the first transistor.

[0033] The pixel array and image sensor described above are particularly suitable for methods of operating the pixel array. Therefore, the features described in relation to the pixel array and image sensor can be used for the method, and vice versa.

[0034] In one embodiment, this method

[0035] - A step of providing a second pulse of a transfer signal to a transfer transistor to transfer additional charge from the photodiode to the capacitance of the circuit node at the start of the second storage step, and

[0036] - A step of providing a pulse of a first control signal to a first transistor before the end of a second storage step to charge a first capacitor as a function of the capacitance voltage at the capacitance of a circuit node — the second capacitor is coupled to the first capacitor through the second transistor, and the first capacitor is coupled to the circuit node through the first transistor — or a step of providing a pulse of a second control signal to a second transistor before the end of a second storage step to charge a second capacitor as a function of the capacitance voltage at the capacitance of a circuit node, wherein the second capacitor is coupled to the circuit node through the second transistor, and the first capacitor is coupled to the circuit node through the first transistor.

[0037] In one embodiment of the method, capacitance exists at the circuit node. The capacitance is realized, for example, as a diffusion capacitance or a floating diffusion capacitance. The capacitance is realized, for example, as a pn-junction. The circuit node may be referred to as a diffusion node or a floating diffusion node. In the example, there are no individual capacitors connected to the circuit node. The capacitance is caused, for example, only by at least one parasitic capacitance.

[0038] In one embodiment of the method, a first pulse of the transfer signal in the first storage step has a first voltage value, and a second pulse of the transfer signal in the second storage step has a second voltage value. The first voltage value is different from the second voltage value. The transfer transistor has a controlled path. The controlled path has a lower conductance value at the first voltage value than at the second voltage value. The controlled path is a barrier for the flow of charge between the photodiode and the capacitance of the circuit node. The first pulse causes a higher barrier than the second pulse. The transfer signal realizes barrier modulation of the barrier originating from the transfer transistor.

[0039] In one embodiment of the method, a second storage step follows a first storage step. A first reading step follows the second storage step. There may be a time gap between the end of the second storage step and the start of the first reading step. The start time of the first reading step is variable. A second reading step follows the first reading step. In the first reading step, one of the first capacitor and the second capacitor is read through a column line, and in the second reading step, the other of the first capacitor and the second capacitor is read through a column line. For example, in the first reading step, a low-sensitivity signal is read, and in the second reading step, a high-sensitivity signal is read.

[0040] In one embodiment of the method, in the third reading step, the capacitance of the circuit node is reset, and the reset signal is read through the thermal line.

[0041] In one embodiment of the method, amplitudes are determined based on the differences between high-sensitivity / low-sensitivity signals and their reset levels. Thus, the first amplitude depends on the high-sensitivity signal and the low-sensitivity signal. The first amplitude is determined, for example, by subtracting the low-sensitivity signal from the high-sensitivity signal or by subtracting the high-sensitivity signal from the low-sensitivity signal. The second amplitude depends on the low-sensitivity signal and the reset signal. The second amplitude is determined, for example, by subtracting the reset signal from the low-sensitivity signal or by subtracting the low-sensitivity signal from the reset signal. What is being counted is not the absolute value of the high-sensitivity signal and the low-sensitivity signal, but the signals referenced by these individual reset levels. The output signal depends on the first amplitude and the second amplitude. The output signal represents the illuminance of the photodiode. The reset signal represents the absence of illuminance. The reset signal or reset level is a "dark" level. For example, to determine the reset signal in the third read step of the read step, a supply voltage is applied to the capacitance of the circuit node through the reset transistor and the coupling transistor.

[0042] In one embodiment, the method further comprises, in the reset step, a pulse of a reset signal to a reset transistor and a pulse of a coupling signal to a coupling transistor to provide a supply voltage to the capacitance of the circuit node and to a third capacitor. In one example, the photodiode is not reset row by row but is reset as a global operation. Therefore, no pulse of the transfer signal is performed during the pixel read operation.

[0043] In one embodiment, the pixel array implements a dual conversion gain voltage domain global shutter pixel having a low area.

[0044] The pixel array is configured for imaging as an application.

[0045] In one embodiment, the image sensor is realized as a complementary metal-oxide-semiconductor image sensor, abbreviated as a CMOS integrated sensor or CIS. The image sensor can be used in augmented reality (AR), virtual reality (VR), industrial and other image sensor applications.

[0046] In one embodiment, the transfer transistor, coupling transistor, reset transistor, bias transistor, first transistor, second transistor, and select transistor are realized as metal-oxide-semiconductor field-effect transistors, abbreviated as MOSFETs. For example, each of these is realized as an n-channel MOSFET. Alternatively, each of these is realized as a p-channel MOSFET.

[0047] Advantageously, the pixel array improves low-light performance while maintaining the standard dynamic range (SDR) by utilizing dual conversion gain (DCG). The pixel array reduces the area of ​​the pixel array by using two sample and hold capacitors implemented by a first capacitor, a second capacitor, and furthermore, a third capacitor. The pixel array performs dual conversion. The pixel array achieves better low-light performance while maintaining the dynamic range for the reduced area. Brief explanation of the drawing

[0048] The following description of the drawings of examples or embodiments may further illustrate and describe aspects of a pixel array, an image sensor, and a method for operating the pixel array. Arrays, devices, and circuit blocks having the same structure and the same effect are each indicated by equivalent reference numerals. Where arrays, devices, and circuit blocks in different drawings correspond to one another in terms of their function, their descriptions are not repeated for each of the following drawings.

[0049] FIGS. 1a through 1f illustrate exemplary embodiments of a pixel array.

[0050] FIG. 2 illustrates an exemplary embodiment of an image sensor having a pixel array.

[0051] FIG. 3 illustrates an additional exemplary embodiment of a pixel array. Specific details for implementing the invention

[0052] FIG. 1a illustrates an exemplary embodiment of a pixel array (10). The pixel array (10) includes a photodiode (20), a circuit node (35), and a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35). A controlled path of the transfer transistor (30) connects a first terminal of the photodiode (20) to the circuit node (35). The transfer transistor (30) may also be referred to as a transfer gate. The pixel array (10) includes an amplifier (60) having an input (62) coupled to the circuit node (35). The circuit node has a capacitance (40), for example, a floating diffusion capacitance. The circuit node (35) is connected to a first terminal of the capacitance (40), for example, or is identical to the first terminal of the capacitance (40).

[0053] The pixel array (10) includes a first capacitor (70), a second capacitor (80), a first transistor (90), and a second transistor (100). The first transistor and the second transistor (90, 100) may be referred to as the first switch and the second switch. The first transistor (90) is coupled to the output (64) of the amplifier (60) and the first capacitor (70). The controlled path of the first transistor (90) connects the output (64) of the amplifier (60) to the first electrode of the first capacitor (70). The second transistor (100) is coupled to the first transistor (90) and the second capacitor (80). The controlled path of the second transistor (100) connects the terminal of the first transistor (90) to the first electrode of the second capacitor (80). Accordingly, the controlled path of the second transistor (100) connects the first electrode of the first capacitor (70) to the first electrode of the second capacitor (80).

[0054] Furthermore, the pixel array (10) includes a coupling transistor (105), a reset transistor (50), and a supply terminal (17). The reset transistor (50) is coupled to the coupling transistor (105) and the supply terminal (17). The coupling transistor (105) is coupled to the circuit node (35) and the reset transistor (50). Thus, the first terminal of the coupling transistor (105) is connected to the circuit node (35). The first terminal of the coupling transistor (105) is connected to the input (62) of the amplifier (60). The first terminal of the coupling transistor (105) is connected to the transfer transistor (30). The second terminal of the coupling transistor (105) is connected to the first electrode of the third capacitor (85). The second terminal of the coupling transistor (105) is connected to the first terminal of the reset transistor (50). The first terminal of the reset transistor (50) is connected to the first electrode of the third capacitor (85). The second terminal of the reset transistor (50) is connected to the supply terminal (17). The second electrode of the third capacitor (85) is connected to the reference voltage terminal (16). The reference voltage terminal (16) is connected, for example, to the supply terminal (17), the additional supply terminal (15) of the pixel array (10), the reference potential terminal (18) of the pixel array (10), the additional reference potential terminal (14) of the pixel array (10), the ground potential terminal (19) of the pixel array (10), or the output of a voltage source (not shown).

[0055] The pixel array (10) further includes a column line (130) and an additional amplifier (110). The additional amplifier (110) has an input (112) and an output (114). The input (112) of the additional amplifier (110) is coupled to a second capacitor (80). Thus, the input (112) of the additional amplifier (110) is connected to the first electrode of the second capacitor (80) and the second terminal of the second transistor (100). The output (114) of the additional amplifier (110) is coupled to the column line (130).

[0056] The pixel array (10) includes a select transistor (120) coupled to the column line (130) and the output (114) of the additional amplifier (110). The pixel array (10) further includes a bias transistor (65) coupled to the output (64) of the amplifier (60) and the reference potential terminal (18) of the pixel array (10).

[0057] The first electrode of the first capacitor (70) is connected to a node between the first transistor (90) and the second transistor (100). The second electrode of the first capacitor (70) is connected to an additional reference potential terminal (14). The first electrode of the second capacitor (80) is connected to a node between the second transistor (100) and the input (112) of the additional amplifier (110). The second electrode of the second capacitor (80) is connected to an additional reference potential terminal (14). The second terminal of the capacitance (40) is connected to the ground terminal (19). The reference potential terminal (18) is connected to the ground terminal (19) or is not connected to the ground terminal (19). The additional reference potential terminal (14) is connected to the ground terminal (19) or is not connected to the ground terminal (19). The additional reference potential terminal (14) is connected to the reference potential terminal (18) or is not connected to the reference potential terminal (18).

[0058] The amplifier (60) includes an amplifier transistor (61) having a control terminal coupled to the input (62) of the amplifier (60). The first terminal of the amplifier transistor (61) is coupled to an additional supply terminal (15) of the pixel array (10). The second terminal of the amplifier transistor (61) is coupled to the output (64) of the amplifier (60). The amplifier (60) is implemented as a source follower.

[0059] The capacitance (40) of the circuit node (35) includes, for example, the capacitance of the control terminal of the amplifier transistor (61), the capacitance of the pn junction of the terminal of the transfer transistor (30), and the capacitance of the pn junction of the first terminal of the coupling transistor (105). Thus, the parasitic capacitances of the transistors connected to the circuit node (35) can cause the capacitance (40) of the circuit node (35). The value of the capacitance (40) of the circuit node (35) may be the sum of the values ​​of the parasitic capacitances of the transistors connected to the circuit node (35). Optionally, the pixel array (10) includes, for example, a capacitor connected to the circuit node (35); this capacitor may contribute to the capacitance (40).

[0060] For example, the capacitance of the first capacitor (70) and the capacitance of the second capacitor (80) are the same. The capacitance of the first capacitor (70) is, for example, higher than the value of the capacitance (40) of the circuit node (35). The capacitance of the second capacitor (80) is, for example, higher than the value of the capacitance (40) of the circuit node (35). The capacitance of the third capacitor (85) is, for example, higher than the value of the capacitance (40) of the circuit node (35). The first capacitor (70) and the second capacitor (80) are realized, for example, as metal-insulator-metal capacitors or as metal-insulator-semiconductor capacitors. The third capacitor (85) is realized, for example, as a metal-insulator-metal capacitor or as a metal-insulator-semiconductor capacitor.

[0061] The additional amplifier (110) includes an additional amplifier transistor (111) having a control terminal coupled to the input (112) of the additional amplifier (110). The first terminal of the additional amplifier transistor (111) is coupled to an additional supply terminal (15). The second terminal of the additional amplifier transistor (111) is coupled to the output (114) of the additional amplifier (110). The additional amplifier (110) is implemented as a source follower.

[0062] The supply voltage (VDD) is tapped at the supply terminal (17). The additional supply voltage (VDD1) is tapped at the additional supply terminal (15). The reference potential (VSS_PC) is tapped at the reference potential terminal (18). The additional reference potential (VSS1) is tapped at the additional reference potential terminal (14). The supply voltage (VDD) and the additional supply voltage (VDD1) are positive voltages relative to the reference potential (VSS_PC). The supply voltage (VDD) and the additional supply voltage (VDD1) have different values. The reference potential (VSS_PC) and the additional reference potential (VSS1) have different values. The ground potential (VSS) is tapped at the ground terminal (19). The ground potential (VSS) is the same as or different from the reference potential (VSS_PC). The ground potential (VSS) is the same as or different from the additional reference potential (VSS1). A reference voltage (VREF) is applied to the reference voltage terminal (16) and, accordingly, to the second electrode of the third capacitor (85).

[0063] A row driver (shown in FIG. 2) is coupled to the control terminals of the transfer transistor (30), the coupling transistor (105), the reset transistor (50), the bias transistor (65), the first transistor (90), the second transistor (100), and the selection transistor (120). The row driver provides a transfer signal (TX) to the transfer transistor (30), a coupling signal (DS) to the coupling transistor (105), a reset signal (RST) to the reset transistor (50), a bias transistor signal (PC) to the bias transistor (65), a first control signal (S1) to the first transistor (90), a second control signal (S2) to the second transistor (100), and a selection signal (SEL) to the selection transistor (120). When the reset signal (RST) sets the bias transistor (65) to a conducting state, the bias transistor (65) delivers a bias current to the amplifier (60).

[0064] The operation is explained using FIGS. 1b and FIGS. 1c.

[0065] In an alternative embodiment not illustrated, the supply terminal (17) is connected to an additional supply terminal (15). The supply voltage (VDD) and the additional supply voltage (VDD1) are the same.

[0066] In an alternative embodiment not illustrated, the reference potential terminal (18) is connected to an additional reference potential terminal (14). The reference potential (VSS_PC) and the additional reference potential (VSS1) are the same.

[0067] FIG. 1b illustrates an exemplary operation performed by, for example, the pixel array (10) illustrated in FIG. 1a. In FIG. 1b, the operation is illustrated in blocks. A method for operating the pixel array (10) includes the following blocks, which may be named, for example, procedures or steps:

[0068] Block (151): Start of exposure: Electromagnetic radiation is converted into electric charge (Q) by the photodiode (20).

[0069] Optionally, the transfer barrier is modified based on system input: a transfer signal (TX) provided to the transfer transistor (30) controls the barrier between the photodiode (20) and the circuit node (35). Typically, between two pulses of the transfer signal (TX), the voltage value of the transfer signal (TX) is selected so that the barrier to the flow of charge between the photodiode (20) and the circuit node (35) is high.

[0070] Block (152): Transfer of a portion of the charge (Q) of the photodiode (20) to the capacitance (40) of the circuit node (35) and the third capacitor (85). A first pulse of the transfer signal (TX) is provided to the transfer transistor (30). A pulse of the coupling signal (DS) is applied to the coupling transistor (105). The first pulse of the transfer signal (TX) has a first voltage value (V1). The charge (Q) is transferred from the photodiode (20) to the third capacitor (85) and the capacitance (40) of the circuit node (35) through the transfer transistor (30) and the coupling transistor (105).

[0071] Block (153): In the first storage step (EP1) of the storage step (EP), charge is stored on the first capacitor (70) and the second capacitor (80): The first transistor and the second transistor (90, 100) are set to a conducting state to transfer charge from the capacitance (40) of the circuit node (35) and, for example, also from the photodiode (20) to the second capacitor (80). Charge (Q) from the photodiode (20) can flow from the photodiode (20) as long as the charge (Q) of the photodiode (20) can overcome the barrier provided by the transfer transistor (30). Thus, the charge (Q) generates a capacitance voltage (VC) at the input (62) of the amplifier (60). The amplified capacitance voltage is applied to the first capacitor (90) and the second capacitor (100). The second control signal (S2) may have a short pulse to equalize the voltages in the first capacitor (70) and the second capacitor (80).

[0072] Block (154): Reading of the second capacitor (80):

[0073] The output voltage (VO) tapped from the second capacitor (80) is amplified by an additional amplifier (110). When the select transistor (120) is set to a conducting state in the first reading step (RO1) of the reading step (RO), the amplified output voltage is provided to the column line (130) for digitization. A first digitized value is generated as a function of a first value of the output voltage (VO) by, for example, an evaluation circuit (shown in FIG. 2).

[0074] Block (155): Transfers the remaining charge (Q) to the capacitance (40) of the circuit node (35). A second pulse of the transfer signal (TX) is applied to the transfer transistor (30) to transfer additional charge (Q) from the photodiode (20) to the capacitance (40) of the circuit node (35). The second pulse of the transfer signal (TX) has a second voltage value (V2). The first voltage value (V1) causes a higher barrier than the second voltage value (V2). In one example, V1 < V2. The coupling transistor (105) is maintained in a non-conducting state.

[0075] Block (156): In the second storage step (EP1) of the storage step (EP), charge is stored on the first capacitor (70): the capacitance voltage (VC) tapped at the capacitance (40) of the circuit node (35) is amplified by the amplifier (60). The amplified capacitance voltage is provided to the first capacitor (70) by providing a pulse of the first control signal (S1) to the first transistor (90).

[0076] Block (157): Reading of the first capacitor (70): After the output voltage (VO) at the second capacitor (80) is read in the first reading step (RO1) in block (154), the second transistor (100) is set to a conducting state. Thus, the voltages at the first capacitor (70) and the second capacitor (80) are equal. Since the capacitance voltage (VC) is still amplified by the amplifier (60), the output voltage (VO) at the second capacitor (80) is equal to the amplified capacitance voltage. The output voltage (VO) is amplified by an additional amplifier (110). When the select transistor (120) is set to a conducting state in the second reading step (RO2) of the reading step (RO), the amplified output voltage is provided to the heat line (130) for digitization. A second digitized value is generated by an evaluation circuit as a function of the second value of the output voltage (VO).

[0077] Typically, the steps of blocks (152, 153, 155, 156) are performed in the storage step (EP). The steps of blocks (154, 157) are performed in the read step (RO).

[0078] Block (158): Subtract the voltage of the first capacitor (70) or the digitized value of the voltage of the first capacitor (70) (high conversion gain, abbreviated as HCG) from the voltage of the second capacitor (80) or the digitized value of the voltage of the second capacitor (80): The illuminance (IL) of the photodiode (20) is a function of the first digitized value (originating from block (153)) and the second digitized value (originating from block (157)). In one example, the first digitized value (originating from block (153)) is subtracted from the second digitized value (originating from block (157)) by an evaluation circuit.

[0079] Block (159): Increases low conversion gain (LCG).

[0080] Block (160): Linearization.

[0081] FIG. 1c illustrates an exemplary timing diagram performed by, for example, the pixel array (10) shown in FIG. 1a and FIG. 1b. The following signals: a transmission signal (TX), a coupling signal (DS), a reset signal (RST), a first control signal (S1), and a second control signal (S2) are shown as a function of time (t).

[0082] Examples of general operations are as follows:

[0083] - The combined signal (DS) becomes high, and the transfer signal (TX) is pulsed to transfer a portion of the charge (Q) of the photodiode (20) to the capacitance (40) of the circuit node (35) and the third capacitor (85) (LCG reading).

[0084] - The combined signal (DS) becomes low, and the remaining charge (Q) of the photodiode (20) is transferred to the capacitance (40) of the circuit node (35) (HCG reading).

[0085] Accordingly, a low-sensitivity signal is stored on the second capacitor (80), and a high-sensitivity signal is stored on the first capacitor (70). This achieves good low-light performance in a small-sized pixel array (10) by using dual conversion gain and only three capacitors.

[0086] The operation includes, for example, a reset step (R), an exposure step (E), a storage step (SP), and a read step (RO). The read step (RO) follows the storage step (SP). The storage step (SP) follows the exposure step (E). The exposure step (E) follows the reset step (R).

[0087] The storage step (SP) includes a first storage step (SP1) and a second storage step (SP2). The second storage step (SP2) follows the first storage step (SP1). The reading step (RO) includes a first reading step (RO1) and a second reading step (RO2). The second reading step (RO2) follows the first reading step (RO1).

[0088] The storage step (SP) is a global storage step, and the read step (RO) is performed individually for each row. Therefore, there may be a time gap between the second storage step (EP2) and the first read step (RO1).

[0089] During the exposure phase (E), all charge is stored in the photodiode (20) through a blooming path available via the transfer transistor (30), coupling transistor (105), and reset transistor (50).

[0090] Storage Phase (SP): Pixel behavior after the exposure phase (E) includes the following:

[0091] Reset the capacitance (40) of the third capacitor (85) and the circuit node (35).

[0092] Partial transfer of the charge (Q) of the photodiode (20) to the capacitance (40) of the circuit node (35) and the third capacitor (85) using the first pulse of the transfer signal (TX) and the pulse of the combined signal (DS). The capacitance voltage (VC) depends on the duration between the end of the last reset of the photodiode (20) and the start of the first pulse of the transfer signal (TX).

[0093] After amplification (LCG) by the amplifier (60) on the first capacitor (70) and the second capacitor (80), a signal is stored in the capacitance (40) of the circuit node (35) (capacitance voltage (VC)).

[0094] The second pulse of the transfer signal (TX) is used to transfer the remaining charge (Q) of the photodiode (20) to the capacitance (40) of the circuit node (35). The coupling transistor (105) is maintained in a non-conducting state. The capacitance voltage (VC) depends on the duration between the end of the first pulse and the start of the second pulse.

[0095] After amplification (HCG) by the amplifier (60) on the first capacitor (70), the remaining signal of the capacitance (40) of the circuit node (35) (capacitance voltage (VC)) is stored.

[0096] High transform gain (abbreviated as HCG) is a correlated double sampling read (abbreviated as CDS read), while low transform gain (abbreviated as LCG) is a differential double sampling read (abbreviated as DDS read).

[0097] In one embodiment, the first pulse of the transfer signal (TX) in the first storage step (SP1) has a first voltage value (V1) (named as a partial voltage level), and a portion of the charge (Q) of the photodiode (20) is transferred through the transfer transistor (30) to the capacitance (40) and the third capacitor (85) of the circuit node (35). The capacitance voltage (VC) depends on the duration between the end of the last reset of the photodiode (20) and the start of the first pulse, and also on the first voltage value (V1).

[0098] The second pulse of the transfer signal (TX) in the second storage stage (SP2) has a second voltage value (V2), and the remainder of the charge (Q) of the photodiode (20) is transferred to the capacitance (40) of the circuit node (35) through the transfer transistor (30). The capacitance voltage (VC) depends on the duration between the end of the first pulse and the start of the second pulse, and also on the second voltage value (V2).

[0099] FIG. 1d illustrates exemplary characteristics of a pixel array (10) illustrated, for example, in FIG. 1a through 1c. The response signal (SIG) of the artificial units is illustrated as a function of the illuminance (IL) of the artificial units. Signal (SIG1) (dotted line) is the signal achieved at low conversion gain. Signal (SIG2) (dashed line) is the signal achieved at high conversion gain. Output signal (SIG3) (solid line) is the signal achieved by a combination of signals (SIG1, SIG2). The output signal (SIG3) depends linearly on the illuminance (IL). Typically, the signal (SIG1) achieved at low conversion gain has a less steep slope compared to the signal (SIG2) achieved at high conversion gain. For example, the slope of the signal (SIG1) achieved at low conversion gain is 1 / 2, 1 / 3, or 1 / 4 of the slope of the signal (SIG2) achieved at high conversion gain. The slope depends, for example, on the value of the capacitance (40) of the circuit node (35) and the value of the capacitance of the third capacitor (85). The difference in slope depends on the gain ratio. The signals (SIG1, SIG2) are combined into an output signal (SIG3). The output signal (SIG3) is a function of the signal (SIG1) achieved at low conversion gain, the signal (SIG2) achieved at high conversion gain, and a reset signal (not shown).

[0100] FIG. 1e illustrates an exemplary timing diagram performed by, for example, the pixel array (10) shown in FIG. 1a through 1d. In the reset step (R), a pulse of the reset signal (RST) is applied to the reset transistor (50), a pulse of the coupling signal (DS) is applied to the coupling transistor (105), and a pulse of the transfer signal (TX) is applied to the transfer transistor (30). Thus, the reset transistor (50), the coupling transistor (105), and the transfer transistor (30) are set to a conducting state, and a supply voltage (VDD) is provided to the photodiode (20), the circuit node (35), and the third capacitor (85).

[0101] In the exposure phase (E), the reset signal (RST) sets the reset transistor (50) to a non-conducting state. During the reset phase (R), the pulse of the coupling signal (DS) initiated is continuously applied to the coupling transistor (105). During the reset phase (R), the pulse of the transfer signal (TX) initiated is continuously applied to the transfer transistor (30). Thus, the supply voltage (VDD) is provided to the circuit node (35) and the third capacitor (85).

[0102] At the start of the first storage step (SP1), the first pulse of the transfer signal (TX) sets the transfer transistor (30) to a conducting state. The pulse of the coupling signal (DS), which was continuously applied to the coupling transistor (105) in the exposure step (E), is additionally applied to the coupling transistor (105). Thus, the coupling transistor (105) is in a conducting state. At the start of the first storage step (SP1), the charge of the photodiode (20) flows through the transfer transistor (30) to the capacitance (40) of the circuit node (35) and through the coupling transistor (105) to the third capacitor (85).

[0103] Before the end of the first storage step (SP1), pulses of the first control signal (S1) and the second control signal (S2) set the first transistor (90) and the second transistor (100) to a conducting state. The capacitance voltage (VC) tapped at the capacitance (40) of the circuit node (35) is amplified by the amplifier (60) and provided to the first capacitor and the second capacitor through the first transistor (90) and the second transistor (100). Thus, the method includes the step of providing the pulse of the first control signal (S1) to the first transistor (90) and the pulse of the second control signal (S2) to the second transistor (100) before the end of the first storage step (SP1) for charging the first capacitor (70) and the second capacitor (80) as a function of the capacitance voltage (VC).

[0104] At the start of the second storage stage (SP2), the second pulse of the transfer signal (TX) sets the transfer transistor (30) to a conducting state. The coupling signal (DS) is in a non-conducting state. The charge of the photodiode (20) flows through the transfer transistor (30) to the capacitance (40) of the circuit node (35). In the second storage stage (SP2), there is no flow to the third capacitor (85).

[0105] Before the end of the second storage step (SP2), a pulse of the first control signal (S1) sets the first transistor (90) to a conducting state. The capacitance voltage (VC) tapped at the capacitance (40) of the circuit node (35) is amplified by the amplifier (60) and provided to the first capacitor (70) through the first transistor (90). Thus, the first capacitor (70) stores a voltage achieved with a high conversion gain, and the second capacitor (80) stores an output voltage (VO) achieved with a low conversion gain. Thus, the method includes the step of providing a pulse of the first control signal (S1) to the first transistor (90) before the end of the second storage step (SP2) for charging the first capacitor (70) as a function of the capacitance voltage (VC).

[0106] The read step (RO) follows the store step. The start time of the read step (RO) is variable. The read step (RO) includes a first read step (RO1) and a second read step (RO2). The first read step (RO1) follows the second store step (SP2), for example, with a time gap. In the first read step (RO1), the second capacitor (80) is read through the additional amplifier (110) and the select transistor (110). Thus, the second transistor (100) is in a non-conducting state in the first read step (RO1). The select transistor (129) is in a conducting state for at least part of the first read step (RO1). In the first read step (RO1), the reset transistor (50) and the coupling transistor (105) are set to a conducting state. Thus, the supply voltage (VDD) is applied to the circuit node (35). Thus, the reset of the capacitance (40) of the circuit node (35) is achieved. Capacitance voltage (VC) indicates the absence of illuminance or dark levels.

[0107] In the second reading step (RO2), the first capacitor (70) is read through the second transistor (100), the additional amplifier (110), and the select transistor (110). Thus, the second transistor (100) and the select transistor (129) are in a conducting state for at least part of the second reading step (RO2). In the second reading step (RO2), the reset transistor (50) and the coupling transistor (105) are set to a non-conducting state.

[0108] The read step (RO) includes a third read step (RO3). The third read step (RO3) follows the second read step (RO2). In the third read step (RO3), the first transistor (90) and the second transistor (100) are set to a conducting state. Thus, the capacitance voltage (VC) is amplified by the amplifier (60), and the amplified capacitance voltage is applied to the first capacitor (70) and the second capacitor (80) and to the input (112) of the additional amplifier (110). The select transistor (129) is in a conducting state for at least part of the first read step (RO1) to provide a signal to the column line (130). The capacitance voltage (VC) is read through the amplifier (60), the first transistor (90) and the second transistor (100), the additional amplifier (110), and the select transistor (110).

[0109] In the read step (RO), the transfer signal (TX) is in a non-conduction state; the coupling signal (DS) and the reset signal (RST) may have different pulses as shown in FIG. 1e. FIG. 1e illustrates only examples of possible timings of the pulses; other timings may also be realized.

[0110] The timings of FIGS. 1d and FIGS. 1e illustrating the exposure phase (E) and storage phase (SP) are global timings that simultaneously affect all pixel arrays (10) of the image sensor array. In the global storage phase, the storage phase (GS) of each pixel array (10) of the image sensor is performed in parallel. Subsequently, during the read phase (RO) or read operation, the pixel arrays (10) are accessed sequentially row by row via the selection signal (SEL) of each row. The reading of the reset level or reset value is performed during the read phase (RO), for example, when rows are accessed sequentially in the third read phase (RO3) after the second read phase (RO2).

[0111] The pixel array (10) implements a dual conversion gain mode in which both gains are stored in the pixel array (10) and are available for reconstruction at the column level. Charge skimming is used to transfer high-irradiance charges from the photodiode (20) to the third capacitor (85) before completing the charge transfer. The barrier level selection depends on the maximum allowable floating diffusion swing.

[0112] FIG. 1f illustrates an exemplary drawing of a pixel array (10) as illustrated in FIG. 1a through 1e, for example. The pixel array (10) uses a standard dynamic range (abbreviated as SDR) plus mode with a simplified reconstruction algorithm.

[0113] In block (170), the image sensor (200) checks whether the barrier affects the photodiode (20). If DDS > 0 is true, block (171) is selected (DDS stands for differential dual sampling). If DDS > 0 is false, block (172) is selected. The image sensor (200) determines whether the illumination is low or high. In the case of high illumination, block (171) is used. In the case of low illumination, block (172) is used.

[0114] In block (171), the output signal (V_recon) of the pixel array (10) is reconstructed using the results of CDS and DDS (CDS stands for Correlated Dual Sampling). Block (171) illustrates the medium / high brightness state. The value achieved by DDS is the reset level read during row reading, and the column CG difference with the signal stored on the second capacitor (80): CDS needs to be taken into account (DDS needs to be multiplied by 0.5*HCG / LCG). CDS is the signal stored on the first capacitor (70) minus the signal stored on the second capacitor (80). Block (171) performs CG coefficient adjustment. The output signal (V_recon) is a function of the signal achieved at low conversion gain (SIG1) and the signal achieved at high conversion gain (SIG2).

[0115] In block (172), the output signal (V_recon) of the pixel array (10) is reconstructed using the result of the CDS. Block (172) illustrates a low light state. The output signal (V_recon) is a function of the signal (SIG2) achieved at high conversion gain and the reset signal.

[0116] In an alternative block (173), the CDS is checked and a safety threshold level is set. If the CDS exceeds the threshold (e.g., 2000 e-), block (171) is selected.

[0117] FIG. 2 illustrates an exemplary embodiment of an image sensor (200) having a pixel array (10) which is a further development of the embodiments illustrated in FIGS. 1a through 1f. The image sensor (200) comprises an array of pixel arrays (10). Furthermore, the image sensor (200) further comprises a row driver (204) that provides a transfer signal (TX), a combination signal (DS), a reset signal (RST), a bias transistor signal (PC), a first control signal (S1), a second control signal (S2), and a selection signal (SEL) to the array of pixel arrays (10). The row driver (204) provides these signals for each of the rows. The image sensor (200) comprises an evaluation circuit (205) for digitizing signals in column lines (130).

[0118] FIG. 3 illustrates an exemplary embodiment of a pixel array (10) that is a further development of the embodiments shown in FIG. 1a through 1f and FIG. 2. The pixel array (10) further includes an additional amplifier (110') having an input (112') coupled to a first capacitor (70) and an output (114') coupled to a column line (130). The additional amplifier (110') includes an additional amplifier transistor (111'). The pixel array (10) further includes an additional select transistor (120') coupled to the column line (130) and the output (114') of the additional amplifier (110'). The second transistor (100) couples the output (64) of the amplifier (60) to the second capacitor (80).

[0119] The operation is similar to the operation illustrated in FIG. 1c and FIG. 1e. A pulse of the first control signal (S1) is provided to the first transistor (90) before the end of the first storage step (SP1) to charge the first capacitor (70) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35). When the additional select transistor (120') is set to a conducting state, the voltage stored on the first capacitor (70) is provided to the heat line (130) through the additional amplifier (110') and the additional select transistor (120').

[0120] A pulse of the second control signal (S2) is provided to the second transistor (100) before the end of the second storage step (SP2) to charge the second capacitor (80) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35). Thus, a voltage with low gain is stored on the first capacitor (70), and a voltage with high gain is stored on the second capacitor (80). When the select transistor (120) is set to a conducting state, the voltage stored on the second capacitor (80) is provided to the heat line (130) through the amplifier (110) and the select transistor (120).

[0121] The pixel array (10) is used in a voltage domain global shutter pixel, for example, abbreviated as VGS pixel. The pixel array (10) is implemented, for example, as a rolling shutter pixel. Two capacitors are used as dual conversion gains.

[0122] The present invention is not limited to the description of the embodiments. Rather, the present invention includes each new feature as well as each combination of features, in particular each combination of features of the claims, even if the feature or combination of features itself is not explicitly given in the claims or embodiments.

[0123] Reference numbers 10 pixel array 14 Additional standard potential terminal 15 additional supply terminals 16 reference voltage terminal 17 supply terminals 18 Reference potential terminal 19 Ground terminal 20, 20' photodiode 30, 30' transfer transistor 35 Circuit Nodes 40 capacitance 50 reset transistors 60 amplifiers 61 Amplifier Transistor 62 input 64 output 65 bias transistor 70 First capacitor 80 second capacitor 85 Third capacitor 90 first transistor 100 second transistor 105 coupling transistor 110, 110' additional amplifier 111, 111' additional amplifier transistor 112, 112' input 114, 114' output 120, 120' selection transistor 130 column lines Blocks 151 to 160 Blocks 170 to 173 200 image sensor 204 row driver 205 Evaluation Circuit DS combined signal E Exposure Level IL illuminance PC bias transistor signal Q, Q' charge R reset step RO reading step RO1 1st reading step RO2 2nd reading step RST reset signal SEL, SEL' selection signal SP storage step SP1 1st storage step SP2 2nd storage step S1 first control signal S2 Second control signal TX, TX' transmission signal VC capacitance voltage VDD supply voltage VDD1 additional supply voltage VO output voltage VREF reference voltage VSS ground potential VSS1 additional reference potential VSS_PC reference potential V1 first voltage value V2 second voltage value

Claims

Claim 1 As a pixel array (10), the array comprises: a photodiode (20); a circuit node (35); a transfer transistor (30) coupled to the photodiode (20) and the circuit node (35); an amplifier (60) having an input (62) coupled to the circuit node (35); a first capacitor (70) and a second capacitor (80); an output (64) of the amplifier (60) and a first transistor (90) coupled to the first capacitor (70); a second transistor (100) coupled to the first transistor (90) and the second capacitor (80); a supply terminal (17); a reset transistor (50) coupled to the supply terminal (17); a coupling transistor (105) coupled to the circuit node (35) and the reset transistor (50); and a third capacitor (85) having a first electrode coupled to a node between the reset transistor (50) and the coupling transistor (105), wherein the transfer transistor (30) and the coupling transistor (105) A transistor (105) is set to a conductive state at the start of a first storage step (SP1), and the first transistor (90) and the second transistor (100), or the first transistor (90) is set to a conductive state before the end of the first storage step (SP1), and the transfer transistor (30) is set to a conductive state at the start of a second storage step (SP2), and the first transistor (90) or the second transistor (100) is set to a conductive state before the end of the second storage step (SP2), and the second storage step follows the first storage step among the storage steps, and the storage step follows the exposure step, pixel array (10). Claim 2 A pixel array (10) further comprising a reference voltage terminal (16) coupled to the second electrode of the third capacitor (85) in claim 1. Claim 3 A pixel array (10) further comprising a reference potential terminal (18) and an output (64) of the amplifier (60) and a bias transistor (65) coupled to the reference potential terminal (18). Claim 4 In any one of claims 1 to 3, the first capacitor (70) comprises a first electrode coupled to a node between the first transistor (90) and the second transistor (100), and a second electrode coupled to an additional reference potential terminal (14), and the second capacitor (80) comprises a first electrode coupled to the second transistor (100), and a second electrode coupled to the additional reference potential terminal (14), pixel array (10). Claim 5 A pixel array (10) further comprising, in any one of claims 1 to 3, an additional photodiode (20'), and an additional transfer transistor (30') coupled to the additional photodiode (20') and the circuit node (35). Claim 6 A pixel array (10) further comprising, in any one of claims 1 to 3, an additional amplifier (110) having an input (112) coupled to the second capacitor (80), a column line (130), and a select transistor (120) coupled to the output (114) of the column line (130) and the additional amplifier (110). Claim 7 In claim 6, a pixel array (10) further comprising: an additional amplifier (110') having an input (112') coupled to the first capacitor (70); and an additional select transistor (120') coupled to the column line (130) and the output (114') of the additional amplifier (110'). Claim 8 An image sensor (200) comprising an array of pixel arrays (10) of any one of claims 1 to 3. Claim 9 An image sensor (200) further comprising a row driver (204) configured to provide a transfer signal (TX) to the control terminal of the transfer transistor (30), a coupling signal (DS) to the control terminal of the coupling transistor (105), a reset signal (RST) to the control terminal of the reset transistor (50), a first control signal (S1) to the control terminal of the first transistor (90), and a second control signal (S2) to the control terminal of the second transistor (100). Claim 10 In claim 9, the row driver (204) is configured to set the transfer transistor (30) to the conduction state by the transfer signal (TX) and the coupling transistor (105) to the conduction state by the coupling signal (DS) at the start of the first storage step (SP1), and to set the first transistor (90) to the conduction state by the first control signal (S1) and the second transistor (100) to the conduction state by the second control signal (S2) before the end of the first storage step (SP1), an image sensor (200). Claim 11 In claim 10, the row driver (204) is configured to set the transfer transistor (30) to a conductive state by the transfer signal (TX) at the start of the second storage step (SP2), and to set the first transistor (90) to a conductive state by the first control signal (S1) before the end of the second storage step (SP2), image sensor (200). Claim 12 In claim 9, the first pulse of the transmission signal (TX) in the first storage step (SP1) has a first voltage value (V1), and the second pulse of the transmission signal (TX) in the second storage step (SP2) has a second voltage value (V2), wherein the first voltage value (V1) is different from the second voltage value (V2), image sensor (200). Claim 13 A method for operating a pixel array (10), comprising: a step of converting electromagnetic radiation into a charge (Q) by a photodiode (20); and a step of providing a first pulse of a transfer signal (TX) to a transfer transistor (30) and a pulse of a coupling signal (DS) to a coupling transistor (105) to transfer the charge from the photodiode (20) to the capacitance (40) of a circuit node (35) and to a third capacitor (85) at the start of a first storage step (SP1); wherein the method comprises: a step of providing a pulse of a first control signal (S1) to a first transistor (90) and a pulse of a second control signal (S2) to a second transistor (100) before the end of the first storage step (SP1) to charge the first capacitor (70) and the second capacitor (80) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35); A method for operating a pixel array (10), further comprising: a step of providing a second pulse of the transfer signal (TX) to the transfer transistor (30) to transfer additional charge from the photodiode (20) to the capacitance (40) of the circuit node (35) at the start of the second storage step (SP2); and a step of providing a pulse of the first control signal (S1) to the first transistor (90) before the end of the second storage step (SP2) to charge the first capacitor (70) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35), wherein the second storage step follows the first storage step among the storage steps, and the storage step follows the exposure step. Claim 14 A method for operating a pixel array (10) comprises: - a step of converting electromagnetic radiation into an electric charge (Q) by a photodiode (20); and - a step of providing a first pulse of a transfer signal (TX) to a transfer transistor (30) and a pulse of a coupling signal (DS) to a coupling transistor (105) to transfer the charge from the photodiode (20) to the capacitance (40) of a circuit node (35) and to a third capacitor (85) at the start of a first storage step (SP1); wherein the method comprises: - a step of providing a pulse of a first control signal (S1) to a first transistor (90) before the end of the first storage step (SP1) to charge the first capacitor (70) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35); and - a step of transferring the charge from the photodiode (20) to the circuit at the start of a second storage step (SP2). A method for operating a pixel array (10), comprising the steps of: providing a second pulse of the transfer signal (TX) to the transfer transistor (30) to transfer additional charge to the capacitance (40) of the node (35); and providing a pulse of the second control signal (S2) to the second transistor (100) before the end of the second storage step (SP2) to charge the second capacitor (80) as a function of the capacitance voltage (VC) at the capacitance (40) of the circuit node (35), wherein the second storage step follows the first storage step among the storage steps, and the storage step follows the exposure step. Claim 15 A method for operating a pixel array (10), wherein, in claim 13 or 14, the first pulse of the transmission signal (TX) has a first voltage value (V1) and the second pulse of the transmission signal has a second voltage value (V2), and the first voltage value (V1) is different from the second voltage value (V2). Claim 16 A method for operating a pixel array (10), wherein in a first reading step (RO1), the second capacitor (80) is read through a column line (130), and in a second reading step (RO2), the first capacitor (70) is read through the column line (130). Claim 17 A method for operating a pixel array (10), wherein, in the third reading step, the capacitance (40) of the circuit node (35) is reset and the reset level is read through the column line (130). Claim 18 A method for operating a pixel array (10), further comprising, in the reset step (R), providing a pulse of a reset signal (RST) to a reset transistor (50), a pulse of the coupling signal (DS) to a coupling transistor (105), and a pulse of the transfer signal (TX) to a transfer transistor (30) to provide a supply voltage (VDD) to the photodiode (20), the circuit node (35), and the third capacitor (85) in the reset step (R). Claim 19 delete Claim 20 delete

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