Semiconductor device

Abstract

A microtransistor is provided. The semiconductor device comprises a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, and a third conductor on the third insulator. The third insulator is in contact with the side of the first insulator. The semiconductor comprises a first region in which the semiconductor overlaps with the bottom surface of the first conductor, a second region in which the semiconductor overlaps with the bottom surface of the second conductor, and a third region in which the semiconductor overlaps with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.

Description

Technology Field

[0001] The present invention relates, for example, to transistors and semiconductor devices, and methods for manufacturing the same. The present invention relates, for example, to display devices, light-emitting devices, lighting devices, capacitor devices, memory devices, imaging devices, processors, or electronic devices. The present invention relates to methods for manufacturing display devices, liquid crystal display devices, light-emitting devices, memory devices, imaging devices, or electronic devices. The present invention relates to methods for driving semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, memory devices, or electronic devices.

[0002] Furthermore, one embodiment of the present invention is not limited to the technical field described above. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an article, a method, or a method of production. Additionally, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter.

[0003] In this specification and others, the term "semiconductor device" generally refers to a device capable of functioning by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include semiconductor devices. Background Technology

[0004] In recent years, transistors containing oxide semiconductors have been attracting attention. It is known that transistors containing oxide semiconductors have very low leakage current in the off state. For example, a low-power CPU utilizing the characteristic of low leakage current of a transistor containing an oxide semiconductor has been disclosed (see Patent Document 1). Prior art literature

[0005] Japanese Patent Publication No. JP2012-257187 The problem to be solved

[0006] The task is to provide a fine transistor. Another task is to provide a transistor with low parasitic capacitance. Another task is to provide a transistor with high frequency characteristics. Another task is to provide a transistor with good electrical characteristics. Another task is to provide a transistor with stable electrical characteristics. Another task is to provide a transistor with low off-state current. Another task is to provide a novel transistor. Another task is to provide a semiconductor device including the above transistor. Another task is to provide a semiconductor device capable of operating at high speed. Another task is to provide a novel semiconductor device. Another task is to provide a module including the above semiconductor device. Another task is to provide an electronic device including the above semiconductor device or the above module.

[0007] However, the description of these problems does not prevent the existence of other problems. In one embodiment of the present invention, it is not necessary to achieve all problems. Other problems will become apparent and can be derived from the description in the specification, drawings, and claims, etc. means of solving the problem

[0008] One embodiment of the present invention is a semiconductor device comprising a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, and a third conductor on the third insulator. The third insulator is in contact with the side of the first insulator. The semiconductor comprises a first region in which the semiconductor overlaps with the bottom surface of the first conductor, a second region in which the semiconductor overlaps with the bottom surface of the second conductor, and a third region in which the semiconductor overlaps with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.

[0009] One embodiment of the present invention is a semiconductor device comprising a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a third conductor on the third insulator, and a fourth conductor on the first insulator and the third conductor. The third insulator is in contact with the side of the first insulator. The semiconductor comprises a first region in which the semiconductor overlaps with the bottom surface of the first conductor, a second region in which the semiconductor overlaps with the bottom surface of the second conductor, and a third region in which the semiconductor overlaps with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region. The length between the fourth conductor and the first conductor or the second conductor is longer than the length between the first region and the second region.

[0010] One embodiment of the present invention is a semiconductor device comprising a semiconductor on a substrate, a first conductor and a second conductor on the semiconductor, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, and a third conductor on the fourth insulator. The fourth insulator is in contact with the side of the first insulator. The semiconductor comprises a first region in which the semiconductor overlaps with the bottom surface of the first conductor, a second region in which the semiconductor overlaps with the bottom surface of the second conductor, and a third region in which the semiconductor overlaps with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.

[0011] One embodiment of the present invention is a semiconductor device comprising a semiconductor on a substrate, a first conductor and a second conductor on the substrate, a first insulator on the first conductor and the second conductor, a second insulator on the semiconductor, a third insulator on the second insulator, a fourth insulator on the third insulator, a third conductor on the fourth insulator, and a fourth conductor on the first insulator and the third conductor. The fourth insulator is in contact with the side of the first insulator. The semiconductor comprises a first region in which the semiconductor overlaps with the bottom surface of the first conductor, a second region in which the semiconductor overlaps with the bottom surface of the second conductor, and a third region in which the semiconductor overlaps with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region. The length between the fourth conductor and the first or second conductor is longer than the length between the first region and the second region.

[0012] In one embodiment of the present invention, the length between the fourth conductor and the first conductor or the second conductor is 1.5 times or more and 2 times or less the length between the first region and the second region. Effects of the invention

[0013] A fine transistor can be provided. A transistor with low parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A transistor with good electrical characteristics can be provided. A transistor with stable electrical characteristics can be provided. A transistor with low off-state current can be provided. A novel transistor can be provided. A semiconductor device including the above transistor can be provided. A semiconductor device capable of operating at high speed can be provided. A novel semiconductor device can be provided. A module including the above semiconductor device can be provided. In addition, an electronic device including the above semiconductor device or the above module can be provided.

[0014] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment of the present invention is not necessarily required to achieve all the effects described above. Other effects may become apparent and derivable from the description in the specification, drawings, and claims, etc. Brief explanation of the drawing

[0015] FIG. 1 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIGS. 2 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIGS. 3 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIGS. 4 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIGS. 5 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIGS. 6 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 7 (A) to (H) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 8 (A) to (F) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 9 (A) to (D) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 10 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. Figures 11 (A) and (B) are cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 12 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. Figures 13 (A) and (B) are cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 14 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 15 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 16 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 17 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 18 (A) to (H) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 19 (A) to (F) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 20 (A) to (F) are cross-sectional views each illustrating a portion of a transistor according to one embodiment of the present invention. FIG. 21 is a cross-sectional view showing a part of a sputtering apparatus. FIG. 22 is a cross-sectional view showing a part of a sputtering apparatus. FIG. 23 is a top view illustrating an example of a sedimentation device. Figures 24 (A) to (C) illustrate examples of the structure of a sedimentation device. FIG. 25 is a top view illustrating a manufacturing apparatus according to one embodiment of the present invention. FIG. 26 is a top view illustrating a chamber according to one embodiment of the present invention. FIG. 27 is a top view illustrating a chamber according to one embodiment of the present invention. Figures 28 (A) to (D) are Cs-corrected high-resolution TEM images of the cross-section of CAAC-OS and a schematic cross-sectional view of CAAC-OS. Figures 29 (A) to (D) are Cs-corrected high-resolution TEM images of the CAAC-OS plane. Figures 30 (A) to (C) show the structural analysis by XRD of CAAC-OS and a single-crystal oxide semiconductor. Figures 31 (A) and (B) show the electron diffraction patterns of CAAC-OS. Figure 32 shows the change in the crystal portion of In-Ga-Zn oxide due to electron irradiation. Figures 33 (A) and (B) are circuit diagrams of a semiconductor device according to one embodiment of the present invention. FIG. 34 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 35 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 36 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. Figures 37 (A) and (B) are circuit diagrams illustrating a memory device according to one embodiment of the present invention. FIG. 38 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 39 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 40 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 41 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 42 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 43 (A) to (E) is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 44 (A) and (B) are top views illustrating a semiconductor device according to one embodiment of the present invention, respectively. FIG. 45 (A) and (B) are block diagrams illustrating a semiconductor device according to one embodiment of the present invention. Figures 46 (A) and (B) are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. (A) and (B) of FIG. 47 are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. (A1), (A2), (A3), (B1), (B2), and (B3) of FIG. 48 are a perspective view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 49 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 50 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 51 (A) to (C) are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 52 (A) and (B) are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 53 (A) to (F) are perspective views illustrating electronic devices according to one embodiment of the present invention. Figures 54 (A) and (B) are images of the surface condition of a sample according to one embodiment of Example 1. Figures 55 (A) to (D) are bright-field images of a sample according to one embodiment of Example 2, taken by scanning transmission electron microscopy. FIG. 56 (A) to (C) are top and cross-sectional views illustrating a transistor according to one embodiment of the present invention. Specific details for implementing the invention

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description below, and it is readily understood by those skilled in the art that the embodiments and details disclosed herein can be varied in many ways. Furthermore, the present invention is not to be interpreted as being limited to the description of the embodiments. In describing the structure of the present invention with reference to the drawings, common reference numerals are used for the same parts among different drawings. Additionally, the same hatch pattern is applied to similar parts, and in some cases, such similar parts are not specifically indicated by reference numerals.

[0017] In addition, the size, film (layer) thickness, or area in the drawings may be exaggerated for the sake of simplification.

[0018] In this specification, for example, to describe the shape of an object, the length of one side of the smallest cube into which the object fits, or the diameter of a circle equivalent to one cross-section of the object, may be interpreted as the “diameter,” “diameter,” “size,” “width,” or “width” of the object. The phrase “diameter of a circle equivalent to one cross-section of the object” refers to the diameter of a perfect circle having the same area as said one cross-section of the object.

[0019] Furthermore, voltage often refers to the potential difference between a specific potential and a reference potential (e.g., ground potential (GND) or source potential). Voltage can be referred to as potential, and vice versa.

[0020] In addition, ordinal numbers such as "first" and "second" in this specification are used for convenience and do not indicate a process order or a stacking order. Accordingly, for example, the term "first" can be appropriately replaced with terms such as "second" or "third." Furthermore, ordinal numbers in this specification and the like do not necessarily have to be the same as those specifying an embodiment of the present invention.

[0021] Furthermore, semiconductor impurities refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic% are considered impurities. If impurities are present, for example, density of states (DOS) may be formed in the semiconductor, carrier mobility may decrease, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that alter the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, examples include hydrogen (containing water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, the introduction of impurities such as hydrogen can lead to the formation of oxygen vacancies. Additionally, when the semiconductor is silicon, examples of impurities that alter the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements, excluding oxygen and hydrogen.

[0022] In addition, channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is turned on) and the gate electrode overlap, or in the region where the channel is formed, for example, in a top view of a transistor. In a single transistor, the channel length is not necessarily the same in all regions. In other words, the channel length of a single transistor may not be limited to a single value. Therefore, in this specification, any single value, maximum value, minimum value, or average value in the region where the channel is formed is defined as the channel length.

[0023] Channel width refers to, for example, the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is turned on) and the gate electrode overlap, or the region where the source and drain face each other in the region where the channel is formed. In a single transistor, the channel width is not necessarily the same in all regions. In other words, the channel width of a single transistor may not be fixed to a single value. Therefore, in this specification, any value, maximum value, minimum value, or average value in the region where the channel is formed is defined as the channel width.

[0024] Furthermore, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in transistors with a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view, and its influence cannot be ignored. For example, in miniaturized transistors with a three-dimensional structure, the proportion of the channel region formed on the side of the semiconductor may increase. In this case, the effective channel width obtained when the channel is actually formed is larger than the apparent channel width shown in the top view.

[0025] In transistors with three-dimensional structures, it can be difficult to measure the effective channel width. For example, to estimate the effective channel width from design values, it is necessary to assume, as a condition, that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0026] Accordingly, in this specification, the apparent channel width, which is the length of the portion where the source and drain face each other in the region where the semiconductor and the gate electrode overlap in the top view of the transistor, may be referred to as SCW (surrounded channel width). Furthermore, when the term "channel width" is used simply in this specification, it may refer to SCW and the apparent channel width. Alternatively, when the term "channel width" is used simply in this specification, it may refer to the effective channel width. Additionally, values ​​such as channel length, channel width, effective channel width, apparent channel width, and SCW can be determined by acquiring and analyzing cross-sectional TEM images, etc.

[0027] In addition, when obtaining the field-effect mobility and current per channel width of a transistor through calculation, SCW can be used in the calculation. In this case, values ​​different from those obtained when the effective channel width is used in the calculation may be obtained.

[0028] Additionally, in this specification, the description “A has a shape in which an end extends beyond an end of B” may indicate, for example, a case in which at least one of the ends of A is located outside of at least one of the ends of B in a top view or a cross-sectional view. Accordingly, for example, the description “A has a shape in which an end extends beyond an end of B” can be read as “in a top view, one end of A is located outside of one end of B.”

[0029] In this specification, the term "parallel" indicates that the angle formed between two straight lines is between -10° and 10°, and thus includes cases where the angle is between -5° and 5°. The term "perpendicular" indicates that the angle formed between two straight lines is between 80° and 100°, and thus includes cases where the angle is between 85° and 95°.

[0030] In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

[0031] In this specification, the term "semiconductor" may be referred to as "oxide semiconductor." As a semiconductor, a Group 14 semiconductor such as silicon or germanium; a compound semiconductor such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, or cadmium sulfide; carbon nanotubes; graphene; or an organic semiconductor may be used.

[0032] In addition, in this specification and others, "silicon nitride film" refers to a film containing oxygen in a higher proportion than nitrogen, and "silicon nitride film" refers to a film containing nitrogen in a higher proportion than oxygen.

[0033] Furthermore, when at least one specific example is described in the drawings or text of an embodiment described in the present specification, etc., it is easily understood by a person skilled in the art that a higher-level concept of that specific example can be derived. Therefore, when at least one specific example is described in the drawings or text of an embodiment described in the present specification, a higher-level concept of that specific example is disclosed as a form of the invention and can constitute a form of the invention. The embodiments of the present invention are clear.

[0034] Furthermore, in this specification and the like, at least the contents described in the drawings (or even a part of the drawings) are disclosed as an embodiment of the invention and may constitute an embodiment of the invention. Therefore, if certain contents are described in the drawings, even if such contents are not written in text, they are disclosed as an embodiment of the invention and may constitute an embodiment of the invention. Likewise, a part of the drawings extracted from the drawings is disclosed as an embodiment of the invention and may constitute an embodiment of the invention. The embodiments of the present invention are clear.

[0035] Furthermore, any content not specified in any sentence or drawing in the specification may be excluded from one embodiment of the present invention. Alternatively, if a range of values ​​limited by upper and lower limits is described, one embodiment of the invention may be configured by appropriately narrowing a part of the range or deleting a part of the range to exclude that part. In this way, the technical scope of one embodiment of the present invention may be specified, for example, so as to exclude prior art.

[0036] (Embodiment 1)

[0037] Transistor Structure 1

[0038] The structure of a transistor included in a semiconductor device according to one embodiment of the present invention is described below.

[0039] FIGS. 1 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 1 (A) is a top view. FIGS. 1 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 1 (A), showing the cross-sectional shape in the channel length direction. FIGS. 1 (C) is a cross-sectional view taken along the dotted line A3-A4 of FIGS. 1 (A), showing the cross-sectional shape in the channel width direction. Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 1 (A).

[0040] The transistors illustrated in (A) to (C) of FIG. 1 each include a conductor (413) and an insulator (401) on a substrate (400), an insulator (402) on the conductor (413) and the insulator (401), an insulator (406a) on the insulator (402), a semiconductor (406b) on the insulator (406a), a conductor (416a) and a conductor (416b) each having a region in contact with the upper surface of the semiconductor (406b), an insulator (410) having an opening in contact with the upper surface of the conductor (416a) and the conductor (416b), an insulator (406c) in contact with the side of the conductor (416a) and the upper surface and side of the semiconductor (406b), an insulator (412) in contact with the upper surface of the insulator (406c) and the side of the opening of the insulator (410), and an insulator (412). It includes a conductor (404) comprising a conductor (404a) and a conductor (404b) which are disposed on a semiconductor (406b) with an insulator (406c) interposed therebetween. Additionally, the conductor (404b) faces the side of the opening of the insulator (410) with an insulator (404a) and an insulator (412) interposed therebetween. A conductor (420) on the conductor (404a) and the conductor (404b), and an insulator (408) on the insulator (412) and the conductor (420) are disposed on the transistor. Alternatively, it is not necessary to provide a conductor (413) and an insulator (401), and a structure without a conductor (413) and an insulator (401) may also be used, as shown in FIG. 56 (A) to (C).

[0041] It is preferable that the insulator (406c) includes at least one element other than oxygen, which is included in the semiconductor (406b). By doing so, the formation of defects at the interface between the semiconductor (406b) and the insulator (406c) can be suppressed. Additionally, the crystallinity of the insulator (406c) can be improved.

[0042] It is preferable that the semiconductor (406b) and the insulator (406c) each include a CAAC-OS, which will be described later. Additionally, it is preferable that the insulator (406a) includes a CAAC-OS.

[0043] In this transistor, the conductors (404a and 404b) function as the first gate electrode. It is preferable that at least one of the conductors (404a and 404b) is a conductor that is difficult to permeate oxygen. For example, if a conductor that is difficult to permeate oxygen is formed as the lower conductor (404a), a decrease in conductivity due to oxidation of the conductor (404b) can be prevented. Additionally, the insulator (412) functions as the first gate insulator.

[0044] The conductor (413) functions as a second gate electrode. The conductor (413) may have a stacked structure including a conductor that is difficult to permeate oxygen. A stacked structure including a conductor that is difficult to permeate oxygen can prevent a decrease in conductivity due to oxidation of the conductor (413). The insulator (402) functions as a second gate insulator. The potential applied to the conductor (413) can control the threshold voltage of the transistor. When the first gate electrode is electrically connected to the second gate electrode, the current in the conductive state (on-state current) can be increased. Additionally, the functions of the first gate electrode and the second gate electrode may be interchanged.

[0045] The conductor (416a) and the conductor (416b) function as a source electrode and a drain electrode. Additionally, the conductivity of the conductor can be measured by a two-terminal method, etc.

[0046] Accordingly, the resistance of the semiconductor (406b) can be controlled by the potential applied to the conductor (404). That is, the conduction or non-conduction between the conductor (416a) and the conductor (416b) can be controlled by the potential applied to the conductor (404).

[0047] As illustrated in (B) of FIG. 1, the upper surface of the semiconductor (406b) is in contact with the conductors (416a and 416b). Additionally, the semiconductor (406b) can be electrically surrounded by the electric field of the conductor (404) which functions as a gate electrode. A structure in which the semiconductor is electrically surrounded by the electric field of the gate electrode is called an s-channel (surrounded channel) structure. Thus, a channel may be formed over the entire semiconductor (406b). In an s-channel structure, a large amount of current can be flowed between the source and drain of the transistor, thereby increasing the on-state current. Additionally, because the semiconductor (406b) is surrounded by the electric field of the conductor (404), the off-state current can be reduced.

[0048] The transistor in this embodiment may also be called a TGSA s-channel FET (trench-gate self-aligned s-channel FET) because the region functioning as a gate electrode is formed self-aligned to fill an opening formed in an insulator (410), etc.

[0049] Here, in (B) of FIG. 1, the length between the upper surface of the region of the semiconductor (406b) overlapping with the conductor (404) and the lower surface of the conductor (404) is denoted as t1. In (B) of FIG. 1, the length between the region of the semiconductor (406b) overlapping with the lower surface of the conductor (416a) and the region of the semiconductor (406b) overlapping with the lower surface of the conductor (404) is denoted as L1. Alternatively, the length between the region of the semiconductor (406b) overlapping with the lower surface of the conductor (416b) and the region of the semiconductor (406b) overlapping with the lower surface of the conductor (404) is denoted as L1.

[0050] In a transistor, a region having L1 is formed between a region where a channel is formed in the semiconductor (406b) (a region where the conductor (404) and the semiconductor (406b) overlap each other) and a source region or drain region (a region where the conductor (416a) or the conductor (416b) overlaps with the semiconductor (406b). The region having L1 can reduce the off-state current of the transistor, but if the region having L1 is excessively large, the on-state current of the transistor may be reduced.

[0051] By covering the region where a channel is formed in the semiconductor (406b) with an insulator (406c), the insulator (406c) can prevent elements other than oxygen (such as hydrogen and silicon) contained in the adjacent insulator from entering the region where the channel is formed. Therefore, the insulator (406c) can be formed on at least the semiconductor (406b).

[0052] L1 can be reduced by not providing an insulator (406c) on the side of the conductor (404) with the insulator (412) interposed, or by forming the insulator (406c) thinner in the area covering the side of the conductor (404) with the insulator (412) interposed than in the area overlapping with the bottom surface of the conductor (404) with the insulator (412). Accordingly, t1 is greater than L1, and L1 / t1 is less than 1.

[0053] In (B) of FIG. 1, the length between the conductor (416a) or the conductor (416b) and the conductor (420) is denoted as t2. Also, in (B) of FIG. 1, the length between the conductor (416a) and the conductor (416b) is denoted as L2.

[0054] As transistors become smaller, parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between a conductor (420) and a conductor (416a) or a conductor (416b). If there is a large parasitic capacitance near the region where the channel is formed, for example, the transistor operation requires time to charge the parasitic capacitance, which degrades not only the responsiveness of the transistor but also the responsiveness of the semiconductor device. In addition, the power consumption of a circuit containing multiple transistors increases due to the extra power consumption required to charge the parasitic capacitance. Therefore, it is desirable that t2 be a length sufficient to allow the parasitic capacitance to be ignored compared to the gate capacitance.

[0055] As the transistor becomes smaller, L2 is reduced, making it difficult to apply a sufficiently large voltage to the conductor (404a) and the conductor (404b). However, if t2 has a sufficient length, the resistance of the conductor (404a) and the resistance of the conductor (404b) can be reduced. Therefore, it is preferable that t2 is at least greater than L2, and that t2 / L2 is between 1.5 and 2.

[0056] As a substrate (400), for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As an insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, a yttria-stabilized zirconia substrate), or a resin substrate may be used. As a semiconductor substrate, for example, a semiconductor substrate made of a single material such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A semiconductor substrate provided with an insulating region on the above-described semiconductor substrate, for example, a silicon-on-insulator (SOI) substrate, etc. may be used. As a conductive substrate, a graphite substrate, a metal substrate, an alloy substrate, or a conductive resin substrate, etc. may be used. A substrate containing a metal nitride or a substrate containing a metal oxide, etc. may be used. An insulating substrate provided with a conductor or semiconductor, a semiconductor substrate provided with a conductor or insulator, or a conductive substrate provided with a semiconductor or insulator, etc. may be used. Alternatively, a device provided on any of these substrates may be used. As the device provided on the substrate, a capacitive element, a resistor, a switching element, a light-emitting element, or a memory element may be used.

[0057] Alternatively, a flexible substrate may be used as the substrate (400). As a method of providing a transistor on a flexible substrate, there is a method of forming a transistor on a non-flexible substrate, then separating the transistor and transferring it to the flexible substrate (400). In this case, it is preferable to provide a separation layer between the non-flexible substrate and the transistor. As the substrate (400), a sheet, film, or foil containing fibers may be used. The substrate (400) may have elasticity. The substrate (400) may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate (400) may have the property of not returning to its original shape. For example, the substrate (400) has a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. If the thickness of the substrate (400) is thin, the weight of the semiconductor device including the transistor can be reduced. If the thickness of the substrate (400) is thin, the substrate (400) may have elasticity, or the property of returning to its original shape when bending or pulling is stopped. Therefore, the impact applied to the semiconductor device on the substrate (400) due to dropping, etc., can be reduced. That is, a durable semiconductor device can be provided.

[0058] For the flexible substrate (400), for example, metal, alloy, resin, glass, or its fibers may be used. It is desirable for the flexible substrate (400) to have a low linear expansion coefficient so that deformation caused by the environment is suppressed. For example, the flexible substrate (400) has a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5It is formed using a material with a coefficient of K or less. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate (400) because it has a low coefficient of linear expansion.

[0059] Additionally, the electrical characteristics of the transistor can be stabilized when the transistor is surrounded by an insulator that has the function of blocking impurities such as oxygen and hydrogen. For example, an insulator that has the function of blocking impurities such as oxygen and hydrogen can be used as the insulator (408).

[0060] An insulator having the function of blocking impurities such as oxygen and hydrogen may have a single-layer structure or a multilayer structure including, for example, an insulator including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

[0061] For example, the insulator (408) may be formed from aluminum oxide, magnesium oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Additionally, it is preferable that the insulator (408) contains aluminum oxide. For example, if the insulator (408) is formed using a plasma containing oxygen, oxygen may be added to the side of the insulator (410) or insulator (412) which forms the lower layer of the insulator (408). The added oxygen becomes excess oxygen within the insulator (410) or insulator (412). If the insulator (408) contains aluminum oxide, it can suppress the entry of impurities such as hydrogen into the semiconductor (406b). Additionally, for example, if the insulator (408) contains aluminum oxide, it can reduce the outward diffusion of excess oxygen added to the insulator (410) and the insulator (412).

[0062] The insulator (402) may be formed to have a single-layer or multilayer structure comprising, for example, an insulator comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator (402) preferably comprises silicon oxide or silicon nitride oxide.

[0063] Additionally, it is preferable that the insulator (410) comprises an insulator with a low dielectric constant. For example, the insulator (410) preferably comprises silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with holes, or a resin. Alternatively, the insulator (410) preferably has a laminated structure of a resin and one of silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with holes. When a thermally stable silicon oxide or silicon nitride oxide is combined with a resin, this laminated structure may have thermal stability and a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

[0064] The insulator (412) may be formed to have a single-layer or multilayer structure including, for example, an insulator comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, it is preferable to use a material comprising silicon oxide or silicon nitride oxide for the insulator (412).

[0065] Additionally, it is preferable that the insulator (412) includes an insulator with a high dielectric constant. For example, it is preferable that the insulator (412) include gallium oxide, hafnium oxide, an oxide containing aluminum and hafnium, an oxide containing aluminum and hafnium, an oxide containing silicon and hafnium, or an oxide containing silicon and hafnium. It is preferable that the insulator (412) have a stacked structure including silicon oxide or silicon nitride and an insulator with a high dielectric constant. Since silicon oxide and silicon nitride are thermally stable, by combining silicon oxide or silicon nitride with an insulator with a high dielectric constant, the stacked structure can be thermally stable and have a high dielectric constant. For example, if the aluminum oxide, gallium oxide, or hafnium oxide of the insulator (412) is on the side of the insulator (406c), the silicon contained in the silicon oxide or silicon nitride can be prevented from entering the semiconductor (406b). For example, if silicon oxide or silicon nitride oxide is on the insulator (406c) side, a capture center may be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon nitride oxide. This capture center may be able to change the threshold voltage of the transistor in a positive direction by capturing electrons.

[0066] The conductors (416a and 416b) may each be formed to have a single-layer or multilayer structure including one or more types of conductors, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used, and a conductor including aluminum, a conductor including copper and titanium, a conductor including copper and manganese, a conductor including indium, tin, and oxygen, or a conductor including titanium and nitrogen, etc. may be used.

[0067] The conductors (404, 413, and 420) may each be formed to have a single-layer or multilayer structure including one or more types of conductors, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used, and a conductor including aluminum, a conductor including copper and titanium, a conductor including copper and manganese, a conductor including indium, tin, and oxygen, or a conductor including titanium and nitrogen, etc. may be used.

[0068] It is preferable to use an oxide semiconductor as the semiconductor (406b). However, silicon (including modified silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or organic semiconductors may be used.

[0069] As for the insulator (406a) and the insulator (406c), it is preferable to use an oxide containing one or more elements other than oxygen included in the semiconductor (406b). However, silicon (including modified silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or organic semiconductors may be used.

[0070] The semiconductor (406b) is, for example, an oxide semiconductor. The semiconductor (406b) can have high carrier mobility (electron mobility) by, for example, including indium. The semiconductor (406b) is an element M It is desirable to include the element M It is preferable that it be aluminum, gallium, yttrium, or tin, etc. Element M Other elements that can be used as such include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc. In addition, the element M As such, two or more of the aforementioned elements may be used in combination. Element M For example, it is an element with a high binding energy with oxygen. Element M Silver is an element with a higher binding energy with oxygen than indium. Element M Zinc is, for example, an element that can increase the energy gap of an oxide semiconductor. Additionally, it is desirable for the semiconductor (406b) to contain zinc. For example, if the oxide semiconductor contains zinc, the oxide semiconductor crystallizes easily.

[0071] Additionally, the semiconductor (406b) is not limited to oxide semiconductors. The semiconductor (406b) may be, for example, an oxide semiconductor containing zinc without indium, an oxide semiconductor containing gallium without indium, or an oxide semiconductor containing tin without indium (e.g., zinc tin oxide or gallium tin oxide).

[0072] For the semiconductor (406b), an oxide with a wide energy gap may be used. The energy gap of the semiconductor (406b) is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0073] Insulators (406a) and (406c) are oxides containing one or more or two or more elements other than oxygen included in the semiconductor (406b). Since insulators (406a) and (406c) each contain one or more or two or more elements other than oxygen included in the semiconductor (406b), it is difficult for defect levels to form at the interface between insulator (406a) and the semiconductor (406b) and at the interface between the semiconductor (406b) and the insulator (406c).

[0074] As the semiconductor (406b), an oxide with a higher electron affinity than the insulators (406a and 406c) is used. For example, as the semiconductor (406b), an oxide with an electron affinity higher than that of the insulators (406a and 406c) is used, which is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. Also, electron affinity refers to the energy gap between the vacuum level and the bottom of the conduction band.

[0075] When a gate voltage is applied to a transistor in which an insulator (406a) is placed below a semiconductor (406b) and an insulator (406c) is placed above a semiconductor (406b), a channel is formed in the semiconductor (406b) which has the highest electron affinity among the insulator (406a), the semiconductor (406b), and the insulator (406c). In this way, a buried channel structure is formed.

[0076] Here, there may be a mixed region of the insulator (406a) and the semiconductor (406b) between the insulator (406a) and the semiconductor (406b). Additionally, there may be a mixed region of the semiconductor (406b) and the insulator (406c) between the semiconductor (406b) and the insulator (406c). The mixed region has a low defect level density. For this reason, in a laminate comprising the insulator (406a), the semiconductor (406b), and the insulator (406c), the energy changes continuously at their interfaces and near these interfaces (continuous junction). Furthermore, the boundaries between the insulator (406a), the semiconductor (406b), and the insulator (406c) may not be clear.

[0077] At this time, the electrons move mainly in the semiconductor (406b), rather than in the insulator (406a) and insulator (406c).

[0078] The more the factors inhibiting electron movement are reduced, the higher the on-state current of the transistor can be increased. Electron movement is inhibited, for example, when the physical irregularities in the channel-forming region are large.

[0079] To increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of a measurement area of ​​1 μm × 1 μm on the upper or lower surface (forming surface; here, the upper surface of the insulator (406a)) of the semiconductor (406b) is set to less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The average surface roughness (also called Ra) of the measurement area of ​​1 μm × 1 μm is set to less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The maximum difference (PV) of the measurement area of ​​1 μm × 1 μm is set to less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope SPA-500 (manufactured by SII Nano Technology Inc.).

[0080] The above-described three-layer structure is an example. For example, any of the insulators described as examples, such as insulator (406a) and insulator (406c), may adopt a laminated structure provided below or above insulator (406a) or below or above insulator (406c).

[0081] In addition, oxide semiconductors that can be used in semiconductors will be described in detail in another embodiment.

[0082] Transistor Fabrication Method 1

[0083] A method for fabricating transistors according to the present invention in FIGS. 1 (A) to (C) is described below with reference to FIGS. 7 (A) to (H), FIGS. 8 (A) to (F), and FIGS. 9 (A) to (D).

[0084] First, prepare a substrate (400).

[0085] Next, as illustrated in (A) and (B) of FIG. 7, an insulator (401) is formed on a substrate (400). An opening is formed in the insulator (401), and a conductor (413) is formed on the insulator (401). The conductor (413) can be formed by sputtering, CVD, MBE, PLD, or ALD. The conductor (413) may have a multilayer structure including a conductor that is difficult to permeate oxygen (also called a conductor with high stability against oxidation). The conductor (413) may be embedded in the opening of the insulator (401) by chemical mechanical polishing (CMP), etc. Alternatively, the conductor (413) may be formed by forming a conductor and processing it by photolithography, etc.

[0086] In the photolithography method, a resist is first exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, etching is performed through the resist mask. As a result, conductors, semiconductors, or insulators can be processed into a desired shape. For example, the resist mask is formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (extreme ultraviolet) light, etc. Alternatively, an immersion technique may be employed in which the area between the substrate and the projection lens is filled with a liquid (e.g., water) to perform the exposure. An electron beam or an ion beam may be used instead of the light described above. Furthermore, dry etching treatments such as ashing or wet etching treatments may be used to remove the resist mask. Alternatively, a wet etching treatment may be performed after a dry etching treatment. Alternatively, a dry etching treatment may be performed after a wet etching treatment.

[0087] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes may be used. The CCP etching apparatus including parallel planar electrodes may have a structure that applies high-frequency power to one of the parallel planar electrodes. Alternatively, the CCP etching apparatus may have a structure that applies a different high-frequency power to one of the parallel planar electrodes. Alternatively, the CCP etching apparatus may have a structure that applies high-frequency power of the same frequency to the parallel planar electrodes. Alternatively, the CCP etching apparatus may have a structure that applies high-frequency power of a different frequency to the parallel planar electrodes. Alternatively, a dry etching apparatus including a high-density plasma source may be used. As a dry etching apparatus including a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus may be used.

[0088] Next, high-density plasma treatment may be performed as indicated by the arrows (A) and (B) of FIG. 7. It is preferable to perform high-density plasma treatment in an oxygen atmosphere or a nitrogen atmosphere. An oxygen atmosphere is a gas atmosphere containing oxygen atoms and includes an atmosphere of oxygen, ozone, and nitrogen oxides (e.g., nitric oxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, or dinitrogen pentoxide). In an oxygen atmosphere, an inert gas such as nitrogen or a noble gas (e.g., helium or argon) may be included. By performing high-density plasma treatment in an oxygen atmosphere in this way, carbon or hydrogen, etc., can be released. In addition, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be easily released from the object.

[0089] High-density plasma treatment in a nitrogen atmosphere may be, for example, in an atmosphere containing nitrogen and noble gases, an atmosphere containing nitrogen, hydrogen, and noble gases, or an atmosphere containing ammonia and noble gases. Through this high-density plasma treatment in a nitrogen atmosphere, the surface of the object to be treated and its vicinity can be nitrided. The nitrided area can be formed very thinly on the surface side of the object to be treated. The diffusion of impurities can be prevented by this nitrided area.

[0090] High-density plasma treatment may be performed in a nitrogen atmosphere after performing high-density plasma treatment in an oxygen atmosphere. Alternatively, high-density plasma treatment may be performed in an oxygen atmosphere after performing high-density plasma treatment in a nitrogen atmosphere. Annealing treatment may be performed before or after each high-density plasma treatment. In addition, to increase plasma density, it may be desirable to flow a sufficient amount of gas. If the amount of gas is insufficient, the rate of radical inactivation may become higher than the rate of radical generation. For example, it may be desirable to flow gas at a rate of 100 sccm or more, 300 sccm or more, or 800 sccm or more.

[0091] High-density plasma treatment is performed using microwaves generated by a high-frequency generator that generates waves with a frequency of, for example, 0.3 GHz or more and 3.0 GHz or less, 0.7 GHz or more and 1.1 GHz or less, or 2.2 GHz or more and 2.8 GHz or less (typically, 2.45 GHz). The treatment pressure can be 10 Pa or more and 5000 Pa or less, preferably 200 Pa or more and 1500 Pa or less, more preferably 300 Pa or more and 1000 Pa or less. The substrate temperature can be 100°C or more and 600°C or less (typically, 400°C). In addition, a mixed gas of oxygen and argon can be used.

[0092] For example, high-density plasma is generated using 2.45 GHz microwaves, and has an electron density of 1 × 10⁻⁶ 11 / cm 3 1×10 13 / cm 3 Furthermore, it is preferable that the electron temperature be 2 eV or less, or the ion energy be 5 eV or less. This high-density plasma treatment produces radicals with low kinetic energy, and compared to conventional plasma treatment, plasma damage is reduced. Therefore, it is possible to form a film with fewer defects. The distance between the antenna generating microwaves and the object being treated is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0093] Alternatively, a plasma power supply that applies an RF (radio frequency) bias to the substrate may be provided. The frequency of the RF bias may be, for example, 13.56 MHz or 27.12 MHz. High-density oxygen ions can be produced by using high-density plasma, and oxygen ions generated by the high-density plasma can be efficiently introduced into the object being processed by applying an RF bias to the substrate. Therefore, it is desirable to perform high-density plasma processing while applying a bias to the substrate.

[0094] After high-density plasma treatment, continuous annealing treatment may be performed without exposure to the atmosphere. By performing high-density plasma treatment and annealing treatment consecutively, the ingress of impurities during treatment can be suppressed. Furthermore, by performing annealing treatment after high-density plasma treatment in an oxygen atmosphere, unnecessary oxygen added to the object being treated that was not used to fill oxygen vacancies can be removed. This annealing treatment can be performed, for example, by lamp annealing.

[0095] It is preferable that the treatment time for high-density plasma treatment be 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0096] It is preferable that the treatment time for annealing at a temperature of 250°C or higher and 800°C or lower, 300°C or higher and 700°C or lower, or 400°C or higher and 600°C or lower be 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0097] Next, an insulator (402) is formed. The insulator (402) can be formed by sputtering, CVD (chemical vapor deposition), MBE (molecular beam epitaxy), PLD (pulsed laser deposition), or ALD (atomic layer deposition).

[0098] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma; thermal CVD (TCVD), which uses heat; and photo CVD, which uses light. Additionally, CVD methods may include metal CVD (MCVD) and metal-organic CVD (MOCVD) methods depending on the source gas.

[0099] By using the PECVD method, high-quality films can be formed at relatively low temperatures. In addition, since the thermal CVD method does not use plasma, plasma damage to the object is minimal. For example, wiring, electrodes, or components (e.g., transistors or capacitive elements) included in a semiconductor device may become charged by receiving charges from the plasma. In this case, the wiring, electrodes, or components included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, if the thermal CVD method, which does not use plasma, is adopted, the aforementioned damage caused by exposure to plasma does not occur, thereby increasing the yield of the semiconductor device. In the thermal CVD method, since the object is not exposed to plasma during deposition, a film with fewer defects can be obtained.

[0100] The ALD method also causes minimal plasma damage to the object. Since the ALD method does not generate plasma damage during deposition, it is possible to obtain films with few defects.

[0101] Unlike deposition methods in which particles emitted from a target are deposited, in CVD and ALD methods, a film is formed by a reaction on the surface of an object. Therefore, CVD and ALD methods can achieve good step coverage regardless of the shape of the object. In particular, for example, ALD can achieve good step coverage and uniformity of thickness, and can be advantageously used to cover the surface of an opening with a high aspect ratio. On the other hand, since ALD has a low deposition rate, it is sometimes desirable to combine ALD with other deposition methods that have a high deposition rate, such as CVD.

[0102] When using the CVD or ALD method, the composition of the formed film can be controlled by the flow rate ratio of the source gas. For example, a film having a specific composition can be formed by the CVD or ALD method depending on the flow rate ratio of the source gas. Furthermore, by changing the flow rate ratio of the source gas during film formation using the CVD or ALD method, a film with a continuously changing composition can be formed. Compared to forming a film using multiple deposition chambers, forming a film while changing the flow rate ratio of the source gas eliminates the time required for transport and pressure adjustment, thereby reducing the time required for film formation. Consequently, semiconductor devices can be fabricated with improved productivity.

[0103] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0104] Additionally, a treatment to add oxygen to the insulator (402) may be performed. For the oxygen addition treatment, an ion implantation method or a plasma treatment method may be used. Additionally, the oxygen added to the insulator (402) is excess oxygen.

[0105] Next, as shown in (C) and (D) of FIG. 7, an insulator (406a), a semiconductor (406b), and a resist mask (430) are formed.

[0106] First, an insulator (406a) is formed on the insulator (402). The insulator (406a) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. It is particularly preferable to use a counter-target sputtering device. Additionally, in this specification and other contexts, deposition using a counter-target sputtering device may also be referred to as VDSP (vapor deposition sputtering).

[0107] Using a counter-target sputtering device can reduce plasma damage induced during the deposition of the insulator. Consequently, oxygen vacancies within the insulator can be reduced. Furthermore, using a counter-target sputtering device allows for deposition in a high vacuum. In such cases, the concentration of impurities (e.g., hydrogen, noble gases (such as argon), or water) within the deposited insulator can be reduced.

[0108] Alternatively, a sputtering device including an inductively coupled antenna conductor plate may be used. Thus, a large film with high uniformity can be formed at a high deposition rate.

[0109] It is preferable that deposition be carried out using a gas containing oxygen, a noble gas, or a gas containing nitrogen. As a gas containing nitrogen, for example, nitrogen (N2), dinitrogen monoxide (N2O), or ammonia (NH3) may be used.

[0110] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0111] Additionally, a treatment to add oxygen to the insulator that becomes the insulator (406a) may be performed. For the treatment to add oxygen, an ion implantation method or a plasma treatment method may be used. Also, the oxygen added to the insulator that becomes the insulator (406a) is excess oxygen.

[0112] Next, a semiconductor (406b) is formed on an insulator (406a). The semiconductor can be formed by sputtering, CVD, MBE, PLD, or ALD. It is particularly preferable to use a counter-target type sputtering apparatus.

[0113] Using a counter-target sputtering device can reduce plasma damage induced during semiconductor deposition. Consequently, oxygen vacancies within the semiconductor can be reduced. Furthermore, using a counter-target sputtering device allows for deposition in a high vacuum. In such cases, the concentration of impurities (e.g., hydrogen, noble gases (such as argon), or water) within the deposited semiconductor can be reduced.

[0114] Alternatively, a sputtering device including an inductively coupled antenna conductor plate may be used. Thus, a large film with high uniformity can be formed at a high deposition rate.

[0115] It is preferable that deposition be carried out using a gas containing oxygen, a noble gas, or a gas containing nitrogen. As a gas containing nitrogen, for example, nitrogen (N2), dinitrogen monoxide (N2O), or ammonia (NH3) may be used.

[0116] Next, it is preferable to perform a first heat treatment. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or higher and 600°C or lower. The first heat treatment is performed in an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed by first performing a heat treatment in an inert gas atmosphere, and then performing another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to preserve the released oxygen. Through the first heat treatment, for example, the crystallinity of the semiconductor can be increased and impurities such as hydrogen and moisture can be removed. Alternatively, in the first heat treatment, a plasma treatment using oxygen may be performed under reduced pressure. It is preferable that the plasma treatment containing oxygen be performed using a device including a power source that generates high-density plasma using microwaves, for example. Alternatively, a plasma power source that applies an RF (radio frequency) voltage to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be produced, and by applying an RF voltage to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor (406b). Alternatively, after performing plasma treatment using an inert gas with the above device, plasma treatment using oxygen may be performed to preserve the released oxygen.

[0117] Next, as illustrated in (E) and (F) of FIG. 7, an insulator (406a) and a semiconductor (406b) are processed using a photolithography method using a resist mask (430) or the like to form a multilayer film including the insulator (406a) and the semiconductor (406b). Additionally, when forming the multilayer film, the insulator (402) may also be etched to have a thin region. That is, the insulator (402) may have a convex portion in the region in contact with the multilayer film.

[0118] Next, carbon and hydrogen, etc. may be released by performing high-density plasma treatment. Additionally, when high-density plasma treatment is performed in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0119] Next, as shown in (G) and (H) of FIG. 7, an insulator is formed that becomes a conductor (416) and an insulator (410).

[0120] First, a conductor (416) is formed. The conductor (416) can be formed by sputtering, CVD, MBE, PLD, or ALD.

[0121] Additionally, the conductor (416) covers the multilayer film. The side of the insulator (406a) and the top and side of the semiconductor (406b) are partially damaged in forming the conductor on the multilayer film, and a region with reduced resistance can then be formed. Since the insulator (406a) and the semiconductor (406b) each include a region with reduced resistance, the contact resistance between the conductor (416) and the semiconductor (406b) can be lowered.

[0122] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0123] Next, the conductor (416) is processed by photolithography or the like to form conductors (416a and 416b).

[0124] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0125] Next, an insulator (410) is formed. The insulator (410) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. Alternatively, the insulator (410) can be formed by a spin coating method, immersion method, droplet discharge method (inkjet method, etc.), printing method (screen printing or offset printing, etc.), doctor knife method, roll coater method, or curtain coater method.

[0126] The insulator (410) may be formed to have a flat upper surface. For example, the upper surface of the insulator (410) may have flatness immediately after film formation. Alternatively, after film formation, the upper surface of the insulator (410) may be removed so that it becomes parallel to a reference surface, such as the back surface of the substrate. This process is called a flattening process. As a flattening process, for example, CMP processing or dry etching processing may be performed. However, the upper surface of the insulator (410) does not necessarily have to be flat.

[0127] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0128] Next, a resist mask (431) is formed on an insulator (410) using a photolithography method or the like. Here, in order to improve the adhesion between the upper surface of the insulator (410) and the resist mask (431), an organic coating film may be formed between the upper surface of the insulator (410) and the resist mask (431).

[0129] Next, as illustrated in (A) and (B) of FIG. 8, an opening is formed in the insulator (410) and the conductor (416). First, after forming a resist mask (431), a first processing step is performed on the insulator (410) using a dry etching method or the like to expose the upper surface of the conductor (416). In the dry etching method, any of the dry etching devices described above may be used, but it is preferable to use a dry etching device in which a high-frequency power source with a different frequency is connected to parallel plate-shaped electrodes.

[0130] Next, a second processing step is performed on the conductor (416) using a dry etching method or the like to separate it into a conductor (416a) and a conductor (416b). Additionally, the insulator (410) and the conductor (416) may be processed in the same photolithography process. By processing them in the same photolithography process, the number of manufacturing steps can be reduced. Therefore, a semiconductor device including a transistor can be manufactured with high productivity.

[0131] At this time, the semiconductor (406b) has an exposed region. The exposed region of the semiconductor (406b) may be partially removed by a second processing step. Additionally, impurity elements, such as residual components of the etching gas, may adhere to the exposed surface of the semiconductor (406b). For example, if a chlorine-based gas is used as the etching gas, chlorine and the like may adhere. If a hydrocarbon-based gas is used as the etching gas, carbon and hydrogen and the like may adhere. It is desirable to reduce the impurity elements attached to the exposed surface of the semiconductor (406b). The impurity elements may be reduced by a cleaning treatment using diluted hydrofluoric acid, a cleaning treatment using ozone, or a cleaning treatment using ultraviolet rays. Additionally, a combination of several types of cleaning treatments may be used. As a result, the exposed surface of the semiconductor (406b), that is, the region where the channel is formed, has high resistance.

[0132] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0133] Next, as shown in (C) and (D) of FIG. 8, an insulator (406c) is formed on the upper and side surfaces of the semiconductor (406b), the side surface of the insulator (406a), the upper surface of the insulator (402), and the upper surface of the insulator (410), which are surfaces excluding at least the side surface of the insulator (410). The insulator (406c) can be formed by sputtering.

[0134] Here, a sputtering apparatus used to form an insulator (406c) is described with reference to FIGS. 21 and FIGS. 22.

[0135] FIG. 21 is a cross-sectional view illustrating a part of a sputtering apparatus (101). The sputtering apparatus (101) illustrated in FIG. 21 includes a member (190), a collimator (150) disposed on the member (190), a target holder (120), a backing plate (110) disposed on the target holder (120), a target (100) disposed on the backing plate (110), a magnet unit (130) comprising a magnet (130N) and a magnet (130S) disposed below the target (100) via the backing plate (110), and a magnet holder (132) supporting the magnet unit (130). Additionally, in this specification, a magnet unit refers to a group of magnets. A magnet unit may be replaced with a "cathode," a "cathode magnet," a "magnetic member," or a "magnetic component," etc.

[0136] A substrate stage (170) positioned opposite the target (100) and a substrate (160) supported by the substrate stage (170) are illustrated. FIG. 21 also illustrates magnetic field lines (180a) and magnetic field lines (180b) formed by a magnet unit (130).

[0137] The target holder (120) and the backing plate (110) are fixed to each other by bolts and have the same potential. The target holder (120) has the function of supporting the target (100) through the backing plate (110).

[0138] The backing plate (110) has the function of fixing the target (100).

[0139] The sputtering device (101) may have a channel inside or under the backing plate (110). By flowing a fluid (air, nitrogen, noble gas, water, or oil, etc.) through the channel, damage to the sputtering device (101) caused by discharge abnormalities due to the temperature rise of the target (100) or deformation of parts such as the target (100) during sputtering can be prevented. In this case, it is desirable to bond the backing plate (110) and the target (100) together with an adhesive so that the cooling performance is improved.

[0140] Providing a gasket between the target holder (120) and the backing plate (110) is desirable because it makes it difficult for impurities to enter the sputtering device (101) from the outside or through the waterway.

[0141] In the magnet unit (130), the magnet (130N) and the magnet (130S) are arranged so that their sides on the target (100) side have opposite polarities. Here, the case where the pole of the magnet (130N) on the target (100) side is the N pole and the pole of the magnet (130S) on the target (100) side is the S pole is described. Furthermore, the arrangement of the magnets and polarities in the magnet unit (130) is not limited to that shown in FIG. 21.

[0142] The magnetic field line (180a) is one of the magnetic field lines that form a horizontal magnetic field near the upper surface of the target (100). The area near the upper surface of the target (100) corresponds, for example, to an area where the vertical distance from the upper surface of the target (100) is 0 mm or more and 10 mm or less, particularly 0 mm or more and 5 mm or less.

[0143] The magnetic field line (180b) is a vertical distance from the upper surface of the magnet unit (130). d It is one of the magnetic field lines that forms a horizontal magnetic field on a plane at a distance of that amount. Vertical distance d For example, it is 0mm or more and 20mm or less, or 5mm or more and 15mm or less.

[0144] When depositing, the potential (V1) applied to the target holder (120) is lower than, for example, the potential (V2) applied to the substrate stage (170). The potential (V2) applied to the substrate stage (170) is, for example, ground potential. The potential (V3) applied to the magnet holder (132) is, for example, ground potential. Furthermore, the potentials (V1, V2, and V3) are not limited to those described above. It is not necessary to supply potential to all of the target holder (120), the substrate stage (170), and the magnet holder (132). For example, the substrate stage (170) may be in an electrically floating state.

[0145] FIG. 21 illustrates an example in which the backing plate (110) and the target holder (120) are not electrically connected to the magnet unit (130) and the magnet holder (132), but the electrical connection is not limited thereto. For example, the backing plate (110) and the target holder (120) may be electrically connected to the magnet unit (130) and the magnet holder (132), and the backing plate (110), the target holder (120), the magnet unit (130), and the magnet holder (132) may have the same potential.

[0146] When a deposition gas (e.g., a noble gas such as oxygen, nitrogen, or argon) is flowed through a sputtering device (101) and a potential (V1) is applied to a target holder (120) under conditions where the pressure of the sputtering device (101) is kept constant (e.g., 0.05 Pa or more and 10 Pa or less, preferably 0.1 Pa or more and 0.8 Pa or less), plasma is formed in the magnetic field formed by the magnet unit (130). The potential of the plasma is a potential (Vp) higher than the potential (V1). At this time, positive ions within the plasma are accelerated toward the target (100) by the potential difference between the potential (Vp) and the potential (V1). Then, the positive ions collide with the target (100), and sputtering particles are emitted. The emitted sputtering particles that reach the substrate (160) are deposited to form a film.

[0147] Generally, in a sputtering device, it is difficult for sputtering particles to reach the bottom portion of a small opening with a high aspect ratio. In addition, sputtering particles flying at an oblique direction relative to the substrate are deposited near the top of the opening, narrowing the width of the top of the opening. In such cases, sputtering particles are not formed in the opening.

[0148] Meanwhile, by using a sputtering apparatus having the structure described above, sputtering particles emitted in an oblique direction with respect to the forming surface of the substrate (160) are attached to the collimator (150). That is, sputtering particles having a component perpendicular to the substrate (160) that have passed through the collimator (150) provided between the target (100) and the substrate (160) reach the substrate. Accordingly, sputtering particles are deposited on a surface parallel to the substrate. Meanwhile, sputtering particles are not deposited on a surface perpendicular to the substrate, or the amount deposited on a surface perpendicular to the substrate is less than the amount deposited on a surface parallel to the substrate. Therefore, by using a sputtering apparatus having the structure described above, an insulator (406c) excluding a surface perpendicular to the substrate can be formed on the surface, as shown in (C) and (D) of FIG. 8.

[0149] The vertical distance between the target (100) and the collimator (150) and the vertical distance between the substrate (160) and the collimator (150) can be appropriately varied depending on the quality of the film being formed. Accordingly, as shown in FIG. 22, the collimator (150) may include a movable part (151) and a movable part (152). By including the movable part (151), it is easy to select whether to use the collimator (150). By including the movable part (152), the vertical distance between the collimator (150) and the substrate (160) and the vertical distance between the collimator (150) and the target (100) can be easily adjusted.

[0150] Alternatively, a long throw sputtering method may be used. In the long throw sputtering method, by increasing the vertical distance between the target (100) and the substrate (160), the incident direction of the sputtering particles can be made substantially perpendicular to the substrate (160). Therefore, even without using a collimator (150), an insulator (406c) excluding the surface perpendicular to the substrate can be formed on the surface. Additionally, the vertical distance between the substrate (160) and the target (100) is 150 mm or more and 500 mm or less. Furthermore, a combination of the long throw sputtering method and the collimator (150) may be adopted.

[0151] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0152] Next, as shown in (E) and (F) of FIG. 8, an insulator (412), a conductor (404a), and a conductor (404b) are formed.

[0153] First, an insulator that becomes an insulator (412) is formed on the insulator (410) and the insulator (406c). The insulator that becomes an insulator (412) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method.

[0154] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0155] Next, a conductor (404a) and a conductor (404b) are formed. The conductor (404a) and the conductor (404b) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. The conductor (404a) and the conductor (404b) are formed to fill an opening formed in an insulator (410), etc. Therefore, the CVD method (particularly the MCVD method) is preferred. In order to increase the adhesion of the conductor formed by the MCVD method, a laminated film of a conductor formed by the ALD method and a conductor formed by the CVD method may be preferred. For example, a laminated film in which titanium nitride and tungsten are formed in this order can be used.

[0156] Next, as shown in (A) and (B) of FIG. 9, the conductor (404a), conductor (404b), insulator (412), and insulator (406c) are removed by CMP processing or the like so that the insulator (410) is exposed. Here, the insulator (410) can be used as a stopper layer, and the thickness of the insulator (410) may be reduced. Accordingly, by making the insulator (410) have sufficient thickness so that the resistance of the conductor (404a) and conductor (404b) in the finished transistor is sufficiently lowered, a plurality of transistors with small variation in characteristics can be manufactured.

[0157] In addition, CMP treatment may be performed only once or multiple times. When CMP treatment is performed multiple times, it is preferable to perform the first polishing at a high polishing rate and the final polishing at a low polishing rate. By combining polishing steps with different polishing rates, the flatness of the polished surface can be further improved.

[0158] Next, a conductor (420) is formed. Additionally, the conductor (420) may have a stacked structure. The conductor (420) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. Next, the conductor (420) is processed by a photolithography method or the like to form the conductor (420).

[0159] Next, as illustrated in (C) and (D) of FIG. 9, an insulator (408) is formed on the insulator (410) and the conductor (420). The insulator (408) can be formed by sputtering, CVD, MBE, PLD, or ALD. It is preferable to form aluminum oxide as the insulator (408) using an oxygen-containing plasma, because the oxygen in the plasma can be added to the upper surface of the insulator (410) as excess oxygen (exO). Excess oxygen can be added to the insulator (408) by supplying oxygen through the insulator (410). Here, a mixed region containing a large amount of excess oxygen can be formed at the interface between the insulator (408) and the insulator (410) and near this interface.

[0160] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0161] Additionally, a second heat treatment may be performed at any timing after forming the insulator (408). Through the second heat treatment, excess oxygen contained in the insulator (410) and the mixing region (414) passes through the insulator (412), insulator (402), insulator (406c), and insulator (406a) to the semiconductor (406b). As described above, since excess oxygen moves to the semiconductor (406b), defects (oxygen vacancies) in the semiconductor (406b) can be reduced.

[0162] Additionally, the second heat treatment can be performed at a temperature at which excess oxygen in the insulator (410) and the mixing region (414) diffuses to the semiconductor (406b). For example, regarding the second heat treatment, one may refer to the description of the first heat treatment. It is preferable that the second heat treatment be performed at a lower temperature than the first heat treatment. It is preferable that the second heat treatment be performed at a temperature 20°C or higher and 150°C or lower, preferably 40°C or higher and 100°C or lower, lower than the first heat treatment. By doing so, the release of excess oxygen beyond what is necessary from the insulator (402), etc., can be suppressed. Furthermore, if the heating during film formation can function as a heat treatment equivalent to the second heat treatment, it is not necessary to perform the second heat treatment.

[0163] Although not shown, an opening reaching a conductor (416a) and an opening reaching a conductor (416b) may be formed in the insulator (408) and the insulator (410), and a conductor functioning as wiring may be formed in the openings. Alternatively, an opening reaching a conductor (404) may be formed in the insulator (408), and a conductor functioning as wiring may be formed in the opening.

[0164] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 1 can be fabricated.

[0165] In Embodiment 1, one embodiment of the present invention was described. However, one embodiment of the present invention is not limited to the example described above. That is, since various forms of the present invention are described in this embodiment and other embodiments, one embodiment of the present invention is not limited to a specific embodiment. Although an example using an oxide semiconductor as a semiconductor was described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on the case or conditions, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or an organic semiconductor may be used in one embodiment of the present invention.

[0166] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0167] (Embodiment 2)

[0168] Transistor Structure 2

[0169] A transistor having a structure different from that of FIGS. 1 (A) to (C) and a method for manufacturing the same will be described with reference to FIGS. 2 (A) to (C). FIGS. 2 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2 (A) is a top view, and FIGS. 2 (B) and (C) are cross-sectional views taken along the dotted lines A1-A2 and A3-A4 of FIG. 2 (A), respectively. Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 2 (A).

[0170] In the transistor of FIG. 2 (B), the angle between the side of the insulator (410) and the top surface of the conductor (416a) θ The angle is greater than 0° and less than 90°, and forms an insulator (406c) on the side of the insulator (410). θThe angle is preferably 75° or more and less than 90°, more preferably 80° or more and less than 90°, and even more preferably 85° or more and less than 90°. The insulator (406c) is formed thinner in the area overlapping the side of the conductor (404) with the insulator (412) interposed than in the area overlapping the bottom surface of the conductor (404). For other components, refer to the description of the transistor in (A) to (C) of FIG. 1.

[0171] Transistor Fabrication Method 2

[0172] First, perform the steps up to the step shown in (H) of FIG. 7 described in Embodiment 1.

[0173] Next, the angle between the side of the insulator (410) and the upper surface of the conductor (416a). θ The sides of the insulator (410) are formed such that the angle is greater than 0° and less than 90°. Then, the insulator (406c) is formed using the film forming device described in Embodiment 1. Here, for example, the angle θ The smaller the angle, the higher the possibility of sputtering particle deposition, and the thicker the insulator (406c) is formed on the side of the insulator (410). θ As the angle increases, the insulator (406c) is formed thinly on the side of the insulator (410). In this way, the thickness of the insulator (406c) formed on the side of the insulator (410) is angle θ It can be adjusted by. That is, the width of the offset area formed, L1, can be reduced. Therefore, t1 is greater than L1, and L1 / t1 is less than 1.

[0174] The next step can be performed in a manner similar to the step described in Method 1 for fabricating a transistor described in Embodiment 1.

[0175] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 2 can be fabricated.

[0176] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0177] (Embodiment 3)

[0178] <Transistor Structures 3 and 4>

[0179] A transistor having a structure different from that of FIGS. 1 (A) to (C) and a method for manufacturing the same will be explained with reference to FIGS. 3 (A) to (C) and FIGS. 4 (A) to (C). FIGS. 3 (A) to (C) and FIGS. 4 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0180] The transistors illustrated in FIGS. 3 (A) to (C) and FIGS. 4 (A) to (C) will be described. FIGS. 3 (A) and FIGS. 4 (A) are top views. FIGS. 3 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 3 (A). FIGS. 3 (C) is a cross-sectional view taken along the dotted line A3-A4 illustrated in FIGS. 3 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 3 (A).

[0181] FIG. 4(B) is a cross-sectional view taken along the dotted line A1-A2 shown in FIG. 4(A). FIG. 4(C) is a cross-sectional view taken along the dotted line A3-A4 shown in FIG. 4(A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 4(A).

[0182] In the transistors of FIGS. 3 (A) to (C) and FIGS. 4 (A) to (C), an insulator (406c2) (an insulator (406c) of FIGS. 4 (A) to (C)), an insulator (412), a conductor (404a), and a conductor (404b) are also formed in a portion of the upper surface of the insulator (410). For other components, refer to the description of the transistors of FIGS. 1 (A) to (C) or FIGS. 2 (A) to (C).

[0183] In the transistors of FIGS. 3 (A) to (C) and FIGS. 4 (A) to (C), a portion of the conductor (404a) and conductor (404b) that function as gate electrodes may function as wiring. That is, a portion of the conductor (404a and 404b) formed on the insulator (410) with the insulator (406c) and insulator (412) interposed corresponds to the conductor (420) in transistor structure 1. That is, in the above structure, t2 is the vertical distance between the conductor (416a) or conductor (416b) and a portion of the conductor (404a) on the insulator (410). Additionally, since the insulator (406c2), insulator (412), conductor (404a), and conductor (404b) are formed simultaneously, the insulator (406c2) (the insulator (406c) of FIG. 4 (A) to (C)) and the insulator (412) are positioned between the upper surface of the insulator (410) and a portion of the conductor (404a) formed on the insulator (410). Therefore, if the length t2 of the total thickness of the insulator (410), insulator (406c2) (the insulator (406c) of FIG. 4 (A) to (C)), and insulator (412) can be made sufficiently large, the parasitic capacitance can be reduced.

[0184] Transistor Fabrication Methods 3 and 4

[0185] The method for fabricating the transistors illustrated in (A) to (C) of FIG. 3 is described below.

[0186] First, perform the steps up to the step shown in (F) of FIG. 8 described in Embodiment 1.

[0187] Next, an insulator (406c), an insulator (412), a conductor (404a), and a conductor (404b) are formed by photolithography or the like. With this structure, a conductor corresponding to the conductor (420) in transistor structure 1 can be formed simultaneously using the conductor (404a) and the conductor (404b).

[0188] Next, an insulator (408) is formed.

[0189] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 3 can be fabricated.

[0190] In the transistors of FIG. 4 (A) to (C), an insulator (406c), an insulator (412), a conductor (404a), and a conductor (404b) are formed in steps similar to those of the transistors illustrated in FIG. 2 (A) to (C). Then, the insulator (406c), the insulator (412), the conductor (404a), and the conductor (404b), each having a desired shape, are formed by photolithography. By this structure, a conductor corresponding to the conductor (420) in transistor structure 1 can be formed using the conductor (404a) and the conductor (404b).

[0191] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 4 can be fabricated.

[0192] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0193] (Embodiment 4)

[0194] <Transistor Structures 5 and 6>

[0195] A transistor having a structure different from that of FIGS. 1 (A) to (C) and a method for manufacturing the same will be explained with reference to FIGS. 5 (A) to (C) and FIGS. 6 (A) to (C). FIGS. 5 (A) to (C) and FIGS. 6 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0196] The transistors illustrated in FIGS. 5 (A) to (C) and FIGS. 6 (A) to (C) will be described. FIGS. 5 (A) and FIGS. 6 (A) are top views. FIGS. 5 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 5 (A). FIGS. 5 (C) is a cross-sectional view taken along the dotted line A3-A4 illustrated in FIGS. 5 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 5 (A).

[0197] FIG. 6(B) is a cross-sectional view taken along the dotted line A1-A2 shown in FIG. 6(A). FIG. 6(C) is a cross-sectional view taken along the dotted line A3-A4 shown in FIG. 6(A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 6(A).

[0198] In the transistors illustrated in FIGS. 5 (A) to (C) and FIGS. 6 (A) to (C), the conductor (416a) and the conductor (416b) are formed only on the semiconductor (406b). For other components, refer to the description of the transistor in FIGS. 1 (A) to (C) or the transistor in FIGS. 2 (A) to (C).

[0199] Transistor Fabrication Methods 5 and 6

[0200] The method for fabricating the transistors illustrated in (A) to (C) of FIG. 5 is described below.

[0201] First, the steps up to the steps illustrated in (A) and (B) of FIG. 7 described in Embodiment 1 are performed.

[0202] Then, after forming the insulator (406a) and the semiconductor (406b), the conductor (416) is formed. Next, a resist is formed on the conductor (416) using a photolithography method or the like, and a first etching is performed on the conductor (416) using the resist as a mask. Then, after removing the resist, a second etching is performed using the conductor (416) as a mask. The second etching is performed on the insulator (406a) and the semiconductor (406b).

[0203] The subsequent steps are similar to the steps following the steps shown in (G) and (H) of FIG. 7 in Embodiment 1. By going through the steps described above, the transistors shown in (A) to (C) of FIG. 5 can be fabricated.

[0204] In the transistors illustrated in FIGS. 6 (A) to (C), an insulator (406a), a semiconductor (406b), and a conductor (416) are formed in a manner similar to that of the transistors illustrated in FIGS. 5 (A) to (C). Additionally, it is preferable to form the transistor through steps similar to those of the transistors illustrated in FIGS. 2 (A) to (C).

[0205] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 6 can be fabricated.

[0206] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0207] (Embodiment 5)

[0208] Transistor Structure 7

[0209] The structure of a transistor included in a semiconductor device according to one embodiment of the present invention is described below.

[0210] FIGS. 10 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 10 (A) is a top view. FIGS. 10 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 10 (A), showing the cross-sectional shape in the channel length direction. FIGS. 10 (C) is a cross-sectional view taken along the dotted line A3-A4 of FIGS. 10 (A), showing the cross-sectional shape in the channel width direction. Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 10 (A).

[0211] The transistors illustrated in (A) to (C) of FIG. 10 each include a conductor (413) and an insulator (401) on a substrate (400), an insulator (402) on the conductor (413) and the insulator (401), an insulator (406a) on the insulator (402), a semiconductor (406b) on the insulator (406a), a conductor (416a) and a conductor (416b) each having a region in contact with the upper surface of the semiconductor (406b), an insulator (410) having an opening that contacts the upper surface of the insulator (402), the conductor (416a), and the conductor (416b), an insulator (410) having an opening that contacts the side of the conductor (416a) and the upper surface and side of the semiconductor (406b), an insulator (406d) on the insulator (406c), and a region in contact with the upper surface of the insulator (406d) and the side of the opening of the insulator (410). A conductor (404) comprising a conductor (404a) and a conductor (404b) is disposed on a semiconductor (406b) via an insulator (412), an insulator (412), an insulator (406c), and an insulator (406d). Additionally, the conductor (404b) faces the side of the opening of the insulator (410) via the conductor (404a) and the insulator (412). A conductor (420) on the conductor (404a) and the conductor (404b), and an insulator (408) on the insulator (412) and the conductor (420) are disposed on the transistor. Alternatively, it is not necessary to provide a conductor (413) and an insulator (401), and a structure without a conductor (413) and an insulator (401) may also be used, as shown in (A) to (C) of FIG. 56.

[0212] It is preferable that the insulator (406c) and the insulator (406d) each contain at least one element other than oxygen, which is included in the semiconductor (406b). By doing so, the formation of defects at the interface between the semiconductor (406b) and the insulator (406c), and at the interface between the insulator (406c) and the insulator (406d), can be suppressed. Additionally, the crystallinity of the insulator (406c) and the insulator (406d) can be improved.

[0213] It is preferable that the semiconductor (406b) and the insulator (406c) each include a CAAC-OS, which will be described later. Additionally, it is preferable that the insulator (406d) includes a CAAC-OS. Additionally, it is preferable that the insulator (406a) includes a CAAC-OS.

[0214] In this transistor, the conductors (404a and 404b) function as the first gate electrode. It is preferable that at least one of the conductors (404a and 404b) is a conductor that is difficult to permeate oxygen. For example, if a conductor that is difficult to permeate oxygen is formed as the lower layer conductor (404a), a decrease in conductivity due to oxidation of the conductor (404b) can be prevented. The insulator (412) functions as the first gate insulator.

[0215] The conductor (413) functions as a second gate electrode. The conductor (413) may have a stacked structure including a conductor that is difficult to permeate oxygen. A stacked structure including a conductor that is difficult to permeate oxygen can prevent a decrease in conductivity due to oxidation of the conductor (413). The insulator (402) functions as a second gate insulator. The potential applied to the conductor (413) can control the threshold voltage of the transistor. When the first gate electrode is electrically connected to the second gate electrode, the current in the conductive state (on-state current) can be increased. Additionally, the functions of the first gate electrode and the second gate electrode may be interchanged.

[0216] The conductor (416a) and the conductor (416b) function as a source electrode and a drain electrode. Additionally, the conductivity of the conductor can be measured by a two-terminal method, etc.

[0217] Accordingly, the resistance of the semiconductor (406b) can be controlled by the potential applied to the conductor (404). That is, the conduction or non-conduction between the conductor (416a) and the conductor (416b) can be controlled by the potential applied to the conductor (404).

[0218] As illustrated in (B) of FIG. 10, the upper surface of the semiconductor (406b) is in contact with the conductors (416a and 416b). Additionally, the semiconductor (406b) can be electrically surrounded by the electric field of the conductor (404) which functions as a gate electrode. A structure in which the semiconductor is electrically surrounded by the electric field of the gate electrode is called an s-channel (surrounded channel) structure. Thus, a channel may be formed over the entire semiconductor (406b). In an s-channel structure, a large amount of current can be flowed between the source and drain of the transistor, thereby increasing the on-state current. Additionally, because the semiconductor (406b) is surrounded by the electric field of the conductor (404), the off-state current can be reduced.

[0219] The transistor in this embodiment may also be called a TGSA s-channel FET (trench-gate self-aligned s-channel FET) because the region functioning as a gate electrode is formed self-aligned to fill an opening formed in an insulator (410), etc.

[0220] Here, in (B) of FIG. 10, the length between the upper surface of the region of the semiconductor (406b) overlapping with the conductor (404) and the lower surface of the conductor (404) is denoted as t1. In (B) of FIG. 10, the length between the region of the semiconductor (406b) overlapping with the lower surface of the conductor (416a) and the region of the semiconductor (406b) overlapping with the lower surface of the conductor (404) is denoted as L1. Alternatively, the length between the region of the semiconductor (406b) overlapping with the lower surface of the conductor (416b) and the region of the semiconductor (406b) overlapping with the lower surface of the conductor (404) is denoted as L1.

[0221] In a transistor, a region having L1 is formed between a region where a channel is formed in the semiconductor (406b) (a region where the conductor (404) and the semiconductor (406b) overlap each other) and a source region or drain region (a region where the conductor (416a) or the conductor (416b) overlaps with the semiconductor (406b). The region having L1 can reduce the off-state current of the transistor, but if the region having L1 is excessively large, the on-state current of the transistor may be reduced.

[0222] By covering the region where a channel is formed in the semiconductor (406b) with an insulator (406c) and an insulator (406d), elements other than oxygen (such as hydrogen and silicon) contained in adjacent insulators can be prevented from entering the region where the channel is formed by the insulator (406c) and the insulator (406d). Accordingly, the insulator (406c) and the insulator (406d) can be formed on at least the semiconductor (406b).

[0223] L1 can be reduced by not providing an insulator (406c) and an insulator (406d) on the side of the conductor (404) with an insulator (412) interposed, or by forming the insulator (406c) and the insulator (406d) thinner in the area covering the side of the conductor (404) with an insulator (412) than in the area overlapping with the bottom surface of the conductor (404) with an insulator (412). Accordingly, t1 is greater than L1, and L1 / t1 is less than 1.

[0224] In FIG. 10 (B) and FIG. 11 (A), the length between the conductor (416a) or the conductor (416b) and the conductor (420) is denoted as t2. Also, in FIG. 10 (B), the length between the conductor (416a) and the conductor (416b) is denoted as L2.

[0225] As transistors become smaller, parasitic capacitance near the transistor becomes a significant problem that cannot be ignored. For example, parasitic capacitance may be formed between a conductor (420) and a conductor (416a) or a conductor (416b). If there is a large parasitic capacitance near the region where the channel is formed, for example, the transistor operation requires time to charge the parasitic capacitance, which degrades not only the responsiveness of the transistor but also the responsiveness of the semiconductor device. In addition, the power consumption of a circuit containing multiple transistors increases due to the extra power consumption required to charge the parasitic capacitance. Therefore, it is desirable that t2 be a length sufficient to allow the parasitic capacitance to be ignored compared to the gate capacitance.

[0226] As the transistor becomes smaller, L2 is reduced, making it difficult to apply a sufficiently large voltage to the conductor (404a) and the conductor (404b). However, if t2 has a sufficient length, the resistance of the conductor (404a) and the resistance of the conductor (404b) can be reduced. Therefore, it is preferable that t2 is at least greater than L2, and that t2 / L2 is between 1.5 and 2.

[0227] Figures 11 (A) and (B) are enlarged views of an opening provided in the insulator (410) of the transistor in this embodiment. The upper surface of the insulator (406d) is substantially the same height as the upper surfaces of the conductor (416a) and the conductor (416b). Additionally, the upper surface of the insulator (406d) is the surface close to the conductor (404a) in the area where the insulator (406d) overlaps with the lower surfaces of the conductor (404a) and the conductor (404b). Ideally, as shown in Figure 11 (A), it is desirable that the upper surface of the insulator (406d) be the same height as the upper surfaces of the conductors (416a and 416b).

[0228] It is preferable that the upper surface of the insulator (406c) has substantially the same height as the interface between the semiconductor (406b) and the conductors (416a and 416b). Additionally, the upper surface of the insulator (406c) is the surface close to the conductor (404a) in the area where the insulator (406c) overlaps with the lower surfaces of the conductors (404a) and (404b). Ideally, it is preferable that the upper surface of the insulator (406c) has the same height as the interface between the semiconductor (406b) and the conductors (416a and 416b). Additionally, the insulator (406c) must fill at least the over-etched portion of the semiconductor (406b), but is not limited thereto, and as shown in (B) of FIG. 11, the upper surface of the insulator (406c) may be above the interface between the semiconductor (406b) and the conductors (416a and 416b).

[0229] The transistor of the present embodiment has a structure in which two insulators (406c and 406d) are provided on a semiconductor (406b), but is not limited thereto, and three or more stacked layers may be provided.

[0230] As a substrate (400), for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As an insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, a yttria-stabilized zirconia substrate), or a resin substrate may be used. As a semiconductor substrate, for example, a semiconductor substrate made of a single material such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A semiconductor substrate provided with an insulating region on the above-described semiconductor substrate, for example, a silicon-on-insulator (SOI) substrate, etc. may be used. As a conductive substrate, a graphite substrate, a metal substrate, an alloy substrate, or a conductive resin substrate, etc. may be used. A substrate containing a metal nitride or a substrate containing a metal oxide, etc. may be used. An insulating substrate provided with a conductor or semiconductor, a semiconductor substrate provided with a conductor or insulator, or a conductive substrate provided with a semiconductor or insulator, etc. may be used. Alternatively, a device provided on any of these substrates may be used. As the device provided on the substrate, a capacitive element, a resistor, a switching element, a light-emitting element, or a memory element may be used.

[0231] Alternatively, a flexible substrate may be used as the substrate (400). As a method of providing a transistor on a flexible substrate, there is a method of forming a transistor on a non-flexible substrate, then separating the transistor and transferring it to the substrate (400) which is the flexible substrate. In this case, it is preferable to provide a separation layer between the non-flexible substrate and the transistor. As the substrate (400), a sheet, film, or foil containing fibers may be used. The substrate (400) may have elasticity. The substrate (400) may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate (400) may have the property of not returning to its original shape. For example, the substrate (400) has a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. If the thickness of the substrate (400) is thin, the weight of the semiconductor device including the transistor can be reduced. If the thickness of the substrate (400) is thin, the substrate (400) may have elasticity, or the property of returning to its original shape when bending or pulling is stopped. Therefore, the impact applied to the semiconductor device on the substrate (400) due to dropping, etc., can be reduced. That is, a durable semiconductor device can be provided.

[0232] For the flexible substrate (400), for example, metal, alloy, resin, glass, or fiber thereof may be used. It is desirable for the flexible substrate (400) to have a low linear expansion coefficient so that deformation caused by the environment is suppressed. For example, the flexible substrate (400) has a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5It is formed using a material with a coefficient of K or less. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate (400) because it has a low coefficient of linear expansion.

[0233] Additionally, the electrical characteristics of the transistor can be stabilized when the transistor is surrounded by an insulator that has the function of blocking impurities such as oxygen and hydrogen. For example, an insulator that has the function of blocking impurities such as oxygen and hydrogen can be used as the insulator (408).

[0234] An insulator having the function of blocking impurities such as oxygen and hydrogen may have a single-layer structure or a multilayer structure including, for example, an insulator including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

[0235] For example, the insulator (408) may be formed from aluminum oxide, magnesium oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Additionally, it is preferable that the insulator (408) contains aluminum oxide. For example, if the insulator (408) is formed using a plasma containing oxygen, oxygen may be added to the side of the insulator (410) or insulator (412) which forms the lower layer of the insulator (408). The added oxygen becomes excess oxygen within the insulator (410) or insulator (412). If the insulator (408) contains aluminum oxide, it can suppress the entry of impurities such as hydrogen into the semiconductor (406b). Additionally, for example, if the insulator (408) contains aluminum oxide, it can reduce the outward diffusion of excess oxygen added to the insulator (410) and the insulator (412).

[0236] The insulator (402) may be formed to have a single-layer or multilayer structure comprising, for example, an insulator comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, the insulator (402) preferably comprises silicon oxide or silicon nitride oxide.

[0237] Additionally, it is preferable that the insulator (410) comprises an insulator with a low dielectric constant. For example, the insulator (410) preferably comprises silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with holes, or a resin. Alternatively, the insulator (410) preferably has a laminated structure of a resin and one of silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with holes. When a thermally stable silicon oxide or silicon nitride oxide is combined with a resin, this laminated structure may have thermal stability and a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic.

[0238] The insulator (412) may be formed to have a single-layer or multilayer structure including, for example, an insulator comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. For example, it is preferable to use a material comprising silicon oxide or silicon nitride oxide for the insulator (412).

[0239] Additionally, it is preferable that the insulator (412) includes an insulator with a high dielectric constant. For example, it is preferable that the insulator (412) include gallium oxide, hafnium oxide, an oxide containing aluminum and hafnium, an oxide containing aluminum and hafnium, an oxide containing silicon and hafnium, or an oxide containing silicon and hafnium. It is preferable that the insulator (412) have a stacked structure including silicon oxide or silicon nitride oxide and an insulator with a high dielectric constant. Since silicon oxide and silicon nitride oxide are thermally stable, by combining silicon oxide or silicon nitride oxide with an insulator with a high dielectric constant, the stacked structure can be thermally stable and have a high dielectric constant. For example, if the aluminum oxide, gallium oxide, or hafnium oxide of the insulator (412) is on the side of the insulator (406c and 406d), the silicon contained in the silicon oxide or silicon nitride oxide can be prevented from entering the semiconductor (406b). For example, if silicon oxide or silicon nitride oxide is on the side of the insulator (406c and 406d), a capture center may be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon nitride oxide. The capture center may be able to change the threshold voltage of the transistor in a positive direction by capturing electrons.

[0240] The conductors (416a and 416b) may each be formed to have a single-layer or multilayer structure including one or more types of conductors, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used, and a conductor including aluminum, a conductor including copper and titanium, a conductor including copper and manganese, a conductor including indium, tin, and oxygen, or a conductor including titanium and nitrogen, etc. may be used.

[0241] The conductors (404, 413, and 420) may each be formed to have a single-layer or multilayer structure including one or more types of conductors, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, an alloy film or a compound film may be used, and a conductor including aluminum, a conductor including copper and titanium, a conductor including copper and manganese, a conductor including indium, tin, and oxygen, or a conductor including titanium and nitrogen, etc. may be used.

[0242] It is preferable to use an oxide semiconductor as the semiconductor (406b). However, silicon (including modified silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or organic semiconductors may be used.

[0243] As for the insulator (406a), insulator (406c), and insulator (406d), it is preferable to use an oxide containing one or more elements other than oxygen included in the semiconductor (406b). However, silicon (including modified silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or organic semiconductors may be used.

[0244] The semiconductor (406b) is, for example, an oxide semiconductor containing indium. By including, for example, indium, the semiconductor (406b) can have high carrier mobility (electron mobility). The semiconductor (406b) is an element M It is desirable to include the element M It is preferable that it be aluminum, gallium, yttrium, or tin, etc. Element M Other elements that can be used as such include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc. In addition, the element M As such, two or more of the aforementioned elements may be used in combination. Element M For example, it is an element with a high binding energy with oxygen. Element M Silver is an element with a higher binding energy with oxygen than indium. Element M Zinc is, for example, an element that can increase the energy gap of an oxide semiconductor. Additionally, it is desirable for the semiconductor (406b) to contain zinc. For example, if the oxide semiconductor contains zinc, the oxide semiconductor crystallizes easily.

[0245] Additionally, the semiconductor (406b) is not limited to an oxide semiconductor containing indium. The semiconductor (406b) may be, for example, an oxide semiconductor containing zinc without indium, an oxide semiconductor containing gallium without indium, or an oxide semiconductor containing tin without indium (e.g., zinc tin oxide or gallium tin oxide).

[0246] For the semiconductor (406b), an oxide with a wide energy gap may be used. The energy gap of the semiconductor (406b) is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0247] Insulators (406a), insulators (406c), and insulators (406d) are oxides containing one or more or two or more elements other than oxygen included in the semiconductor (406b). Since insulators (406a), insulators (406c), and insulators (406d) each contain one or more or two or more elements other than oxygen included in the semiconductor (406b), it is difficult for defect levels to form at the interface between insulator (406a) and the semiconductor (406b), the interface between the semiconductor (406b) and the insulator (406c), and the interface between insulator (406c) and the insulator (406d).

[0248] As the semiconductor (406b), an oxide with a higher electron affinity than that of the insulators (406a, 406c, and 406d) is used. For example, as the semiconductor (406b), an oxide with an electron affinity higher than that of the insulators (406a, 406c, and 406d) is used, which is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. Furthermore, electron affinity refers to the energy gap between the vacuum level and the bottom of the conduction band. Additionally, it is preferable that the insulator (406c) has a higher electron affinity than the insulator (406d).

[0249] In this way, when a gate voltage is applied to a transistor in which an insulator (406a) is placed below a semiconductor (406b) and insulators (406c and 406d) are placed above a semiconductor (406b), a channel is formed in the semiconductor (406b) which has the highest electron affinity among the insulator (406a), semiconductor (406b), insulator (406c), and insulator (406d). In this manner, a buried channel structure can be formed.

[0250] Here, there may be a mixed region of the insulator (406a) and the semiconductor (406b) between the insulator (406a) and the semiconductor (406b). Additionally, there may be a mixed region of the semiconductor (406b) and the insulator (406c) between the semiconductor (406b) and the insulator (406c). Additionally, there may be a mixed region of the insulator (406c) and the insulator (406d) between the insulator (406c) and the insulator (406d). The mixed region has a low defect level density. For this reason, in a laminate comprising the insulator (406a), the semiconductor (406b), the insulator (406c), and the insulator (406d), the energy changes continuously at their interfaces and near these interfaces (continuous junction). Furthermore, the boundaries between the insulator (406a), the semiconductor (406b), and the insulator (406c) may not be clear.

[0251] At this time, the electrons move mainly in the semiconductor (406b), rather than in the insulator (406a), insulator (406c), and insulator (406d).

[0252] The more the factors inhibiting electron movement are reduced, the higher the on-state current of the transistor can be increased. Electron movement is inhibited, for example, when the physical irregularities in the channel-forming region are large.

[0253] To increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of a measurement area of ​​1 μm × 1 μm on the upper or lower surface (forming surface; here, the upper surface of the insulator (406a)) of the semiconductor (406b) is set to less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The average surface roughness (also called Ra) of the measurement area of ​​1 μm × 1 μm is set to less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The maximum difference (PV) of the measurement area of ​​1 μm × 1 μm is set to less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope SPA-500 (manufactured by SII Nano Technology Inc.).

[0254] The above-described four-layer structure is an example. For example, any of the insulators described as examples, such as insulator (406a), insulator (406c), and insulator (406d), may adopt a laminated structure provided below or above insulator (406a) or below or above insulator (406d).

[0255] In addition, oxide semiconductors that can be used in semiconductors will be described in detail in another embodiment.

[0256] Transistor Fabrication Method 7

[0257] A method for fabricating transistors according to the present invention in FIGS. 10 (A) to (C) is described below with reference to FIGS. 18 (A) to (H), FIGS. 19 (A) to (F), and FIGS. 20 (A) to (F).

[0258] First, prepare a substrate (400).

[0259] Next, as illustrated in (A) and (B) of FIG. 18, an insulator (401) is formed on a substrate (400). An opening is formed in the insulator (401), and a conductor (413) is formed on the insulator (401). The conductor (413) can be formed by sputtering, CVD, MBE, PLD, or ALD. The conductor (413) may have a multilayer structure including a conductor that is difficult to permeate oxygen. The conductor (413) may be embedded in the opening of the insulator (401) by chemical mechanical polishing (CMP), etc. Alternatively, the conductor (413) may be formed by forming a conductor and processing it by photolithography, etc.

[0260] In the photolithography method, a resist is first exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, etching is performed through the resist mask. As a result, conductors, semiconductors, or insulators can be processed into a desired shape. For example, the resist mask is formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (extreme ultraviolet) light, etc. Alternatively, an immersion technique may be employed in which the area between the substrate and the projection lens is filled with a liquid (e.g., water) to perform the exposure. An electron beam or an ion beam may be used instead of the light described above. Furthermore, dry etching treatments such as ashing or wet etching treatments may be used to remove the resist mask. Alternatively, a wet etching treatment may be performed after a dry etching treatment. Alternatively, a dry etching treatment may be performed after a wet etching treatment.

[0261] As a dry etching device, a capacitively coupled plasma (CCP) etching device including parallel planar electrodes may be used. The CCP etching device including parallel planar electrodes may have a structure that applies high-frequency power to one of the parallel planar electrodes. Alternatively, the CCP etching device may have a structure that applies a different high-frequency power to one of the parallel planar electrodes. Alternatively, the CCP etching device may have a structure that applies high-frequency power of the same frequency to the parallel planar electrodes. Alternatively, the CCP etching device may have a structure that applies high-frequency power of a different frequency to the parallel planar electrodes. Alternatively, a dry etching device including a high-density plasma source may be used. As a dry etching device including a high-density plasma source, for example, an inductively coupled plasma (ICP) etching device may be used.

[0262] Next, high-density plasma treatment may be performed as indicated by the arrows (A) and (B) of FIG. 18. It is preferable to perform high-density plasma treatment in an oxygen atmosphere or a nitrogen atmosphere. An oxygen atmosphere is a gas atmosphere containing oxygen atoms and includes an atmosphere of oxygen, ozone, and nitrogen oxides (e.g., nitric oxide, nitrogen dioxide, dinitrogen monoxide, dinitrogen trioxide, dinitrogen tetroxide, or dinitrogen pentoxide). In an oxygen atmosphere, an inert gas such as nitrogen or a noble gas (e.g., helium or argon) may be included. By performing high-density plasma treatment in an oxygen atmosphere in this way, carbon or hydrogen, etc., can be released. In addition, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be easily released from the object.

[0263] High-density plasma treatment in a nitrogen atmosphere may be, for example, in an atmosphere containing nitrogen and noble gases, an atmosphere containing nitrogen, hydrogen, and noble gases, or an atmosphere containing ammonia and noble gases. Through this high-density plasma treatment in a nitrogen atmosphere, the surface of the object to be treated and its vicinity can be nitrided. The nitrided area can be formed very thinly on the surface side of the object to be treated. The diffusion of impurities can be prevented by this nitrided area.

[0264] High-density plasma treatment may be performed in a nitrogen atmosphere after performing high-density plasma treatment in an oxygen atmosphere. Alternatively, high-density plasma treatment may be performed in an oxygen atmosphere after performing high-density plasma treatment in a nitrogen atmosphere. Annealing treatment may be performed before or after each high-density plasma treatment. In addition, to increase plasma density, it may be desirable to flow a sufficient amount of gas. If the amount of gas is insufficient, the rate of radical inactivation may become higher than the rate of radical generation. For example, it may be desirable to flow gas at a rate of 100 sccm or more, 300 sccm or more, or 800 sccm or more.

[0265] High-density plasma treatment is performed using microwaves generated by a high-frequency generator that generates waves with a frequency of, for example, 0.3 GHz or higher and 3.0 GHz or lower, 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower (typically, 2.45 GHz). The treatment pressure can be 10 Pa or higher and 5000 Pa or lower, preferably 200 Pa or higher and 1500 Pa or lower, more preferably 300 Pa or higher and 1000 Pa or lower. The substrate temperature can be 100°C or higher and 600°C or lower (typically, 400°C). In addition, a mixed gas of oxygen and argon can be used.

[0266] For example, high-density plasma is generated using 2.45 GHz microwaves, and has an electron density of 1 × 10⁻⁶ 11 / cm 3 1×10 13 / cm 3 Furthermore, it is preferable that the electron temperature be 2 eV or less, or the ion energy be 5 eV or less. This high-density plasma treatment produces radicals with low kinetic energy, and compared to conventional plasma treatment, plasma damage is reduced. Therefore, it is possible to form a film with fewer defects. The distance between the antenna generating microwaves and the object being treated is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0267] Alternatively, a plasma power supply that applies an RF (radio frequency) bias to the substrate may be provided. The frequency of the RF bias may be, for example, 13.56 MHz or 27.12 MHz. High-density oxygen ions can be produced by using high-density plasma, and oxygen ions generated by the high-density plasma can be efficiently introduced into the object being processed by applying an RF bias to the substrate. Therefore, it is desirable to perform high-density plasma processing while applying a bias to the substrate.

[0268] After high-density plasma treatment, continuous annealing treatment may be performed without exposure to the atmosphere. By performing high-density plasma treatment and annealing treatment consecutively, the ingress of impurities during treatment can be suppressed. Furthermore, by performing annealing treatment after high-density plasma treatment in an oxygen atmosphere, unnecessary oxygen added to the object being treated that was not used to fill oxygen vacancies can be removed. This annealing treatment can be performed, for example, by lamp annealing.

[0269] It is preferable that the treatment time for high-density plasma treatment be 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0270] It is preferable that the treatment time for annealing at a temperature of 250°C or higher and 800°C or lower, 300°C or higher and 700°C or lower, or 400°C or higher and 600°C or lower be 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0271] Next, an insulator (402) is formed. The insulator (402) can be formed by sputtering, CVD, MBE, PLD, or ALD.

[0272] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma; thermal CVD (TCVD), which uses heat; and photo CVD, which uses light. Additionally, CVD methods may include metal CVD (MCVD) and metal-organic CVD (MOCVD) methods depending on the source gas.

[0273] By using the PECVD method, high-quality films can be formed at relatively low temperatures. Additionally, since the thermal CVD method does not use plasma, plasma damage to the object is minimal. For example, wiring, electrodes, or components (e.g., transistors or capacitive elements) included in a semiconductor device may become charged by receiving charges from the plasma. In this case, the wiring, electrodes, or components included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, if the thermal CVD method, which does not use plasma, is adopted, the aforementioned damage caused by exposure to plasma does not occur, thereby increasing the yield of the semiconductor device. In the thermal CVD method, since the object is not exposed to plasma during deposition, a film with fewer defects can be obtained.

[0274] The ALD method also causes minimal plasma damage to the object. Since the ALD method does not generate plasma damage during deposition, it is possible to obtain films with few defects.

[0275] Unlike deposition methods in which particles emitted from a target are deposited, in CVD and ALD methods, a film is formed by a reaction on the surface of an object. Therefore, CVD and ALD methods can achieve good step coverage regardless of the shape of the object. In particular, for example, ALD can achieve good step coverage and uniformity of thickness, and can be advantageously used to cover the surface of an opening with a high aspect ratio. On the other hand, since ALD has a low deposition rate, it is sometimes desirable to combine ALD with other deposition methods that have a high deposition rate, such as CVD.

[0276] When using the CVD or ALD method, the composition of the formed film can be controlled by the flow rate ratio of the source gas. For example, a film with a specific composition can be formed by the CVD or ALD method depending on the flow rate ratio of the source gas. Furthermore, by changing the flow rate ratio of the source gas during film formation using the CVD or ALD method, a film with a continuously changing composition can be formed. Compared to forming a film using multiple deposition chambers, forming a film while changing the flow rate ratio of the source gas eliminates the time required for transport and pressure adjustment, thereby reducing the time required for film formation. Consequently, semiconductor devices can be fabricated with improved productivity.

[0277] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0278] Additionally, a treatment to add oxygen to the insulator (402) may be performed. For the oxygen addition treatment, an ion implantation method or a plasma treatment method may be used. Additionally, the oxygen added to the insulator (402) is excess oxygen.

[0279] Next, as shown in (C) and (D) of FIG. 18, an insulator (406a), a semiconductor (406b), and a resist mask (430) are formed.

[0280] First, an insulator (406a) is formed on the insulator (402). The insulator (406a) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. It is particularly preferable to use a counter-target sputtering device. Additionally, in this specification and other contexts, deposition using a counter-target sputtering device may also be referred to as VDSP (vapor deposition sputtering).

[0281] Using a counter-target sputtering device can reduce plasma damage induced during the deposition of the insulator. Consequently, oxygen vacancies within the insulator can be reduced. Furthermore, using a counter-target sputtering device allows for deposition in a high vacuum. In such cases, the concentration of impurities (e.g., hydrogen, noble gases (such as argon), or water) within the deposited insulator can be reduced.

[0282] Alternatively, a sputtering device including an inductively coupled antenna conductor plate may be used. Thus, a large film with high uniformity can be formed at a high deposition rate.

[0283] It is preferable that deposition be carried out using a gas containing oxygen or a gas containing nitrogen, etc. As a gas containing nitrogen, for example, nitrogen (N2), dinitrogen monoxide (N2O), or ammonia (NH3) may be used.

[0284] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when high-density plasma treatment is performed under an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0285] Additionally, a treatment to add oxygen to the insulator that becomes the insulator (406a) may be performed. For the treatment to add oxygen, an ion implantation method or a plasma treatment method may be used. Also, the oxygen added to the insulator that becomes the insulator (406a) is excess oxygen.

[0286] Next, a semiconductor (406b) is formed on an insulator (406a). The semiconductor can be formed by sputtering, CVD, MBE, PLD, or ALD. It is particularly preferable to use a counter-target type sputtering apparatus.

[0287] Using a counter-target sputtering device can reduce plasma damage induced during semiconductor deposition. Consequently, oxygen vacancies within the semiconductor can be reduced. Furthermore, using a counter-target sputtering device allows for deposition in a high vacuum. In such cases, the concentration of impurities (e.g., hydrogen, noble gases (such as argon), or water) within the deposited semiconductor can be reduced.

[0288] Alternatively, a sputtering device including an inductively coupled antenna conductor plate may be used. Thus, a large film with high uniformity can be formed at a high deposition rate.

[0289] It is preferable that deposition be carried out using a gas containing oxygen, a noble gas, or a gas containing nitrogen. As a gas containing nitrogen, for example, nitrogen (N2), dinitrogen monoxide (N2O), or ammonia (NH3) may be used.

[0290] Next, it is preferable to perform a first heat treatment. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or higher and 600°C or lower. The first heat treatment is performed in an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed by first performing a heat treatment in an inert gas atmosphere, and then performing another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to preserve the released oxygen. Through the first heat treatment, for example, the crystallinity of the semiconductor can be increased and impurities such as hydrogen and moisture can be removed. Alternatively, in the first heat treatment, a plasma treatment using oxygen may be performed under reduced pressure. It is preferable that the plasma treatment containing oxygen be performed using a device including a power source that generates high-density plasma using microwaves, for example. Alternatively, a plasma power source that applies an RF (radio frequency) voltage to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be produced, and by applying an RF voltage to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor (406b). Alternatively, after performing plasma treatment using an inert gas with the above device, plasma treatment using oxygen may be performed to preserve the released oxygen.

[0291] Next, as illustrated in (E) and (F) of FIG. 18, an insulator (406a) and a semiconductor (406b) are processed using a photolithography method or the like using a resist mask (430) to form a multilayer film including the insulator (406a) and the semiconductor (406b). Additionally, when forming the multilayer film, the insulator (402) may also be etched to have a thin region. That is, the insulator (402) may have a convex portion in the region in contact with the multilayer film.

[0292] Next, carbon and hydrogen, etc. may be released by performing high-density plasma treatment. Additionally, when high-density plasma treatment is performed in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0293] Next, as shown in (G) and (H) of FIG. 18, an insulator is formed that becomes a conductor (416) and an insulator (410).

[0294] First, a conductor (416) is formed. The conductor (416) can be formed by sputtering, CVD, MBE, PLD, or ALD.

[0295] Additionally, the conductor (416) covers the multilayer film. The side of the insulator (406a) and the top and side of the semiconductor (406b) are partially damaged in forming the conductor on the multilayer film, and a region with reduced resistance can then be formed. Since the insulator (406a) and the semiconductor (406b) each include a region with reduced resistance, the contact resistance between the conductor (416) and the semiconductor (406b) can be lowered.

[0296] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0297] Next, the conductor (416) is processed by photolithography or the like to form conductors (416a and 416b).

[0298] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0299] Next, an insulator (410) is formed. The insulator (410) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. Alternatively, the insulator (410) can be formed by a spin coating method, immersion method, droplet discharge method (inkjet method, etc.), printing method (screen printing or offset printing, etc.), doctor knife method, roll coater method, or curtain coater method.

[0300] The insulator (410) may be formed to have a flat upper surface. For example, the upper surface of the insulator (410) may have flatness immediately after film formation. Alternatively, after film formation, the upper surface of the insulator (410) may be removed so that it becomes parallel to a reference surface, such as the back surface of the substrate. This process is called a flattening process. As a flattening process, for example, CMP processing or dry etching processing may be performed. However, the upper surface of the insulator (410) does not necessarily have to be flat.

[0301] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0302] Next, a resist mask (431) is formed on an insulator (410) using a photolithography method or the like. Here, in order to improve the adhesion between the upper surface of the insulator (410) and the resist mask (431), an organic coating film may be formed between the upper surface of the insulator (410) and the resist mask (431).

[0303] Next, as illustrated in (A) and (B) of FIG. 19, an opening is formed in the insulator (410) and the conductor (416). First, in order to expose the upper surface of the conductor (416), a first processing is performed on the insulator that becomes the insulator (410) using a dry etching method or the like. In the dry etching method, any of the dry etching devices described above may be used, but it is preferable to use a dry etching device in which a high-frequency power source with a different frequency is connected to parallel plate-shaped electrodes.

[0304] Next, a second processing step is performed on the conductor (416) using a dry etching method or the like to separate it into a conductor (416a) and a conductor (416b). Additionally, the insulator (410) and the conductor (416) may be processed in the same photolithography process. By processing them in the same photolithography process, the number of manufacturing steps can be reduced. Therefore, a semiconductor device including a transistor can be manufactured with high productivity.

[0305] At this time, the semiconductor (406b) has an exposed region. The exposed region of the semiconductor (406b) may be partially removed by a second processing step. Additionally, impurity elements, such as residual components of the etching gas, may adhere to the exposed surface of the semiconductor (406b). For example, if a chlorine-based gas is used as the etching gas, chlorine and the like may adhere. If a hydrocarbon-based gas is used as the etching gas, carbon and hydrogen and the like may adhere. It is desirable to reduce the impurity elements attached to the exposed surface of the semiconductor (406b). The impurity elements may be reduced by a cleaning treatment using diluted hydrofluoric acid, a cleaning treatment using ozone, or a cleaning treatment using ultraviolet rays. Additionally, a combination of several types of cleaning treatments may be used. As a result, the exposed surface of the semiconductor (406b), that is, the region where the channel is formed, has high resistance.

[0306] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0307] Next, as illustrated in (C) and (D) of FIG. 19, an insulator (406c) is formed on the upper and side surfaces of the semiconductor (406b), the side surface of the insulator (406a), the upper surface of the insulator (402), and the upper surface of the insulator (410), which are surfaces excluding at least the side surface of the insulator (410). Additionally, it is preferable that the insulator (406c) be formed to fill the concave portion formed in the semiconductor (406b). The insulator (406c) can be formed by sputtering.

[0308] Here, a sputtering apparatus used for forming insulators (406c) and (406d) is described with reference to FIGS. 21 and FIGS. 22.

[0309] FIG. 21 is a cross-sectional view illustrating a part of a sputtering apparatus (101). The sputtering apparatus (101) illustrated in FIG. 21 includes a member (190), a collimator (150) on the member (190), a target holder (120), a backing plate (110) placed on the target holder (120), a target (100) placed on the backing plate (110), a magnet unit (130) including a magnet (130N) and a magnet (130S) placed below the target (100) via the backing plate (110), and a magnet holder (132) supporting the magnet unit (130). Additionally, in this specification, a magnet unit refers to a group of magnets. A magnet unit may be replaced with a "cathode," a "cathode magnet," a "magnetic member," or a "magnetic component," etc.

[0310] A substrate stage (170) positioned opposite the target (100) and a substrate (160) supported by the substrate stage (170) are illustrated. FIG. 21 also illustrates magnetic field lines (180a) and magnetic field lines (180b) formed by a magnet unit (130).

[0311] The target holder (120) and the backing plate (110) are fixed to each other by bolts and have the same potential. The target holder (120) has the function of supporting the target (100) through the backing plate (110).

[0312] The backing plate (110) has the function of fixing the target (100).

[0313] The sputtering device (101) may have a channel inside or under the backing plate (110). By flowing a fluid (air, nitrogen, noble gas, water, or oil, etc.) through the channel, damage to the sputtering device (101) caused by discharge abnormalities due to the temperature rise of the target (100) or deformation of parts such as the target (100) during sputtering can be prevented. In this case, it is desirable to bond the backing plate (110) and the target (100) together with an adhesive so that the cooling performance is improved.

[0314] Providing a gasket between the target holder (120) and the backing plate (110) is desirable because it makes it difficult for impurities to enter the sputtering device (101) from the outside or through the waterway.

[0315] In the magnet unit (130), the magnet (130N) and the magnet (130S) are arranged so that their sides on the target (100) side have opposite polarities. Here, the case where the pole of the magnet (130N) on the target (100) side is the N pole and the pole of the magnet (130S) on the target (100) side is the S pole is described. Furthermore, the arrangement of the magnet and pole in the magnet unit (130) is not limited to that shown in FIG. 21.

[0316] The magnetic field line (180a) is one of the magnetic field lines that form a horizontal magnetic field near the upper surface of the target (100). The area near the upper surface of the target (100) corresponds, for example, to an area where the vertical distance from the upper surface of the target (100) is 0 mm or more and 10 mm or less, particularly 0 mm or more and 5 mm or less.

[0317] The magnetic field line (180b) is a vertical distance from the upper surface of the magnet unit (130). d It is one of the magnetic field lines that forms a horizontal magnetic field on a plane at a distance of that amount. Vertical distance d For example, it is 0mm or more and 20mm or less, or 5mm or more and 15mm or less.

[0318] When depositing, the potential (V1) applied to the target holder (120) is lower than, for example, the potential (V2) applied to the substrate stage (170). The potential (V2) applied to the substrate stage (170) is, for example, ground potential. The potential (V3) applied to the magnet holder (132) is, for example, ground potential. Furthermore, the potentials (V1, V2, and V3) are not limited to those described above. It is not necessary to supply potential to all of the target holder (120), the substrate stage (170), and the magnet holder (132). For example, the substrate stage (170) may be in an electrically floating state.

[0319] FIG. 21 illustrates an example in which the backing plate (110) and the target holder (120) are not electrically connected to the magnet unit (130) and the magnet holder (132), but the electrical connection is not limited thereto. For example, the backing plate (110) and the target holder (120) may be electrically connected to the magnet unit (130) and the magnet holder (132), and the backing plate (110), the target holder (120), the magnet unit (130), and the magnet holder (132) may have the same potential.

[0320] When a deposition gas (e.g., a noble gas such as oxygen, nitrogen, or argon) is flowed through a sputtering device (101) and a potential (V1) is applied to a target holder (120) under conditions where the pressure of the sputtering device (101) is kept constant (e.g., 0.05 Pa or more and 10 Pa or less, preferably 0.1 Pa or more and 0.8 Pa or less), plasma is formed in the magnetic field formed by the magnet unit (130). The potential of the plasma is a potential (Vp) higher than the potential (V1). At this time, positive ions within the plasma are accelerated toward the target (100) by the potential difference between the potential (Vp) and the potential (V1). Then, the positive ions collide with the target (100), and sputtering particles are emitted. The emitted sputtering particles that reach the substrate (160) are deposited to form a film.

[0321] Generally, in a sputtering device, it is difficult for sputtering particles to reach the bottom portion of a small opening with a high aspect ratio. In addition, sputtering particles flying at an oblique direction relative to the substrate are deposited near the top of the opening, narrowing the width of the top of the opening. In such cases, sputtering particles are not formed in the opening.

[0322] Meanwhile, by using a sputtering apparatus having the structure described above, sputtering particles emitted in an oblique direction with respect to the forming surface of the substrate (160) are attached to the collimator (150). That is, sputtering particles having a component perpendicular to the substrate (160) that have passed through the collimator (150) provided between the target (100) and the substrate (160) reach the substrate. Accordingly, sputtering particles are deposited on a surface parallel to the substrate. Meanwhile, sputtering particles are not deposited on a surface perpendicular to the substrate, or the amount deposited on a surface perpendicular to the substrate is less than the amount deposited on a surface parallel to the substrate. Therefore, by using a sputtering apparatus having the structure described above, an insulator (406c) excluding a surface perpendicular to the substrate can be formed on the surface, as shown in (C) and (D) of FIG. 19.

[0323] The vertical distance between the target (100) and the collimator (150) and the vertical distance between the substrate (160) and the collimator (150) can be appropriately varied depending on the quality of the film being formed. Accordingly, as shown in FIG. 22, the collimator (150) may include a movable part (151) and a movable part (152). By including the movable part (151), it is easy to select whether to use the collimator (150). By including the movable part (152), the vertical distance between the collimator (150) and the substrate (160) and the vertical distance between the collimator (150) and the target (100) can be easily adjusted.

[0324] Alternatively, a long throw sputtering method may be used. In the long throw sputtering method, by increasing the vertical distance between the target (100) and the substrate (160), the incident direction of the sputtering particles can be made substantially perpendicular to the substrate (160). Therefore, even without using a collimator (150), an insulator (406c) excluding the surface perpendicular to the substrate can be formed on the surface. Additionally, the vertical distance between the substrate (160) and the target (100) is 150 mm or more and 500 mm or less. Furthermore, a combination of the long throw sputtering method and the collimator (150) may be adopted.

[0325] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0326] Next, an insulator (406d) is formed as shown in (E) and (F) of FIG. 19. The insulator (406d) can be formed in a similar step to the insulator (406c).

[0327] Next, as shown in (A) and (B) of FIG. 20, an insulator (412), a conductor (404a), and a conductor (404b) are formed.

[0328] First, an insulator that becomes an insulator (412) is formed on the insulator (410) and the insulator (406d). The insulator that becomes an insulator (412) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method.

[0329] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0330] Next, a conductor (404a) and a conductor (404b) are formed. The conductor (404a) and the conductor (404b) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. The conductor (404a) and the conductor (404b) are formed to fill an opening formed in an insulator (410), etc. Therefore, the CVD method (particularly the MCVD method) is preferred. In order to increase the adhesion of the conductor formed by the MCVD method, a laminated film of a conductor formed by the ALD method and a conductor formed by the CVD method may be preferred. For example, a laminated film in which titanium nitride and tungsten are formed in this order can be used.

[0331] Next, as shown in (C) and (D) of FIG. 20, the conductor (404a), conductor (404b), insulator (412), insulator (406c), and insulator (406d) are removed by CMP processing or the like so that the insulator (410) is exposed. Here, the insulator (410) can be used as a stopper layer, and the thickness of the insulator (410) may be reduced. Accordingly, by making the insulator (410) have sufficient thickness so that the resistance of the conductor (404a) and conductor (404b) in the finished transistor is sufficiently lowered, a plurality of transistors with small variation in characteristics can be manufactured.

[0332] In addition, CMP treatment may be performed only once or multiple times. When CMP treatment is performed multiple times, it is preferable to perform the first polishing at a high polishing rate and the final polishing at a low polishing rate. By combining polishing steps with different polishing rates, the flatness of the polished surface can be further improved.

[0333] Next, a conductor (420) is formed. Additionally, the conductor (420) may have a stacked structure. The conductor (420) can be formed by a sputtering method, CVD method, MBE method, PLD method, or ALD method. Next, the conductor (420) is processed by a photolithography method or the like to form the conductor (420).

[0334] Next, as illustrated in (E) and (F) of FIG. 20, an insulator (408) is formed on the insulator (410) and the conductor (420). The insulator (408) can be formed by sputtering, CVD, MBE, PLD, or ALD. It is preferable to form aluminum oxide as the insulator (408) using an oxygen-containing plasma, because the oxygen in the plasma can be added to the upper surface of the insulator (410) as excess oxygen (exO). Excess oxygen can be added to the insulator (408) by supplying oxygen through the insulator (410). Here, a mixed region containing a large amount of excess oxygen can be formed at the interface between the insulator (408) and the insulator (410) and near this interface.

[0335] Next, carbon and hydrogen, etc. may be released by performing the above high-density plasma treatment. Additionally, when performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons may be released from the object.

[0336] Additionally, a second heat treatment may be performed at any timing after forming the insulator (408). Through the second heat treatment, excess oxygen contained in the insulator (410) and the mixing region (414) passes through the insulator (412), insulator (402), insulator (406d), insulator (406c), and insulator (406a) to the semiconductor (406b). As described above, since excess oxygen moves to the semiconductor (406b), defects (oxygen vacancies) in the semiconductor (406b) can be reduced.

[0337] Additionally, the second heat treatment can be performed at a temperature at which excess oxygen in the insulator (410) and the mixing region (414) diffuses to the semiconductor (406b). For example, regarding the second heat treatment, one may refer to the description of the first heat treatment. It is preferable that the second heat treatment be performed at a lower temperature than the first heat treatment. It is preferable that the second heat treatment be performed at a temperature 20°C or higher and 150°C or lower, preferably 40°C or higher and 100°C or lower, lower than the first heat treatment. By doing so, the release of excess oxygen beyond what is necessary from the insulator (402), etc., can be suppressed. Furthermore, if the heating during film formation can function as a heat treatment equivalent to the second heat treatment, it is not necessary to perform the second heat treatment.

[0338] Although not shown, an opening reaching a conductor (416a) and an opening reaching a conductor (416b) may be formed in the insulator (408) and the insulator (410), and a conductor functioning as wiring may be formed in the openings. Alternatively, an opening reaching a conductor (404) may be formed in the insulator (408), and a conductor functioning as wiring may be formed in the opening.

[0339] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 10 can be fabricated.

[0340] In Embodiment 5, one embodiment of the present invention has been described. However, one embodiment of the present invention is not limited to the example described above. That is, since various forms of the present invention are described in this embodiment and other embodiments, one embodiment of the present invention is not limited to a specific embodiment. Although an example using an oxide semiconductor as a semiconductor has been described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on the case or conditions, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphorus, gallium nitride, or an organic semiconductor may be used in one embodiment of the present invention.

[0341] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0342] (Embodiment 6)

[0343] Transistor Structure 8

[0344] A transistor having a structure different from that of FIGS. 10 (A) to (C) and a method for manufacturing the same will be described with reference to FIGS. 12 (A) to (C) and FIGS. 13 (A) and (B). FIGS. 12 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 12 (A) is a top view, and FIGS. 12 (B) and (C) are cross-sectional views taken along the dotted lines A1-A2 and A3-A4 of FIG. 12 (A), respectively. Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 12 (A). FIGS. 13 (A) and (B) are enlarged views of the cross-sectional views shown in FIGS. 12 (B) and (C).

[0345] In the transistor of FIG. 12 (B), the angle between the side of the insulator (410) and the top surface of the conductor (416a) θThe angle is greater than 0° and less than 90°, and an insulator (406d) is formed by interposing an insulator (406c) on the side of the insulator (410). θ The angle is preferably 75° or more and less than 90°, more preferably 80° or more and less than 90°, and even more preferably 85° or more and less than 90°. The insulator (406c) and the insulator (406d) are formed thinner in the area overlapping the side of the conductor (404) with the insulator (412) interposed than in the area overlapping the bottom surface of the conductor (404). For other components, refer to the description of the transistor in (A) to (C) of FIG. 10.

[0346] As long as t1 is greater than L1 and L1 / t1 is less than 1, either the insulator (406c) or the insulator (406d) in the area covering the side of the insulator (410) may be formed thinly. Additionally, either the insulator (406c) or the insulator (406d) in the area covering the side of the insulator (410) may be formed, and the other one does not necessarily need to be provided.

[0347] Figures 13 (A) and (B) are enlarged views of an opening provided in the insulator (410) of the transistor in this embodiment. The upper surface of the insulator (406d) is substantially the same height as the upper surfaces of the conductor (416a) and the conductor (416b). Additionally, the upper surface of the insulator (406d) is the surface close to the conductor (404a) in the area where the insulator (406d) overlaps with the lower surfaces of the conductor (404a) and the conductor (404b). Ideally, as shown in Figure 13 (A), it is desirable that the upper surface of the insulator (406d) be the same height as the upper surfaces of the conductors (416a and 416b).

[0348] It is preferable that the upper surface of the insulator (406c) has substantially the same height as the interface between the semiconductor (406b) and the conductors (416a and 416b). Additionally, the upper surface of the insulator (406c) is the surface close to the conductor (404a) in the area where the insulator (406c) overlaps with the lower surfaces of the conductors (404a) and (404b). Ideally, it is preferable that the upper surface of the insulator (406c) has the same height as the interface between the semiconductor (406b) and the conductors (416a and 416b). Additionally, the insulator (406c) must fill at least the over-etched portion of the semiconductor (406b), but is not limited thereto, and as shown in (B) of FIG. 13, the upper surface of the insulator (406c) may be above the interface between the semiconductor (406b) and the conductors (416a and 416b).

[0349] The transistor of the present embodiment has a structure in which two insulators (406c and 406d) are provided on a semiconductor (406b), but is not limited thereto, and three or more stacked layers may be provided.

[0350] Transistor Fabrication Method 8

[0351] First, perform the steps up to the step shown in (H) of FIG. 18 described in Embodiment 5.

[0352] Next, the angle between the side of the insulator (410) and the upper surface of the conductor (416a). θ The sides of the insulator (410) are formed such that the angle is greater than 0° and less than 90°. Then, insulators (406c) and insulators (406d) are formed using the film forming device described in Embodiment 5. Here, for example, the angle θ The smaller the angle, the higher the possibility of sputtering particle deposition, and the insulator (406c) and insulator (406d) are formed thickly on the side of the insulator (410). θAs the angle increases, the insulator (406c) and the insulator (406d) are formed thinly on the side of the insulator (410). In this way, the thickness of the insulator (406c) and the insulator (406d) formed on the side of the insulator (410) is angle θ It can be adjusted by. That is, the width of the offset area formed, L1, can be reduced. Therefore, t1 is greater than L1, and L1 / t1 is less than 1.

[0353] The next step can be performed in a manner similar to the step described in Method 1 for fabricating a transistor described in Embodiment 5.

[0354] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 12 can be fabricated.

[0355] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0356] (Embodiment 7)

[0357] <Transistor Structures 9 and 10>

[0358] A transistor having a structure different from that of FIGS. 10 (A) to (C) and a method for manufacturing the same will be explained with reference to FIGS. 14 (A) to (C) and FIGS. 15 (A) to (C). FIGS. 14 (A) to (C) and FIGS. 15 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0359] The transistors illustrated in FIGS. 14 (A) to (C) and FIGS. 15 (A) to (C) will be described. FIGS. 14 (A) and FIGS. 15 (A) are top views. FIGS. 14 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 14 (A). FIGS. 14 (C) is a cross-sectional view taken along the dotted line A3-A4 illustrated in FIGS. 14 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 14 (A).

[0360] FIG. 15 (B) is a cross-sectional view taken along the dotted line A1-A2 shown in FIG. 15 (A). FIG. 15 (C) is a cross-sectional view taken along the dotted line A3-A4 shown in FIG. 15 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 15 (A).

[0361] In the transistors of FIGS. 14 (A) to (C) and FIGS. 15 (A) to (C), an insulator (406c2) (an insulator (406c) of FIGS. 4 (A) to (C)), an insulator (406d2) (an insulator (406d) of FIGS. 4 (A) to (C)), an insulator (412), a conductor (404a), and a conductor (404b) are also formed in a portion of the upper surface of the insulator (410). For other components, refer to the description of the transistors of FIGS. 10 (A) to (C) or FIGS. 12 (A) to (C).

[0362] In the transistors of FIGS. 14 (A) to (C) and FIGS. 15 (A) to (C), a portion of the conductor (404a) and conductor (404b) that function as gate electrodes may function as wiring. That is, a portion of the conductor (404a and 404b) formed on the insulator (410) via an insulator (406c2) (an insulator (406c) of FIGS. 4 (A) to (C)), an insulator (406d2) (an insulator (406d) of FIGS. 4 (A) to (C)), and an insulator (412) corresponds to the conductor (420) in transistor structure 1. That is, in the above structure, t2 is the vertical distance between the conductor (416a) or conductor (416b) and a portion of the conductor (404a) on the insulator (410). In addition, since the insulator (406c2) (the insulator (406c) of FIG. 4 (A) to (C)), the insulator (406d2) (the insulator (406d) of FIG. 4 (A) to (C)), the insulator (412), the conductor (404a), and the conductor (404b) are formed simultaneously, the insulator (406c), the insulator (406d2) (the insulator (406d) of FIG. 4 (A) to (C)), and the insulator (412) are positioned between the upper surface of the insulator (410) and a portion of the conductor (404a) formed on the insulator (410). Accordingly, if the total thickness length t2 of the insulator (410), insulator (406c2) (insulator (406c) of FIG. 4 (A) to (C)), and insulator (406d2) (insulator (406d) of FIG. 4 (A) to (C)) can be made sufficiently large, parasitic capacitance can be reduced.

[0363] Transistor Fabrication Methods 9 and 10

[0364] The method for fabricating the transistors illustrated in (A) to (C) of FIG. 14 is described below.

[0365] First, perform the steps up to the step shown in (F) of FIG. 19 described in Embodiment 5.

[0366] Next, an insulator (406c), an insulator (406d), an insulator (412), a conductor (404a), and a conductor (404b) are formed by photolithography or the like. With this structure, a conductor corresponding to the conductor (420) in transistor structure 1 can be formed simultaneously using the conductor (404a) and the conductor (404b).

[0367] Next, an insulator (408) is formed.

[0368] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 14 can be fabricated.

[0369] In the transistors of FIG. 15 (A) to (C), an insulator (406c), an insulator (406d), an insulator (412), a conductor (404a), and a conductor (404b) are formed, each having a desired shape, in a similar step to the transistors shown in FIG. 12 (A) to (C). Then, the insulator (406c), the insulator (406d), the insulator (412), the conductor (404a), and the conductor (404b) are formed by photolithography. With this structure, a conductor corresponding to the conductor (420) in transistor structure 1 can be formed using the conductor (404a) and the conductor (404b).

[0370] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 15 can be fabricated.

[0371] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0372] (Embodiment 8)

[0373] <Transistor Structures 11 and 12>

[0374] A transistor having a structure different from that of FIGS. 10 (A) to (C) and a method for manufacturing the same will be explained with reference to FIGS. 16 (A) to (C) and FIGS. 17 (A) to (C). FIGS. 16 (A) to (C) and FIGS. 17 (A) to (C) are top view and cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0375] The transistors described in FIGS. 16 (A) to (C) and FIGS. 17 (A) to (C) will be described. FIGS. 16 (A) and FIGS. 17 (A) are top views. FIGS. 16 (B) is a cross-sectional view taken along the dotted line A1-A2 of FIGS. 16 (A). FIGS. 16 (C) is a cross-sectional view taken along the dotted line A3-A4 shown in FIGS. 16 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIGS. 16 (A).

[0376] FIG. 17 (B) is a cross-sectional view taken along the dotted line A1-A2 shown in FIG. 17 (A). FIG. 17 (C) is a cross-sectional view taken along the dotted line A3-A4 shown in FIG. 17 (A). Additionally, for the sake of simplification of the drawings, some components are not shown in the top view of FIG. 17 (A).

[0377] In the transistors illustrated in FIGS. 16 (A) to (C) and FIGS. 17 (A) to (C), the conductor (416a) and the conductor (416b) are formed only on the semiconductor (406b). For other components, refer to the description of the transistor in FIGS. 10 (A) to (C) or the transistor in FIGS. 12 (A) to (C).

[0378] Transistor Fabrication Methods 11 and 12

[0379] The method for fabricating the transistors illustrated in (A) to (C) of FIG. 16 is described below.

[0380] First, perform the steps up to the steps illustrated in (A) and (B) of FIG. 18 described in Embodiment 5.

[0381] Then, after forming the insulator (406a) and the semiconductor (406b), the conductor (416) is formed. Next, a resist is formed on the conductor (416) using a photolithography method or the like, and a first etching is performed on the conductor (416) using the resist as a mask. Then, after removing the resist, a second etching is performed using the conductor (416) as a mask. The second etching is performed on the insulator (406a) and the semiconductor (406b).

[0382] The subsequent steps are similar to the steps following the steps shown in (G) and (H) of FIG. 18. By going through the steps described above, the transistors shown in (A) to (C) of FIG. 16 can be fabricated.

[0383] In the transistors illustrated in (A) to (C) of FIG. 17, an insulator (406a), a semiconductor (406b), and a conductor (416) are formed in a manner similar to that of the transistors illustrated in (A) to (C) of FIG. 16. Additionally, it is preferable to form the transistor through steps similar to those of the transistors illustrated in (A) to (C) of FIG. 12.

[0384] By following the steps described above, the transistors illustrated in (A) to (C) of FIG. 17 can be fabricated.

[0385] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0386] (Embodiment 9)

[0387] <Sedimentation device>

[0388] The structure of a deposition apparatus including the sputtering apparatus described above is explained below. The structure of a deposition apparatus capable of preventing impurities from entering the film during deposition is explained with reference to (A) to (C) of FIGS. 23 and 24.

[0389] FIG. 23 is a top view schematically illustrating a single-leaf multi-chamber deposition device (1700). The deposition device (1700) comprises an atmospheric side substrate supply chamber (1701) including a cassette port (1761) for receiving a substrate and an alignment port (1762) for performing alignment of the substrate, an atmospheric side substrate return chamber (1702) for returning a substrate from the atmospheric side substrate supply chamber (1701), a load lock chamber (1703a) for receiving a substrate and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber (1703b) for releasing a substrate and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a return chamber (1704) for returning a substrate in a vacuum, a substrate heating chamber (1705) for heating a substrate, a deposition chamber (1706a, 1706b), and It includes 1706c). Additionally, the sputtering device (101) can be used in all or some of the deposition chambers (1706a, 1706b, and 1706c).

[0390] Additionally, as shown in FIG. 23, a plurality of cassette ports (1761) may be provided (in FIG. 23, three cassette ports (1761) are provided).

[0391] The air-side substrate return chamber (1702) is connected to the load lock chamber (1703a) and the unload lock chamber (1703b), the load lock chamber (1703a) and the unload lock chamber (1703b) are connected to the return chamber (1704), and the return chamber (1704) is connected to the substrate heating chamber (1705) and the deposition chambers (1706a, 1706b, and 1706c).

[0392] A gate valve (1764) is provided at the connection between the chambers, so that the pressure of each chamber, excluding the air-side substrate supply chamber (1701) and the air-side substrate return chamber (1702), can be controlled independently. Additionally, the air-side substrate return chamber (1702) includes a return robot (1763a), and the return chamber (1704) includes a return robot (1763b). Substrates can be returned by the return robot.

[0393] It is preferable that the substrate heating chamber (1705) also function as a plasma treatment chamber. In the deposition device (1700), since the substrate can be transported without exposing it to the atmosphere between treatments, the adsorption of impurities on the substrate in the atmosphere can be suppressed. In addition, the order of deposition or heat treatment can be freely determined. Furthermore, the structures of the transport chamber, deposition chamber, load lock chamber, unload lock chamber, and substrate heating chamber are not limited to those described above, and their structures can be appropriately set according to the installation space or process conditions.

[0394] Next, (A), (B), and (C) of FIG. 24 are, respectively, cross-sectional views taken along the dashed line X1-X2, the dashed line Y1-Y2, and the dashed line Y2-Y3 in the deposition device (1700) shown in FIG. 23.

[0395] FIG. 24 (A) is a cross-section of a substrate heating chamber (1705) and a return chamber (1704), and the substrate heating chamber (1705) includes a plurality of heating stages (1765) capable of receiving a substrate. In addition, the number of heating stages (1765) shown in FIG. 24 (A) is 7, but is not limited thereto; it may be one or more but less than 7, or eight or more. By increasing the number of heating stages (1765), heating treatment can be performed on a plurality of substrates simultaneously, thereby improving productivity. In addition, the substrate heating chamber (1705) is connected to a vacuum pump (1770) through a valve. As the vacuum pump (1770), for example, a dry pump and a mechanical booster pump may be used.

[0396] As for the substrate heating chamber (1705), for example, a resistance heating element may be used for heating. Alternatively, heat conduction or heat radiation from a medium such as heated gas may be used as a heating mechanism. For example, RTA (rapid thermal annealing), such as GRTA (gas rapid thermal annealing) or LRTA (lamp rapid thermal annealing), may be used. LRTA is a method for heating an object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. In GRTA, heat treatment is performed using high-temperature gas. An inert gas is used as the gas.

[0397] Additionally, the substrate heating chamber (1705) is connected to a purifier (1781) via a mass flow controller (1780). Additionally, the mass flow controller (1780) and the purifier (1781) may be provided for each of multiple types of gases, but for ease of understanding, only one mass flow controller (1780) and one purifier (1781) are provided. As for the gas introduced into the substrate heating chamber (1705), a gas with a dew point of -80°C or lower, preferably -100°C or lower, may be used, for example, oxygen gas, nitrogen gas, and noble gases (for example, argon gas).

[0398] The return chamber (1704) includes a return robot (1763b). The return robot (1763b) includes a plurality of movable parts and an arm that holds a substrate, and can return a substrate to each chamber. Additionally, the return chamber (1704) is connected to a vacuum pump (1770) and a cryopump (1771) through a valve. By this structure, evacuation can be performed using the vacuum pump (1770) when the pressure inside the return chamber (2704) is in the range of atmospheric pressure to low vacuum or medium vacuum (0.1 Pa to several hundred Pa), and by switching the valve, the pressure inside the return chamber (1704) can be in the range of medium vacuum to high vacuum or ultra-high vacuum (0.1 Pa to 1×10⁻⁶). -7 When the range is Pa), exhaust can be performed using a cryopump (1771).

[0399] Alternatively, two or more cryopumps (1771) may be connected in parallel to the return chamber (1704). By having this structure, even if one of the cryopumps is undergoing regeneration, any of the other cryopumps can be used to perform evacuation. Furthermore, the aforementioned regeneration refers to a process of releasing molecules (or atoms) trapped in the cryopumps. Since the evacuation capacity of the cryopumps decreases when molecules (or atoms) are excessively trapped in the cryopumps, regeneration is performed periodically.

[0400] (B) of FIG. 24 is a cross-section of the sedimentation chamber (1706b), the return chamber (1704), and the load lock chamber (1703a).

[0401] Here, details regarding each deposition chamber are described with reference to FIG. 24 (B). Additionally, regarding the structure of each deposition chamber, the description of the sputtering apparatus (101) shown in FIG. 21 can be appropriately combined with the following description. The deposition chamber (1706b) shown in FIG. 24 (B) includes a target (100), a substrate stage (170), and a collimator (150) provided between the target and the substrate stage. Also, here, a substrate is provided on the substrate stage (170). Although not shown, the substrate stage (170) may include a substrate holding mechanism for holding the substrate, or a back-side heater for heating the substrate from the back side.

[0402] The deposition chamber (1706b) is connected to a mass flow meter (1780) through a gas heating device (1782), and the gas heating device (1782) is connected to a purifier (1781) through the mass flow meter (1780). By the gas heating device (1782), the deposition gas can be heated to a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. Additionally, the gas heating device (1782), the mass flow meter (1780), and the purifier (1781) may be provided for each of multiple types of gas, but for ease of understanding, only one gas heating device (1782), one mass flow meter (1780), and one purifier (1781) are provided. As for the deposition gas, it is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower.

[0403] Additionally, a parallel plate-type sputtering device or an ion beam sputtering device may be provided in the deposition chamber (1706b).

[0404] When a purifier is provided near the gas inlet, the length of the piping between the purifier (1781) and the sedimentation chamber (1706b) is set to 10m or less, preferably 5m or less, and more preferably 1m or less. By making the length of the piping 10m or less, 5m or less, or 1m or less, the effect of the discharged gas from the piping can be reduced accordingly. As the gas piping, a metal pipe with an interior covered with iron fluoride, aluminum oxide, or chromium oxide can be used. With the above-described piping, the amount of discharged gas containing impurities is reduced compared to, for example, SUS316L-EP piping, thereby reducing the intrusion of impurities into the sedimentation gas. In addition, a high-performance ultra-small metal gasket connection part (UPG connection part) can be used as the connection part of the piping. A structure in which the entire piping material is metal is desirable because it can reduce the effect of generated discharged gas or external leakage compared to a structure using resin, etc.

[0405] The deposition chamber (1706b) is connected to a turbo molecular pump (1772) and a vacuum pump (1770) through a valve. Additionally, the deposition chamber (1706b) preferably includes a cryo trap.

[0406] A cryo trap (1751) is a device capable of adsorbing molecules (or atoms) with a relatively high melting point, such as water. A turbo molecular pump (1772) can stably exhaust large molecules (or atoms) and has a low frequency of maintenance, which can increase productivity, but has a low exhaust capacity for hydrogen and water. Therefore, a cryo trap (1751) is connected to a deposition chamber (1706b) to increase the exhaust capacity for water, etc. The temperature of the cryo trap (1751) is set to 100K or less, preferably 80K or less. If the cryo trap (1751) includes multiple chillers, it is desirable to set the temperature of each chiller to a different temperature so that efficient exhaust is possible. For example, the temperature of the first stage chiller can be set to 100K or less, and the temperature of the second stage chiller can be set to 20K or less.

[0407] In addition, the exhaust method of the deposition chamber (1706b) is not limited to that described above, and may adopt a structure similar to the exhaust method described in the return chamber (1704) (an exhaust method using a cryopump and a vacuum pump). Of course, the exhaust method of the return chamber (1704) may have a structure similar to the exhaust method of the deposition chamber (1706b) (an exhaust method using a turbo molecular pump and a vacuum pump).

[0408] In addition, in each of the aforementioned return chamber (1704), substrate heating chamber (1705), and deposition chamber (1706b), it is preferable to set the back pressure (total pressure) and the partial pressure of each gas molecule (atom) as follows. In particular, since impurities may enter the film to be formed, care must be taken with the back pressure of the deposition chamber (1706b) and the partial pressure of each gas molecule (atom).

[0409] The back pressure (total pressure) in each of the chambers described above is 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 It is less than Pa. In each of the chambers described above, the mass-to-charge ratio ( m / z The partial pressure of a gas molecule (atom) with a value of 18 is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 It is less than Pa. In addition, the mass-to-charge ratio in each of the chambers described above ( m / z The partial pressure of a gas molecule (atom) with ) 28 is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 It is less than Pa. In addition, the mass-to-charge ratio in each of the chambers described above ( m / z The partial pressure of a gas molecule (atom) with ) 44 is 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa is less than or equal to

[0410] In addition, the total pressure and partial pressure inside the vacuum chamber can be measured using a mass spectrometer. For example, the Qulee CGM-051 (a quadrupole mass spectrometer manufactured by ULVAC, Inc., also known as Q-mass) can be used.

[0411] In addition, it is desirable that the above-described return chamber (1704), substrate heating chamber (1705), and deposition chamber (1706b) have a small amount of external or internal leakage.

[0412] For example, in each of the above-described return chamber (1704), substrate heating chamber (1705), and deposition chamber (1706b), the leakage rate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 It is less than / s. Mass-to-charge ratio ( m / z The leakage rate of a gas molecule (atom) with ) 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 It is less than / s. Mass-to-charge ratio ( m / z The leakage rate of a gas molecule (atom) with ) 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 It is less than / s. Mass-to-charge ratio ( m / z The leakage rate of a gas molecule (atom) with ) 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s is less than

[0413] In addition, the leakage rate can be obtained from the total pressure and partial pressure measured using the mass spectrometer above.

[0414] The leakage rate depends on external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system through minute holes or seal failures. Internal leakage is caused by leakage within the vacuum system through partitions, such as valves, or by gases released from internal components. To ensure the leakage rate is set below the aforementioned value, it is necessary to take measures against both external and internal leakage.

[0415] For example, the opening and closing portion of the sedimentation chamber (1706b) can be sealed with a metal gasket. It is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide for the metal gasket. The metal gasket can achieve a higher seal than an O-ring and reduce external leakage. In addition, by using a metal coated with a passive state such as iron fluoride, aluminum oxide, or chromium oxide, the release of gas containing impurities from the metal gasket is suppressed, thereby reducing internal leakage.

[0416] For the components of the deposition device (1700), aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits a small amount of gas containing impurities, may be used. Alternatively, for the components described above, an alloy containing iron, chromium, nickel, etc., coated with the aforementioned materials may be used. The alloy containing iron, chromium, nickel, etc. is hard, heat-resistant, and suitable for processing. Here, if the surface irregularities of the components are reduced by grinding or the like to reduce the surface area, the emission of gas can be reduced.

[0417] Alternatively, the member of the aforementioned deposition device (1700) may be coated with iron fluoride, aluminum oxide, or chromium oxide, etc.

[0418] It is preferable that the member of the deposition device (1700) be formed of metal as much as possible. For example, if a viewing window formed of quartz or the like is provided, it is preferable to thinly coat the surface of the viewing window with iron fluoride, aluminum oxide, or chromium oxide or the like to suppress the release of gas.

[0419] When adsorbents are present in the deposition chamber, they do not affect the pressure of the chamber because they are adsorbed onto the inner walls, etc.; however, when the interior of the deposition chamber is evacuated, the adsorbents cause gas release. Therefore, although there is no correlation between the leakage rate and the evacuation speed, it is important to use a pump with a high evacuation capacity to remove as much of the adsorbent present in the deposition chamber as possible and to evacuate it in advance. Additionally, baking may be performed in the deposition chamber to promote the removal of adsorbents. Baking can increase the removal rate of adsorbents by approximately tenfold. Baking can be performed at a temperature ranging from 100°C to 450°C. At this time, if an inert gas is introduced into the deposition chamber while removing adsorbents, the removal rate of substances such as water, which are difficult to remove by evacuation alone, can be further increased. Furthermore, if the inert gas is heated to a temperature substantially equal to the baking temperature of the deposition chamber, the removal rate of adsorbents can be further increased. Here, it is preferable to use a noble gas as the inert gas. Depending on the type of film being deposited, oxygen or the like may be used instead of an inert gas. For example, when depositing oxides, it may be preferable to use oxygen, which is the main component of the oxide.

[0420] Alternatively, it is preferable to perform a treatment to increase the pressure inside the sedimentation chamber using heated oxygen or heated inert gas, such as heated noble gas, and then exhaust the inside of the sedimentation chamber after a certain period. The heated gas can remove adsorbed substances inside the sedimentation chamber and reduce impurities present inside the sedimentation chamber. Furthermore, beneficial effects can be achieved by repeating this treatment 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen, etc., with a temperature of 40°C to 400°C, preferably 50°C to 200°C, into the sedimentation chamber, the pressure inside the sedimentation chamber can be maintained at 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, within a time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the inside of the sedimentation chamber is evacuated for a time range of 5 to 300 minutes, preferably 10 to 120 minutes.

[0421] The removal rate of adsorbates can also be further increased by dummy deposition. Here, dummy deposition refers to deposition onto a dummy substrate by methods such as sputtering, in which a film is deposited on a dummy substrate and the inner wall of a deposition chamber to trap impurities within the chamber and adsorbates on the inner wall of the chamber within the film. It is preferable to use a substrate with low gas emission as the dummy substrate. By performing dummy deposition, the concentration of impurities within the film to be deposited later can be reduced. Additionally, dummy deposition may be performed simultaneously with the baking of the deposition chamber.

[0422] Next, details regarding the return chamber (1704) and load lock chamber (1703a) shown in (B) of FIG. 24, and the air-side substrate return chamber (1702) and air-side substrate supply chamber (1701) shown in (C) of FIG. 24 will be described. Additionally, FIG. 24 (C) is a cross-section of the air-side substrate return chamber (1702) and the air-side substrate supply chamber (1701).

[0423] For the return chamber (1704) shown in (B) of FIG. 24, reference may be made to the description of the return chamber (1704) shown in (A) of FIG. 24.

[0424] The load lock chamber (1703a) includes a substrate transfer stage (1752). When the pressure in the load lock chamber (1703a) rises from reduced pressure to atmospheric pressure, the substrate transfer stage (1752) receives a substrate from a transfer robot (1763a) provided in the atmospheric side substrate transfer chamber (1702). Then, the load lock chamber (1703a) is evacuated to a vacuum to reduce the pressure therein, and then a transfer robot (1763b) provided in the transfer chamber (1704) receives a substrate from the substrate transfer stage (1752).

[0425] Additionally, the load lock chamber (1703a) is connected to the vacuum pump (1770) and the cryo pump (1771) through a valve. For the connection method of the exhaust system, such as the vacuum pump (1770) and the cryo pump (1771), one can refer to the description of the connection method of the return chamber (1704), and the description thereof is omitted here. Also, the unload lock chamber (1703b) shown in FIG. 23 may have a structure similar to that of the load lock chamber (1703a).

[0426] The atmospheric side substrate return chamber (1702) includes a return robot (1763a). The return robot (1763a) can return a substrate from the cassette port (1761) to the load lock chamber (1703a) or from the load lock chamber (1703a) to the cassette port (1761). Additionally, a mechanism for suppressing the intrusion of dust or particles, such as a HEPA (high efficiency particulate air) filter, may be provided above the atmospheric side substrate return chamber (1702) and the atmospheric side substrate supply chamber (1701).

[0427] The standby side substrate supply chamber (1701) includes a plurality of cassette ports (1761). The cassette ports (1761) can accommodate a plurality of substrates.

[0428] The surface temperature of the target is set to 100°C or lower, preferably 50°C or lower, and more preferably room temperature (typically 25°C). In sputtering apparatus for large substrates, large targets are often used. However, it is difficult to form a target for a large substrate without junctions. In practice, a large shape is obtained by arranging multiple targets so that the gap between them is as small as possible, but very small gaps inevitably occur. If the surface temperature of the target rises, zinc, etc., volatilizes from these very small gaps, and the gaps may gradually widen. If the gaps widen, the metal of the backing plate or the metal used for adhesion may be sputtered, which can lead to an increase in the impurity concentration. Therefore, it is desirable for the target to be sufficiently cooled.

[0429] Specifically, a metal with high conductivity and high heat dissipation (specifically copper) is used for the backing plate. By flowing a sufficient amount of cooling water through the channels formed in the backing plate, the target can be efficiently cooled.

[0430] In addition, when the target contains zinc, plasma damage is mitigated by deposition in an oxygen gas atmosphere, so an oxide semiconductor in which zinc is difficult to volatilize can be obtained.

[0431] By the aforementioned deposition device, it is possible to prevent impurities from entering the film to be formed.

[0432] (Embodiment 10)

[0433] <Production Device>

[0434] A manufacturing apparatus for performing high-density plasma treatment according to one embodiment of the present invention is described below.

[0435] First, the structure of a manufacturing device capable of preventing almost all impurities from entering during the manufacturing of semiconductor devices, etc., will be explained with reference to FIGS. 25, 26, and 27.

[0436] FIG. 25 is a top view schematically illustrating a single-wafer multi-chamber manufacturing device (2700). The manufacturing device (2700) includes an atmospheric side substrate supply chamber (2701) comprising a cassette port (2761) for receiving a substrate and an alignment port (2762) for performing alignment of the substrate, an atmospheric side substrate return chamber (2702) for returning a substrate from the atmospheric side substrate supply chamber (2701), a load lock chamber (2703a) for receiving a substrate and changing the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber (2703b) for releasing a substrate and changing the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a return chamber (2704) for returning a substrate in a vacuum, and chambers (2706a, 2706b, 2706c, and 2706d).

[0437] The standby side substrate return chamber (2702) is connected to the load lock chamber (2703a) and the unload lock chamber (2703b), the load lock chamber (2703a) and the unload lock chamber (2703b) are connected to the return chamber (2704), and the return chamber (2704) is connected to the chambers (2706a, 2706b, 2706c, and 2706d).

[0438] Additionally, a gate valve (GV) is provided at the connection between the chambers, so that each chamber, excluding the atmospheric side substrate supply chamber (2701) and the atmospheric side substrate return chamber (2702), can be independently maintained in a vacuum state. Furthermore, a return robot (2763a) is provided in the atmospheric side substrate return chamber (2702), and a return robot (2763b) is provided in the return chamber (2704). Substrates can be returned within the manufacturing device (2700) by the return robot (2763a) and the return robot (2763b).

[0439] In the return chamber (2704) and each chamber (2706a to 2706d), the back pressure (total pressure) is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 It is less than or equal to Pa. In the return chamber (2704) and each chamber (2706a to 2706d), the mass-to-charge ratio ( m / z The partial pressure of a gas molecule (atom) with ) = 18 is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 It is less than or equal to Pa. Also, in the return chamber (2704) and each chamber (2706a to 2706d), the mass-to-charge ratio ( m / z The partial pressure of a gas molecule (atom) with ) 28 is, for example, 3×10 -5 Pa or less, preferably 1×10 -5Pa or less, more preferably 3×10 -6 It is less than or equal to Pa. Also, in the return chamber (2704) and each chamber (2706a to 2706d), the mass-to-charge ratio ( m / z The partial pressure of a gas molecule (atom) with ) ) 44 is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa is less than or equal to

[0440] Additionally, the total pressure and partial pressure within the return chamber (2704) and each chamber (2706a to 2706d) can be measured using a mass spectrometer. For example, a Qulee CGM-051 (a quadrupole mass spectrometer manufactured by ULVAC, Inc., also known as Q-mass) can be used.

[0441] In addition, it is desirable that the amount of external or internal leakage in the return chamber (2704) and each chamber (2706a to 2706d) is small. For example, in the return chamber (2704) and each chamber (2706a to 2706d), the leakage rate is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 It is less than / s. For example, the mass-to-charge ratio ( m / z The leakage rate of a gas molecule (atom) with ) 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 It is less than / s. For example, the mass-to-charge ratio ( m / z The leakage rate of a gas molecule (atom) with ) 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 It is less than / s. For example, the mass-to-charge ratio (m / z The leakage rate of a gas molecule (atom) with ) 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s is less than

[0442] In addition, the leakage rate can be obtained from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leakage rate depends on external leakage and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system through minute holes or seal failures. Internal leakage is caused by leakage within the vacuum system through partitions, such as valves, or by gas released from internal components. To ensure that the leakage rate is set to be below the aforementioned value, it is necessary to take measures regarding both external and internal leakage.

[0443] For example, the opening and closing portions of the return chamber (2704) and chambers (2706a to 2706d) can be sealed with a metal gasket. It is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide for the metal gasket. The metal gasket can achieve a higher seal than an O-ring and reduce external leakage. In addition, by using a metal coated with a passive state such as iron fluoride, aluminum oxide, or chromium oxide, the release of gas containing impurities from the metal gasket is suppressed, thereby reducing internal leakage.

[0444] For the components of the manufacturing device (2700), aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits a small amount of gas containing impurities, may be used. Alternatively, an alloy containing iron, chromium, or nickel, etc., coated with the above-mentioned materials may be used. An alloy containing iron, chromium, or nickel, etc., is hard, heat-resistant, and suitable for processing. Here, if the surface irregularities of the component are reduced by grinding or the like to reduce the surface area, the emission of gas can be reduced.

[0445] Alternatively, the member of the above-described manufacturing device (2700) may be coated with iron fluoride, aluminum oxide, or chromium oxide, etc.

[0446] It is preferable that the components of the manufacturing device (2700) be formed using only metal if possible. For example, if an observation window formed of quartz or the like is provided, it is preferable to thinly coat the surface of the observation window with iron fluoride, aluminum oxide, or chromium oxide or the like to suppress the release of gas.

[0447] When adsorbents are present in the return chamber (2704) and each chamber (2706a to 2706d), the adsorbents do not affect the pressure of the return chamber (2704) and each chamber (2706a to 2706d) because they are adsorbed to the inner walls, etc., but when the inside of the return chamber (2704) and each chamber (2706a to 2706d) is exhausted, the adsorbents cause gas release. Therefore, although there is no correlation between the leakage rate and the exhaust speed, it is important to use a pump with high exhaust capacity to remove as much of the adsorbents present in the return chamber (2704) and each chamber (2706a to 2706d) as possible and to exhaust in advance. In addition, baking may be performed in the return chamber (2704) and each chamber (2706a to 2706d) to promote the removal of adsorbents. By baking, the removal rate of adsorbents can be increased by approximately 10 times. Baking can be performed at a temperature between 100°C and 450°C. At this time, if adsorbents are removed while introducing an inert gas into the return chamber (2704) and each chamber (2706a to 2706d), the removal rate of substances such as water, which are difficult to remove by exhaust alone, can be further increased. Additionally, if the introduced inert gas is heated to a temperature substantially equal to the baking temperature, the removal rate of adsorbents can be further increased. Here, it is preferable to use a noble gas as the inert gas.

[0448] Alternatively, it is preferable to perform a treatment to increase the pressure within the return chamber (2704) and each chamber (2706a to 2706d) by introducing heated oxygen or heated inert gas, and then exhaust the interior of the return chamber (2704) and each chamber (2706a to 2706d) after a certain period. By introducing heated gas, adsorbed substances within the return chamber (2704) and each chamber (2706a to 2706d) can be removed, and impurities present within the return chamber (2704) and each chamber (2706a to 2706d) can be reduced. Furthermore, beneficial effects can be achieved by repeating this treatment 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen, etc., with a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower, into the return chamber (2704) and each chamber (2706a to 2706d), the pressure inside the deposition chamber can be maintained at 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher and 1 kPa or lower, more preferably 5 Pa or higher and 100 Pa or lower, within a time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the interior of the return chamber (2704) and each chamber (2706a to 2706d) is exhausted within a time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0449] Next, the chambers (2706b and 2706c) will be described with reference to the cross-sectional schematic diagram of FIG. 26.

[0450] Chambers (2706b and 2706c) are chambers capable of performing high-density plasma treatment on an object, for example. Since chambers (2706b and 2706c) have a common structure except for the atmosphere used for high-density plasma treatment, they will be described collectively below.

[0451] Chambers (2706b and 2706c) each include a slot antenna plate (2808), a dielectric plate (2809), a substrate stage (2812), and an exhaust port (2819). A gas source (2801), a valve (2802), a high-frequency generator (2803), a waveguide (2804), a mode converter (2805), a gas pipe (2806), a waveguide (2807), a matching box (2815), a high-frequency power supply (2816), a vacuum pump (2817), and a valve (2818) are provided outside the chambers (2706b and 2706c).

[0452] A high-frequency generator (2803) is connected to a mode converter (2805) through a waveguide (2804). The mode converter (2805) is connected to a slot antenna plate (2808) through a waveguide (2807). The slot antenna plate (2808) is positioned in contact with a dielectric plate (2809). Additionally, a gas source (2801) is connected to the mode converter (2805) through a valve (2802). Gas is returned to chambers (2706b and 2706c) through a gas pipe (2806) passing through the mode converter (2805), the waveguide (2807), and the dielectric plate (2809). A vacuum pump (2817) has the function of exhausting gas, etc. from chambers (2706b and 2706c) through a valve (2818) and an exhaust port (2819). The high-frequency power supply (2816) is connected to the substrate stage (2812) through the matching box (2815).

[0453] The substrate stage (2812) has the function of holding the substrate (2811). For example, the substrate stage (2812) has the function of holding the substrate (2811) by electrostatic or mechanical strength. Additionally, the substrate stage (2812) has the function of an electrode that receives power from a high-frequency power source (2816). Since the substrate stage (2812) includes a heating mechanism (2813) inside, it has the function of heating the substrate (2811).

[0454] As for the vacuum pump (2817), for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump may be used. In addition to the vacuum pump (2817), a cryopump may also be used. It is particularly desirable to use a combination of a cryopump and a cryo trap so that water can be effectively exhausted.

[0455] For example, the heating device (2813) may be a heating device that uses a resistance heating element or the like for heating. Alternatively, a heating device that utilizes heat conduction or heat radiation from a medium such as heated gas for heating may be used. For example, an RTA such as GRTA or LRTA may be used. In GRTA, the heating treatment is performed using a high-temperature gas. An inert gas is used as the gas.

[0456] The gas supply source (2801) may be connected to a purifier through a mass flow meter. As for the gas, it is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, or a noble gas (e.g., argon gas) may be used.

[0457] As the dielectric plate (2809), for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used. A protective layer may also be formed on the surface of the dielectric plate (2809). As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide may be used. The dielectric plate (2809) is particularly exposed to the high-density region of the high-density plasma (2810) described later. Therefore, the protective layer can reduce damage, and consequently, prevent particle increase during processing.

[0458] The high-frequency generator (2803) has the function of generating microwaves with a frequency of, for example, 0.3 GHz or higher and 3.0 GHz or lower, 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower. The microwaves generated by the high-frequency generator (2803) are propagated to a mode converter (2805) through a waveguide (2804). The mode converter (2805) converts the microwaves propagated in TE mode into microwaves in TEM mode. Then, the microwaves are propagated to a slot antenna plate (2808) through a waveguide (2807). A plurality of slot holes are provided in the slot antenna plate (2808), and the microwaves are propagated through the slot holes and the dielectric plate (2809). Then, an electric field is generated below the dielectric plate (2809), and a high-density plasma (2810) can be generated. The high-density plasma (2810) contains ions and radicals according to the type of gas supplied from the gas source (2801). For example, it contains oxygen radicals or nitrogen radicals, etc.

[0459] At this time, the film, etc. on the substrate (2811) can be modified by ions and radicals generated in the high-density plasma (2810). In addition, it is preferable to apply a bias to the substrate (2811) using a high-frequency power supply (2816). As for the high-frequency power supply (2816), for example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz or 27.12 MHz can be used. By applying a bias to the substrate, the ions in the high-density plasma (2810) can be efficiently delivered to the deep parts of the openings in the film, etc. on the substrate (2811).

[0460] For example, in chamber (2706b), oxygen radical treatment using high-density plasma (2810) can be performed by introducing oxygen from gas source (2801). In chamber (2706c), nitrogen radical treatment using high-density plasma (2810) can be performed by introducing nitrogen from gas source (2801).

[0461] Next, the chambers (2706a and 2706d) will be described with reference to the cross-sectional schematic diagram of FIG. 27.

[0462] Chambers (2706a and 2706d) are chambers capable of irradiating an object with electromagnetic waves, for example. Since chambers (2706a and 2706d) have a common structure except for the type of electromagnetic waves, they will be described collectively below.

[0463] Chambers (2706a and 2706d) each include one or more lamps (2820), a substrate stage (2825), a gas inlet (2823), and an exhaust port (2830). Outside the chambers (2706a and 2706d), a gas source (2821), a valve (2822), a vacuum pump (2828), and a valve (2829) are provided.

[0464] A gas supply source (2821) is connected to a gas inlet (2823) through a valve (2822). A vacuum pump (2828) is connected to an exhaust port (2830) through a valve (2829). A lamp (2820) is provided facing the substrate stage (2825). The substrate stage (2825) has the function of holding the substrate (2824). Since the substrate stage (2825) contains a heating mechanism (2826) inside, it has the function of heating the substrate (2824).

[0465] As the lamp (2820), a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used, for example. For example, a light source having the function of emitting electromagnetic waves having a peak in a wavelength range of 10 nm or more and 2500 nm or less, 500 nm or more and 2000 nm or less, or 40 nm or more and 340 nm or less may be used.

[0466] For example, as the lamp (2820), a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp can be used.

[0467] For example, some or all of the electromagnetic waves emitted from the lamp (2820) can be absorbed by the substrate (2824), thereby modifying the film, etc., on the substrate (2824). For example, defects can be created or reduced, or impurities can be removed. When the lamp (2820) emits electromagnetic waves while heating the substrate (2824), the creation or reduction of defects, or the removal of impurities, can be performed efficiently.

[0468] Alternatively, for example, the substrate (2824) may be heated by heating the substrate stage (2825) by electromagnetic waves emitted from the lamp (2820). In this case, the heating mechanism (2826) inside the substrate stage (2825) may be omitted.

[0469] For the vacuum pump (2828), refer to the description of the vacuum pump (2817). For the heating device (2826), refer to the description of the heating device (2813). For the gas supply source (2821), refer to the description of the gas supply source (2801).

[0470] With the above-described manufacturing device, the membrane can be modified while suppressing impurities from entering the object.

[0471] The structure and method described in this embodiment may be implemented by appropriately combining any of the other structures and methods described in other embodiments.

[0472] (Embodiment 11)

[0473] Structure of Oxide Semiconductors

[0474] The structure of oxide semiconductors is explained below.

[0475] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), amorphous-like oxide semiconductor (a-like OS), and amorphous oxide semiconductor.

[0476] From another perspective, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0477] Amorphous structures are generally known to be defined as metastable, unbound, isotropic, and non-uniform. In other words, amorphous structures possess flexible bonding angles and short-range order, but not long-range order.

[0478] This implies that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Furthermore, a non-isotropic oxide semiconductor (e.g., an oxide semiconductor with a periodic structure in minute regions) cannot be regarded as a completely amorphous oxide semiconductor. Additionally, while a-like OS possesses a periodic structure in minute regions, it simultaneously has voids and an unstable structure. For these reasons, a-like OS exhibits physical properties similar to those of amorphous oxide semiconductors.

[0479] <caac-os>

[0480] First, I will explain CAAC-OS.

[0481] CAAC-OS is one of the oxide semiconductors having multiple c-axis oriented crystal regions (also called pellets).

[0482] Multiple pellets can be observed in the combined analysis image of the bright-field image and diffraction pattern of CAAC-OS obtained using a transmission electron microscope (TEM) (also referred to as a high-resolution TEM image). However, in high-resolution TEM images, the boundaries of the pellets, i.e., grain boundaries, are not clearly observed. Therefore, it is difficult for a decrease in electron mobility due to grain boundaries to occur in CAAC-OS.

[0483] The CAAC-OS observed by TEM is described below. Figure 28 (A) shows a high-resolution TEM image of a cross-section of the CAAC-OS observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained by a spherical aberration corrector function. The high-resolution TEM image obtained by the spherical aberration corrector function is specifically referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained, for example, by the atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0484] Figure 28 (B) is a Cs-corrected high-resolution TEM image of the region (1) in Figure 28 (A). Figure 28 (B) shows that metal atoms are arranged in layers in the pellet. Each metal atomic layer has a shape that reflects the irregularities of the surface on which the CAAC-OS is formed (hereinafter referred to as the formation surface) or the upper surface of the CAAC-OS, and is arranged parallel to the formation surface or the upper surface of the CAAC-OS.

[0485] As shown in Fig. 28 (B), CAAC-OS has a characteristic atomic arrangement. This characteristic atomic arrangement is indicated by auxiliary lines in Fig. 28 (C). Figs. 28 (B) and (C) demonstrate that the pellet size is greater than 1 nm or greater than 3 nm, and the gap size due to the slope of the pellets is about 0.8 nm. Therefore, the pellets may be referred to as nanocrystals (nc). Additionally, CAAC-OS may be referred to as an oxide semiconductor containing c-axis aligned nanocrystals (CANC).

[0486] Here, according to the Cs corrected high-resolution TEM image, the schematic arrangement of the CAAC-OS pellets (5100) on the substrate (5120) is shown as a structure resembling stacked bricks or blocks (see (D) of FIG. 28). As observed in (C) of FIG. 28, the tilted portion of the pellets corresponds to the area (5161) shown in (D) of FIG. 28.

[0487] Figure 29 (A) shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. Figures 29 (B), (C), and (D) are Cs-corrected high-resolution TEM images magnified from regions (1), (2), and (3) in Figure 29 (A), respectively. Figures 29 (B), (C), and (D) show that metal atoms in the pellets are arranged in triangular, square, or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different pellets.

[0488] Next, the CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS containing an InGaZnO4 crystal is analyzed by the out-of-plane method, the diffraction angle (2) as shown in (A) of FIG. 30 θ A peak appears when the angle is around 31°. This peak originates from the (009) plane of the InGaZnO4 crystal, indicating that the CAAC-OS crystal has a c-axis orientation and that the c-axis is oriented in a direction substantially perpendicular to the formation plane or the top plane of the CAAC-OS.

[0489] In addition, in the structural analysis of CAAC-OS by the out-of-plane method, 2 θ In addition to the peak when θ is near 31°, 2 θ Another peak may appear when θ is near 36°. 2 θ The peak when θ is near 36° indicates that a portion of the CAAC-OS contains crystals that do not have c-axis orientation. In the CAAC-OS analyzed by the out-of-plane method, 2 θ It is desirable for a peak to appear when θ is near 31°, and 2 θ It is desirable that no peak appears when the angle is around 36°.

[0490] Meanwhile, in the structural analysis of CAAC-OS by the in-plane method in which an X-ray beam is incident on the sample in a direction substantially perpendicular to the c-axis, 2 θ A peak appears when θ is near 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In the case of CAAC-OS, 2 θ Fix it near 56° and the normal vector of the sample surface is the axis ( φ Use as an axis to rotate the sample for analysis ( φ When a scan is performed, a peak is not clearly observed as shown in (B) of Fig. 30. On the other hand, in the case of the InGaZnO4 single-crystal oxide semiconductor, 2 θ Fix it near 56° and φ When a scan is performed, six peaks originating from crystal planes equivalent to the (110) plane are observed, as shown in (C) of Fig. 30. Thus, structural analysis using XRD shows that the a-axis and b-axis directions in CAAC-OS are irregularly oriented.

[0491] Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS containing an InGaZnO4 crystal in a direction parallel to the sample surface, the diffraction pattern shown in (A) of FIG. 31 (also called a limited-field transmission electron diffraction pattern) can be obtained. This diffraction pattern includes spots originating from the (009) plane of the InGaZnO4 crystal. Thus, electron diffraction also indicates that the pellet contained in the CAAC-OS has a c-axis orientation and that the c-axis is oriented in a direction substantially perpendicular to the formation plane or top plane of the CAAC-OS. Meanwhile, FIG. 31 (B) shows the diffraction pattern obtained by incidenting an electron beam with a probe diameter of 300 nm on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 31 (B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also indicates that the a-axis and b-axis of the pellet included in the CAAC-OS do not have a regular orientation. The first ring in (B) of FIG. 31 is thought to originate from the (010) plane and (100) plane of the InGaZnO4 crystal, etc. The second ring in (B) of FIG. 31 is thought to originate from the (110) plane, etc.

[0492] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. The intrusion of impurities or the formation of defects can degrade the crystallinity of oxide semiconductors. This implies that CAAC-OS has low amounts of impurities and defects (e.g., oxygen vacancies).

[0493] Furthermore, impurities refer to elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or transition metal elements. For example, elements with a higher bonding affinity for oxygen than the metal elements contained in the oxide semiconductor (specifically, silicon, etc.) extract oxygen from the oxide semiconductor; as a result, the atomic arrangement of the oxide semiconductor becomes disordered, and its crystallinity deteriorates. Heavy metals such as iron or nickel, argon, or carbon dioxide, among others, have large atomic radii (or molecular radii), which causes the atomic arrangement of the oxide semiconductor to become disordered and lowers its crystallinity.

[0494] The properties of oxide semiconductors containing impurities or defects can be altered by light or heat. For example, impurities contained in oxide semiconductors can act as carrier traps or carrier sources. Additionally, oxygen vacancies in oxide semiconductors act as carrier traps, or act as carrier sources when hydrogen is captured.

[0495] CAAC-OS with low amounts of impurities and oxygen vacancies has a low carrier density (specifically, 8×10⁻⁶). 11 / cm 3 Less than, preferably 1×10 11 / cm 3 Less than, more preferably 1×10 10 / cm 3 Less than and 1×10 -9 / cm 3 It is an oxide semiconductor. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect state density. Therefore, CAAC-OS can be described as an oxide semiconductor with stable characteristics.

[0496] <nc-os>

[0497] Next, nc-OS will be explained.

[0498] nc-OS has regions where crystal regions are observed in high-resolution TEM images, and regions where crystal regions are not clearly observed. In most cases, the size of the crystal regions included in nc-OS is 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. Additionally, oxide semiconductors containing crystal regions larger than 10 nm and smaller than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. In high-resolution TEM images of nc-OS, for example, grain boundaries may not be clearly observed. Furthermore, the origin of the nanocrystals may be the same as the pellets in CAAC-OS. Therefore, in the following description, the crystal regions of nc-OS can be referred to as pellets.

[0499] In nc-OS, microscopic regions (e.g., regions with a size between 1 nm and 10 nm, particularly regions between 1 nm and 3 nm) exhibit a periodic atomic arrangement. In nc-OS, there is no regularity in crystal orientation between different pellets. Consequently, the orientation of the entire film is not aligned. Therefore, depending on the analysis method, nc-OS cannot be distinguished from α-like OS or amorphous oxide semiconductors. For example, when nc-OS is analyzed by the out-of-plane method using an X-ray beam with a diameter larger than the pellet size, peaks indicating crystal planes do not appear. Furthermore, when electron diffraction is performed on nc-OS using an electron beam with a probe diameter larger than the pellet size (e.g., 50 nm or more), diffraction patterns such as halo patterns are observed. On the other hand, when an electron beam with a probe diameter close to or smaller than the pellet size is applied, spots appear in the nanobeam electron diffraction pattern of nc-OS. In addition, there are cases where high-intensity regions of a circular pattern appear in the nanobeam electron diffraction pattern of nc-OS. There are also cases where multiple spots appear in the circular region in the nanobeam electron diffraction pattern of nc-OS.

[0500] As described above, since there is no regularity of crystal orientation among the pellets (nano crystals), nc-OS may be referred to as an oxide semiconductor containing RANC (randomly aligned nanocrystals) or an oxide semiconductor containing NANC (non-aligned nanocrystals).

[0501] nc-OS is an oxide semiconductor with higher regularity compared to amorphous oxide semiconductors. Therefore, nc-OS tends to have a lower defect state density than a-like OS and amorphous oxide semiconductors. Additionally, there is no regularity in crystal orientation between different pellets in nc-OS. Consequently, nc-OS has a higher defect state density than CAAC-OS.

[0502] <a-like OS>

[0503] a-like OS has a structure intermediate between nc-OS and amorphous oxide semiconductors.

[0504] Voids can be observed in high-resolution TEM images of a-like OS. In addition, in high-resolution TEM images, there are regions where crystallization is clearly observed and regions where crystallization is not observed.

[0505] a-like OS has an unstable structure because it contains voids. To prove that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are explained below.

[0506] a-like OS (referred to as Sample A), nc-OS (referred to as Sample B), and CAAC-OS (referred to as Sample C) are prepared as samples to be subjected to electron irradiation. Each sample is an In-Ga-Zn oxide.

[0507] First, high-resolution cross-sectional TEM images of each sample are obtained. The high-resolution cross-sectional TEM images show that all samples have crystalline regions.

[0508] In addition, which part is considered as the crystal region is determined as follows. It is known that the unit cell of an InGaZnO4 crystal has a structure in which 9 layers, including 3 In-O layers and 6 Ga-Zn-O layers, are stacked in the c-axis direction. The distance between adjacent layers is the interlattice distance of the (009) plane ( d It is equivalent to (also called the value). The value is calculated to be 0.29 nm from crystal structure analysis. Therefore, the region where the interlattice distance between lattice fringes is 0.28 nm or greater and 0.30 nm or less is considered the crystalline region of InGaZnO4. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0509] FIG. 32 shows the change in the average size of the crystal region (points 22 to 45) of each sample. In addition, the size of the crystal region corresponds to the length of the lattice stripe. FIG. 32 shows that the size of the crystal region in an a-like OS increases with increasing cumulative electron irradiation dose. Specifically, as shown in (1) in FIG. 32, a crystal region (also called an initial nucleus) of about 1.2 nm at the start of TEM observation, when the cumulative electron irradiation dose is 4.2 × 10⁻⁶ 8 e - / nm 2 It grows to a size of approximately 2.6 nm at that time. Meanwhile, the size of the crystal portion of nc-OS and CAAC-OS is when the cumulative electron irradiation dose from the start of electron irradiation is 4.2 × 10⁻⁶ 8 e - / nm 2 It shows almost no change until it becomes. Specifically, as shown in (2) and (3) in FIG. 32, the average crystal size of nc-OS and CAAC-OS is about 1.4 nm and about 2.1 nm, respectively, regardless of the cumulative electron irradiation amount.

[0510] As such, the growth of crystal regions in a-like OS is induced by electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of crystal regions is hardly induced by electron irradiation. Therefore, a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0511] a-like OS has a lower density than nc-OS and CAAC-OS because it contains voids. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single-crystal oxide semiconductor with the same composition. The densities of nc-OS and CAAC-OS, respectively, are 92.3% or more and less than 100% of the density of a single-crystal oxide semiconductor with the same composition. Furthermore, oxide semiconductors having a density of less than 78% of the density of a single-crystal oxide semiconductor are difficult to deposit.

[0512] For example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a single-crystal InGaZnO4 having a rhombohedral structure is 6.357 g / cm³ 3 Therefore, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of the a-like OS is 5.0 g / cm³. 3 Above 5.9 g / cm² 3 It is less than. For example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS, respectively, are 5.9 g / cm³. 3 Above 6.3g / cm² 3 It is less than.

[0513] Furthermore, there is a possibility that an oxide semiconductor having a specific composition may not exist in a single-crystal structure. In such cases, by combining single-crystal oxide semiconductors of different compositions in appropriate proportions, a density equivalent to that of a single-crystal oxide semiconductor having a desired composition can be calculated. The density of a single-crystal oxide semiconductor having a desired composition can be calculated using a weighted average based on the combination ratio of single-crystal oxide semiconductors of different compositions. Additionally, to calculate the density, it is desirable to use as few types of single-crystal oxide semiconductors as possible.

[0514] As described above, oxide semiconductors have various structures and various properties. In addition, the oxide semiconductor may be a stack comprising two or more of, for example, amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0515] (Embodiment 12)

[0516] In this embodiment, an example of a circuit of a semiconductor device including a transistor, etc., according to one embodiment of the present invention will be described.

[0517] <CMOS 인버터>

[0518] The circuit diagram of FIG. 33 (A) shows the configuration of a so-called CMOS inverter in which a p-channel transistor (2200) and an n-channel transistor (2100) are connected in series with each other and their gates are connected to each other.

[0519] Structure of Semiconductor Devices 1

[0520] FIG. 34 is a cross-sectional view of the semiconductor device of FIG. 33 (A). The semiconductor device shown in FIG. 34 includes a transistor (2200) and a transistor (2100). The transistor (2100) is placed on top of the transistor (2200). Any of the transistors described in the above embodiment may be used as the transistor (2100). Accordingly, the description of the transistor described above may be appropriately referenced with respect to the transistor (2100).

[0521] The transistor (2200) shown in FIG. 34 is a transistor using a semiconductor substrate (450). The transistor (2200) includes a region (472a) within the semiconductor substrate (450), a region (472b) within the semiconductor substrate (450), an insulator (462), and a conductor (454).

[0522] In the transistor (2200), regions (472a and 472b) function as source and drain regions. The insulator (462) functions as a gate insulator. The conductor (454) functions as a gate electrode. Thus, the resistance of the channel-forming region can be controlled by the potential applied to the conductor (454). In other words, the conduction or non-conduction between region (472a) and region (472b) can be controlled by the potential applied to the conductor (454).

[0523] For the semiconductor substrate (450), a single-material semiconductor substrate formed using, for example, silicon or germanium, or a semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. It is preferable to use a single-crystal silicon substrate as the semiconductor substrate (450).

[0524] For the semiconductor substrate (450), a semiconductor substrate containing impurities that impart an n-type conductivity type is used. However, a semiconductor substrate containing impurities that impart a p-type conductivity type may also be used as the semiconductor substrate (450). In this case, a well containing impurities that impart an n-type conductivity type may be provided in the region where the transistor (2200) is formed. Alternatively, the semiconductor substrate (450) may be an i-type semiconductor substrate.

[0525] It is preferable that the upper surface of the semiconductor substrate (450) has a (110) surface. By doing so, the on-state characteristics of the transistor (2200) can be improved.

[0526] Regions (472a and 472b) are regions containing impurities that impart a p-type conductivity type. Thus, the transistor (2200) has the structure of a p-channel transistor.

[0527] Additionally, the transistor (2200) is separated from adjacent transistors by a region (460), etc. The region (460) is an insulating region.

[0528] The semiconductor device illustrated in FIG. 34 includes an insulator (464), an insulator (466), an insulator (468), a conductor (480a), a conductor (480b), a conductor (480c), a conductor (478a), a conductor (478b), a conductor (478c), a conductor (476a), a conductor (476b), a conductor (474a), a conductor (474b), a conductor (474c), a conductor (496a), a conductor (496b), a conductor (496c), a conductor (496d), a conductor (498a), a conductor (498b), a conductor (498c), an insulator (489), an insulator (490), an insulator (492), an insulator (493), an insulator (494), and an insulator (495).

[0529] An insulator (464) is placed over the transistor (2200). An insulator (466) is placed over the insulator (464). An insulator (468) is placed over the insulator (466). An insulator (489) is placed over the insulator (468). The transistor (2100) is placed over the insulator (489). An insulator (493) is placed over the transistor (2100). An insulator (494) is placed over the insulator (493).

[0530] The insulator (464) includes an opening reaching region (472a), an opening reaching region (472b), and an opening reaching conductor (454). Conductors (480a), conductor (480b), and conductor (480c) are embedded in the openings.

[0531] The insulator (466) includes an opening reaching a conductor (480a), an opening reaching a conductor (480b), and an opening reaching a conductor (480c). Conductors (478a), conductor (478b), and conductor (478c) are embedded in the openings.

[0532] The insulator (468) includes an opening reaching the conductor (478b) and an opening reaching the conductor (478c). The conductors (476a) and (476b) are embedded in the openings.

[0533] The insulator (489) includes an opening that overlaps with the channel forming region of the transistor (2100), an opening that reaches a conductor (476a), and an opening that reaches a conductor (476b). Conductors (474a), conductor (474b), and conductor (474c) are embedded in the openings.

[0534] The conductor (474a) may function as the gate electrode of the transistor (2100). For example, electrical characteristics such as the threshold voltage of the transistor (2100) may be controlled by applying a predetermined potential to the conductor (474a). For example, the conductor (474a) may be electrically connected to a conductor (504) that functions as the gate electrode of the transistor (2100). In this case, the on-state current of the transistor (2100) can be increased. In addition, since the punch-through phenomenon can be suppressed, the electrical characteristics in the saturation region of the transistor (2100) can be stabilized. Also, since the conductor (474a) corresponds to the conductor (413) in the above-described embodiment, the details of the conductor (474a) may be referred to in the description of the conductor (413).

[0535] The insulator (490) includes an opening that reaches the conductor (474b). Additionally, since the insulator (490) corresponds to the insulator (402) in the above-described embodiment, the details of the insulator (490) may be referenced in the description of the insulator (402).

[0536] The insulator (495) includes an opening reaching a conductor (474b) through a conductor (507b) which is one of the source and drain of the transistor (2100), an opening reaching a conductor (507a) which is the other of the source and drain of the transistor (2100), an opening reaching a conductor (504) which is the gate electrode of the transistor (2100), and an opening reaching a conductor (474c). Additionally, since the insulator (495) corresponds to the insulator (410) in the above-described embodiment, the description of the insulator (410) may be referenced for details of the insulator (495).

[0537] The insulator (493) includes an opening reaching a conductor (474b) through a conductor (507b) which is one of the source and drain of the transistor (2100), an opening reaching a conductor (507a) which is the other of the source and drain of the transistor (2100), an opening reaching a conductor (504) which is the gate electrode of the transistor (2100), and an opening reaching a conductor (474c). Conductors (496a), conductor (496b), conductor (496c), and conductor (496d) are embedded in the openings. Additionally, an opening provided to any component, such as the transistor (2100), may be positioned between openings provided to other components.

[0538] The insulator (494) includes an opening reaching a conductor (496a), an opening reaching a conductor (496b) and a conductor (496d), and an opening reaching a conductor (496c). Conductors (498a), a conductor (498b), and a conductor (498c) are embedded in the openings.

[0539] The insulators (464, 466, 468, 489, 493, and 494) may each be formed to have a single-layer or multilayer structure including an insulator comprising, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

[0540] It is preferable that an insulator having the function of blocking impurities such as oxygen and hydrogen be included in at least one of the insulators (464, 466, 468, 489, 493, and 494). If an insulator having the function of blocking impurities such as oxygen and hydrogen is placed near the transistor (2100), the electrical characteristics of the transistor (2100) can be stabilized.

[0541] An insulator having the function of blocking impurities such as oxygen and hydrogen may be formed to have a single-layer structure or a multilayer structure including, for example, an insulator comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

[0542] The conductors (480a), conductor (480b), conductor (480c), conductor (478a), conductor (478b), conductor (478c), conductor (476a), conductor (476b), conductor (474a), conductor (474b), conductor (474c), conductor (496a), conductor (496b), conductor (496c), conductor (496d), conductor (498a), conductor (498b), and conductor (498c) each have a single-layer structure or a multilayer structure comprising a conductor comprising one or more types selected from, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. It may be formed. For example, an alloy or compound containing the aforementioned elements may be used, or a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, or a conductor containing titanium and nitrogen, etc. may be used.

[0543] In addition, the semiconductor device of FIG. 35 is the same as the semiconductor device of FIG. 34 except for the structure of the transistor (2200). Therefore, for the semiconductor device of FIG. 35, the description of the semiconductor device of FIG. 34 is referenced. In the semiconductor device of FIG. 35, the transistor (2200) is a Fin-type transistor. In the Fin-type transistor (2200), the on-state characteristics of the transistor (2200) can be improved by increasing the effective channel width. In addition, the off-state characteristics of the transistor (2200) can be improved because the contribution of the electric field of the gate electrode can be greatly increased.

[0544] In addition, the semiconductor device of FIG. 36 is the same as the semiconductor device of FIG. 34 except for the structure of the transistor (2200). Therefore, for the semiconductor device of FIG. 36, reference is made to the description of the semiconductor device of FIG. 34. Specifically, in the semiconductor device of FIG. 36, the transistor (2200) is formed on a semiconductor substrate (450) which is an SOI substrate. In the structure of FIG. 36, the region (456) is separated from the semiconductor substrate (450) by an insulator (452). Since an SOI substrate is used as the semiconductor substrate (450), the punch-through phenomenon and the like can be suppressed, and the off-state characteristics of the transistor (2200) can be improved. In addition, the insulator (452) can be formed by making the semiconductor substrate (450) an insulator. For example, silicon oxide can be used as the insulator (452).

[0545] In each of the semiconductor devices shown in FIGS. 34, 35, and 36, a p-channel transistor is formed using a semiconductor substrate, and an n-channel transistor is formed thereon, so the area occupied by the device can be reduced. In other words, the integration density of the semiconductor device can be improved. In addition, since the fabrication process can be simplified compared to the case where n-channel transistors and p-channel transistors are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. Furthermore, the yield of the semiconductor device can be improved. For the p-channel transistor, some of the complex steps, such as the formation of a lightly doped drain (LDD) region, the formation of a shallow trench structure, or distortion design, may be omitted. Therefore, compared to a semiconductor device in which an n-channel transistor is formed using a semiconductor substrate, the productivity and yield of the semiconductor device may be increased.

[0546] <CMOS 아날로그 스위치>

[0547] The circuit diagram of FIG. 33 (B) shows a configuration in which the sources of transistors (2100 and 2200) are connected to each other and the drains of transistors (2100 and 2200) are connected to each other. With this configuration, the transistors can function as so-called CMOS analog switches.

[0548] <Memory Device 1>

[0549] Examples of semiconductor devices (memory devices) including a transistor according to one embodiment of the present invention, which can maintain stored data even when power is not supplied and has no limit on the number of recording cycles, are shown in (A) and (B) of FIG. 37.

[0550] The semiconductor device illustrated in (A) of FIG. 37 includes a transistor (3200) using a first semiconductor, a transistor (3300) using a second semiconductor, and a capacitance element (3400). Additionally, a transistor similar to the transistor (2100) can be used as the transistor (3300).

[0551] Additionally, it is preferable that the transistor (3300) be a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor (3300). Because the off-state current of the transistor (3300) is low, stored data can be maintained for a long time at a specific node of the semiconductor device. In other words, since refresh operations become unnecessary or the frequency of refresh operations can be reduced significantly, the power consumption of the semiconductor device can be reduced.

[0552] In FIG. 37 (A), the first wire (3001) is electrically connected to the source of the transistor (3200). The second wire (3002) is electrically connected to the drain of the transistor (3200). The third wire (3003) is electrically connected to one of the source and drain of the transistor (3300). The fourth wire (3004) is electrically connected to the gate of the transistor (3300). The gate of the transistor (3200) and the other of the source and drain of the transistor (3300) are electrically connected to one electrode of the capacitance element (3400). The fifth wire (3005) is electrically connected to the other electrode of the capacitance element (3400).

[0553] Since the semiconductor device of Fig. 37 (A) has the characteristic that the potential of the gate of the transistor (3200) can be maintained, data can be recorded, maintained, and read as follows.

[0554] The recording and maintenance of data is described. First, the potential of the fourth wire (3004) is set to a potential at which the transistor (3300) turns on, and the transistor (3300) is turned on. Accordingly, the potential of the third wire (3003) is supplied to a node (FG) where the gate of the transistor (3200) and one electrode of the capacitance element (3400) are electrically connected to each other. That is, a predetermined charge is supplied (recorded) to the gate of the transistor (3200). Here, one of two types of charges providing different potential levels (hereinafter referred to as low-level charge and high-level charge) is supplied. After that, the potential of the fourth wire (3004) is set to a potential at which the transistor (3300) turns off, and the transistor (3300) is turned off. Accordingly, the charge is maintained (maintained) at the node (FG).

[0555] Because the off-state current of the transistor (3300) is low, the charge of the node (FG) is maintained for a long time.

[0556] Next, the reading of data is described. By supplying a predetermined potential (positive potential) to the first wiring (3001) and an appropriate potential (reading potential) to the fifth wiring (3005), the potential of the second wiring (3002) changes according to the amount of charge maintained at the node (FG). This is the apparent threshold voltage when a high-level charge is applied to the gate of the transistor (3200) when an n-channel transistor is used as the transistor (3200). V th_H a, apparent threshold voltage when a low-level charge is applied to the gate of the transistor (3200) V th_L This is because it is lower. Here, the apparent threshold voltage refers to the potential of the fifth wire (3005) required to turn the transistor (3200) "on." Therefore, the potential of the fifth wire (3005) V th_H and V th_L potential between V By setting it to 0, the charge supplied to the node (FG) can be determined. For example, if a high-level charge is supplied to the node (FG) in the record, the potential of the fifth wiring (3005) V 0(> V th_H If ), the transistor (3200) becomes "on". When a low-level charge is supplied to the node (FG) during recording, the potential of the fifth wiring (3005) is V 0(< V th_L Even so, the transistor (3200) remains in an "off state." Therefore, data maintained at the node (FG) can be read by determining the potential of the second wiring (3002).

[0557] In addition, when memory cells are arranged, it is necessary to read the data of the desired memory cell during a read operation. For example, a potential at which the transistor (3200) becomes "off" regardless of the charge supplied to the node (FG), i.e. V th_H By supplying a lower potential to the fifth wiring (3005) of a memory cell where data is not read, a configuration can be adopted that allows reading only the data of the desired memory cell. Alternatively, a potential at which the transistor (3200) becomes "on" regardless of the charge supplied to the node (FG), i.e. V th_L By supplying a higher potential to the fifth wiring (3005) of a memory cell where data is not read, a configuration can be adopted that allows only the data of the desired memory cell to be read.

[0558] Although an example has been described in which two types of charges are maintained at the node (FG), the semiconductor device according to the present invention is not limited to this example. For example, a structure in which three or more types of charges can be maintained at the node (FG) of the semiconductor device may be adopted. By adopting such a structure, the semiconductor device can be made multi-valued and the storage capacity can be increased.

[0559] Structure of Memory Devices 2

[0560] FIG. 38 is a cross-sectional view of the semiconductor device of FIG. 37 (A). The semiconductor device shown in FIG. 38 includes a transistor (3200), a transistor (3300), and a capacitance element (3400). The transistor (3300) and the capacitance element (3400) are placed on the transistor (3200). Also, regarding the transistor (3300), refer to the description of the transistor (2100) described above. Also, regarding the transistor (3200), refer to the description of the transistor (2200) in FIG. 34. Also, although the transistor (2200) is shown as a p-channel transistor in FIG. 34, the transistor (3200) may be an n-channel transistor.

[0561] The transistor (2200) illustrated in FIG. 38 is a transistor using a semiconductor substrate (450). The transistor (2200) includes a region (472a) within the semiconductor substrate (450), a region (472b) within the semiconductor substrate (450), an insulator (462), and a conductor (454).

[0562] The semiconductor device illustrated in FIG. 38 includes an insulator (464), an insulator (466), an insulator (468), a conductor (480a), a conductor (480b), a conductor (480c), a conductor (478a), a conductor (478b), a conductor (478c), a conductor (476a), a conductor (476b), a conductor (474a), a conductor (474b), a conductor (474c), a conductor (496a), a conductor (496b), a conductor (496c), a conductor (496d), a conductor (498a), a conductor (498b), a conductor (498c), an insulator (489), an insulator (490), an insulator (492), an insulator (493), an insulator (494), and an insulator (495).

[0563] An insulator (464) is provided over the transistor (3200). An insulator (466) is provided over the insulator (464). An insulator (468) is provided over the insulator (466). An insulator (489) is provided over the insulator (468). The transistor (2100) is provided over the insulator (489). An insulator (493) is provided over the transistor (2100). An insulator (494) is provided over the insulator (493).

[0564] The insulator (464) has an opening reaching region (472a), an opening reaching region (472b), and an opening reaching conductor (454). Conductors (480a), conductor (480b), and conductor (480c) are embedded in the openings.

[0565] The insulator (466) includes an opening reaching a conductor (480a), an opening reaching a conductor (480b), and an opening reaching a conductor (480c). Conductors (478a), conductor (478b), and conductor (478c) are embedded in the openings.

[0566] The insulator (468) includes an opening reaching the conductor (478b) and an opening reaching the conductor (478c). The conductors (476a) and (476b) are embedded in the openings.

[0567] The insulator (489) includes an opening that overlaps with the channel forming region of the transistor (3300), an opening reaching a conductor (476a), and an opening reaching a conductor (476b). Conductors (474a), conductor (474b), and conductor (474c) are embedded in the openings.

[0568] The conductor (474a) may function as the bottom gate electrode of the transistor (3300). Alternatively, for example, electrical characteristics such as the threshold voltage of the transistor (3300) may be controlled by applying a constant potential to the conductor (474a). Alternatively, for example, the conductor (474a) and the conductor (504), which are the top gate electrodes of the transistor (3300), may be electrically connected to each other. Then, the on-state current of the transistor (3300) can be increased. Since the punch-through phenomenon can be suppressed, the electrical characteristics in the saturation region of the transistor (3300) can be stabilized.

[0569] The insulator (490) includes an opening reaching the conductor (474b) and an opening reaching the conductor (474c). Additionally, since the insulator (490) corresponds to the insulator (402) in the above-described embodiment, the description of the insulator (402) can be referenced for details of the insulator (490).

[0570] The insulator (495) includes an opening reaching a conductor (474b) through a conductor (507b) which is one of the source and drain of the transistor (3300), an opening reaching a conductor (515) through a conductor (507a) which is the other of the source and drain of the transistor (3300), and an opening reaching a conductor (474c) through a conductor (507a) which is the other of the source and drain of the transistor (3300). Additionally, since the insulator (495) corresponds to the insulator (410) in the above-described embodiment, the description of the insulator (410) may be referenced for details of the insulator (495).

[0571] The insulator (493) includes an opening reaching a conductor (514) that overlaps a conductor (515) via an insulator (511), an opening reaching a conductor that is the gate electrode of a transistor (3300), and an opening reaching a conductor (516) that is electrically connected to a conductor (507b) that is one of the source and drain of the transistor (3300). Conductors (496e), conductor (496b), and conductor (496f) are embedded in the openings. Additionally, an opening provided to any component, such as a transistor (3300), may pass through another component.

[0572] The insulator (494) includes an opening reaching a conductor (496e), an opening reaching a conductor (496b), and an opening reaching a conductor (496f). Conductors (498a, 498b, and 498c) are embedded in the openings.

[0573] It is preferable that at least one of the insulators (464, 466, 468, 489, 493, and 494) has the function of blocking impurities such as oxygen and hydrogen. If an insulator having the function of blocking impurities such as oxygen and hydrogen is placed near the transistor (3300), the electrical characteristics of the transistor (3300) can be stabilized.

[0574] The source or drain of the transistor (3200) is electrically connected to one of the source and drain of the transistor (3300), specifically the conductor (507b), through conductors (480b), (478b), (476a), (474b), and (496c). The conductor (454), which is the gate electrode of the transistor (3200), is electrically connected to the other of the source and drain of the transistor (3300), specifically the conductor (507a), through conductors (480c), (478c), (476b), (474c), and (496d).

[0575] The capacitive element (3400) includes a conductor (515), a conductor (514), and an insulator (511).

[0576] For the structure of other components, appropriate reference can be made to the description in FIG. 34, etc.

[0577] The semiconductor device of FIG. 39 is the same as the semiconductor device of FIG. 38, except for the structure of the transistor (3200). Therefore, for the semiconductor device of FIG. 39, the description of the semiconductor device of FIG. 38 is referenced. Specifically, in the semiconductor device of FIG. 39, the transistor (3200) is a Fin-type transistor. For the Fin-type transistor (3200), the description of the transistor (2200) of FIG. 35 is referenced. Additionally, although the transistor (2200) is shown as a p-channel transistor in FIG. 35, the transistor (3200) may be an n-channel transistor.

[0578] The semiconductor device of FIG. 40 is the same as the semiconductor device of FIG. 38, except for the structure of the transistor (3200). Therefore, for the semiconductor device of FIG. 40, the description of the semiconductor device of FIG. 38 is referenced. Specifically, in the semiconductor device of FIG. 40, the transistor (3200) is provided on a semiconductor substrate (450) which is an SOI substrate. For the transistor (3200) provided on the semiconductor substrate (450) (SOI substrate), the description of the transistor (2200) of FIG. 36 is referenced. Additionally, although the transistor (2200) in FIG. 36 is illustrated as a p-channel transistor, the transistor (3200) may be an n-channel transistor.

[0579] Memory Device 2

[0580] The semiconductor device of FIG. 37 (B) differs from the semiconductor device of FIG. 37 (A) in that it is not provided with a transistor (3200). Even in this case, data can be recorded and maintained in a manner similar to that of the semiconductor device of FIG. 37 (A).

[0581] The reading of data in the semiconductor device of FIG. 37 (B) is described. When the transistor (3300) is turned on, the third wiring (3003) in a floating state and the capacitance element (3400) conduct, and charge is redistributed between the third wiring (3003) and the capacitance element (3400). As a result, the potential of the third wiring (3003) changes. The amount of change in the potential of the third wiring (3003) depends on the potential of one electrode of the capacitance element (3400) (or the charge accumulated in the capacitance element (3400)).

[0582] For example, the potential of the third wiring (3003) after charge redistribution is ( C B × V B0 + C × V ) / ( C B + C ) and, V is the potential of one electrode of the capacitive element (3400), C is the capacitance of the capacitance element (3400), C B is the capacitive component of the third wiring (3003), and V B0 Silver is the potential of the third wiring (3003) before charge redistribution. Therefore, the potential of one electrode of the capacitance element (3400) of the memory cell is V 1 and V 0( V 1> V Assuming it is in one of the two states where 0), the potential V The potential of the third wiring (3003) when maintaining 1 (=( C B × V B0 + C × V 1) / ( C B + C )) is, potential V The potential of the third wiring (3003) when maintaining 0 (=( C B × V B0 + C × V 0) / ( C B + C It can be seen that it is higher than ))

[0583] And, by comparing the potential of the third wire (3003) with a predetermined potential, data can be read.

[0584] In this case, a transistor including the first semiconductor can be used in a driving circuit for driving a memory cell, and a transistor including the second semiconductor can be stacked on the driving circuit as a transistor (3300).

[0585] When including a transistor with a low off-state current using an oxide semiconductor, the semiconductor device described above can retain stored data for a long time. In other words, since refresh operations become unnecessary or the frequency of refresh operations can be reduced significantly, the power consumption of the semiconductor device can be reduced. Furthermore, stored data can be retained for a long time even when power is not supplied (and the potential is preferably fixed).

[0586] In the semiconductor device described above, since high voltage is not required for data recording, device degradation is unlikely to occur. For example, unlike conventional non-volatile memory, since electron injection into the floating gate and electron extraction from the floating gate are unnecessary, problems such as insulator degradation do not occur. In other words, the semiconductor device according to one embodiment of the present invention has no limitation on the number of times data can be rewritten, which is a problem of conventional non-volatile memory, and its reliability is significantly improved. Furthermore, since data is recorded according to the on / off state of the transistor, high-speed operation can be achieved.

[0587] Memory Device 3

[0588] A modified example of the semiconductor device (memory device) shown in (A) of FIG. 37 will be explained with reference to the circuit diagram of FIG. 41.

[0589] The semiconductor device illustrated in FIG. 41 includes a transistor (4100), a transistor (4200), a transistor (4300), a transistor (4400), a capacitance element (4500), and a capacitance element (4600). Here, a transistor similar to the transistor (3200) can be used as the transistor (4100), and a transistor similar to the transistor (3300) can be used as the transistors (4200, 4300, and 4400). Although not illustrated in FIG. 41, a plurality of semiconductor devices are provided as a matrix in FIG. 41. The semiconductor device of FIG. 41 can control the recording and reading of data voltage according to a signal or potential supplied to a wiring (4001), wiring (4003), wiring (4005), wiring (4006), wiring (4007), wiring (4008), and wiring (4009).

[0590] One of the source and drain of the transistor (4100) is connected to the wiring (4003). The other of the source and drain of the transistor (4100) is connected to the wiring (4001). In FIG. 41, the transistor (4100) is a p-channel transistor, but the transistor (4100) may be an n-channel transistor.

[0591] The semiconductor device of FIG. 41 includes two data holding units. For example, the first data holding unit holds a charge between one of the source and drain of a transistor (4400) connected to a node (FG1), one electrode of a capacitive element (4600), and one of the source and drain of a transistor (4200). The second data holding unit holds a charge between the gate of a transistor (4100) connected to a node (FG2), the other of the source and drain of a transistor (4200), one of the source and drain of a transistor (4300), and one electrode of a capacitive element (4500).

[0592] The other end of the source and drain of the transistor (4300) is connected to the wiring (4003). The other end of the source and drain of the transistor (4400) is connected to the wiring (4001). The gate of the transistor (4400) is connected to the wiring (4005). The gate of the transistor (4200) is connected to the wiring (4006). The gate of the transistor (4300) is connected to the wiring (4007). The other electrode of the capacitance element (4600) is connected to the wiring (4008). The other electrode of the capacitance element (4500) is connected to the wiring (4009).

[0593] The transistors (4200, 4300, and 4400) each function as switches that control the recording of data voltage and the retention of charge. Additionally, for each of the transistors (4200, 4300, and 4400), it is preferable to use a transistor with a low off-state current (low off-state current) that has a low current flowing between the source and drain in the off state. As an example of a transistor with a low off-state current, it is preferable to use a transistor (OS transistor) that includes an oxide semiconductor in the channel forming region. The OS transistor can be fabricated, for example, by superimposing a transistor that has a low off-state current and includes silicon. In FIG. 41, the transistors (4200, 4300, and 4400) are n-channel transistors, but the transistors (4200, 4300, and 4400) may be p-channel transistors.

[0594] It is preferable that the transistors (4200 and 4300) and the transistor (4400) be provided on different layers, even if the transistors (4200, 4300, and 4400) are transistors comprising an oxide semiconductor. In other words, the semiconductor device of FIG. 41 preferably includes a first layer (4021) on which the transistor (4100) is provided, a second layer (4022) on which the transistors (4200 and 4300) are provided, and a third layer (4023) on which the transistor (4400) is provided, as shown in FIG. 41. By stacking the layers on which the transistors are provided, the circuit area can be reduced, and thus the size of the semiconductor device can be reduced.

[0595] Next, the data recording operation for the semiconductor device illustrated in FIG. 41 will be described.

[0596] First, the recording operation of the data voltage for the data holding unit connected to the node (FG1) (hereinafter referred to as recording operation 1) is explained. In the following description, the data voltage recorded in the data holding unit connected to the node (FG1) V D1 Set as such, and the threshold voltage of the transistor (4100) V th ...does as.

[0597] In recording operation 1, the potential of the wiring (4003) V D1 After setting the potential of the wiring (4001) to the ground potential, the wiring (4001) is electrically set to a floating state. The wiring (4005 and 4006) is set to a high level. The wiring (4007 to 4009) is set to a low level. Then, because the potential of the node (FG2) in the electrically floating state increases, current flows through the transistor (4100). Because current flows through the transistor (4100), the potential of the wiring (4001) increases. The transistors (4400 and 4200) are turned on. Therefore, as the potential of the wiring (4001) increases, the potential of the nodes (FG1 and FG2) increases. As the potential of the node (FG2) increases, the voltage between the gate and source of the transistor (4100) V gs The threshold voltage of the transistor (4100) V th When this occurs, the current flowing through the transistor (4100) decreases. Therefore, the increase in potential between the wiring (4001) and the nodes (FG1 and FG2) stops, and the potential of the nodes (FG1 and FG2) V D1 this V th Degraded to that extent " V D1 - V th It is fixed in.

[0598] When current flows through the transistor (4100), the current supplied to the wiring (4003) V D1 Since silver is supplied to the wiring (4001), the potential of nodes (FG1 and FG2) increases. As the potential increases, the potential of node (FG2) " V D1 - V th When this happens, the transistor (4100) V gs Is V th Because it becomes so, the flow of current stops.

[0599] Next, the recording operation of the data voltage for the data holding unit connected to the node (FG2) (hereinafter referred to as recording operation 2) will be explained. In the following description, the data voltage recorded in the data holding unit connected to the node (FG2) V D2 ...does as.

[0600] In recording operation 2, the potential of the wiring (4001) V D2 After setting the potential of the wiring (4003) to the ground potential, the wiring (4003) is electrically floated. The wiring (4007) is set to a high level. The wirings (4005, 4006, 4008, and 4009) are set to a low level. The transistor (4300) is turned on to set the wiring (4003) to a low level. Consequently, the potential of the node (FG2) is lowered to a low level, and current flows through the transistor (4100). As current flows, the potential of the wiring (4003) increases. The transistor (4300) is turned on. Consequently, as the potential of the wiring (4003) increases, the potential of the node (FG2) increases. As the potential of the node (FG2) increases, the transistor (4100) V gs of the transistor (4100) V th When this happens, the current flowing through the transistor (4100) decreases. Therefore, the increase in the potential of the wiring (4003) and the node (FG2) stops, and the potential of the node (FG2) V D2 go V th Degraded to that extent " V D2 - V th It is fixed in.

[0601] In other words, when current flows through the transistor (4100), the current supplied to the wiring (4001) V D2 Since it is supplied to the wiring (4003), the potential of node (FG2) increases. As the potential increases, the potential of node (FG2) " V D2 - V th When this happens, the transistor (4100) V gs Is V th Because this is the case, the flow of current stops. At this time, transistors (4200 and 4400) are off, and the potential of node (FG1) is the " recorded in record operation 1 V D1 - V th It is maintained in.

[0602] In the semiconductor device illustrated in FIG. 41, after recording data voltage in a plurality of data holding units, the wiring (4009) is set to a high level to increase the potential of the nodes (FG1 and FG2). Then, the transistor is turned off to stop the movement of charge, so the recorded data voltage is maintained.

[0603] By recording the data voltage for the nodes (FG1 and FG2) described above, the data voltage can be maintained in a plurality of data holding units. As the potential to be recorded, " V D1 - V th " and " V D2 - V th Although explained using " as an example, these are data voltages corresponding to multi-valued data. Therefore, if the data holding section holds 4 bits of data each, the 16 values ​​of " V D1 - V th " and 16 value " V D2 - V th You can obtain "

[0604] Next, the data reading operation from the semiconductor device illustrated in FIG. 41 will be described.

[0605] First, the reading operation of the data voltage for the data holding part connected to the node (FG2) (hereinafter referred to as reading operation 1) will be explained.

[0606] In read operation 1, after performing pre-charging, the electrically floating wiring (4003) is discharged. The wiring (4005 to 4008) is set to a low level. When the wiring (4009) is set to a low level, the potential of the electrically floating node (FG2) is " V D2 - V th "It becomes. As the potential of the node (FG2) decreases, current flows through the transistor (4100). As current flows, the potential of the wiring (4003), which is in an electrically floating state, decreases. As the potential of the wiring (4003) decreases, the transistor (4100) V gs The value of the transistor (4100) is reduced. V gs of the transistor (4100) V th When this happens, the current flowing through the transistor (4100) decreases. In other words, the potential of the wiring (4003) is the potential of the node (FG2) V D2 - V th "see V th as big as V D2 "It becomes. The potential of the wiring (4003) corresponds to the data voltage of the data holding unit connected to the node (FG2). By performing A / D conversion on the data voltage of the read analog value, the data of the data holding unit connected to the node (FG2) is obtained.

[0607] In other words, by making the wiring (4003) after pre-charging into a floating state and changing the potential of the wiring (4009) from a high level to a low level, current flows through the transistor (4100). When current flows, the potential of the wiring (4003) in the floating state decreases, and " V D2 "becomes. In the transistor (4100), the " of node (FG2)" V D2 - V th "and wiring (4003)" V D2 " between V gs Is V th Because it becomes so, the current stops. And, on the wiring (4003), "recorded in recording operation 2" V D2 " is read.

[0608] After obtaining data from the data holding section connected to node (FG2), turn on the transistor (4300) to obtain the " of node (FG2" V D2 - V th Discharges ".

[0609] Then, the charge maintained in node (FG1) is distributed between node (FG1) and node (FG2), and the data voltage of the data holding part connected to node (FG1) is transferred to the data holding part connected to node (FG2). Wiring (4001 and 4003) is set to a low level. Wiring (4006) is set to a high level. Wiring (4005) and wiring (4007 to 4009) are set to a low level. When the transistor (4200) is turned on, the charge of node (FG1) is distributed between node (FG1) and node (FG2).

[0610] Here, the potential after charge distribution is the recorded potential " V D1 - V th It decreases from ". Therefore, it is desirable to make the capacitance of the capacitance element (4600) greater than the capacitance of the capacitance element (4500). Or, the potential recorded at node (FG1) " V D1 - V th "Position equivalent to the same data" V D2 - V th It is desirable to make it larger. As described above, the drop in potential after charge distribution can be suppressed by changing the capacitance ratio or by making the recorded potential larger in advance. Fluctuations in potential due to charge distribution are explained below.

[0611] Next, the reading operation of the data voltage for the data holding part connected to the node (FG1) (hereinafter referred to as reading operation 2) will be described.

[0612] In reading operation 2, the wiring (4003), which is in an electrically floating state after pre-charging, is discharged. The wiring (4005 to 4008) is set to a low level. The wiring (4009) is set to a high level during pre-charging and then to a low level. When the wiring (4009) is set to a low level, the potential of the node (FG2) in an electrically floating state is " V D1 - V th "It becomes. As the potential of the node (FG2) decreases, current flows through the transistor (4100). When current flows, the potential of the wiring (4003), which is in an electrically floating state, decreases. As the potential of the wiring (4003) decreases, the transistor (4100) V gs The transistor's performance deteriorates. V gs of the transistor (4100) V th When this happens, the current flowing through the transistor (4100) decreases. In other words, the potential of the wiring (4003) is the potential of the node (FG2) V D1 - V th "see V th as big as V D1 This becomes. The potential of the wiring (4003) corresponds to the data voltage of the data holding unit connected to the node (FG1). By performing A / D conversion on the data voltage of the read analog value, the data of the data holding unit connected to the node (FG1) is obtained. The above description is the operation of reading the data voltage of the data holding unit connected to the node (FG1).

[0613] In other words, by making the wiring (4003) after pre-charging into a floating state and changing the potential of the wiring (4009) from a high level to a low level, current flows through the transistor (4100). When current flows, the potential of the wiring (4003) in the floating state decreases, and " V D1 "This becomes. In the transistor (4100), the " of node (FG2)" V D1 - V th "and wiring (4003)" V D1 " between V gs Is V th Because it becomes so, the current stops. And, on the wiring (4003), "recorded in recording operation 1" V D1 This is read.

[0614] In the operation of reading data voltage from the nodes (FG1 and FG2) described above, data voltage can be read from a plurality of data holding units. For example, by holding 4 bits (16 values) of data in each of the nodes (FG1) and (FG2), a total of 8 bits (256 values) of data can be held. In the structure illustrated in FIG. 41, the first to third layers (4021 to 4023) are provided, but by adding layers, the storage capacity can be increased without increasing the area of ​​the semiconductor device.

[0615] The read potential is higher than the recorded data voltage V th It can be read as a voltage as large as that. Therefore, the " recorded in the recording operation V D1 - V th "of V th and " V D2 - V th "of V th It can be read by offsetting it. As a result, the memory capacity per memory cell can be improved, and the data being read can be made closer to accurate data, so the reliability of the data becomes excellent.

[0616] FIG. 42 is a cross-sectional view of a semiconductor device corresponding to FIG. 41. The semiconductor device illustrated in FIG. 42 includes transistors (4100, 4200, 4300, and 4400) and capacitance elements (4500 and 4600). Here, the transistor (4100) is formed in a first layer (4021), the transistors (4200 and 4300) and the capacitance element (4500) are formed in a second layer (4022), and the transistor (4400) and the capacitance element (4600) are formed in a third layer (4023).

[0617] Here, regarding the transistors (4200, 4300, and 4400), reference may be made to the description of the transistor (3300), and regarding the transistor (4100), reference may be made to the description of the transistor (3200). Regarding other wiring and other insulators, reference may be made to the description of FIG. 38.

[0618] In addition, the conductive layer of the capacitance element (3400) in the semiconductor device of FIG. 38 is parallel to the substrate, but the capacitance elements (4500 and 4600) are each formed to include a conductive layer having a trench shape. By having this structure, a larger capacitance can be obtained without increasing the occupied area.

[0619] <fpga>

[0620] One embodiment of the present invention may be applied to an LSI such as a field programmable gate array (FPGA).

[0621] FIG. 43 (A) illustrates an example of a block diagram of an FPGA. The FPGA includes a routing switch element (521) and a logic element (522). The logic element (522) can switch the function of a logic circuit, such as a combinational circuit or a sequence circuit, according to configuration data stored in a configuration memory.

[0622] FIG. 43 (B) is a schematic diagram illustrating the function of a routing switch element (521). The routing switch element (521) can switch the connection between logic elements (522) according to configuration data stored in the configuration memory (523). Additionally, FIG. 43 (B) illustrates a single switch that switches the connection between terminal (IN) and terminal (OUT), but in an actual FPGA, multiple switches are provided between multiple logic elements (522).

[0623] Fig. 43 (C) illustrates an example of a circuit configuration that functions as a configuration memory (523). The configuration memory (523) includes a transistor (M11) which is an OS transistor and a transistor (M12) which is a silicon (Si) transistor. Configuration data (D SW ) is through the transistor (M11) to the node (FN SW It is supplied to ). This configuration data (D SW The potential of ) can be maintained by turning off the transistor (M11). The maintained configuration data (D SW Since the on / off state of the transistor (M12) can be switched according to the potential of ), the connection between terminal (IN) and terminal (OUT) can be switched.

[0624] Fig. 43 (D) is a schematic diagram illustrating the function of a logic element (522). The logic element (522), according to the configuration data stored in the configuration memory (527), [uses] a terminal (OUT mem The potential of ) can be switched. The lookup table (524) is the terminal (OUT mem Depending on the potential of ), the function of the combinational circuit processing the signal of the terminal (IN) can be switched. The logic element (522) includes a selector (526) that switches the signal of the terminal (OUT) and the register (525), which is a sequential circuit. The selector (526) is for the terminal (OUT) output from the configuration memory (527). mem Depending on the potential of ), you can choose whether to output a signal from the lookup table (524) or a signal from the register (525).

[0625] Figure 43 (E) illustrates an example of a circuit configuration that functions as a configuration memory (527). The configuration memory (527) includes OS transistors, transistors (M13) and (M14), and Si transistors, transistors (M15) and (M16). Configuration data (D LE ) is through the transistor (M13) to the node (FN LE It is supplied to ). Configuration data (DB LE ) is through the transistor (M14) to the node (FNB LE It is supplied to ). Configuration data (DB LE ) is configuration data with reversed logic (D LE Equivalent to the potential of ). Configuration data (D LE ) transposition and configuration data (DB LE The potential of ) can be maintained by turning off transistors (M13) and (M14), respectively. Configuration data (D LE ) and configuration data (DB LE Since the on / off state of one of the transistors (M15 and M16) is switched depending on the potential maintained by ), the terminal (OUT mem You can supply potential (VDD) or potential (VSS) to ).

[0626] For the configurations illustrated in FIG. 43 (A) to (E), any of the structures described in the above-described embodiments may be used. For example, Si transistors may be used as transistors (M12, M15, and M16), and OS transistors may be used as transistors (M11, M13, and M14). In this case, the wiring connecting the Si transistors provided in the lower layer may be formed from a low-resistance conductive material. Thus, a circuit with fast access speed and low power consumption can be obtained.

[0627] The structure described in this embodiment may be used in appropriate combination with any of the structures described in other embodiments.

[0628] (Embodiment 13)

[0629] In this embodiment, an example of an imaging device including a transistor, etc., according to one form of the present invention will be described.

[0630] Configuration of the imaging device

[0631] FIG. 44 (A) is a plan view illustrating an example of an imaging device (200) according to one embodiment of the present invention. The imaging device (200) includes a pixel unit (210) and peripheral circuits (peripheral circuit (260), peripheral circuit (270), peripheral circuit (280), and peripheral circuit (290)) for driving the pixel unit (210). The pixel unit (210) p line q heat( p and q Each includes a plurality of pixels (211) arranged in a matrix of at least two integers. Peripheral circuits (260), peripheral circuits (270), peripheral circuits (280), and peripheral circuits (290) are each connected to the plurality of pixels (211), and a signal for driving the plurality of pixels (211) is supplied. In the present specification, etc., "peripheral circuit" or "driving circuit" may refer to all of the peripheral circuits (260, 270, 280, and 290). For example, peripheral circuit (260) may be considered part of the peripheral circuit.

[0632] The imaging device (200) preferably includes a light source (291). The light source (291) can emit detection light (P1).

[0633] The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. The peripheral circuit may be formed on a substrate on which the pixel portion (210) is formed. Alternatively, a semiconductor device such as an IC chip may be used in part or all of the peripheral circuit. Additionally, as for the peripheral circuit, one or more of the peripheral circuits (260, 270, 280, and 290) may be omitted.

[0634] As illustrated in (B) of FIG. 44, pixels (211) may be provided at an angle in the pixel portion (210) included in the imaging device (200). By arranging the pixels (211) at an angle, the spacing (pitch) between pixels in the row direction and column direction can be shortened. Accordingly, the quality of the image captured by the imaging device (200) can be improved.

[0635] <Example of Pixel Composition 1>

[0636] By forming a pixel (211) included in an imaging device (200) into a plurality of subpixels (212) and combining each subpixel (212) with a filter (color filter) that transmits light in a specific wavelength range, data for realizing a color image display can be obtained.

[0637] FIG. 45 (A) is a top view showing an example of a pixel (211) for obtaining a color image. The pixel (211) shown in FIG. 45 (A) includes a subpixel (212) (also called subpixel (212R)) provided with a color filter that transmits light in the wavelength region of red (R), a subpixel (212) (also called subpixel (212G)) provided with a color filter that transmits light in the wavelength region of green (G), and a subpixel (212) (also called subpixel (212B)) provided with a color filter that transmits light in the wavelength region of blue (B). The subpixel (212) can function as a photosensor.

[0638] The subpixel (212) (subpixel (212R), subpixel (212G), and subpixel (212B)) is electrically connected to wiring (231), wiring (247), wiring (248), wiring (249), and wiring (250). Additionally, the subpixel (212R), subpixel (212G), and subpixel (212B) are each connected to wirings (253) provided independently. In the present specification, for example, n Wiring (248) and wiring (249) connected to the row pixel (211) are wiring (248[ n ]) and wiring(249[ n It is called ]). For example, m The wiring (253) connected to the tenth pixel (211) is wiring (253[ m It is called ]). Also, in (A) of Fig. 45. m The wiring (253) connected to the subpixel (212R), subpixel (212G), and subpixel (212B) of the tenth pixel (211) is wiring (253[ m ]R), wiring(253[ m ]G), and wiring(253[ m ]B). The subpixel (212) is electrically connected to a surrounding circuit through the wiring described above.

[0639] The imaging device (200) has a structure in which a subpixel (212) is electrically connected via a switch to a subpixel (212) of an adjacent pixel (211) that is provided with a color filter that transmits light in the same wavelength range as the subpixel (212). Figure 45 (B) shows an example of the connection of the subpixels (212). n (n is 1 or more p Integers below) row m (m is 1 or more q A subpixel (212) of a pixel (211) arranged in a column of integers below, and ( n +1) row m This illustrates an example of the connection of a subpixel (212) of an adjacent pixel (211) arranged in a column. In (B) of FIG. 45, n line m Subpixels (212R) arranged in a row, and ( n +1) row m The subpixels (212R) arranged in the row are connected to each other through a switch (201). n line m Subpixels (212G) arranged in a row, and ( n +1) row m The subpixels (212G) arranged in the row are connected to each other through a switch (202). n line m Subpixels (212B) arranged in a row, and ( n +1) row m The subpixels (212B) arranged in the row are connected to each other through a switch (203).

[0640] The color filter used in the subpixel (212) is not limited to red (R), green (G), and blue (B) color filters, and may also use a color filter that transmits cyan (C), yellow (Y), and magenta (M) light. By providing subpixels (212) that detect light in three different wavelength regions in one pixel (211), a full-color image can be obtained.

[0641] In addition to subpixels (212) provided with color filters that transmit red (R), green (G), and blue (B) light, a pixel (211) may be provided that includes a subpixel (212) provided with a color filter that transmits yellow (Y) light. In addition to subpixels (212) provided with color filters that transmit cyan (C), yellow (Y), and magenta (M) light, a pixel (211) may be provided that includes a subpixel (212) provided with a color filter that transmits blue (B) light. By providing subpixels (212) that detect light in four different wavelength regions in a single pixel (211), the color reproduction of the resulting image can be improved.

[0642] For example, regarding the subpixel (212) detecting light in the red wavelength region, the subpixel (212) detecting light in the green wavelength region, and the subpixel (212) detecting light in the blue wavelength region in (A) of FIG. 45, the ratio of the number of pixels (or the ratio of the light-receiving area) may not be 1:1:1. For example, a Bayer array may be adopted in which the ratio of the number of pixels (ratio of the light-receiving area) is red:green:blue = 1:2:1. Alternatively, the ratio of the number of pixels (ratio of the light-receiving area) of red, green, and blue may be 1:6:1.

[0643] The number of subpixels (212) provided to the pixel (211) may be one, but it is preferable to provide two or more subpixels. For example, if two or more subpixels (212) that detect light in the same wavelength range are provided, redundancy is increased and the reliability of the imaging device (200) can be increased.

[0644] If an IR (infrared) filter that transmits infrared light and absorbs or reflects visible light is used as a filter, an imaging device (200) that detects infrared light can be implemented.

[0645] In addition, using an ND (neutral density) filter (photosensitive filter) can prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (photoreceiving element). By combining ND filters with different photosensitive performance, the dynamic range of the imaging device can be increased.

[0646] In addition to the filter described above, a lens may be provided to the pixel (211). An example of the arrangement of the pixel (211), filter (254), and lens (255) is described with reference to the cross-sectional views (A) and (B) of FIG. 46. Through the lens (255), the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 46 (A), light (256) enters the photoelectric conversion element (220) through the lens (255), filter (254) (filter (254R), fil...

Claims

Claim 1 A semiconductor device comprising: a first transistor; a second transistor; and a capacitive element, wherein the semiconductor device comprises: a substrate; a first insulator on the substrate; a first channel forming region of the first transistor on the first insulator, wherein the first channel forming region comprises silicon; a second insulator on the first channel forming region; a first conductor on the second insulator, wherein the first conductor comprises a region functioning as a first gate electrode of the first transistor; a third insulator on the first conductor; a layer comprising a second channel forming region of the second transistor on the third insulator, wherein the second channel forming region comprises an oxide semiconductor; a second conductor overlapping with the layer comprising the second channel forming region of the second transistor, wherein the second conductor comprises a region functioning as a second gate electrode of the second transistor; and a fourth insulator on the layer comprising the second channel forming region of the second transistor. A semiconductor device further comprising a third conductor and a fourth conductor on the fourth insulator, wherein the third conductor includes a region that functions as a first electrode of the capacitive element, the third conductor is electrically connected to one of the source and drain of the second transistor, the third conductor is electrically connected to the first gate electrode of the first transistor through a fifth conductor formed of the same conductive layer as the second conductor, and the fourth conductor is electrically connected to the other of the source and drain of the second transistor and one of the source and drain of the first transistor. Claim 2 A semiconductor device comprising: a first transistor; a second transistor; and a capacitive element, wherein the semiconductor device comprises: a substrate; a first insulator on the substrate; a first channel forming region of the first transistor on the first insulator, wherein the first channel forming region comprises silicon; a second insulator on the first channel forming region; a first conductor on the second insulator, wherein the first conductor comprises a region functioning as a first gate electrode of the first transistor; a third insulator on the first conductor; a layer comprising a second channel forming region of the second transistor on the third insulator, wherein the second channel forming region comprises an oxide semiconductor; a second conductor overlapping with the layer comprising the second channel forming region of the second transistor, wherein the second conductor comprises a region functioning as a second gate electrode of the second transistor; a fourth insulator on the layer comprising the second channel forming region of the second transistor; a third conductor and a fourth conductor on the fourth insulator; and a fifth insulator on the third conductor and the fourth conductor. A semiconductor device further comprising a fifth conductor on the fifth insulator, wherein the third conductor includes a region that functions as a first electrode of the capacitance element, the fifth conductor includes a region that functions as a second electrode of the capacitance element, the third conductor is electrically connected to one of the source and drain of the second transistor, the third conductor is electrically connected to the first gate electrode of the first transistor through a sixth conductor formed of the same conductive layer as the second conductor, and the fourth conductor is electrically connected to the other of the source and drain of the second transistor and one of the source and drain of the first transistor. Claim 3 A semiconductor device comprising: a first transistor; a second transistor; and a capacitance element, wherein the semiconductor device comprises: a substrate; a first insulator on the substrate; a first channel forming region of the first transistor on the first insulator comprising silicon; a second insulator on the first channel forming region; a first conductor on the second insulator comprising a region that functions as a first gate electrode of the first transistor; a third insulator on the first conductor; a second conductor and a third conductor on the third insulator, wherein the second conductor comprises a region that functions as a second gate electrode of the second transistor; a fourth insulator on the second conductor and the third conductor; a layer comprising a second channel forming region of the second transistor on the fourth insulator, wherein the second channel forming region comprises an oxide semiconductor; and a fifth insulator on the layer comprising a second channel forming region of the second transistor. A semiconductor device comprising: a fourth conductor having a region functioning as a third gate electrode of the second transistor as a fourth conductor on the fifth insulator; and further comprising a fifth conductor and a sixth conductor on the fourth conductor, wherein the fifth conductor is electrically connected to the layer having the second channel forming region of the second transistor and the third conductor, and the sixth conductor has a region functioning as a first electrode of the capacitive element, and the sixth conductor is electrically connected to the layer having the second channel forming region of the second transistor and the first conductor. Claim 4 A semiconductor device comprising: a first transistor; a second transistor; and a capacitance element, wherein the semiconductor device comprises: a substrate; a first insulator on the substrate; a first channel forming region of the first transistor on the first insulator comprising silicon; a second insulator on the first channel forming region; a first conductor on the second insulator comprising a region that functions as a first gate electrode of the first transistor; a third insulator on the first conductor; a second conductor and a third conductor on the third insulator, wherein the second conductor comprises a region that functions as a second gate electrode of the second transistor; a fourth insulator on the second conductor and the third conductor; a layer comprising a second channel forming region of the second transistor on the fourth insulator, wherein the second channel forming region comprises an oxide semiconductor; and a fifth insulator on the layer comprising a second channel forming region of the second transistor. A semiconductor device comprising: a fourth conductor on the fifth insulator, the fourth conductor including a region that functions as a third gate electrode of the second transistor; a fifth conductor and a sixth conductor on the fourth conductor; a sixth insulator on the fifth conductor and the sixth conductor; and a seventh conductor on the sixth insulator, wherein the fifth conductor is electrically connected to the layer including the second channel forming region of the second transistor and the third conductor, the sixth conductor includes a region that functions as a first electrode of the capacitance element, the sixth conductor is electrically connected to the layer including the second channel forming region of the second transistor and the first conductor, and the seventh conductor includes a region that functions as a second electrode of the capacitance element. Claim 5 A semiconductor device comprising: a first transistor; a second transistor; and a capacitance element, wherein the semiconductor device comprises: a substrate; a first insulator on the substrate; a first channel forming region of the first transistor on the first insulator comprising silicon; a second insulator on the first channel forming region; a first conductor on the second insulator comprising a region that functions as a first gate electrode of the first transistor; a third insulator on the first conductor; a second conductor and a third conductor on the third insulator, wherein the second conductor comprises a region that functions as a second gate electrode of the second transistor; a fourth insulator on the second conductor and the third conductor; a layer comprising a second channel forming region of the second transistor on the fourth insulator, wherein the second channel forming region comprises an oxide semiconductor; and a fifth insulator on the layer comprising a second channel forming region of the second transistor. A semiconductor device comprising: a fourth conductor on the fifth insulator; and further comprising a fifth conductor and a sixth conductor on the fourth conductor, wherein the fifth conductor is electrically connected to the layer including the second channel forming region of the second transistor and the third conductor, the sixth conductor includes a region functioning as a first electrode of the capacitive element, the sixth conductor is electrically connected to the layer including the second channel forming region of the second transistor, and the sixth conductor is electrically connected to the first conductor through a seventh conductor that overlaps with the first conductor. Claim 6 delete

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