Circuit board and semiconductor package comprising the same

Abstract

A circuit board according to an embodiment comprises: a first insulating layer; a first pattern layer disposed on the upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and including a cavity; and a barrier layer disposed on the first pattern layer that is vertically superimposed with the cavity among the first pattern layers, wherein the upper surface of the first insulating layer includes a first upper surface that is vertically superimposed with the lower surface of the cavity and a second upper surface that is not vertically superimposed with the lower surface of the cavity, and the first pattern layer includes a first pattern portion disposed on the first upper surface of the first insulating layer and a second pattern portion disposed on the second upper surface of the first insulating layer, wherein the upper surface of the first pattern portion is exposed through the cavity without contacting the first and second insulating layers, and the barrier layer is disposed on the upper surface of the first pattern portion.

Description

Technology Field

[0001] An embodiment relates to a circuit board and a semiconductor package including the same. Background Technology

[0002] Recently, efforts are being made to develop improved 5G (5th generation) communication systems or pre-5G communication systems to meet the demand for wireless data traffic.

[0003] To achieve high data transfer rates, 5G communication systems use ultra-high frequency (mmWave) bands (sub 6 GHz, 28 GHz, 38 GHz, or higher frequencies). These high frequency bands are called mmWave due to their wavelengths.

[0004] In order to mitigate path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, integrated technologies such as beamforming, massive MIMO, and array antennas are being developed in 5G communication systems.

[0005] Considering that these frequency bands can consist of hundreds of active antennas of different wavelengths, the antenna system can be relatively large.

[0006] This means that multiple substrates constituting an active antenna system—namely, the antenna substrate, antenna feed substrate, transceiver substrate, and baseband substrate—must be integrated into a single compact unit.

[0007] Accordingly, the circuit boards applied to conventional 5G communication systems had a structure in which multiple boards were integrated, and thus had a relatively thick thickness.

[0008] Meanwhile, conventionally, in order to reduce the thickness of a circuit board, a cavity is formed in the circuit board, and various component elements are placed within the formed cavity. At this time, the circuit board includes a pad on which the various component elements are mounted. Furthermore, the pad has a structure in which its surface is exposed through the cavity.

[0009] However, in a circuit board containing a cavity as described above, there is a problem in that the pad exposed through the cavity is continuously exposed during subsequent processes and suffers damage (e.g., chemical damage). Furthermore, due to this damage, the pad may have a thickness thinner than the target thickness or undergo shape deformation, resulting in physical or electrical reliability issues.

[0010] In addition, conventionally, the thickness of the pad is set to compensate for changes in the thickness of the pad. For example, when the target final thickness of the pad is 10㎛, the initial thickness of the pad is formed to be approximately 15㎛ to 20㎛ to account for chemical damage. However, when the thickness of the pad increases, there is a limit to the miniaturization of the circuit pattern layer including the pad, and consequently, there is a problem that the overall volume of the circuit board increases.

[0011] Accordingly, new circuit boards and semiconductor packages are required. The problem to be solved

[0012] An embodiment provides a circuit board with a new structure and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board capable of preventing damage to a pad that occurs during a laser process for forming a cavity, and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board capable of miniaturizing pads exposed through a cavity and a semiconductor package including the same.

[0015] In addition, the embodiment provides a circuit board capable of preventing damage to the pads that occurs during a subsequent process after cavity formation, and a package board including the same.

[0016] The technical problems to be solved in the embodiments are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0017] A circuit board according to an embodiment comprises: a first insulating layer; a first pattern layer disposed on the upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and including a cavity; and a barrier layer disposed on the first pattern layer that is vertically superimposed with the cavity among the first pattern layers, wherein the upper surface of the first insulating layer includes a first upper surface that is vertically superimposed with the lower surface of the cavity and a second upper surface that is not vertically superimposed with the lower surface of the cavity, and the first pattern layer includes a first pattern portion disposed on the first upper surface of the first insulating layer and a second pattern portion disposed on the second upper surface of the first insulating layer, wherein the upper surface of the first pattern portion is exposed through the cavity without contacting the first and second insulating layers, and the barrier layer is disposed on the upper surface of the first pattern portion.

[0018] Additionally, the first upper surface of the first insulating layer forms the lower surface of the cavity, the second upper surface of the first insulating layer has a step difference from the first upper surface, the thickness of the first pattern portion is smaller than the thickness of the second pattern portion, and at least a portion of the side of the first pattern portion is covered by the first insulating layer.

[0019] Additionally, the side of the first pattern portion is entirely covered by the first insulating layer, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion extending from the first portion and disposed on the first upper surface of the first insulating layer.

[0020] In addition, the thickness of the first pattern portion is smaller than the thickness of the second pattern portion, the upper surface of the first pattern portion is located lower than the upper surface of the second pattern portion, and the lower surface of the first pattern portion is located on the same plane as the lower surface of the second pattern portion.

[0021] Additionally, the first pattern layer includes a third pattern portion disposed in the boundary region between the first upper surface and the second upper surface of the first insulating layer, and the thickness of the third pattern portion is smaller than the thickness of the second pattern portion.

[0022] Additionally, the upper surface of the first pattern part does not come into contact with the second insulating layer, and the upper surfaces of the second and third pattern parts come into contact with the second insulating layer; the upper surface of the third pattern part is positioned higher than the upper surface of the first pattern part and is located on the same plane as the upper surface of the second pattern part, and the lower surface of the third pattern part is positioned higher than the lower surface of the second pattern part and is greater than the height of the upper surface of the first pattern part.

[0023] Additionally, the second pattern portion comprises a first metal layer horizontally overlapping the first pattern portion; and a second metal layer disposed on the first metal layer and in contact with the second upper surface of the first insulating layer, wherein the thickness of the first metal layer of the second pattern portion corresponds to the thickness of the first pattern portion, and the thickness of the second metal layer of the second pattern portion corresponds to the thickness of the third pattern portion.

[0024] In addition, the first upper surface of the first insulating layer is positioned lower than the second upper surface, the upper surface of the second pattern part, and the upper surface of the third pattern part.

[0025] Additionally, the first upper surface of the first insulating layer is positioned lower than the upper surface of the first pattern portion, and the side of the first pattern portion includes a first side that is covered by the first insulating layer and a second side that is not covered by the first insulating layer and is exposed through the cavity, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the second side of the first pattern portion.

[0026] Additionally, the first upper surface of the first insulating layer is positioned higher than the upper surface of the first pattern portion, and the first insulating layer includes a recess formed by a step difference between the first upper surface and the upper surface of the first pattern portion, and the barrier layer is disposed within the recess.

[0027] Additionally, the first pattern portion protrudes above the first upper surface of the first insulating layer, and the side of the first pattern portion includes a first side that is covered by the second insulating layer and a second side that is not covered by the second insulating layer and is exposed through the cavity, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the second side of the first pattern portion.

[0028] Additionally, the first pattern portion protrudes above the first upper surface of the first insulating layer, and the side of the first pattern portion is exposed through the cavity without contacting the first insulating layer and the second insulating layer as a whole, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the side of the first pattern portion.

[0029] In addition, the barrier layer is disposed on the first pattern portion having a plurality of layer structures.

[0030] In addition, the barrier layer comprises a first layer comprising nickel disposed on the first pattern portion, a second layer comprising palladium disposed on the first layer, and a third layer comprising gold disposed on the second layer.

[0031] Meanwhile, a semiconductor package according to an embodiment comprises: a first insulating layer; a second insulating layer disposed on one side of the first insulating layer and including a cavity; a first pattern layer disposed between the first insulating layer and the second insulating layer and including a first pattern portion disposed in a first region that overlaps vertically with the cavity, a second pattern portion disposed in a second region that does not overlap vertically with the cavity, and a third pattern portion disposed in a boundary region between the first and second regions; a second pattern layer disposed on the other side of the first insulating layer; a third pattern layer disposed on the upper surface of the second insulating layer; a barrier layer disposed on the first pattern portion of the first pattern layer; and a connection portion disposed on the barrier layer. The device includes a component mounted on the connection portion, wherein the upper surface of the first pattern portion is positioned lower than the upper surfaces of the second and third pattern portions, the upper surface of the second pattern portion is positioned on the same plane as the upper surface of the third pattern portion, the lower surface of the third pattern portion is positioned higher than the lower surfaces of the first and second pattern portions, and the lower surface of the first pattern portion is positioned on the same plane as the lower surface of the second pattern portion. Effects of the invention

[0032] According to the above embodiment, the circuit board includes a first pattern portion with its upper surface exposed through a cavity. A barrier layer is disposed on the first pattern portion. The barrier layer may be composed of a plurality of layers. For example, the barrier layer may include first to third layers. The barrier layer can function to protect the first pattern portion during a subsequent process after the cavity is formed. Through this, in the embodiment, it is not necessary to increase the thickness of the first pattern portion by taking into account the change in thickness of the first pattern portion that occurs during the subsequent process. Accordingly, in the embodiment, the first pattern portion can be miniaturized. Furthermore, in the embodiment, since the thickness of the first pattern portion can be reduced, the manufacturing cost can be reduced accordingly. In addition, in the embodiment, the shape change of the first pattern portion that occurs during the subsequent process can be prevented. Accordingly, in the embodiment, a chip can be stably mounted on the first pattern portion. Accordingly, in the embodiment, the physical and electrical reliability of the circuit board can be improved.

[0033] In addition, according to the above embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a first-1 insulating layer disposed closest to the first substrate layer and a first pattern layer disposed on the upper surface of the first-1 insulating layer. At this time, the first pattern layer includes a first pattern portion disposed in a first region vertically superimposed with the cavity, a second pattern portion disposed in a second region not vertically superimposed with the cavity, and a third pattern portion formed in a boundary region between the first and second regions. At this time, the thickness of at least one of the first to third pattern portions in the embodiment is different from the thickness of at least one other. In addition, at least one upper or lower surface of the first to third pattern portions in the embodiment is located on a different plane from at least one other upper or lower surface. As described above, in the embodiment, the first pattern layer disposed in an area adjacent to the cavity has a structure in which the thickness or surface is disposed at different positions, thereby improving the processability of cavity formation and resolving reliability issues that may occur during the cavity process.

[0034] Specifically, in the embodiment, during the process of forming the first pattern layer, a two-layer structure including a first metal layer and a second metal layer is formed through two-stage plating, and either of the first metal layer or the second metal layer is used as a first pattern portion which is a mounting pad, and the other is used as a third pattern portion which is a laser stopper, and both are used to form a second pattern portion. Through this, the embodiment can solve the reliability problem that occurs when the mounting pad and the stopper are placed on the same plane. For example, in the comparative example, a separate protective layer (not shown) is formed on the mounting pad to prevent damage to the mounting pad during the laser process of forming the cavity, and a process of removing it is performed later. In contrast, in the embodiment, a part of the third pattern portion used as the laser stopper can be utilized as a protective portion for the first pattern portion which is the mounting pad, and accordingly, the process of forming an additional protective layer to protect the first pattern portion can be omitted while preventing damage to the first pattern portion which is the mounting pad during the process of forming the cavity.

[0035] Furthermore, the first substrate layer includes a first region vertically superimposed with the cavity and a second region excluding the first region. Additionally, the second substrate layer includes a third region corresponding to the cavity and a fourth region excluding the third region. In this embodiment, the third region of the second substrate layer is a region where a driving element is placed, and the fourth region is a region where an antenna pattern layer is placed. In the above embodiment, the driving element is placed using the cavity of the second substrate layer, and the antenna pattern layer is placed in the fourth region of the second substrate layer that is horizontally adjacent to the driving element. Accordingly, in the embodiment, the signal transmission distance between the antenna pattern layer and the driving element can be minimized, and the resulting signal transmission loss can be minimized. For example, in the embodiment, compared to the comparative example where the substrate on which the driving element is placed and the substrate on which the antenna pattern layer is placed are connected using a separate connection means, the signal transmission distance can be reduced, and the signal transmission loss caused by the separate connection means can be reduced. In addition, in the embodiment, the antenna pattern layer and the driving element are arranged in a horizontal direction, so that the second region of the first substrate layer, which is vertically superimposed with the fourth region of the second substrate layer, can be utilized as the second antenna pattern layer, and accordingly, antenna pattern radiation and signal reception in different directions can be made possible in a single circuit pattern.

[0036] In addition, in the embodiment, by placing a driving element within the cavity of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavity.

[0037] Additionally, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. At this time, with respect to the bottom surface of the cavity, the second slope has an angle of inclination smaller than the first slope. Furthermore, the vertical length of the second part having the second slope in the embodiment is longer than the vertical length of the first part having the first slope. Accordingly, in the embodiment, the space occupied by the cavity can be reduced compared to the comparative example, and thus the circuit integration density can be improved. For example, in the embodiment, by reducing the space occupied by the cavity, the length of the antenna pattern layer can be increased within a substrate having the same size as the comparative example, and the communication performance can be improved accordingly.

[0038] In addition, in the embodiment, the thickness of the through electrode can be made to be the same as or smaller than the thickness of the circuit layer. Accordingly, in the embodiment, the thickness of the through electrode can be made to be the same as or smaller than the thickness of the circuit layer, thereby reducing the thickness of the circuit board. Furthermore, in the embodiment, by reducing the thickness of the through electrode, the signal transmission distance in the signal transmission path including the through electrode can be reduced, and the resulting signal transmission loss can be minimized.

[0039] In addition, in the embodiment, in the structure of a circuit board having the same thickness as the comparative example, the number of circuit layers can be increased by reducing the thickness of the insulating layer and the through-electrode, thereby improving circuit integration and communication performance. Brief explanation of the drawing

[0040] FIG. 1 is a drawing showing a circuit board according to an embodiment. Figure 2 is an enlarged view of the cavity area of ​​Figure 1. FIG. 3a is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to the first embodiment. FIG. 3b is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to the second embodiment. FIG. 3c is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to the third embodiment. Figures 4a and 4b show a top view of the second substrate layer. FIG. 5a is a drawing showing a circuit board according to a first modified example. FIG. 5b is a drawing showing a circuit board according to a second modified example. FIG. 5c is a drawing showing a circuit board according to a third variation example. FIG. 6 is a drawing showing a circuit board according to a second embodiment. Figure 7 is an enlarged view of a portion of Figure 6. FIG. 8 is a drawing showing a circuit board according to a third embodiment. FIG. 9 is a drawing showing a circuit board according to the fourth embodiment. FIG. 10 is a drawing showing a semiconductor package according to an embodiment. FIGS. 11a to 11q are drawings showing the manufacturing method of a circuit board according to the embodiment shown in FIG. 1 in process order. Specific details for implementing the invention

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0042] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0043] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0044] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as "at least one of A and B and C (or more than one)," it may include one or more of all combinations that can be formed from A, B, and C.

[0045] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are intended merely to distinguish the component from other components and are not to limit the essence, order, or sequence of the component. Furthermore, where it is stated that a component is 'connected,' 'combined,' or 'connected' to another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component.

[0046] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0048] Before describing the embodiments, we will describe an electronic device to which the circuit board of the embodiment and the semiconductor package including the same are applied.

[0049] Electronic devices

[0050] Prior to describing the embodiments, a semiconductor package having a structure in which a chip is mounted on a circuit board of the embodiments can be applied to an electronic device. In this case, the circuit board may be used as an antenna board on which a driving chip for driving an antenna device is mounted, but is not limited thereto.

[0051] The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate may mount memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC). Furthermore, the circuit board of the embodiment may also be used as a package substrate on which memory chips or logic chips are mounted.

[0052] The circuit board of the embodiment includes a cavity, and is configured to allow at least one, and furthermore at least two or more, chips to be mounted within the cavity. As an example, the chip may be an RFIC including a transmitting chip and a receiving chip of an antenna device.

[0053] At this time, the electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to these, and it is obvious that it may be any other electronic device that processes data in addition to these.

[0055] FIG. 1 is a drawing showing a circuit board according to an embodiment, and FIG. 2 is a drawing showing an enlarged view of the cavity area of ​​FIG. 1.

[0056] Hereinafter, a circuit board (100) according to an embodiment will be described with reference to FIGS. 1 and FIGS. 2. At this time, for the convenience of explaining the invention, the circuit board (100) is described as being applied to an antenna device.

[0057] The circuit board (100) of the embodiment may be provided for driving, feeding, and supporting the antenna portion. For example, the circuit board (100) may be a printed circuit board (PCB). Such a circuit board (100) has a flat structure. Such a circuit board (100) may have a multilayer structure in which a plurality of layers are stacked.

[0058] The above circuit board (100) may include a grounding layer (not shown) for grounding and a power supply section (not shown) for power supply.

[0059] The circuit board (100) of the embodiment may be divided into an antenna section in which a conductive antenna pattern layer is disposed and a driving section in which a driving unit for driving the antenna section is disposed. The conductive antenna pattern layer may refer to any one of a plurality of circuit layers described below.

[0060] The conductive antenna pattern layer may be provided for signal transmission and reception on the circuit board of the embodiment. For example, the conductive antenna pattern layer may transmit and receive signals in a predetermined resonant frequency band. For example, the conductive antenna pattern layer may operate in a resonant frequency band to transmit and receive electromagnetic waves. The conductive antenna pattern layer may operate as power is supplied from a power supply unit (not shown) of the circuit board (100), and the power supply operation of the power supply unit may be controlled by the driving unit.

[0061] The conductive antenna pattern layer may resonate in a plurality of resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonant antenna that resonates in different resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonant antenna that resonates in a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz, respectively, but is not limited thereto. The resonant frequency band of the conductive antenna pattern layer may vary depending on the communication standard of the antenna device to which the circuit board is applied.

[0063] The circuit board (100) of the embodiment may include a first substrate layer (200) and a second substrate layer (300).

[0064] At this time, the first substrate layer (200) and the second substrate layer (300) do not refer to a plurality of substrates that are manufactured separately and then joined together through a bonding layer, but rather refer to a single substrate manufactured through a single manufacturing process. That is, the first substrate layer (200) and the second substrate layer (300) are intended to distinguish, in a single circuit board, a first substrate region in which a cavity (C) is formed and a second substrate region other than the first substrate region.

[0065] The first substrate layer (200) may include a single insulating layer, or alternatively, may include a plurality of insulating layers sequentially stacked in the thickness direction.

[0066] At this time, the first substrate layer (200) is connected to at least one chip and can be connected to a main board (not shown) of an antenna device (e.g., electronic device) including a circuit board of the embodiment, while connecting between the chip and the circuit layer.

[0067] At this time, the insulating layer of the first substrate layer (200) may have a single-layer structure, but in order to arrange a plurality of signal lines on the first substrate layer (200) with a single-layer structure, the width of the first substrate layer (200) in the horizontal direction increases, and accordingly, the area occupied by the circuit board in the antenna device may increase. Accordingly, the first substrate layer (200) may include two or more insulating layers to reduce the width of the circuit board in the horizontal direction and minimize the distance of the signal connection lines. In the following description, the first substrate layer (200) is described as having a layer structure of two or more layers. However, the embodiment is not limited thereto, and the first substrate layer (200) may have a single insulating layer structure.

[0068] A second substrate layer (300) may be disposed on the first substrate layer (200). The second substrate layer (300) may have a layer structure of at least two layers. The second substrate layer (300) provides a circuit layer and a cavity (C). At this time, the circuit layer of the second substrate layer (300) is a conductive antenna pattern layer that functions as an antenna.

[0069] If the second substrate layer (300) has a single-layer structure, sufficient depth of the cavity (C) formed in the second substrate layer (300) may not be secured, and as a result, the effect of reducing thickness in the semiconductor package on which the chip is mounted may be insufficient. In addition, if the second substrate layer (300) has a single-layer structure, the placement area of ​​the circuit layer cannot be sufficiently secured within a limited space, so communication performance may be degraded. That is, the communication performance of the antenna pattern increases in proportion to the length of the antenna pattern. At this time, if the second substrate layer (300) has a single-layer structure, the length of the antenna pattern decreases in correspondence, and a problem may occur in which communication performance is degraded.

[0070] Accordingly, in the embodiment, the second substrate layer (300) is configured to include two or more insulating layers in order to provide a cavity (C) of sufficient space (e.g., sufficient depth) for mounting a chip while satisfying the communication performance of the antenna pattern. However, the embodiment is not limited thereto, and depending on the product to which the circuit board of the embodiment is applied or the thickness of the chip mounted in the cavity (C), the second substrate layer (300) may include only one insulating layer.

[0072] Hereinafter, the first substrate layer (200) and the second substrate layer (300) according to the embodiment will be described in detail.

[0073] The first substrate layer (200) may include an insulating layer, a circuit layer, and a through electrode. The through electrode may also be referred to as a ‘connector’ or ‘via’ that functions to connect circuit patterns placed on different layers.

[0074] The first substrate layer (200) may include a first insulating layer. The first insulating layer may have a layer structure of one layer or two or more layers. Although the first insulating layer of the first substrate layer (200) is shown in the drawing as having a three-layer structure, it is not limited thereto.

[0075] The first insulating layer may include a first-1 insulating layer (211), a first-2 insulating layer (212), and a first-3 insulating layer (213). For example, the first insulating layer may include a first-1 insulating layer (211), a first-2 insulating layer (212), and a first-3 insulating layer (213) in a region adjacent to the second substrate layer (300).

[0076] The first-1 insulating layer (211) may refer to the first uppermost insulating layer among the first insulating layers that is positioned closest to the second substrate layer (300). Additionally, the first-3 insulating layer (213) may refer to the first lowermost insulating layer among the first insulating layers that is furthest from the second substrate layer (300). Furthermore, the first-2 insulating layer (212) may refer to the first inner insulating layer positioned between the first uppermost insulating layer and the first lowermost insulating layer. And, if the first substrate layer (200) has an insulating layer structure of four or more layers, the first inner insulating layer may be composed of multiple layers.

[0077] The first insulating layer may include prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with epoxy resin or the like, and then performing heat pressing. However, the embodiments are not limited thereto, and the prepreg constituting the first insulating layer may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0078] The first insulating layer may comprise a resin and reinforcing fibers disposed within the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not specifically limited to an epoxy resin; for example, it may contain one or more epoxy groups within the molecule, or two or more epoxy groups, or four or more epoxy groups. Additionally, the resin of the first insulating layer may contain a naphthalene group, and for example, may be of the aromatic amine type, but is not limited thereto. For example, the resin may include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of a condensation product of phenols and an aromatic aldehyde having a phenolic hydroxyl group, biphenylaralkyl type epoxy resin, fluorene type epoxy resin, xanthene type epoxy resin, triglycidyl isocyanurate, rubber-modified epoxy resin, and phosphorus-based epoxy resin, and may include naphthalene-based epoxy resin, bisphenol A type epoxy resin, phenol novolak epoxy resin, cresol novolak epoxy resin, rubber-modified epoxy resin, and phosphorus-based epoxy resin. In addition, the reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (e.g., aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. The reinforcing fibers may be arranged within the resin in a planar direction, intersecting each other.

[0079] Meanwhile, the above glass fiber, carbon fiber, aramid fiber (e.g., aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material may be used.

[0080] However, the embodiments are not limited thereto, and the first insulating layer may be composed of an insulating material other than the prepreg.

[0081] In addition, alternatively, at least one insulating layer among the plurality of insulating layers constituting the first insulating layer may include prepreg, and another insulating layer may include an insulating material other than prepreg.

[0082] For example, at least one of the plurality of insulating layers of the first insulating layer may be rigid or flexible. For example, at least one of the plurality of insulating layers of the first insulating layer may comprise glass or plastic. Specifically, at least one of the first insulating layers may comprise chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may comprise reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire. For example, at least one of the plurality of insulating layers of the first insulating layer may comprise an optically isotropic film. For example, at least one of the plurality of insulating layers of the first insulating layer may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA), etc. For example, at least one of the plurality of insulating layers of the first insulating layer may be formed from a material comprising an inorganic filler and an insulating resin. For example, at least one of the plurality of insulating layers of the first insulating layer may be a resin containing reinforcing materials such as inorganic fillers such as silica or alumina together with a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric Resin), BT, etc. For example, at least one of the plurality of insulating layers of the first insulating layer may be composed of RCC (Resin coated copper).

[0083] Each insulating layer of the first insulating layer may have a thickness in the range of 10 μm to 60 μm. For example, the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) may each have a thickness in the range of 10 μm to 60 μm. For example, the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) may each have a thickness in the range of 12 μm to 45 μm. For example, each of the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) may have a thickness in the range of 15 μm to 30 μm.

[0084] The respective thicknesses of the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) may represent the vertical distance between adjacent different circuit layers. If the respective thicknesses of the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) are less than 10 μm, the distance between adjacent different circuit layers becomes closer, and consequently, they may be susceptible to noise due to mutual signal interference. If the respective thicknesses of the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) exceed 60 μm, the overall thickness of the circuit board may increase. In addition, if the thickness of each of the first-1 insulating layer (211), the first-2 insulating layer (212), and the first-3 insulating layer (213) exceeds 60 μm, the thickness of the penetrating electrode increases accordingly, and the signal transmission distance increases accordingly, which may increase the signal transmission loss.

[0085] The first substrate layer (200) of the embodiment may include a first circuit layer. For example, the first substrate layer (200) may include a first circuit layer comprising a plurality of pattern layers each disposed on a plurality of insulating layers of the first insulating layer.

[0086] For example, the first substrate layer (200) may include a first pattern layer (221) disposed on the upper surface of the first-1 insulating layer (211). For example, the first substrate layer (200) may include a second pattern layer (222) disposed between the lower surface of the first-1 insulating layer (211) and the upper surface of the first-2 insulating layer (212). For example, the first substrate layer (200) may include a third pattern layer (223) disposed between the lower surface of the first-2 insulating layer (212) and the upper surface of the first-3 insulating layer (213). For example, the first substrate layer (200) may include a fourth pattern layer (224) disposed on the lower surface of the first-3 insulating layer (213).

[0087] The first pattern layer (221) may be disposed within the first-1 insulating layer (211). For example, at least a portion of the side surface of the first pattern layer (221) may be covered by the first-1 insulating layer (211). Preferably, the first pattern layer (221) may have a buried structure in which at least a portion of the side surface and the bottom surface are covered by the first-1 insulating layer (211), while the top surface is exposed.

[0088] The first pattern layer (221) may refer to a circuit layer positioned at the uppermost position among the circuit layers of the first substrate layer.

[0089] The first pattern layer (221) may have different heights depending on the location. For example, the first pattern layer (221) may include a plurality of pattern sections, and the height of at least one upper surface among the plurality of pattern sections may differ from the height of at least one upper surface. For example, at least one upper surface among the plurality of pattern sections of the first pattern layer (221) may have a step difference from at least one upper surface. Additionally, at least one lower surface among the plurality of pattern sections of the first pattern layer (221) may have a different height or step difference from at least one lower surface. Furthermore, the thickness of at least one of the plurality of pattern sections of the first pattern layer (221) may differ from the thickness of at least one other.

[0090] For example, the first substrate layer (200) may be divided into a plurality of regions in the width direction or length direction.

[0091] The first substrate layer (200) may include a first region (RB1) that overlaps vertically with the cavity (C) and a second region (RB2) other than the first region (RB1). In this case, the cavity (C) may include a region in which the width changes in the thickness direction. Furthermore, the first region (RB1) may refer to a region that overlaps vertically with the region having the largest width among the entire regions of the cavity (C). However, the embodiments are not limited thereto, and the first region (RB1) may refer to a region that overlaps vertically with the region having the smallest width among the entire regions of the cavity (C), or alternatively, may refer to a region that overlaps vertically with a region between the upper region and the lower region of the cavity (C).

[0092] The first pattern layer (221) includes a plurality of pattern portions. For example, the first pattern layer (221) may include a first pattern portion (221-1) disposed on the upper surface of a first region (RB1) of the first-1 insulating layer (211), and a second pattern portion (221-2) disposed on the upper surface of a second region (RB2) of the first-1 insulating layer (211). Additionally, the first substrate layer (200) includes a boundary region between the first region (RB1) and the second region (RB2). The boundary region may overlap with at least a portion of the first region (RB1) and / or the second region (RB2). The boundary region may refer to a region that overlaps vertically with at least a portion of the inner wall of the cavity (C). Furthermore, the first pattern layer (221) may include a third pattern portion (221-3) disposed in the boundary region.

[0093] At this time, the thickness of at least one of the first to third pattern portions (221-1, 221-2, 221-3) of the first pattern layer (221) may be different from the thickness of at least one other. Additionally, at least one upper surface of the first to third pattern portions (221-1, 221-2, 221-3) of the first pattern layer (221) may be located on a different plane from at least one other upper surface. Additionally, at least one lower surface of the first to third pattern portions (221-1, 221-2, 221-3) of the first pattern layer (221) may be located on a different plane from at least one other lower surface.

[0094] Preferably, the upper surface of the first pattern portion (221-1) may be positioned lower than the upper surface of the second pattern portion (221-2) and the upper surface of the third pattern portion (221-3). The first pattern portion (221-1) functions as a mounting pad on which a chip is mounted. In this embodiment, by positioning the first pattern portion (221-1) lower than the second pattern portion (221-2) and the third pattern portion (221-3), damage to the first pattern portion (221-1) can be prevented during the laser process for forming the cavity (C), thereby improving the reliability of the chip mounting.

[0095] The respective thicknesses of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3), as well as the positional relationship between their respective upper and lower surfaces, will be explained in detail below.

[0096] Meanwhile, the first circuit layer, comprising the first pattern layer (221), the second pattern layer (222), the third pattern layer (223), and the fourth pattern layer (224), may be formed from at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit layers may be formed from a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit layer may be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0097] Each of the first circuit layers may have a thickness in the range of 5 μm to 50 μm. For example, each of the first circuit layers may have a thickness in the range of 10 μm to 40 μm. For example, the first circuit layer may have a thickness in the range of 15 μm to 30 μm. If the thickness of the first circuit layer is less than 5 μm, the resistance of the circuit layer increases, and the signal transmission loss may increase accordingly. If the thickness of the first circuit layer is less than 5 μm, the allowable current of the signal that can be transmitted to the first circuit layer decreases, and problems with communication performance, such as a decrease in the signal transmission speed, may occur. In addition, if the thickness of the first circuit layer exceeds 50 μm, the line width of each pattern portion of the first circuit layer increases accordingly, and it may be difficult to miniaturize the pattern portion accordingly. In addition, if the thickness of the first circuit layer exceeds 50 μm, the thickness of the circuit board may increase accordingly.

[0098] Meanwhile, the first circuit layer described above can be manufactured using conventional circuit board manufacturing processes such as the Additive Process, Subtractive Process, Modified Semi-Additive Process (MSAP), and Semi-Additive Process (SAP), and a detailed description is omitted here.

[0100] Meanwhile, the first substrate layer (200) includes a through-hole. For example, the through-hole may be formed by penetrating each insulating layer of the first substrate layer (200).

[0101] For example, the penetration portion may include a first penetration electrode (231) that penetrates the first-1 insulating layer (211). For example, the penetration portion may include a first penetration electrode (231) that penetrates the first-1 insulating layer (211) and electrically connects the first pattern layer (221) and the second pattern layer (222).

[0102] Additionally, the penetration portion may include a second penetration electrode (232) that penetrates the first-second insulating layer (212). For example, the penetration portion may include a second penetration electrode (232) that penetrates the first-second insulating layer (212) and connects the second pattern layer (222) and the third pattern layer (223).

[0103] The above penetration portion may include a third penetration electrode (233) that penetrates the first-third insulating layer (213). For example, the above penetration portion may include a third penetration electrode (233) that penetrates the first-third insulating layer (213) and electrically connects the third pattern layer (223) and the fourth pattern layer (224).

[0104] The above-described through hole may be formed by filling the interior of the through hole penetrating each insulating layer of the first insulating layer with a conductive material. The through hole may be formed by any one of mechanical, laser, or chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used; when it is formed by laser processing, UV or CO2 laser methods may be used; and when it is formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened using a chemical agent including aminosilanes, ketones, etc.

[0105] Meanwhile, the above-mentioned laser processing is a cutting method that concentrates optical energy on a surface to melt and evaporate a portion of the material to form a desired shape, and can easily process complex shapes created by computer programs and can also process composite materials that are difficult to cut by other methods.

[0106] In addition, the processing by the above laser has the advantage of a cutting diameter of at least 0.005 mm and a wide range of processable thicknesses. The above laser drill may include a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. A YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, while a CO2 laser is a laser capable of processing only the insulating layer.

[0107] When the through hole is formed, the inside of the through hole can be filled with a conductive material to form each through electrode. The metal material forming the through electrode may be any one of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material may be performed using any one of electroless plating, electroplating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0109] The second substrate layer (300) may include a plurality of second insulating layers. For example, the second substrate layer (300) may include a second-1 insulating layer (311), a second-2 insulating layer (312), a second-3 insulating layer (313), and a second-4 insulating layer (314).

[0110] For example, the second substrate layer (300) may include four insulating layers. However, the embodiment is not limited thereto, and the second insulating layer constituting the second substrate layer (300) may include three or fewer insulating layers, or five or more insulating layers.

[0111] The above second-1 insulating layer (311) may be disposed on the first substrate layer (200). For example, the second-1 insulating layer (311) may be disposed on the upper surface of the first-1 insulating layer (211) disposed at the uppermost side of the first substrate layer (200).

[0112] The second-2 insulating layer (312) may be placed on the second-1 insulating layer (311). Additionally, the second-3 insulating layer (313) may be placed on the second-2 insulating layer (312). Additionally, the second-4 insulating layer (314) may be placed on the second-3 insulating layer (313).

[0113] The second insulating layer of the fourth layer constituting the second substrate layer (300) may include the same insulating material as the first insulating layer constituting the first substrate layer (200), but is not limited thereto.

[0114] The second substrate layer (300) may include a second circuit layer.

[0115] For example, the second circuit layer may include a fifth pattern layer (321) disposed on the upper surface of the second-1 insulating layer (311). For example, the second circuit layer may include a sixth pattern layer (322) disposed on the upper surface of the second-2 insulating layer (312). For example, the second circuit layer may include a seventh pattern layer (323) disposed on the upper surface of the second-3 insulating layer (313). For example, the second circuit layer may include an eighth pattern layer (324) disposed on the upper surface of the second-4 insulating layer (314).

[0116] At this time, the second circuit layer constituting the second substrate layer (300) may be a conductive antenna pattern layer that functions as an antenna. For example, the fifth pattern layer (321), the sixth pattern layer (322), the seventh pattern layer (323), and the eighth pattern layer (324) may be antenna parts that are connected to the first circuit layer of the first substrate layer (200) and, accordingly, function as antennas that transmit a transmission signal to the outside or receive a signal transmitted from the outside.

[0117] The second substrate layer (300) may include a second through-hole. For example, the second substrate layer (300) may include a plurality of through-hole electrodes that each penetrate the second insulating layer.

[0118] For example, the second penetration portion may include a fourth penetration electrode (331) penetrating the second-1 insulating layer (311). The fourth penetration electrode (331) may electrically connect the first pattern layer (221) of the first substrate layer (200) and the fifth pattern layer (321). For example, the second penetration portion may include a fifth penetration electrode (332) penetrating the second-2 insulating layer (312). The fifth penetration electrode (332) may electrically connect the fifth pattern layer (321) and the sixth pattern layer (322). For example, the second penetration portion may include a sixth penetration electrode (333) penetrating the second-3 insulating layer (313). The sixth penetration electrode (333) may electrically connect the sixth pattern layer (322) and the seventh pattern layer (323). For example, the second penetration may include a seventh penetration electrode (334) penetrating the second-fourth insulating layer (314). The seventh penetration electrode (334) may electrically connect the seventh pattern layer (323) and the eighth pattern layer (334).

[0119] Meanwhile, the second substrate layer (300) includes a cavity (C).

[0120] Accordingly, the second substrate layer (300) may include a region where the cavity (C) is formed, for example, a third region (RT1) that overlaps vertically with the cavity (C), and a fourth region (RT2) other than the third region (RT1).

[0121] The third region (RT1) may be a region that overlaps vertically with the first region (RB1) of the first substrate layer (200). The fourth region (RT2) may be a region that overlaps vertically with the second region (RB2) of the first substrate layer (200).

[0122] Additionally, in the third region (RT1) of the second substrate layer (300), a cavity (C) of a mounting space in which chips such as driving elements or passive elements are mounted on the package substrate may be formed. Furthermore, in the fourth region (RT2) of the second substrate layer (300), a second circuit layer having an antenna pattern that functions as an antenna may be formed.

[0123] At this time, if the circuit board (100) of the present invention is an antenna board applied to an antenna device, the circuit layers arranged in each layer of the circuit board can perform different functions.

[0124] For example, each of the first pattern layer (221), second pattern layer (222), third pattern layer (223), and fourth pattern layer (224) of the first circuit layer of the first substrate layer (200) may include a first circuit portion that overlaps vertically with the first region (RB1). The first circuit portion may overlap vertically with the cavity (C). The first circuit portion may function as a mounting pad on which a chip, such as a driving element or a passive element, is mounted, or as a terminal pad connecting the circuit board of the embodiment and an external board (e.g., the main board of a terminal).

[0125] Additionally, each of the first pattern layer (221), second pattern layer (222), third pattern layer (223), and fourth pattern layer (224) of the first circuit layer may include a second circuit portion that overlaps vertically with the second region (RB2). Furthermore, the second circuit portion may overlap vertically with the second circuit layers formed in the fourth region (RT2) of the second substrate layer (300).

[0126] In this case, in one embodiment, the second circuit portions of the first circuit layer can function as terminal pads together with the first circuit portion. And when the second circuit portion functions as a terminal pad together with the first circuit portion, the circuit board of the embodiment can function as an antenna only in the fourth region (RT2) of the second substrate layer (300). For example, if the second circuit portion of the first circuit layer is not an antenna pattern layer that functions as an antenna, the circuit board of the embodiment can transmit a transmission signal to the upper side of the fourth region (RT2) of the second substrate layer (300) or receive a signal transmitted from the upper side of the fourth region (RT2).

[0127] In addition, in another embodiment, the second circuit portion is connected to the second circuit layers disposed in the fourth region (RT2) of the second substrate layer (300), and accordingly, can function as an antenna pattern that performs a signal transmission or signal reception function.

[0128] For example, the second circuit layer in the fourth region (RT2) of the second substrate layer (300) may be referred to as the first antenna pattern layer, and the second circuit portion disposed in the region vertically superimposed with the second region (RB2) among the first circuit layers of the first substrate layer (200) may be the second antenna pattern layer connected to the first antenna pattern layer. Accordingly, in the embodiment, a signal can be transmitted in both directions of the circuit board, or a signal transmitted from both directions of the circuit board can be received. For example, in the embodiment, a signal can be transmitted to the upper side of the first antenna pattern layer, and a signal can be transmitted to the lower side of the second antenna pattern layer. In addition, in the embodiment, a signal transmitted from the upper side of the first antenna pattern layer can be received, and a signal transmitted from the lower side of the second antenna pattern layer can be received.

[0129] Meanwhile, in the embodiment, it was stated that all first circuit portions that overlap vertically with the first region (RB1) among the first circuit layers of the first substrate layer (200) function as mounting pads or terminal pads, but this is not limited thereto. For example, some of the first circuit portions disposed in the first region (RB1) of the first substrate layer (200) may function as mounting pads or terminal pads, and the remaining portions may function as antenna patterns together with the second antenna pattern layer.

[0130] Meanwhile, the circuit board (100) may include a protective layer. For example, the circuit board (100) may include a first protective layer (110) disposed on the lower surface of an insulating layer disposed at the lowest side of the first substrate layer (200). For example, the circuit board (100) may include a second protective layer (120) disposed on the upper surface of an insulating layer disposed at the upper side of the second substrate layer (300).

[0131] The first protective layer (110) and the second protective layer (120) may be resist layers. For example, the first protective layer (110) and the second protective layer (120) may be solder resist layers containing organic polymer materials. As an example, the first protective layer (110) and the second protective layer (120) may include an epoxy acrylate-based resin. Specifically, the first protective layer (110) and the second protective layer (120) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic-based monomer, etc. However, the embodiments are not limited thereto, and the first protective layer (110) and the second protective layer (120) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0132] The thickness of the first protective layer (110) and the second protective layer (120) may be 1 μm to 20 μm. The thickness of the first protective layer (110) and the second protective layer (120) may be 1 μm to 15 μm. For example, the thickness of the first protective layer (110) and the second protective layer (120) may be 5 μm to 20 μm. If the thickness of the first protective layer (110) and the second protective layer (120) exceeds 20 μm, the thickness of the circuit board may increase. If the thickness of the first protective layer (110) and the second protective layer (120) is less than 1 μm, electrical reliability or physical reliability may be reduced as the pattern layers included in the circuit board are not stably protected.

[0133] Meanwhile, the circuit board (100) includes a barrier layer (130). The barrier layer (130) may be formed in an area that overlaps vertically with the cavity (C).

[0134] Specifically, the barrier layer (130) may be disposed on the first pattern portion (221-1) of the first pattern layer (221). Preferably, the barrier layer (130) may be disposed on the surface of the first pattern portion (221-1) exposed through the cavity (C). At this time, the first pattern portion (221-1) in FIGS. 1 and 2 has a structure in which the upper surface is exposed through the cavity (C). For example, in one embodiment, the side and lower surfaces of the first pattern portion (221-1) are covered by the first insulating layer, and the upper surface is exposed through the cavity (C). And, the barrier layer (130) may be disposed on the upper surface of the first pattern portion (221-1) exposed through the cavity (C).

[0135] The barrier layer (130) may also be described as a surface treatment layer for protecting the upper surface of the first pattern portion (221-1) exposed through the cavity (C). The barrier layer (130) may have different layer structures depending on the surface treatment method. For example, the barrier layer (130) may be formed using the ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) method. Accordingly, the barrier layer (130) may include first to third barrier layers. Alternatively, the barrier layer (130) may be formed using the ENIG (Electroless Nickel Immersion Gold) method. Accordingly, the barrier layer (130) may include first and second barrier layers. The detailed layer structure of the barrier layer (130) will be described in more detail below.

[0137] Below, the thickness and positional relationship of each pattern portion of the cavity (C) and the first pattern layer (221) of the embodiment, and the layer structure of the barrier layer (130) will be explained in detail.

[0138] Referring to FIG. 2, the cavity (C) in the embodiment penetrates the second substrate layer (300). For example, the cavity (C) penetrates the second insulating layer. If the second insulating layer has a plurality of layer structures, the cavity (C) can penetrate the plurality of second insulating layers in common. The cavity (C) may include a plurality of parts. For example, the cavity (C) may be divided into a plurality of parts in the thickness direction. In this case, the plurality of parts of the cavity (C) may be divided based on the slope of the inner wall (IW) of the cavity (C).

[0139] For example, the cavity (C) may include a first part (P1) adjacent to the upper surface of the second substrate layer (300). Additionally, the cavity (C) may include a second part (P2) adjacent to the lower surface of the second substrate layer (300) and below the first part (P1).

[0140] At this time, the first part (P1) may include a region in which the width decreases as it approaches the lower surface of the second substrate layer (300). For example, the inner wall (IW1) of the first part (P1) may have a first slope in which the width decreases as it approaches the first substrate layer (200). The first slope of the inner wall (IW) of the first part (P1) may refer to the interior angle between a virtual straight line connected to the inner wall (IW) and a reference line (BL). The reference line (BL) may be parallel to the upper surface of the first substrate layer (200) that overlaps perpendicularly with the cavity (C).

[0141] Meanwhile, the first inclination (θ1) of the inner wall (IW1) of the first part (P1) may have a range between 115 degrees and 150 degrees. For example, the first inclination (θ1) of the inner wall (IW1) of the first part (P1) may have a range between 118 degrees and 148 degrees. For example, the first inclination (θ1) of the inner wall (IW1) of the first part (P1) may have a range between 120 degrees and 145 degrees.

[0142] If the first inclination (θ1) of the inner wall (IW1) of the first part (P1) is less than 115 degrees, the process time required to form the cavity (C) according to the embodiment may increase. For example, the fact that the first inclination (θ1) of the inner wall (IW1) of the first part (P1) is less than 115 degrees means that the laser beam width (e.g., laser mask) used in the process of forming the first cavity described below is small, and the time required to form the cavity (C) may increase accordingly.

[0143] Additionally, if the first inclination (θ1) of the inner wall (IW1) of the first part (P1) is greater than 150, the circuit integration density may decrease as the upper width of the cavity (C) increases. For example, the lower width of the cavity (C) is determined to correspond to the placement space of the device to be mounted, and the cavity formation process is carried out centered on the determined lower width. At this time, if the upper width of the cavity (C) increases, it means that the space wasted meaninglessly increases, and accordingly, the placement space of the circuit layer may decrease by the amount that the upper width of the cavity (C) has increased. Accordingly, in the embodiment, the first inclination (θ1) of the inner wall (IW1) of the first part (P1) is set to have a range between 115 degrees and 150 degrees.

[0144] Meanwhile, the cavity (C) of the embodiment includes a second part (P2) below the first part (P1). The second part (P2) may include a region in which the width decreases toward the lower surface of the second substrate layer (300). For example, the second part (P2) may include an inner wall (IW2) that has a second slope (θ2) different from the first slope (θ1) of the inner wall (IW1) of the first part (P1), while the width decreases toward the first substrate layer (200). For example, the second slope (θ2) of the second part (P2) may be smaller than the first slope (θ1) of the first part (P1).

[0145] At this time, the second slope (θ2) may refer to the slope of the inner wall (IW2) of the second part (P2). For example, the second slope (θ2) may refer to the interior angle between a virtual straight line extending from the inner wall (IW2) of the second part (P2) and a reference line (BL).

[0146] The second slope (θ2) of the inner wall (IW2) of the second part (P2) may be smaller than the first slope (θ1) and may have a range between 91 and 120 degrees. For example, the second slope (θ2) of the inner wall (IW2) of the second part (P2) may be smaller than the first slope (θ1) and may have a range between 95 and 118 degrees. For example, the second slope (θ2) of the inner wall (IW2) of the second part (P2) may be smaller than the first slope (θ1) and may have a range between 98 and 115 degrees.

[0147] If the second inclination (θ2) of the inner wall (IW2) of the second part (P2) is less than 91 degrees, a chip such as a driving element or a passive element may not be stably placed within the cavity (C). Specifically, if the second inclination (θ2) of the inner wall (IW2) of the second part (P2) is less than 91 degrees, the second part (P2) may have a shape in which its width decreases as it approaches the upper surface of the second substrate layer (300), and sufficient space for placing the chip may not be provided in the middle region of the cavity (C). As a result, the inner wall of the cavity (C) and the chip may come into contact in the middle region of the cavity (C), and this may cause problems such as the mounting position of the chip being misaligned or the chip being mounted in a tilted state during the chip mounting process.

[0148] In addition, if the second inclination (θ2) of the inner wall (IW2) of the second part (P2) is greater than 120 degrees, the cavity (C) may be formed with a size larger than the space required for the device mounting space. Accordingly, the fact that the second inclination (θ2) of the inner wall (IW2) of the second part (P2) is greater than 120 degrees means that there is a large difference between the width of the lower region and the width of the upper region of the second part (P2). And, the width of the general cavity determines the width of the lower region of the second part (P2) in correspondence with the size of the chip. If the second inclination (θ2) of the inner wall (IW2) of the second part (P2) is greater than 120 degrees, the space or area occupied by the cavity (C) relative to the size of the chip may increase, and as a result, problems may arise such as a decrease in circuit integration density or an increase in the width in the horizontal direction or the thickness in the vertical direction of the circuit board.

[0149] Meanwhile, the lengths of the first part (P1) and the second part (P2) of the cavity (C) may differ from each other. For example, the first part (P1) of the cavity (C) may have a first length (L1), and the second part (P2) may have a second length (L2) that is longer than the first length (L1). In this case, the first length (L1) may refer to the depth in the vertical direction of the first part (P1). For example, the first length (L1) may refer to the vertical distance of the first part (P1). Additionally, the second length (L2) may refer to the depth of the second part (P2). For example, the second length (L2) may refer to the depth or vertical distance in the vertical direction of the second part (P2).

[0150] At this time, the second length (L2) may be at least 1.5 times the first length (L1). For example, the second length (L2) may be at least 3 times the first length (L1). For example, the second length (L2) may be at least 5 times the first length (L1). For example, the second length (L2) may be at least 10 times the first length (L1).

[0151] For example, the second length (L2) may satisfy a range between 1.5 times and 30 times the first length (L1). For example, the second length (L2) may satisfy a range between 3 times and 28 times the first length (L1). For example, the second length (L2) may satisfy a range between 5 times and 25 times the first length (L1). For example, the second length (L2) may satisfy a range between 10 times and 20 times the first length (L1).

[0152] At this time, if the second length (L2) is less than 1.5 times the first length (L1), the effect resulting from the difference between the first slope of the first part (P1) and the second slope of the second part (P2) may be insufficient. Additionally, if the second length (L2) is 30 times or more the first length (L1), the thickness of the second substrate layer (300) to satisfy this increases, and the overall thickness of the circuit board may increase accordingly.

[0153] Meanwhile, the cavity (C) of the embodiment may include a third part (P3) below the second part (P2). The third part (P3) may be located lower than the second substrate layer (300). The third part (P3) of the cavity (C) may refer to a configuration formed on the first substrate layer (200) rather than a configuration formed on the second substrate layer (300). For example, the third part (P3) of the cavity (C) may overlap horizontally with at least a portion of the first pattern layer (221) of the first substrate layer (200). That is, the third part (P3) may be formed by removing at least one pattern portion of the first pattern layer (221) by etching. Furthermore, the third part (P3) may be formed by removing a portion of the first region (RB1) of the first insulating layer (211) disposed on the uppermost side of the first substrate layer (200) together with a portion of the first pattern layer (221). Specifically, the third part (P3) may be a portion formed by removing a laser stopper layer (e.g., a portion of the third pattern portion (221-3) of the first pattern layer (221)) that was formed in a region vertically overlapping with the cavity (C) of the first pattern layer (221) of the first substrate layer (200).

[0154] For example, the total depth of the cavity (C) may be greater than the total thickness of the second insulating layer constituting the second substrate layer (300). For example, in the first embodiment, the depth of the cavity (C) may be greater than the total thickness of the second insulating layer plus the thickness of the third pattern portion (221-3).

[0155] Accordingly, the bottom surface of the cavity (C) can be positioned lower than the bottom surface of the second substrate layer (300).

[0156] The third part (P3) may have a third slope. The third slope may refer to the slope of the inner wall (IW3) of the third part (P3). In this case, the inner wall (IW1) of the first part (P1) and the inner wall (IW2) of the second part (P2) refer to the inner wall of the second insulating layer constituting the second substrate layer (300). Alternatively, the inner wall (IW3) of the third part (P3) in the first embodiment may refer to the slope of the side of the third pattern portion (221-3) of the first pattern layer (221).

[0157] Specifically, the first pattern layer (221) of the first substrate layer (200) includes a third pattern portion (221-3) arranged to surround the boundary region between the first region (RB1) and the second region (RB2). The third pattern portion (221-3) may be part of a stopper layer used as a laser stopper in the laser process for forming the cavity (C). Furthermore, the lower width of the cavity (C) may be smaller than the width of the stopper layer. If the cavity (C) is formed with a lower width equal to the width of the stopper layer, a problem may arise where a portion of the upper surface of the first-1 insulating layer (211) adjacent to the edge of the stopper layer is laser-processed due to process deviations in the laser process, and a reliability problem may occur as a result. Accordingly, in the embodiment, the cavity (C) has a lower width smaller than the width of the stopper layer. Accordingly, a portion of the stopper layer may have its upper surface exposed through the cavity (C), while the remaining portion may not have its upper surface exposed through the cavity (C). At this time, the stopper layer with its upper surface exposed through the cavity (C) can be removed by etching to form a third part (P3) of the cavity (C). Furthermore, the stopper layer with its upper surface not exposed through the cavity (C) is not removed during the etching process, thereby forming a third pattern portion (221-3) of the first pattern layer (221). Additionally, the inner wall (IW3) of the third part (P3) of the cavity (C) may represent the angle of inclination of the side of the third pattern portion (221-3). The third inclination of the inner wall (IW3) of the third part (P3) may be determined by the etching conditions of the stopper layer.

[0158] For example, in the first embodiment, the third slope of the inner wall (IW3) of the third part (P3) may be perpendicular to the reference line (BL).

[0160] Meanwhile, in the embodiment, the upper surface of the first substrate layer (200) may have a step. For example, the upper surface of the first-1 insulating layer (211) may have a step. Specifically, the upper surface of the first-1 insulating layer (211) may include a first upper surface (211T1) and a second upper surface (211T2) having a step with respect to the first upper surface (211T1). The first upper surface (211T1) of the first-1 insulating layer (211) may form the lower surface or bottom surface of the cavity (C).

[0161] For example, the upper surface of the first-1 insulating layer (211) may include a first upper surface (211T1) that overlaps vertically with the cavity (C) and a second upper surface (211T2) that does not overlap vertically with the cavity (C). That is, the first upper surface (211T1) of the first-1 insulating layer (211) may correspond to the first region (RB1) of the first substrate layer (200), and the second upper surface (211T2) of the first-1 insulating layer (211) may correspond to the second region (RB2) of the first substrate layer (200). Additionally, the first upper surface (211T1) of the first-1 insulating layer (211) may represent a portion that constitutes the lower surface of the cavity (C) and does not come into contact with the second substrate layer (300). Additionally, the second upper surface (211T2) of the first insulating layer (211) may have a step difference with the lower surface of the cavity (C) and may refer to a portion in contact with the second substrate layer (300). The second upper surface (211T2) of the first insulating layer (211) may not overlap perpendicularly with the first upper surface (211T1).

[0162] At this time, the first upper surface (211T1) may include a first overlapping area that is vertically overlapping with the first pattern portion (221-1) and a first non-overlapping area that is not vertically overlapping with the first pattern portion (221-1).

[0163] Additionally, the second upper surface (211T2) includes a second overlapping area vertically overlapping with the second pattern part (221-2), a third overlapping area vertically overlapping with the third pattern part (221-3), and a second non-overlapping area that is not vertically overlapping with the second pattern part (221-2) and the third pattern part (221-3).

[0164] At this time, in the circuit board of the comparative example, the first non-overlapping region of the first upper surface (211T1) of the first-1 insulating layer (211) is located on the same plane as the second non-overlapping region of the second upper surface (211T2). Alternatively, in the embodiment, the first non-overlapping region of the first upper surface (211T1) of the first-1 insulating layer (211) may be located on a different plane from the second non-overlapping region of the second upper surface (211T2). For example, the first non-overlapping region of the first upper surface (211T1) of the first-1 insulating layer (211) may be located lower than the second non-overlapping region of the second upper surface (211T2). For example, in the first embodiment, the first non-overlapping region may be located lower than the second non-overlapping region by the thickness of the third pattern portion (221-3). In the following description, the first upper surface (211T1) of the first-1 insulating layer (211) is described as representing the first non-overlapping region, and the second upper surface (211T2) of the first-1 insulating layer (211) is described as representing the second non-overlapping region.

[0165] The first upper surface (211T1) of the first-1 insulating layer (211) may be positioned higher than the lower surface of the second pattern portion (221-2) of the first pattern layer (221). The first upper surface (211T1) of the first-1 insulating layer (211) may be positioned on the same plane as the lower surface of the third pattern portion (221-3) of the first pattern layer (221). At this time, being positioned on the same plane may mean that the height difference between them is 1 μm or less, or 0.5 μm or less, or 0.1 μm or less. Alternatively, being positioned on the same plane may mean that the height difference between them is 5% or less, or 3% or less, or 1% or less of the thickness of the third pattern portion (221-3).

[0166] The second upper surface (211T2) of the first-1 insulating layer (211) may be positioned higher than the upper surface of the first pattern portion (221-1) of the first pattern layer (221). The second upper surface (211T2) of the first-1 insulating layer (211) may be positioned on the same plane as the upper surface of the third pattern portion (221-3). At this time, being positioned on the same plane may mean that the height difference between them is 1 μm or less, or 0.5 μm or less, or 0.1 μm or less. Alternatively, being positioned on the same plane may mean that the height difference between them is 5% or less, or 3% or less, or 1% or less of the thickness of the third pattern portion (221-3).

[0167] The first upper surface (211T1) and the second upper surface (211T2) of the first-1 insulating layer (211) may have different surface roughness. For example, the first upper surface (211T1) of the first-1 insulating layer (211) may have a surface roughness corresponding to the surface roughness of the lower surface of the first pattern layer (221) formed through a plating process. Alternatively, the second upper surface (211T2) of the first-1 insulating layer (211) may have a surface roughness corresponding to the surface roughness of the lower surface of the second-1 insulating layer (311).

[0168] In the first embodiment, the first pattern portion (221-1) of the first pattern layer (221) is placed in a first region (RB1) that overlaps vertically with the cavity (C). Additionally, the second pattern portion (221-2) of the first pattern layer (221) is placed in a second region (RB2) that does not overlap vertically with the cavity (C). Furthermore, the third pattern portion (221-3) of the first pattern layer (221) is placed in a boundary region between the first region (RB1) and the second region (RB2).

[0169] Any one of the first pattern part (221-1), the second pattern part (221-2), and the third pattern part (221-3) may have a thickness different from the other. The upper surface of any one of the first pattern part (221-1), the second pattern part (221-2), and the third pattern part (221-3) may be located on a different plane from the upper surface of the other. For example, the lower surface of any one of the first pattern part (221-1), the second pattern part (221-2), and the third pattern part (221-3) may be located on a different plane from the lower surface of the other.

[0170] Hereinafter, with reference to the drawings, the thickness of each of the first pattern part (221-1), the second pattern part (221-2), and the third pattern part (221-3) of the first pattern layer (221), their positional relationship, and the layer structure of the barrier layer (130) will be described.

[0172] FIG. 3a is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to a first embodiment, FIG. 3b is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to a second embodiment, and FIG. 3c is an enlarged view of the arrangement area of ​​the first pattern layer of a circuit board according to a third embodiment.

[0173] Referring to FIG. 3a, the first pattern layer (221) includes a first pattern portion (221-1), a second pattern portion (221-2), and a third pattern portion (221-3).

[0174] The first pattern portion (221-1) is positioned in the first region (RB1) of the first-1 insulating layer (211). That is, the first pattern portion (221-1) can be vertically overlapped with the cavity (C). The upper surface of the first pattern portion (221-1) may be positioned lower than the upper surfaces of other pattern portions of the first pattern layer (221) (e.g., the second pattern portion (221-2) and the third pattern portion (221-3)). For example, the upper surface of the first pattern portion (221-1) may be positioned lower than the second upper surface (211T2) of the first-1 insulating layer (211). For example, the upper surface of the first pattern portion (221-1) may be positioned lower than the lowest side of the second substrate layer (300). The first pattern portion (221-1) may have a first thickness (T1). Specific characteristics of the first thickness (T1) will be described below.

[0175] The second pattern portion (221-2) may be placed in the second region (RB2) of the first-1 insulating layer (211). The second pattern portion (221-2) may not overlap vertically with the cavity (C). The upper surface of the second pattern portion (221-2) may be positioned higher than the upper surface of the first pattern portion (221-1). The upper surface of the second pattern portion (221-2) may be positioned higher than the first upper surface (211T1) of the first-1 insulating layer (211). The upper surface of the second pattern portion (221-2) may be located on the same plane as the upper surface of the third pattern portion (221-3). The upper surface of the second pattern portion (221-2) may be located on the same plane as the second upper surface (211T2) of the first-1 insulating layer (211). The lower surface of the second pattern part (221-2) may be positioned lower than the first upper surface (211T1) of the first-1 insulating layer (211). The lower surface of the second pattern part (221-2) may be positioned lower than the upper surface of the first pattern part (221-1). The lower surface of the second pattern part (221-2) may be positioned on the same plane as the lower surface of the first pattern part (221-1). The lower surface of the second pattern part (221-2) may be positioned lower than the lower surface of the third pattern part (221-3). The second pattern part (221-2) may have a plurality of layer structures. For example, the second pattern part (221-2) may have a two-layer structure formed through a two-stage plating process. At this time, the statement that the second pattern part (221-2) has a two-layer structure may mean that when the second pattern part (221-2) is formed by an SAP or MSAP process, the electrolytic plating layer, excluding the copper foil layer and chemical copper plating layer used as a seed layer, is composed of two layers. At this time, the second pattern part (221-2) may have a second thickness (T2) greater than the first thickness (T1). At this time, being located on the same plane may mean that the height difference between them is 1 μm or less, or 0.5 μm or less, or 0.1 μm or less.Or, being located on the same plane may mean that the height difference between them is 5% or less, 3% or less, or 1% or less of the thickness of the first pattern part (221-1), the second pattern part (221-2), or the third pattern part (221-3).

[0176] The third pattern portion (221-3) may be formed in the boundary area between the first region (RB1) and the second region (RB2). Accordingly, a portion of the third pattern portion (221-3) may overlap vertically with the cavity (C), or alternatively, may not overlap vertically. Preferably, at least a portion of the third pattern portion (221-3) may overlap vertically with at least a portion of the inner wall (IW) of the cavity (C).

[0177] The upper surface of the third pattern section (221-3) may be positioned higher than the upper surface of the first pattern section (221-1). The upper surface of the third pattern section (221-3) may be positioned higher than the first upper surface (211T1) of the first-1 insulating layer (211). The upper surface of the third pattern section (221-3) may be positioned on the same plane as the upper surface of the second pattern section (221-2). The upper surface of the third pattern section (221-3) may be positioned on the same plane as the second upper surface (211T2) of the first-1 insulating layer (211). The lower surface of the third pattern section (221-3) may be positioned on the same plane as the upper surface of the first-1 insulating layer (211) or the upper surface of the first pattern section (221-1). The lower surface of the third pattern part (221-3) may be positioned higher than the lower surface of the first pattern part (221-1) and the lower surface of the second pattern part (221-2). The third pattern part (221-3) may have a third thickness (T3) that is smaller than the second thickness (T2) of the second pattern part (221-2). At this time, being located on the same plane may mean that the height difference between them is 1 μm or less, or 0.5 μm or less, or 0.1 μm or less. Alternatively, being located on the same plane may mean that the height difference between them is 5% or less, or 3% or less, or 1% or less of the thickness of the first pattern part (221-1), the second pattern part (221-2), or the third pattern part (221-3).

[0178] The first thickness (T1) of the first pattern part (221-1) can be determined based on the second thickness (T2) of the second pattern part (221-2).

[0179] That is, the second thickness (T2) of the second pattern portion (221-2) may correspond to the thickness of other pattern layers, excluding the first pattern portion (221-1) and the third pattern portion (221-3), in the circuit board of the embodiment. At this time, "corresponding to thickness" may mean that the difference between the second thickness (T2) of the second pattern portion (221-2) and the thickness of other pattern layers is 10% or less, 5% or less, 3% or less, or 1% or less of the thickness of other pattern layers.

[0180] For example, the second thickness (T2) of the second pattern part (221-2) may satisfy a range of 5 µm to 50 µm. For example, the second thickness (T2) of the second pattern part (221-2) may satisfy a range of 10 µm to 40 µm. For example, the second thickness (T2) of the second pattern part (221-2) may have a thickness in the range of 15 µm to 30 µm.

[0181] And, the sum (T1+T3) of the first thickness (T1) of the first pattern part (221-1) and the third thickness (T3) of the third pattern part (221-3) in the first embodiment can correspond to the second thickness (T2) of the second pattern part (221-2).

[0182] That is, in the embodiment, through a two-stage plating process, the first pattern layer (221) is configured to include a first metal layer and a second metal layer, and the first metal layer formed in the two-stage plating process is used as the first pattern part (221-1) and the third pattern part (221-3), and the second metal layer is used as the second pattern part (221-2) and the third pattern part (221-3).

[0183] Accordingly, in the embodiment, the first pattern portion (221-1) may include only the first metal layer, and the third pattern portion (221-3) may include only the second metal layer. Also, the second pattern portion (221-2) may include both the first metal layer (221-21) and the second metal layer (221-22). Accordingly, the first metal layer (221-21) of the second pattern portion (221-2) may have a first thickness (T1) corresponding to the first pattern portion (221-1). At this time, "corresponding to thickness" means that the difference between the thickness of the first metal layer (221-21) of the second pattern portion (221-2) and the first thickness (T1) is 10% or less, 5% or less, 3% or less, or 1% or less of the first thickness (T1). The second metal layer (221-22) of the second pattern portion (221-2) may have a third thickness (T3) corresponding to the third pattern portion (221-3). At this time, "corresponding to thickness" may mean that the difference between the thickness of the second metal layer (221-22) and the third thickness (T3) is 10% or less, 5% or less, 3% or less, or 1% or less of the third thickness (T3).

[0184] As described above, in the embodiment, the first pattern layer (221) is formed by dividing it into two layers, and each is utilized as a mounting pad and a laser stopper layer, respectively. Accordingly, in the embodiment, the first pattern portion (221-1) corresponding to the mounting pad and the third pattern portion (221-3) corresponding to the stopper layer may have a structure in which they are arranged on different planes. Through this, in the embodiment, damage to the first pattern portion (221-1), which is the mounting pad, can be prevented during the process of forming the cavity (C).

[0185] The first thickness (T1) of the first pattern part (221-1) may satisfy a thickness of 51% to 85% of the second thickness (T2) of the second pattern part (221-2). The first thickness (T1) of the first pattern part (221-1) may satisfy a range of 53% to 83% of the second thickness (T2) of the second pattern part (221-2). For example, the first thickness (T1) of the first pattern part (221-1) may satisfy a range of 55% to 80% of the second thickness (T2) of the second pattern part (221-2).

[0186] If the first thickness (T1) of the first pattern part (221-1) is less than 51% of the second thickness (T2) of the second pattern part (221-2), the third thickness (T3) of the third pattern part (221-3) may be increased accordingly. And if the third thickness (T3) of the third pattern part (221-3) is increased, after the formation of the cavity (C) is completed, the time required to remove the third pattern part (221-3) by etching in the area that overlaps vertically with the cavity (C) increases, and the processability may be reduced accordingly. Additionally, if the third thickness (T3) of the third pattern part (221-3) increases, a portion of the third pattern part (221-3) in the area that overlaps vertically with the cavity (C) may not be removed during the etching process, and this may cause reliability issues such as a short circuit resulting from the first pattern part (221-1) being electrically connected to the third pattern part (221-3). Furthermore, if the first thickness (T1) of the first pattern part (221-1) is less than 51% of the second thickness (T2) of the second pattern part (221-2), the allowable current of the first pattern part (221-1) decreases, and communication performance may be degraded accordingly. Meanwhile, if the first thickness (T1) of the first pattern part (221-1) exceeds 85% of the second thickness (T2) of the second pattern part (221-2), the third thickness (T3) of the third pattern part (221-3) may be reduced accordingly. Accordingly, in the laser process for forming the cavity (C), a problem may occur in which the laser penetrates the third pattern part (221-3), and consequently, a problem may occur in which the upper surface of the first-1 insulating layer (211) is damaged in the process for forming the cavity (C). Preferably, the first thickness (T1) of the first pattern part (221-1) may satisfy a range of 2.7 μm to 42.5 μm. For example, the first thickness (T1) of the first pattern part (221-1) may satisfy a range of 5.1 μm to 33.2 μm.For example, the first thickness (T1) of the first pattern portion (221-1) may satisfy a range of 7.65㎛ to 25.5㎛.

[0187] The third thickness (T3) of the third pattern part (221-3) may satisfy a thickness of 15% to 49% of the second thickness (T2) of the second pattern part (221-2). The third thickness (T3) of the third pattern part (221-3) may satisfy a range of 17% to 47% of the second thickness (T2) of the second pattern part (221-2). For example, the third thickness (T3) of the third pattern part (221-3) may satisfy a range of 20% to 45% of the second thickness (T2) of the second pattern part (221-2).

[0188] If the third thickness (T3) of the third pattern part (221-3) is less than 15% of the second thickness (T2) of the second pattern part (221-2), a problem may occur in which the laser penetrates the third pattern part (221-3) during the laser process of forming the cavity (C), and consequently, a problem may occur in which the upper surface of the first insulating layer (211) is damaged during the process of forming the cavity (C).

[0189] If the third thickness (T3) of the third pattern part (221-3) is greater than 49% of the second thickness (T2) of the second pattern part (221-2), the time required to remove the third pattern part (221-3) by etching in the area vertically overlapping with the cavity (C) increases, and the processability may be reduced accordingly. Additionally, if the third thickness (T3) of the third pattern part (221-3) is greater than 49% of the second thickness (T2) of the second pattern part (221-2), a portion of the third pattern part (221-3) in the area vertically overlapping with the cavity (C) may not be removed during the etching process, and this may result in reliability issues such as a short circuit caused by the first pattern part (221-1) being electrically connected to the third pattern part (221-3). If the third thickness (T3) of the third pattern part (221-3) is greater than 49% of the second thickness (T2) of the second pattern part (221-2), it may be difficult to perform precise etching in the first metal layer and the second metal layer of the first pattern layer (221) to the thickness corresponding to the second metal layer, and accordingly, as the second metal layer is also partially etched in the etching process, a communication performance problem may occur as the thickness of the first pattern part (221-1) decreases.

[0190] Meanwhile, although it was explained above that the thickness (T1) of the first pattern section (221-1) is greater than the thickness (T3) of the third pattern section (221-3), the thickness of the first pattern section (221-1) and the thickness of the third pattern section (221-3) may be the same. For example, the thicknesses of the first metal layer (221-21) and the second metal layer (221-22) of the second pattern section (221-2) may be the same. However, the communication performance of the circuit board improves as the thickness of the first pattern section (221-1) increases, and accordingly, in the embodiment, the thickness of the first pattern section (221-1) is made larger relative to the thickness of the third pattern section (221-3). Through this, in the embodiment, communication performance can be maximized by increasing the thickness of the first pattern part (221-1) while reducing the time required for the etching process of the third pattern part (221-3).

[0191] As described above, in the embodiment, during the process of forming the first pattern layer (221), the first pattern layer (221) is formed to have a two-layer structure including a first metal layer and a second metal layer through two-stage plating, and either of the first metal layer and the second metal layer is used as a mounting pad and the other as a stopper, and both are used to form a second pattern portion. Through this, the reliability problem caused by the mounting pad and the stopper being placed on the same plane can be resolved in the embodiment. For example, in the comparative example, in order to prevent damage to the mounting pad during the laser process of forming the cavity, a separate protective layer (not shown) is formed on the mounting pad, and a process of removing it is performed later. In contrast, in the embodiment, a portion of the third pattern portion (221-3) used as the laser stopper can be utilized as a protective portion for the first pattern portion (221-1) which is the mounting pad, and accordingly, the process of forming an additional protective layer to protect the first pattern portion (221-1) can be omitted while preventing damage to the first pattern portion (221-1) which is the mounting pad during the process of forming the cavity.

[0192] Meanwhile, in the drawing, the first pattern portion (221-1), the second pattern portion (221-2), and the third pattern portion (221-3) are shown as being entirely embedded in the first insulating layer (more clearly, the first-1 insulating layer (211)), but are not limited thereto. Specifically, in the drawing, the entire area of ​​each side of the first pattern portion (221-1), the second pattern portion (221-2), and the third pattern portion (221-3) is shown as being covered by the first insulating layer (more clearly, the first-1 insulating layer (211)), but are not limited thereto.

[0193] For example, only a portion of the total area in the thickness direction of each of the first pattern portion (221-1), second pattern portion (221-2), and third pattern portion (221-3) may be embedded in the first insulating layer. And, the remaining portion of the total area in the thickness direction of the first pattern portion (221-1), excluding the aforementioned portion, may protrude above the first upper surface (211T1). And, the remaining portion of the total area in the thickness direction of the second pattern portion (221-2) and third pattern portion (221-3), excluding the aforementioned portion, may be embedded within the second insulating layer (clearly, the second-1 insulating layer (311)).

[0194] However, in the embodiment, in order to ensure physical and electrical reliability of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3), the thickness of each of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3) is greater than the thickness of the remaining area. For example, at least 80% of the total area in the thickness direction of each of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3) may be embedded within the first insulating layer. For example, at least 90% of the total area in the thickness direction of each of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3) may be embedded within the first insulating layer. For example, each of the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3) may have more than 98% of its total area in the thickness direction embedded within the first insulating layer.

[0195] Meanwhile, other pattern layers excluding the first pattern layer (221) may have a second thickness (T2) of the second pattern portion (221-2) of the first pattern layer (221).

[0196] Specifically, the second pattern layer (222), the third pattern layer (223), the fourth pattern layer (224), the fifth pattern layer (321), the sixth pattern layer (322), the seventh pattern layer (323), and the eighth pattern layer (324) may have a second thickness (T2) equal to the second pattern portion (221-2) of the first pattern layer (221). At this time, having the same thickness means that the difference from the second thickness (T2) is 10% or less, 5% or less, 3% or less, or 1% or less of the second thickness (T2).

[0197] However, the second pattern layer (222), third pattern layer (223), fourth pattern layer (224), fifth pattern layer (321), sixth pattern layer (322), seventh pattern layer (323) and eighth pattern layer (324) may have a layer structure different from the second pattern portion (221-2) of the first pattern layer (221). For example, the second pattern portion (221-2) of the first pattern layer (221) is formed to have the second thickness (T2) through a two-stage plating process to distinguish between the stopper and the mounting pad. Unlike the second pattern layer (222), third pattern layer (223), fourth pattern layer (224), fifth pattern layer (321), sixth pattern layer (322), seventh pattern layer (323), and eighth pattern layer (324) of the first pattern layer (221), layer separation is unnecessary, and accordingly, they can be formed through a single plating process. For example, the second pattern layer (222), third pattern layer (223), fourth pattern layer (224), fifth pattern layer (321), sixth pattern layer (322), seventh pattern layer (323), and eighth pattern layer (324) may have a single-layer structure based on the electroplated layer. However, the embodiments are not limited thereto, and the second pattern layer (222), third pattern layer (223), fourth pattern layer (224), fifth pattern layer (321), sixth pattern layer (322), seventh pattern layer (323) and eighth pattern layer (324) can also be formed by performing two-stage plating as in the second pattern portion (221-2) of the first pattern layer (221), and accordingly, a two-layer structure based on the electroplated layer can be formed.

[0198] In the first embodiment, the first through electrode (231) may have a fourth thickness (T4). For example, the first through electrode (231) may have the same thickness as the first-1 insulating layer (211) in the region that overlaps vertically with the first circuit layer.

[0199] For example, the first penetrating electrode (231) may each have a fourth thickness (T4) in the range of 10 μm to 60 μm. For example, the first penetrating electrode (231) may each have a thickness (T4) in the range of 12 μm to 45 μm. For example, the first penetrating electrode (231) may have a thickness of 15 μm to 30 μm.

[0200] Meanwhile, one side (221-3S1) of the third pattern part (221-3) facing the cavity (C) while overlapping horizontally with the cavity (C) forms the inner wall (IW3) of the third part (P3) of the cavity (C). At this time, as shown in FIG. 3a, the one side (221-3S1) of the third pattern part (221-3), which is the inner wall (IW3) of the third part (P3), is connected to the inner wall (IW2) of the second part (P2) and may have a third slope perpendicular to the reference line (BL).

[0201] Meanwhile, a barrier layer (130) may be disposed on the upper surface of the first pattern portion (221-1) exposed through the cavity (C). The barrier layer (130) may have a plurality of layer structures.

[0202] For example, the barrier layer (130) may include a first layer (131), a second layer (132), and a third layer (133).

[0203] The first layer (131) may include nickel. The first layer (131) may be disposed on the upper surface of the first layer (131). At this time, the first layer (131) may be formed by electroless plating a metal containing nickel on the upper surface of the first pattern portion (221-1). Accordingly, at least a portion of the lower surface of the first layer (131) may not come into contact with the first pattern portion (221-1). For example, at least a portion of the first layer (131) may not overlap with the first pattern portion (221-1) in a vertical direction. For example, the lower surface of the first layer (131) may include a first portion that comes into contact with the upper surface of the first pattern portion (221-1), and a second portion that extends outward from the first portion and comes into contact with the first upper surface (211T1) of the first-1 insulating layer (211). For example, the width of the first layer (131) may be greater than the width of the first pattern portion (221-1). Accordingly, the first layer (131) may partially contact the upper surface of the first pattern portion (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211).

[0204] The first layer (131) can prevent the diffusion of the metal constituting the first pattern portion (221-1). For example, the first layer (131) can prevent copper constituting the first pattern portion (221-1) from diffusing into the third layer (133) of the barrier layer (130). The first layer (131) may have a thickness in the range of 0.1 μm to 1 μm. The first layer (131) may have a thickness in the range of 0.2 μm to 0.9 μm. The first layer (131) may have a thickness in the range of 0.3 μm to 0.8 μm. If the thickness of the first layer (131) is less than 0.1 μm, the diffusion prevention effect may be insufficient. If the thickness of the first layer (131) is greater than 1 μm, the overall thickness of the barrier layer (130) may increase.

[0205] The second layer (132) may be disposed on the first layer (131). The second layer (132) may contain palladium. For example, the second layer (132) may be formed by electroless plating a metal containing palladium on the first layer (131). The second layer (132) may be formed to improve bonding with solder and to ensure reliability in a high-temperature reflow process. The second layer (132) may have a thickness in the range of 0.01 μm to 0.1 μm. The second layer (132) may have a thickness in the range of 0.02 μm to 0.08 μm. The second layer (132) may have a thickness in the range of 0.03 μm to 0.06 μm.

[0206] The third layer (133) may be disposed on the second layer (132). The second layer (132) may contain gold. For example, the third layer (133) may be formed by displacement plating a metal containing gold on the second layer (132). The third layer (133) may function to prevent oxidation of the first pattern portion (221-1). Additionally, the third layer (133) may be formed to improve bonding properties with solder or wire during chip mounting. Preferably, the third layer (133) may be formed to prevent thickness or shape changes of the first pattern portion (221-1) in a subsequent process after the cavity (C) is formed during the manufacturing process of the circuit board of the embodiment. The third layer (133) may have a thickness in the range of 0.01 μm to 0.1 μm. The third layer (133) may have a thickness in the range of 0.02 μm to 0.08 μm. The third layer (133) may have a thickness in the range of 0.03 μm to 0.06 μm.

[0207] As described above, a barrier layer (130) is disposed on the first pattern portion (221-1) in the embodiment. The barrier layer (130) includes a first layer (131), a second layer (132), and a third layer (133). The barrier layer (130) can function to protect the first pattern portion (221-1) in a subsequent process after the cavity (C) is formed. Through this, in the embodiment, it is not necessary to increase the thickness of the first pattern portion (221-1) by taking into account the change in thickness of the first pattern portion (221-1) that occurs in the subsequent process. Accordingly, in the embodiment, the first pattern portion (221-1) can be miniaturized. Furthermore, in the embodiment, the thickness of the first pattern portion (221-1) can be reduced, thereby reducing the manufacturing cost. Additionally, in the embodiment, shape changes of the first pattern portion (221-1) occurring during the subsequent process can be prevented. Accordingly, in the embodiment, a chip can be stably mounted on the first pattern portion (221-1). Accordingly, in the embodiment, the physical and electrical reliability of the circuit board can be improved.

[0208] As described above, the barrier layer (130) includes a first layer (131), a second layer (132), and a third layer (133). The barrier layer (130) can protect the first pattern portion (221-1) from chemical damage as well as physical damage. At this time, even if parts of the third layer (133) and the second layer (132) of the barrier layer (130) are damaged or corroded from chemical or physical damage, the first pattern portion (221-1) can be reliably protected through the first layer (131) of the barrier layer (130). For example, the first layer (131) contains nickel. At this time, the reduction potential of the nickel is approximately -0.25V. This has a value lower than the reduction potential of the copper constituting the first pattern portion (221-1), which is +0.16V. Accordingly, in the embodiment, the first pattern portion (221-1) receives electrons from the first layer (131) based on the principle of galvanic corrosion. Through this, the corrosion resistance of the first pattern portion (221-1) can be improved compared to the case where the first layer (131) does not exist on the first pattern portion (221-1).

[0210] Meanwhile, the slope and shape of one side of the third pattern part (221-3) may vary depending on the etching conditions in the etching process.

[0211] For example, as illustrated in FIG. 3b, one side (221-3S2) of the third pattern portion (221-3) may have a certain slope inclined with respect to a reference line. For example, the width of the third pattern portion (221-3) may decrease from the bottom surface to the top surface. That is, the third part (P3) of the cavity (C) may have a slope in which the width decreases as it gets closer to the first insulating layer (211).

[0213] Additionally, as illustrated in FIG. 3c, in the embodiment, the third pattern portion (221-3) may include a recess (221-3U). This can be achieved by adjusting the etching conditions in a process of removing a portion of the third pattern portion (221-3) that overlaps vertically with the cavity (C) by etching after the formation of the cavity (C) is completed. For example, the side of the third pattern portion (221-3) may be spaced apart in a horizontal direction away from the cavity (C) from the bottom of the inner wall (IW2) of the second part (P2) of the cavity (C). Through this, the third part (P3) of the cavity (C) may be larger than the width of the lower area of ​​the second part (P2) by an area corresponding to the recess (221-3U).

[0214] The horizontal distance of the above-mentioned indentation (221-3U) may have a range between 1 µm and 12 µm. The horizontal distance of the above-mentioned indentation (221-3U) may have a range between 2 µm and 10 µm. The horizontal distance of the above-mentioned indentation (221-3U) may have a range between 3 µm and 8 µm.

[0215] Here, the horizontal distance may refer to the horizontal distance from the inner wall of the cavity (C) adjacent to the recess (221-3U) to one side of the third pattern portion (221-3). At this time, the third pattern portion (221-3) may include an area in which the width changes (e.g., increases or decreases) from the bottom surface to the top surface depending on the etching conditions. Furthermore, the horizontal distance may refer to any one of the maximum horizontal distance of the most recessed area, the minimum horizontal distance of the least recessed area, and the average distance of the horizontal distance of the entire area.

[0216] Meanwhile, in the embodiment, the third pattern portion (221-3) may be removed during the etching process. For example, in the embodiment, the third pattern portion (221-3) may be completely removed during the etching process so that the third pattern portion (221-3) does not exist in the indentation (221-3U).

[0218] Figures 4a and 4b show a top view of the second substrate layer.

[0219] Referring to FIG. 4a, the second substrate layer (300) includes a third region (RT1) and a fourth region (RT2). The third region (RT1) is a region in which a cavity (C) penetrating the second substrate layer (300) is formed. At this time, the third region (RT1) and the fourth region (RT2) may each be formed in the width direction or the length direction of the second substrate layer (300). For example, the third region (RT1) may be positioned on one side of the fourth region (RT2).

[0220] Alternatively, referring to FIG. 4b, the third region (RT1) may be positioned in the center of the second substrate layer (300). And the fourth region (RT2) may be formed surrounding the third region (RT1).

[0222] Hereinafter, an example of modification of the first pattern portion of the first insulating layer (211) and the first pattern layer (221) according to the embodiment and the structure of the barrier layer according to the same will be described.

[0223] FIG. 5a is a drawing showing a circuit board according to a first modified example, FIG. 5b is a drawing showing a circuit board according to a second modified example, and FIG. 5c is a drawing showing a circuit board according to a third modified example.

[0224] Before describing the first to third variations, the manufacturing process of the first pattern portion (221-1) and the third pattern portion (221-3) of the first pattern layer (221) in the embodiment will be briefly described.

[0225] Before the cavity (C) is formed, the third pattern part (221-3) is placed entirely on the first pattern part (221-1) and the boundary area, which overlaps vertically with the cavity (C).

[0226] Then, after the cavity (C) is formed through a laser process, an etching process is performed on the first region (RB1) that is vertically superimposed with the cavity (C) among the entire area of ​​the third pattern part (221-3). At this time, under ideal process conditions, only the third pattern part (221-3) placed on the first pattern part (221-1) can be selectively removed. Accordingly, the first pattern part (221-1) and the third pattern part (221-3) may have a positional relationship and a thickness relationship as shown in FIG. 3a.

[0227] At this time, in the embodiment, during the etching process for removing the third pattern portion (221-3), etching may proceed beyond the thickness of the third pattern portion (221-3) depending on the etching conditions.

[0228] As illustrated in FIG. 5a, the first pattern portion (221-1) may have a first 'thickness (T1a) that is smaller than the first thickness (T1) of the first pattern portion in FIG. 3a. That is, in the embodiment, during the process of etching the third pattern portion (221-3), a part of the first pattern portion (221-1) is also etched. Accordingly, the first pattern portion (221-1) may have a first 'thickness (T1a).

[0229] Accordingly, the upper surface of the first pattern portion (221-1) may be positioned lower than the first upper surface (211T1) of the first-1 insulating layer (211). Additionally, the upper surface of the first pattern portion (221-1) may be positioned lower than the lower surface of the third pattern portion (221-3). Furthermore, the upper surface of the first pattern portion (221-1) may be positioned lower than the upper surface of the first metal layer (221-21) of the second pattern portion (221-2). For example, the thickness (T1) of the first pattern portion (221-1) in FIG. 3a corresponds to the thickness of the first metal layer (221-21) of the second pattern portion (221-2). Alternatively, the first thickness (T1a) of the first pattern portion (221-1) in the first variation example may be smaller than the thickness (T1) of the first metal layer (221-21) of the second pattern portion (221-2).

[0230] Meanwhile, as described above, prior to the etching process, the third pattern portion (221-3) is formed entirely in the first region (RB1) which is vertically superimposed with the cavity (C). At this time, if the etching is not entirely performed on the region vertically superimposed with the first region (RB1) among the entire area of ​​the third pattern portion (221-3), a part of the third pattern portion (221-3) may remain on the first region (RB1). And an electrical short circuit problem may occur as a result of connecting multiple first pattern portions (221-1) by the remaining part of the third pattern portion (221-3). In this way, in the embodiment, to solve the problem of a portion of the third pattern portion (221-3) remaining on the first region (RB1) as described above, the etching conditions are adjusted so that a portion of the first pattern portion (221-1) is etched together with the third pattern portion (221-3) on the first region (RB1). Through this, in the embodiment, the electrical reliability problem caused by the remaining portion of the third pattern portion (221-3) can be solved, and thereby product reliability can be improved.

[0231] Additionally, in the first modified example, as described above, a step is formed between the upper surface of the first pattern portion (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211). For example, the upper surface of the first pattern portion (221-1) in the first modified example may include a recessed portion (not shown) that is recessed downwards relative to the first upper surface (211T1) of the first-1 insulating layer (211).

[0232] For example, the upper surface of the first pattern portion (221-1) may be positioned lower than the first upper surface (211T1) of the first-1 insulating layer (211). For example, a recessed portion having a step difference with respect to the first upper surface (211T1) of the first-1 insulating layer (211) may be formed on the first pattern portion (221-1).

[0233] In addition, the barrier layer (130) in the embodiment may be disposed within the recess. For example, the first layer (131), the second layer (132), and the third layer (133) of the barrier layer (130) may each be disposed within the recess.

[0234] Meanwhile, the vertical distance (e.g., T1-T1a) between the lower surface of the third pattern part (221-3) or the first upper surface (211T1) of the first-1 insulating layer (211) and the upper surface of the first pattern part (221-1) is to satisfy a range of 2% to 10% of the first thickness (T1). The vertical distance (e.g., T1-T1a) between the lower surface of the third pattern part (221-3) or the first upper surface (211T1) of the first-1 insulating layer (211) and the upper surface of the first pattern part (221-1) is to satisfy a range of 3% to 9% of the first thickness (T1). The vertical distance (e.g., T1-T1a) between the lower surface of the third pattern part (221-3) or the first upper surface (211T1) of the first-1 insulating layer (211) and the upper surface of the first pattern part (221-1) is to satisfy a range of 3.5% to 8% of the first thickness (T1). If the vertical distance (e.g., T1-T1a) between the lower surface of the third pattern part (221-3) or the first upper surface (211T1) of the first-1 insulating layer (211) and the upper surface of the first pattern part (221-1) is less than 2% of the first thickness (T1), the effect of the dam function may be insufficient as the depth of the recessed part of the first pattern part (221-1) is small. Additionally, if the vertical distance (e.g., T1-T1a) between the lower surface of the third pattern section (221-3) or the first upper surface (211T1) of the first insulating layer (211) and the upper surface of the first pattern section (221-1) exceeds 10% of the first thickness (T1), the allowable current of the first pattern section (221-1) decreases due to the reduction in the thickness (T1a) of the first pattern section (221-1), and the communication performance may be degraded accordingly.

[0236] Meanwhile, as shown in FIG. 5b, the second variation example may have a difference in the height of the first upper surface (211T1a) of the first insulating layer (211) compared to the circuit board of FIG. 3a.

[0237] That is, in the second variation example, after etching the third pattern portion (221-3), an additional etching process can be performed on the first region (RB1) of the first-1 insulating layer (211a). Accordingly, the first upper surface (211T1) of the first-1 insulating layer (211a) can be positioned lower than the upper surface of the first pattern portion (221-1).

[0238] That is, the first upper surface (211T1) of the first insulating layer (211a) may be positioned lower than the lower surface of the third pattern portion (221-3). For example, the first upper surface (211T1) of the first insulating layer (211a) may be positioned lower than the upper surface of the first metal layer (221-21) of the second pattern portion (221-2).

[0239] That is, in the second modified example, unlike the first modified example, the problem of the remaining portion of the third pattern portion (221-3) is not solved by etching a part of the first pattern portion (221-1), and the problem of the remaining portion is solved by etching a part of the first upper surface (211T1) of the first insulating layer (211a) that overlaps vertically with the first region (RB1).

[0240] Meanwhile, the vertical distance (T5) between the lower surface of the third pattern part (221-3) or the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211a) is to satisfy a range of 2% to 10% of the first thickness (T1). For example, the vertical distance (T5) between the lower surface of the third pattern part (221-3) or the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211a) is to satisfy a range of 3% to 9% of the first thickness (T1). For example, the vertical distance (T5) between the lower surface of the third pattern part (221-3) or the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211a) satisfies a range of 3.5% to 8% of the first thickness (T1).

[0241] If the vertical distance (T5) between the lower surface of the third pattern part (221-3) or the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211a) is less than 2% of the first thickness (T1), the remaining problem may not be completely resolved. Additionally, if the vertical distance (T5) between the lower surface of the third pattern part (221-3) or the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211a) exceeds 10% of the first thickness (T1), the area not covered by the first-1 insulating layer (211a) on the side of the first pattern part (221-1) (e.g., exposed area) increases, and consequently, a physical reliability problem may occur regarding the first pattern part (221-1).

[0242] Meanwhile, in the second variation example, at least a portion of the side of the first pattern portion (221-1) is not covered by the first-1 insulating layer (211).

[0243] Accordingly, the barrier layer (130) may cover at least a portion of the side of the first pattern portion (221-1). The first layer (131) of the barrier layer (130) may include a first portion disposed on the upper surface of the first pattern portion (221-1) and a second portion extending downward from the first portion and disposed on the side of the first pattern portion (221-1). Additionally, the second layer (132) of the barrier layer (130) may be disposed on the first portion and the second portion of the first layer (131). Additionally, the third layer (133) of the barrier layer (130) may be disposed on the first portion and the second portion of the second layer (132).

[0245] Meanwhile, as illustrated in FIG. 5c, in the third variation example, both the first variation example and the second variation example are applied so that the upper surface of the first pattern part (221-1) and the first upper surface (211T1) of the first-1 insulating layer (211) are located on the same plane.

[0246] Accordingly, the upper surface of the first pattern part (221-1) and the first upper surface (211T1a) of the first-1 insulating layer (211) may be positioned lower than the lower surface of the third pattern part (221-3), the upper surface of the first metal layer (221-21) of the second pattern part (221-2), and the lower surface of the second metal layer (221-22) of the second pattern part (221-2).

[0248] FIG. 6 is a drawing showing a circuit board according to a second embodiment, and FIG. 7 is an enlarged view of a part of FIG. 6.

[0249] The circuit board according to FIGS. 6 and FIGS. 7 has the same overall structure as the circuit board of FIGS. 1, except for the thickness of the through electrodes of the first substrate layer and the second substrate layer and the thickness of the first insulating layer and the second insulating layer accordingly.

[0250] Referring to FIGS. 6 and FIGS. 7, the circuit board (1100) includes a first substrate layer (1200) and a second substrate layer (1300).

[0251] The overall structure of the first substrate layer (1200) and the second substrate layer (1300) is the same as the first substrate layer (200) and the second substrate layer (300) of the first embodiment shown in FIG. 1, and a detailed description thereof is omitted.

[0252] Meanwhile, the thickness of the through-electrode in the circuit board in Fig. 1 is greater than the thickness of the circuit layer.

[0253] Alternatively, the thickness of the through electrode in the circuit board of the second embodiment may be the same as or smaller than the thickness of the circuit layer.

[0254] This can be achieved by reducing the thickness of the insulating layer and the thickness of the through electrodes accordingly, while maintaining the thickness of the circuit layer of the circuit board in Fig. 1.

[0255] That is, in the embodiment, a cavity (C) is formed in the second substrate layer, and a chip, such as a driving element and a passive element of the driving unit, is placed in the cavity (C). Accordingly, the driving unit in the embodiment is positioned in a horizontal direction rather than in the vertical direction of the antenna unit. For example, the driving unit is positioned in a direction different from the signal radiation direction of the antenna pattern layer of the antenna unit (e.g., the vertical direction thereof). Accordingly, in the embodiment, signal interference between the antenna unit and the driving unit can be resolved. Through this, in the embodiment, communication performance can be not affected even if the thickness of the insulating layer and the thickness of the through electrode are increased and the gap between the antenna and the driving unit is not sufficiently maintained. Accordingly, in the embodiment, the thickness of the insulating layer of the first substrate layer and the second substrate layer, respectively, is reduced, and thereby, the thickness of the through electrode penetrating the insulating layer can be reduced.

[0256] Hereinafter, regarding the first substrate layer (1200) and the second substrate layer (1300) of the second embodiment, the first insulating layer (1211) and the first through electrode (1231) disposed on the first insulating layer (1211) will be described. However, other insulating layers and through electrodes other than the first insulating layer (1211) and the first through electrode (1231) may also have the thickness described below.

[0257] The first substrate layer (1200) may include a first insulating layer (1211), a first pattern layer (1221), a second pattern layer (1222), and a first through electrode (1231).

[0258] The first pattern layer (1221) includes a first pattern section (1221-1), a second pattern section (1221-2), and a third pattern section (1221-3).

[0259] The first pattern section (1221-1), the second pattern section (1221-2), and the third pattern section (1221-3) of the first pattern layer (1221) are substantially identical to the first pattern section (221-1), the second pattern section (221-2), and the third pattern section (221-3) described in the first embodiment, and accordingly, a detailed description thereof is omitted. In addition, the second pattern layer (1222) is substantially identical to the second pattern layer (222) described in the first embodiment, and accordingly, a description thereof is omitted.

[0260] Meanwhile, the first through electrode (1231) is disposed within the first-1 insulating layer (1211). The first through electrode (1231) can connect the first pattern layer (1221) and the second pattern layer (1222).

[0261] The first penetrating electrode (1231) may have a fourth' thickness (T4a) that is smaller than the fourth thickness (T4) of the first penetrating electrode (231) of the first embodiment.

[0262] For example, the first penetrating electrode (1231) may have the same thickness as at least one of the pattern portions of the first pattern layer (1221) of the first pattern layer (1221).

[0263] For example, the first through electrode (1231) may have the same thickness as the first pattern layer (1221) of the first pattern layer (1221). For example, the first through electrode (1231) may have the same thickness as the second pattern portion (1221-2) of the first pattern layer (1221).

[0264] Preferably, the fourth thickness (T4a) of the first through electrode (1231) may be less than or equal to the second thickness (T2) of the second pattern portion (1221-2) of the first pattern layer (1221). That is, the fourth thickness (T4a) of the first through electrode (1231) may be equal to or less than the second thickness (T2) of the second pattern portion (1221-2).

[0265] The 4' thickness (T4a) of the first penetrating electrode (1231) may satisfy a range of 51% to 100% of the second thickness (T2) of the second pattern portion (1221-2). For example, the 4' thickness (T4a) of the first penetrating electrode (1231) may satisfy a range of 60% to 95% of the second thickness (T2) of the second pattern portion (1221-2). The 4' thickness (T4a) of the first penetrating electrode (1231) may satisfy a range of 65% to 90% of the second thickness (T2) of the second pattern portion (1221-2).

[0266] If the 4' thickness (T4a) of the first through electrode (1231) is less than 51% of the second thickness (T2) of the second pattern portion (1221-2), signal interference between the first pattern layer (1221) and the second pattern layer (1222) may occur as the distance between them becomes too close, and the resulting signal transmission loss may increase. If the 4' thickness (T4a) of the first through electrode (1231) exceeds 100% of the second thickness (T2) of the second pattern portion (1221-2), the effect of reducing the thickness of the circuit board according to the embodiment may be insufficient.

[0267] As described above, in the embodiment, the 4' thickness (T4a) of the first through electrode (1231) can be made to have the same thickness as the first circuit layer or a thickness smaller than the first circuit layer, thereby reducing the thickness of the circuit board. In addition, in the embodiment, by reducing the thickness of the first through electrode, the signal transmission distance in the signal transmission path including the first through electrode can be reduced, and the resulting signal transmission loss can be minimized.

[0268] Meanwhile, in the embodiment, a chip is mounted on the cavity (C), and accordingly, by reducing the thickness of the through electrode placed in the area adjacent to the cavity (C), the transmission path of the signal transmitted from the chip or the signal provided to the chip can be minimized, and the resulting signal transmission loss can be minimized.

[0269] Accordingly, in the embodiment, among the through electrodes disposed in each insulating layer, only the first through electrode (1231) disposed closest to the cavity (C) may have the fourth' thickness (T4a). Furthermore, the remaining through electrodes excluding the first through electrode (1231) (e.g., through electrodes disposed in the second insulating layer, through electrodes disposed in the first-second insulating layer, and through electrodes disposed in the first-third insulating layer) may have a thickness (e.g., T4) greater than the fourth' thickness (T4a) of the first through electrode (1231). In particular, the through electrodes disposed in the second insulating layer that overlaps horizontally with the cavity (C) may transmit or receive a signal through an antenna pattern. At this time, the transmission strength or reception strength of the signal through the antenna pattern may increase proportionally to the signal transmission path. Accordingly, in the embodiment, the through electrodes disposed in the second insulating layer excluding the first through electrode (1231), the through electrodes disposed in the first-second insulating layer, and the through electrodes disposed in the first-third insulating layer are made to have a fourth thickness (T4), thereby maximizing communication performance.

[0270] In addition, in the embodiment, in the structure of a circuit board having the same thickness as the comparative example, the number of circuit layers can be increased by reducing the thickness of the insulating layer and the through-electrode, thereby improving circuit integration and communication performance.

[0272] Meanwhile, the first pattern portion in FIG. 1 has a structure embedded within the first insulating layer. For example, the side of the first pattern portion in FIG. 1 is covered by the first insulating layer. Additionally, at least a portion of the side of the first pattern portion in FIG. 5b is covered by the first insulating layer, and the remaining at least a portion is not covered by the first insulating layer.

[0273] Alternatively, the side of the first pattern portion is partially covered by an insulating layer, and the insulating layer covering at least a portion of the side of the first pattern portion may be a second insulating layer, unlike in FIG. 5b. Additionally, the first pattern portion may have a structure protruding on the first insulating layer.

[0275] FIG. 8 is a drawing showing a circuit board according to a third embodiment, and FIG. 9 is a drawing showing a circuit board according to a fourth embodiment.

[0276] Referring to FIG. 8, the overall structure of the circuit board is the same as the structure of the previous embodiment.

[0277] However, the first pattern layer (2221) may have a structure protruding above the upper surface of the first insulating layer (2211).

[0278] Additionally, the second insulating layer (2311) is disposed on the first insulating layer (2211) and may include a cavity (C). At this time, the bottom surface of the cavity (C) may be positioned higher than the top surface of the first insulating layer (2211). For example, at least a portion of the second insulating layer (2311) may cover at least a portion of the side of the first pattern portion (2221-1) whose top surface is exposed through the cavity (C).

[0279] Additionally, the barrier layer (2130) may include a first portion disposed on the upper surface of the first pattern portion (2221-1) and a second portion disposed on the side of the first pattern portion (2221-1) that is not covered by the second insulating layer (2311). For example, the structure of the barrier layer (2130) is the same as the structure of the barrier layer in FIG. 5b, provided that, compared with FIG. 5b, at least a portion of the side of the first pattern portion (2221-1) may have a structure covered by the second insulating layer rather than the first insulating layer.

[0280] Meanwhile, referring to FIG. 9, the circuit board includes a first insulating layer (3211), a second insulating layer (3311), and a first pattern layer (3221). The second insulating layer (3311) includes a cavity (C). Additionally, the first pattern layer (3221) includes the first pattern portion (3221-1).

[0281] At this time, at least a portion of the side of the first pattern portion (3221-1) in the previous embodiment had a structure in which it was covered by the first insulating layer or the second insulating layer.

[0282] Alternatively, the side of the first pattern portion (3221-1) in FIG. 9 may have a structure that is not covered by the first insulating layer and the second insulating layer.

[0283] Accordingly, the barrier layer (3130) may include a first portion that covers the entire upper surface of the first pattern portion (3221-1) and a second portion that covers the entire side of the first pattern portion (3221-1).

[0285] According to the above embodiment, the circuit board includes a first pattern portion with its upper surface exposed through a cavity. A barrier layer is disposed on the first pattern portion. The barrier layer may be composed of a plurality of layers. For example, the barrier layer may include first to third layers. The barrier layer can function to protect the first pattern portion during a subsequent process after the cavity is formed. Through this, in the embodiment, it is not necessary to increase the thickness of the first pattern portion by taking into account the change in thickness of the first pattern portion that occurs during the subsequent process. Accordingly, in the embodiment, the first pattern portion can be miniaturized. Furthermore, in the embodiment, since the thickness of the first pattern portion can be reduced, the manufacturing cost can be reduced accordingly. In addition, in the embodiment, the shape change of the first pattern portion that occurs during the subsequent process can be prevented. Accordingly, in the embodiment, a chip can be stably mounted on the first pattern portion. Accordingly, in the embodiment, the physical and electrical reliability of the circuit board can be improved.

[0286] In addition, according to the above embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a first-1 insulating layer disposed closest to the first substrate layer and a first pattern layer disposed on the upper surface of the first-1 insulating layer. At this time, the first pattern layer includes a first pattern portion disposed in a first region vertically superimposed with the cavity, a second pattern portion disposed in a second region not vertically superimposed with the cavity, and a third pattern portion formed in a boundary region between the first and second regions. At this time, the thickness of at least one of the first to third pattern portions in the embodiment is different from the thickness of at least one other. In addition, at least one upper or lower surface of the first to third pattern portions in the embodiment is located on a different plane from at least one other upper or lower surface. As described above, in the embodiment, the first pattern layer disposed in an area adjacent to the cavity has a structure in which the thickness or surface is disposed at different positions, thereby improving the processability of cavity formation and resolving reliability issues that may occur during the cavity process.

[0287] Specifically, in the embodiment, during the process of forming the first pattern layer, a two-layer structure including a first metal layer and a second metal layer is formed through two-stage plating, and either of the first metal layer or the second metal layer is used as a first pattern portion which is a mounting pad, and the other is used as a third pattern portion which is a laser stopper, and both are used to form a second pattern portion. Through this, the embodiment can solve the reliability problem that occurs when the mounting pad and the stopper are placed on the same plane. For example, in the comparative example, a separate protective layer (not shown) is formed on the mounting pad to prevent damage to the mounting pad during the laser process of forming the cavity, and a process of removing it is performed later. In contrast, in the embodiment, a part of the third pattern portion used as the laser stopper can be utilized as a protective portion for the first pattern portion which is the mounting pad, and accordingly, the process of forming an additional protective layer to protect the first pattern portion can be omitted while preventing damage to the first pattern portion which is the mounting pad during the process of forming the cavity.

[0288] Furthermore, the first substrate layer includes a first region vertically superimposed with the cavity and a second region excluding the first region. Additionally, the second substrate layer includes a third region corresponding to the cavity and a fourth region excluding the third region. In this embodiment, the third region of the second substrate layer is a region where a driving element is placed, and the fourth region is a region where an antenna pattern layer is placed. In the above embodiment, the driving element is placed using the cavity of the second substrate layer, and the antenna pattern layer is placed in the fourth region of the second substrate layer that is horizontally adjacent to the driving element. Accordingly, in the embodiment, the signal transmission distance between the antenna pattern layer and the driving element can be minimized, and the resulting signal transmission loss can be minimized. For example, in the embodiment, compared to the comparative example where the substrate on which the driving element is placed and the substrate on which the antenna pattern layer is placed are connected using a separate connection means, the signal transmission distance can be reduced, and the signal transmission loss caused by the separate connection means can be reduced. In addition, in the embodiment, the antenna pattern layer and the driving element are arranged in a horizontal direction, so that the second region of the first substrate layer, which is vertically superimposed with the fourth region of the second substrate layer, can be utilized as the second antenna pattern layer, and accordingly, antenna pattern radiation and signal reception in different directions can be made possible in a single circuit pattern.

[0289] In addition, in the embodiment, by placing a driving element within the cavity of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavity.

[0290] Additionally, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. At this time, with respect to the bottom surface of the cavity, the second slope has an angle of inclination smaller than the first slope. Furthermore, the vertical length of the second part having the second slope in the embodiment is longer than the vertical length of the first part having the first slope. Accordingly, in the embodiment, the space occupied by the cavity can be reduced compared to the comparative example, and thus the circuit integration density can be improved. For example, in the embodiment, by reducing the space occupied by the cavity, the length of the antenna pattern layer can be increased within a substrate having the same size as the comparative example, and the communication performance can be improved accordingly.

[0291] In addition, in the embodiment, the thickness of the through electrode can be made to be the same as or smaller than the thickness of the circuit layer. Accordingly, in the embodiment, the thickness of the through electrode can be made to be the same as or smaller than the thickness of the circuit layer, thereby reducing the thickness of the circuit board. Furthermore, in the embodiment, by reducing the thickness of the through electrode, the signal transmission distance in the signal transmission path including the through electrode can be reduced, and the resulting signal transmission loss can be minimized.

[0292] In addition, in the embodiment, in the structure of a circuit board having the same thickness as the comparative example, the number of circuit layers can be increased by reducing the thickness of the insulating layer and the through-electrode, thereby improving circuit integration and communication performance.

[0294] FIG. 10 is a drawing showing a semiconductor package according to an embodiment.

[0295] Referring to FIG. 10, the semiconductor package includes a circuit board (100) illustrated in FIG. 1.

[0296] The semiconductor package includes a barrier layer (130) disposed on a first pattern portion (221-1) disposed in an area vertically overlapping with the cavity (C) among the first pattern layer (221) of the first substrate layer (200). Additionally, a first connection portion (410) may be disposed on the barrier layer (130).

[0297] The planar shape of the first connection part (410) may be circular. Alternatively, the planar shape of the first connection part (410) may be rectangular. The first connection part (410) may be placed on the first pattern part (221-1) to connect the first pattern part (221-1) and the terminal (425) of the element (420). The first connection part (410) may be, for example, a solder ball. The first connection part (410) may contain a heterogeneous material in the solder. The solder may be composed of at least one of SnCu, SnPb, and SnAgCu. And, the heterogeneous material may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0298] A component (420) is disposed on the first connection portion (410), and the component (420) may be a driver component. For example, the component (420) may be a driving component that drives an antenna pattern layer included in the circuit board. Also, in the drawing, only one component is shown mounted in the cavity (C), but it is not limited thereto. For example, in addition to the component (420), a passive component (not shown) for the operation of the component (420) may be additionally mounted in the cavity (C).

[0299] Meanwhile, a molding layer (430) may be formed within the cavity (C) to cover the element (420). The molding layer (430) may be an EMC (Epoxy Molding Compound), but is not limited thereto.

[0300] Additionally, the embodiment includes a second connection portion (440) disposed on the lower surface of a pattern layer disposed on the lower surface of a first region (RB1) of a first substrate layer (200). The second connection portion (440) can connect the semiconductor package and an external substrate (e.g., a main board of a terminal).

[0302] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described in the order of process.

[0303] At this time, the circuit board in the embodiment may have a coreless structure as shown in FIG. 1.

[0304] However, the embodiments are not limited thereto. For example, the circuit board of the embodiment may be a core substrate including a core insulating layer. For example, the circuit board of the embodiment may have an ETS structure manufactured by the ETS (Embedded Trace Substrate) method. However, for convenience of explanation, the embodiments will be described as having a coreless substrate structure in which the circuit board has a coreless substrate structure.

[0305] FIGS. 11a to 11q are drawings showing the manufacturing method of a circuit board according to the embodiment shown in FIG. 1 in process order.

[0306] Hereinafter, a method for manufacturing a circuit board according to the first embodiment of FIG. 1 will be described with reference to FIG. 11a to FIG. 11q. However, circuit boards of other embodiments excluding the first embodiment may also be manufactured using the process described below.

[0307] The manufacturing process of a circuit board according to an embodiment of the present invention may largely include a first process of manufacturing a part of a first substrate layer and a part of a second substrate layer using a carrier board, a process of manufacturing the remaining part of the first substrate layer and the remaining part of the second substrate layer above and below the substrate layer manufactured through the first process, respectively, a process of forming a cavity in the second substrate layer, and a process of removing a stopper layer in an area vertically superimposed with the cavity.

[0308] First, referring to FIG. 11a, a carrier board, which is a basic material for manufacturing a circuit board according to an embodiment, can be prepared.

[0309] The above carrier board may include a carrier insulating layer (510) and a carrier copper foil layer (520) disposed on one side of the carrier insulating layer (510).

[0310] The carrier copper foil layer (520) may be disposed on one side of the carrier insulating layer (510), or alternatively, may be disposed on both sides. When the carrier copper foil layer (520) is disposed on both sides of the carrier insulating layer (510), in the following process, the manufacturing process of the circuit board may proceed on each side of the carrier board until the carrier board is removed.

[0311] The carrier copper foil layer (520) can be formed by performing electroless plating on the surface of the carrier insulating layer (510). Alternatively, the carrier insulating layer (510) and the carrier copper foil layer (520) may be CCL (copper clad laminate).

[0312] At this time, the carrier board may be divided into a plurality of regions corresponding to the first region (RB1) and the second region (RB2) of the first substrate layer (200).

[0313] Next, in the embodiment, a process of forming a mask (530) on the lower surface of the carrier copper foil layer (520) can be performed. At this time, a process of forming an opening (540) in the mask (530) can be performed. The opening (540) of the mask (530) can be vertically overlapped with the area on the lower surface of the carrier copper foil layer (520) where the fifth pattern layer (321) is to be formed.

[0314] Next, as illustrated in FIG. 11b, the carrier copper foil layer (520) can be electroplated as a seed layer to form a fifth pattern layer (321) that fills the opening (540) of the mask (530).

[0315] In addition, in the embodiment, when the fifth pattern layer (321) is formed, a process of removing the mask (530) can be performed. Next, in the embodiment, as the mask (530) is removed, a process of forming a second-1 insulating layer (311), which is part of the second insulating layer of the second substrate layer (300), on the lower surface of the carrier copper foil layer (520) and the lower surface of the fifth pattern layer (321) can be performed.

[0316] Next, as illustrated in FIG. 11c, in the embodiment, a process of forming a through hole (not shown) penetrating the second-1 insulating layer (311) can be carried out. Next, in the embodiment, a process of forming a first dry film (DF1) on the lower surface of the second-1 insulating layer (311) can be carried out. The first dry film (DF1) may include an opening (not shown) that overlaps vertically with the area where the first pattern layer (221) is to be formed. Next, in the embodiment, a process of forming a fourth through electrode (331) that fills the through hole of the second-1 insulating layer (311) and a part of the first pattern layer (221) of the first substrate layer (200) can be carried out.

[0317] Preferably, the first pattern layer (221) is formed through a two-stage plating process. Here, two-stage plating may mean that the plating process of the electrolytic plating layer, excluding the seed layer, is performed twice. For example, in a general circuit board manufacturing process, electrolytic plating is performed on the seed layer to form a pattern layer, and accordingly, the electrolytic plating layer of the pattern layer has a single-layer structure. Alternatively, in the embodiment, since the functions of each region of the first pattern layer (221) differ, the first pattern layer (221) may be formed through two-stage plating to form a pattern portion suitable for each function, so that the electrolytic plating layer of the first pattern layer (221) has a two-layer structure.

[0318] For example, in an embodiment, a process may be carried out to form a first electrolytic plating layer (221a) that fills at least a portion of the opening of the first dry film (DF1) on the lower surface of the second-1 insulating layer (311). At this time, the first electrolytic plating layer (221a) may correspond to the second metal layer (221-22) and the third pattern part (221-3) of the second pattern part (221-2) of the first pattern layer (221).

[0319] Next, as illustrated in FIG. 11d, in the embodiment, a process of forming a second dry film (DF2) on at least a portion of the lower surface of the first electrolytic plating layer (221a) can be carried out. At this time, the second dry film (DF2) is formed to cover at least a portion of the first electrolytic plating layer (221a). In other words, the second dry film (DF2) includes an opening (not shown) that overlaps vertically with at least a portion of the lower surface of the first electrolytic plating layer (221a).

[0320] Next, as illustrated in FIG. 11e, in the embodiment, a second electroplating step may be performed on the lower surface of the first electroplating layer (221a) to form a second electroplating layer (221b) that fills at least a portion of the opening of the second dry film (DF2).

[0321] At this time, the second electrolytic plating layer (221b) may correspond to the first pattern portion (221-1) of the first pattern layer (221) and the first metal layer (221-21) of the second pattern portion (221-2). Accordingly, the planar area of ​​the first electrolytic plating layer (221a) may differ from the planar area of ​​the second electrolytic plating layer (221b). For example, the planar area of ​​the first electrolytic plating layer (221a) may be larger than the planar area of ​​the second electrolytic plating layer (221b). Specifically, the entire area of ​​the second electrolytic plating layer (221b) may overlap vertically with the first electrolytic plating layer (221a). However, the first electrolytic plating layer (221a) may include an overlapping area that overlaps vertically with the second electrolytic plating layer (221b) and a non-overlapping area that does not overlap vertically with the second electrolytic plating layer (221b). For example, in the embodiment, the first electrolytic plating layer (221a) corresponds to a laser stopper and can function to protect the upper surface of the second electrolytic plating layer (221b) corresponding to the first pattern portion (221-1) during the laser process. Accordingly, the planar area of ​​the first electrolytic plating layer (221a) may be larger than the planar area of ​​the region where the cavity (C) is to be formed, relative to the planar area of ​​the second electrolytic plating layer (221b).

[0322] Next, as illustrated in FIG. 11f, in the embodiment, a process of removing the first dry film (DF1) and the second dry film (DF2) can be carried out. Additionally, in the embodiment, a process of removing the carrier insulating layer (510) and the carrier copper foil layer (520) can be carried out.

[0323] Subsequently, in the embodiment, a process of manufacturing a part of the second substrate layer (300) and a part of the first substrate layer (200) can be carried out at the upper and lower portions of the second-1 insulating layer (311), respectively.

[0324] For example, as illustrated in FIG. 11g, in an embodiment, a first-1 insulating layer (211) may be formed on the lower surface of the second-1 insulating layer (311), and a first penetrating electrode (231) penetrating the first-1 insulating layer (211) and a second pattern layer (222) may be formed on the lower surface of the first-1 insulating layer (211). Additionally, in an embodiment, a second-2 insulating layer (312) may be formed on the upper surface of the second-1 insulating layer (311), and a fifth penetrating electrode (332) penetrating the second-2 insulating layer (312) and a sixth pattern layer (322) may be formed on the upper surface of the second-2 insulating layer (312).

[0325] Additionally, as illustrated in FIG. 11h, in the embodiment, a process of forming a first-2 insulating layer (212) on the lower surface of the first-1 insulating layer (211) can be carried out. Additionally, in the embodiment, a process of forming a second penetrating electrode (232) penetrating the first-2 insulating layer (212) and a third pattern layer (223) on the lower surface of the first-2 insulating layer (212) can be carried out.

[0326] In addition, in the embodiment, a process of forming a second-third insulating layer (313) on the upper surface of the second-third insulating layer (312) may be performed. In addition, in the embodiment, a process of forming a sixth penetrating electrode (333) penetrating the second-third insulating layer (313) and a seventh pattern layer (323) on the upper surface of the second-third insulating layer (313) may be performed.

[0327] Next, in the embodiment, as shown in FIG. 11i, a process of forming a first-third insulating layer (213) on the lower surface of the first-third insulating layer (212) can be carried out. Additionally, in the embodiment, a process of forming a third penetrating electrode (233) penetrating the first-third insulating layer (213) and a fourth pattern layer (224) on the lower surface of the first-third insulating layer (213) can be carried out.

[0328] Additionally, in the embodiment, a process of forming a second-fourth insulating layer (314) on the upper surface of the second-third insulating layer (313) may be performed. Next, in the embodiment, a process of forming a seventh penetrating electrode (334) penetrating the second-fourth insulating layer (314) and an eighth pattern layer (324) on the second-fourth insulating layer (314) may be performed.

[0329] Through this, in the embodiment, the manufacturing of a circuit board (100) including a first substrate layer (200) and a second substrate layer (300) before the cavity (C) is formed can be completed.

[0330] Meanwhile, in the embodiment, as shown in FIG. 11j, in the process of forming the eighth pattern layer (324), the seed layer of the eighth pattern layer (324) is left intact without being partially removed, and can be used as a mask in the process of forming the cavity (C).

[0331] For example, as illustrated in FIG. 11k, when looking at the manufacturing process of the eighth pattern layer (324), a seed layer (324-1) for forming the eighth pattern layer (324) by electroplating is located on the upper surface of the second-fourth insulating layer (314). And, the seed layer (324-1) can be used as a seed layer for electroplating the eighth pattern layer (324).

[0332] Next, as illustrated in FIG. 11, in the embodiment, as the eighth pattern layer (324) is formed, a process can be performed to remove the area of ​​the seed layer (324-1) that does not overlap vertically with the eighth pattern layer (324). At this time, in the embodiment, the area (324-1a) adjacent to the area where the cavity (C) is to be formed in the seed layer (324-1) is left intact without being removed. Furthermore, in the embodiment, during the cavity formation process below, the area (324-1a) of the seed layer (324-1) can be used as a laser mask to perform the cavity formation process only on the portion corresponding to the third area (RT1). At this time, the area (RB1) of the seed layer (324-1) may cover a part of the third area (RT1), which is the area where the cavity (C) is to be formed. This may be done to account for undercuts caused by process deviations occurring during the laser formation process.

[0333] Next, as illustrated in FIG. 11m, in the embodiment, a process can be carried out to form a first cavity (C1) penetrating the second insulating layers of the second substrate layer (300) by utilizing the region (RB1) of the seed layer (324-1). At this time, the first cavity (C1) can be formed up to the upper surface of the first electrolytic plating layer (221a), which is part of the first pattern layer (221) of the first substrate layer (200) (e.g., the upper surface of the third pattern portion (221-3)). At this time, the inner wall (IW1) of the first cavity (C1) can have a first slope. For example, in the embodiment, a first cavity process can be carried out. At this time, the width of the laser mask in the first cavity process can have a first width. The laser mask determines the width of the laser beam in the laser equipment. At this time, in the embodiment, the first cavity process can be performed using a first laser beam having a relatively large width to open the entire area where the cavity is to be formed. Accordingly, the inner wall (IW1) of the first cavity (C1) formed by the first cavity process has a first slope corresponding to the first laser beam overall.

[0334] Next, as illustrated in FIG. 11n, in an embodiment, a process of forming a second cavity (C2) by performing a second cavity process on the first cavity (C1) can be performed. At this time, the width of the laser mask in the second cavity process may have a second width that is smaller than the first width. Also, the second cavity process may be performed only on the portion corresponding to the inner wall of the first cavity (C1) formed in the first cavity process. Since the width of the laser mask in the second cavity process has a second width that is smaller than the first width, the inner wall of the second cavity (C2) may have a plurality of slopes. For example, the inner wall of the second cavity (C2) may include a first slope formed by the first cavity process and a second slope formed by the second cavity process.

[0335] For example, referring to FIG. 110, in an embodiment, a process of forming the first cavity (C1) can be carried out by using a mask having a first width of about 280 μm and irradiating a corresponding first laser beam (L1). Subsequently, in an embodiment, a process of forming the second cavity (C2) can be carried out by using a mask having a second width of about 100 μm, which is smaller than the first width, and irradiating a corresponding second laser beam (L2). Accordingly, the cavity in the embodiment includes a first slope corresponding to the first laser beam (L1) and a second slope corresponding to the second laser beam (L2). At this time, the overall slope of the cavity can be made to have the second slope, but in the first cavity formation process, the first laser beam (L1) penetrates into the lower surface of the region (RB1) of the seed layer (324-1), and thus includes an undercut region. And, the portion corresponding to the first slope in the cavity (C) may correspond to the undercut area formed in the first cavity process.

[0336] Next, as illustrated in FIG. 11p, a process can be performed to remove a portion of the third pattern portion (221-3) exposed through the second cavity process. For example, the third pattern portion (221-3) may be removed in an area that overlaps vertically with the cavity (C) after the cavity (C) formation process is completed. However, the third pattern portion (221-3) may have an area larger than the area of ​​the lower region of the cavity (C). Accordingly, in the etching process, at least a portion of the third pattern portion (221-3) may remain without being removed. For example, the third pattern portion (221-3) in the boundary area of ​​the first region (RB1) that overlaps vertically with the cavity (C) and the second region (RB2) excluding the first region (RB1) may not be removed. In addition, in the embodiment, a third part of the cavity (C) can be formed by removing a portion of the third pattern part (221-3). At this time, the inner wall of the third part may be a side of the third pattern part (221-3).

[0337] Next, as illustrated in FIG. 11q, in the embodiment, after the cavity (C) is formed, a process of forming a barrier layer (130) on the first pattern portion (221-1) exposed through the cavity (C) can be carried out. The barrier layer (130) can be formed to cover the exposed surface of the first pattern portion (221-1) (e.g., the top surface and / or at least a part of the side surface). The barrier layer (130) prevents changes in thickness or shape of the first pattern portion (221-1) in subsequent processes after the cavity (C) is formed. Next, in the embodiment, a process of forming a first protective layer (110) and a second protective layer (120) can be carried out.

[0339] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0340] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0341] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0342] Although the above description has focused on embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art to which the embodiments pertain will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 A first insulating layer; a first pattern layer disposed on the upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and including a cavity; The first pattern layer comprises a barrier layer disposed on a first pattern layer that is vertically superimposed with respect to the cavity, wherein the upper surface of the first insulating layer comprises a first upper surface that is vertically superimposed with respect to the lower surface of the cavity and a second upper surface that is not vertically superimposed with respect to the lower surface of the cavity, wherein the first pattern layer comprises a first pattern portion disposed on the first upper surface of the first insulating layer, a second pattern portion disposed on the second upper surface of the first insulating layer, and a third pattern portion disposed in a boundary region between the first upper surface and the second upper surface of the first insulating layer and including a side surface exposed through the cavity, wherein the upper surface of the first pattern portion is exposed through the cavity without contacting the first and second insulating layers, and the barrier layer is disposed on the upper surface of the first pattern portion, and the inner wall of the cavity comprises a first part having a first inclination angle with respect to the lower surface of the cavity, and a second part formed below the first part and having an inclination angle different from the first inclination angle with respect to the lower surface of the cavity. A circuit board comprising a second part having an inclination angle, and a third part formed below the second part and having a third inclination angle different from the first inclination angle and the second inclination angle with respect to the lower surface of the cavity, wherein the first part and the second part of the cavity are formed in the second insulating layer, and the third part is formed on the side of the third pattern portion exposed through the cavity, and among the first to third inclination angles, the first inclination angle is the largest and the third inclination angle is the smallest. Claim 2 A circuit board according to claim 1, wherein the lower surface of the cavity is the first upper surface of the first insulating layer, the first upper surface and the second upper surface of the first insulating layer have a step difference, the thickness of the first pattern portion is smaller than the thickness of the second pattern portion, and at least a portion of the side of the first pattern portion is covered by the first insulating layer. Claim 3 A circuit board according to paragraph 2, wherein the side of the first pattern portion is entirely covered by the first insulating layer, and the barrier layer comprises a first portion disposed on the upper surface of the first pattern portion and a second portion extending from the first portion and disposed on the first upper surface of the first insulating layer. Claim 4 A circuit board according to paragraph 2, wherein the thickness of the first pattern portion is smaller than the thickness of the second pattern portion, the upper surface of the first pattern portion is located lower than the upper surface of the second pattern portion, and the lower surface of the first pattern portion is located on the same plane as the lower surface of the second pattern portion. Claim 5 A circuit board according to claim 1, wherein the thickness of the third pattern portion is smaller than the thickness of the second pattern portion. Claim 6 A circuit board according to claim 5, wherein the upper surface of the first pattern portion does not contact the second insulating layer, the upper surfaces of the second and third pattern portions contact the second insulating layer, the upper surface of the third pattern portion is positioned higher than the upper surface of the first pattern portion and is located on the same plane as the upper surface of the second pattern portion, and the lower surface of the third pattern portion is positioned higher than the lower surface of the second pattern portion and is greater than the height of the upper surface of the first pattern portion. Claim 7 In claim 5, the second pattern portion comprises a first metal layer; and a second metal layer disposed on the first metal layer, wherein the first pattern portion is horizontally overlapped with the first metal layer and is not horizontally overlapped with the second metal layer, and the third pattern portion is not horizontally overlapped with the first metal layer and is horizontally overlapped with the second metal layer. Claim 8 A circuit board according to claim 7, wherein the first upper surface of the first insulating layer is positioned lower than the second upper surface, the upper surface of the second pattern portion, and the upper surface of the third pattern portion. Claim 9 A circuit board according to claim 1, wherein the first upper surface of the first insulating layer is positioned lower than the upper surface of the first pattern portion, and the side of the first pattern portion includes a first side that is covered by the first insulating layer and a second side that is not covered by the first insulating layer and is exposed through the cavity, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the second side of the first pattern portion. Claim 10 A circuit board according to claim 1, wherein the first upper surface of the first insulating layer is positioned higher than the upper surface of the first pattern portion, the first insulating layer includes a recess formed by a step difference between the first upper surface and the upper surface of the first pattern portion, and the barrier layer is disposed within the recess. Claim 11 A circuit board according to claim 1, wherein the first pattern portion protrudes over the first upper surface of the first insulating layer, and the side of the first pattern portion includes a first side that is covered by the second insulating layer and a second side that is not covered by the second insulating layer and is exposed through the cavity, and the barrier layer includes a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the second side of the first pattern portion. Claim 12 A circuit board according to claim 1, wherein the first pattern portion protrudes over the first upper surface of the first insulating layer, and the side of the first pattern portion is exposed through the cavity without contacting the first insulating layer and the second insulating layer in its entirety, and the barrier layer comprises a first portion disposed on the upper surface of the first pattern portion and a second portion disposed on the side of the first pattern portion. Claim 13 A circuit board according to any one of claims 1 to 12, wherein the barrier layer is disposed on the first pattern portion having a plurality of layer structures. Claim 14 In claim 13, the barrier layer comprises a first layer comprising nickel disposed on the first pattern portion, a second layer comprising palladium disposed on the first layer, and a third layer comprising gold disposed on the second layer. Claim 15 A semiconductor package comprising: a circuit board described in any one of claims 1 to 12; a connection portion disposed on a barrier layer of said circuit board; and a component mounted on said connection portion.

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