Circuit board and semiconductor package comprising the same

Abstract

A circuit board according to an embodiment comprises a first insulating layer; and a circuit layer disposed on the first insulating layer, wherein the circuit layer comprises a first layer disposed on the first insulating layer and a second layer partially disposed on the first layer, and the profile of the surface of the first layer is different from the profile of the surface of the second layer.

Description

Technology Field

[0001] An embodiment relates to a circuit board and a semiconductor package including the same. Background Technology

[0002] A circuit board is formed by creating a pattern of circuit lines using a conductive material, such as copper, on an electrically insulating substrate. A circuit board refers to the substrate prior to the mounting of electronic components.

[0003] In other words, a circuit board can mean that the mounting position of each component is determined to mount many different types of electronic components on a flat plate, and a circuit layer connecting said electronic components is formed.

[0004] Meanwhile, signal transmission on the circuit board can be achieved through the circuit layer. For example, a semiconductor package has a structure in which electronic components are mounted on a circuit board. Furthermore, signal transmission on the semiconductor package is achieved through a circuit layer formed on the circuit board. In this case, the signal may include a signal input to the electronic component, a signal output from the electronic component, a signal input from an external board, and a signal output to the external board.

[0005] Meanwhile, with the increasing functionality of portable electronic devices, signal frequencies are being raised to high frequencies to enable high-speed processing of large amounts of information. Consequently, circuit boards suitable for high-frequency applications are being required.

[0006] The circuit layers of such circuit boards must be capable of transmitting signals without degrading the quality of high-frequency signals. For example, the circuit layers of the circuit board must be able to minimize signal transmission loss.

[0007] In this case, the transmission loss of the circuit layer on the circuit board mainly consists of conductor loss caused by metal thin films such as copper and dielectric loss caused by insulators such as insulating layers.

[0008] Conductor loss attributable to metal thin films is related to the surface roughness of the circuit layer. In other words, as the surface roughness of the circuit layer increases, transmission loss may increase due to the skin effect.

[0009] Furthermore, reducing the surface roughness of the circuit layer can reduce signal transmission loss. However, when the surface roughness of the circuit layer is reduced, there is a problem in that the bonding strength between the circuit layer and the insulating layer is reduced accordingly.

[0010] Therefore, a new circuit board is required that can improve the bonding strength between the circuit layer and the insulating layer while minimizing signal transmission loss. The problem to be solved

[0011] An embodiment provides a circuit board capable of minimizing signal transmission loss and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board capable of improving the bonding strength between a circuit layer and an insulating layer, and a semiconductor package including the same.

[0013] In addition, the embodiment provides a circuit board suitable for high-frequency applications and a semiconductor package including the same.

[0014] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0015] A circuit board according to an embodiment comprises a first insulating layer; and a circuit layer disposed on the first insulating layer, wherein the circuit layer comprises a first layer disposed on the first insulating layer and a second layer partially disposed on the surface of the first layer, and the profile of the surface of the first layer is different from the profile of the surface of the second layer.

[0016] Additionally, the first layer of the circuit layer comprises a first metal layer disposed on the upper surface of the first insulating layer and a second metal layer disposed on the upper surface of the first metal layer, and the second layer of the circuit layer comprises a third metal layer disposed on the upper surface of the second metal layer, wherein the profile of the upper surface of the second metal layer is different from the profile of the upper surface of the third metal layer.

[0017] Additionally, the upper surface of the second metal layer comprises a plurality of peaks and valleys, and the third metal layer is formed on the upper surface of the second metal layer by filling a portion of at least one of the plurality of valleys.

[0018] In addition, the third metal layer is disposed on the side of the first metal layer and on the side of the second metal layer, and the respective profiles of the side of the first metal layer and the side of the second metal layer are different from the profile of the side of the third metal layer.

[0019] Additionally, each of the sides of the first metal layer and the second metal layer comprises a plurality of peaks and valleys, and the third metal layer fills at least one portion of the plurality of valleys on each of the sides of the first and second metal layers.

[0020] In addition, the upper surface of the circuit layer includes a first portion corresponding to the upper surface of the second metal layer and a second portion corresponding to the upper surface of the third metal layer.

[0021] In addition, the arithmetic mean roughness (Ra) of the upper surface of the circuit layer has a range between 0.05 μm and 0.2 μm, and the ten-point average roughness (Rz) of the upper surface of the circuit layer has a range between 0.1 μm and 1.0 μm.

[0022] In addition, the side of the circuit layer includes a first portion corresponding to the side of the first and second metal layers and a second portion corresponding to the side of the third metal layer.

[0023] In addition, the arithmetic mean roughness (Ra) of the side of the circuit layer has a range between 0.05 μm and 0.2 μm, and the ten-point average roughness (Rz) of the side of the circuit layer has a range between 0.1 μm and 1.0 μm.

[0024] Additionally, the circuit board further comprises a second insulating layer disposed on the first insulating layer to cover the circuit layer, and the lower surface of the second insulating layer comprises a first lower surface in contact with the first layer of the circuit layer, a second lower surface in contact with the second layer of the circuit layer, and a third lower surface in contact with the first insulating layer.

[0025] In addition, the first layer of the circuit layer comprises a first metal material, and the second layer of the circuit layer comprises a second metal material different from the first metal material.

[0026] In addition, the first metal material contains copper, and the second metal material contains tin.

[0027] Additionally, the first metal layer comprises a first-1 metal layer and a first-2 metal layer disposed on the first-1 metal layer, and the second metal layer is disposed on the first-2 metal layer.

[0028] Meanwhile, a circuit board according to an embodiment comprises an insulating layer; and a circuit layer disposed on the insulating layer; wherein the surface of the circuit layer comprises a first portion comprising a first metal material and a second portion comprising a second metal material different from the first metal material, the first metal material comprising copper and the second metal material comprising tin.

[0029] In addition, the surface of the circuit layer includes an upper surface, a left surface, a right surface, and a lower surface of the circuit layer, and the arithmetic mean roughness (Ra) of at least two surfaces among the upper surface, left surface, right surface, and lower surface of the circuit layer has a range between 0.05 μm and 0.2 μm.

[0030] Additionally, the surface of the circuit layer includes an upper surface, a left surface, a right surface, and a lower surface of the circuit layer, and the ten-point average roughness (Rz) of at least two surfaces among the upper surface, left surface, right surface, and lower surface of the circuit layer has a range between 0.1 μm and 1.0 μm.

[0031] Meanwhile, a semiconductor package according to an embodiment comprises: a plurality of insulating layers; a plurality of circuit layers each disposed on the surface of the plurality of insulating layers; and a first connection portion disposed on the uppermost circuit layer among the plurality of circuit layers. The above includes an element disposed on the first connection portion, and at least one of the plurality of circuit layers, the first circuit layer comprises a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the first metal layer and the second metal layer, the upper surface of the first circuit layer comprises a first upper surface corresponding to the second metal layer and a second upper surface corresponding to the third metal layer, and the side surface of the first circuit layer comprises a first side surface corresponding to the first metal layer and the second metal layer and a second side surface corresponding to the third metal layer, and at least one of the upper surface of the first circuit layer and the side surface of the first circuit layer has an arithmetic mean roughness (Ra) in the range of 0.05 μm to 0.2 μm and a ten-point average roughness (Rz) in the range of 0.1 μm to 1.0 μm. Effects of the invention

[0032] The circuit board of the embodiment includes a circuit layer. The circuit layer includes a first metal layer corresponding to a seed layer and a second metal layer disposed on the first metal layer. At this time, the surface of the circuit layer may be imparted with a certain level of surface roughness during the etching process of the first metal layer. Furthermore, the imparted surface roughness may act as a factor that increases signal transmission loss. Consequently, it may be difficult to apply it for high-frequency applications.

[0033] Accordingly, the circuit layer of the embodiment includes a third metal layer. The third metal layer is selectively disposed on the surface of the first metal layer and the surface of the second metal layer. For example, the surface of the circuit layer includes a first surface corresponding to the upper surface of the second metal layer. And, the third metal layer is partially disposed on the first surface. Specifically, the first surface includes a plurality of valleys and peaks corresponding to the applied surface roughness. And, the third metal layer is formed by filling a portion of the valleys on the first surface through the control of the crystal grains of metal ions in the plating solution. Accordingly, in the embodiment, the surface roughness of the first surface can be lowered to correspond to the thickness of the third metal layer.

[0034] Accordingly, the surface of the circuit layer includes a second surface corresponding to the first side of the first metal layer and the first side of the second metal layer. Additionally, the surface of the circuit layer includes a third surface corresponding to the second side of the first metal layer and the second side of the second metal layer. Furthermore, the third metal layer is arranged to fill not only the first surface but also a portion of the grooves of the second surface and a portion of the grooves of the third surface. Accordingly, in the embodiment, the surface roughness of the second surface and the third surface of the circuit layer can be reduced.

[0035] Through this, the embodiment can reduce the signal transmission loss of the circuit layer compared to the comparative example. By doing so, the signal characteristics of the circuit board can be improved in the embodiment. Furthermore, the embodiment can provide a circuit board suitable for high frequency applications.

[0036] Meanwhile, in the embodiment, the third metal layer is arranged to fill only a portion of the grooves on the first to third surfaces. Accordingly, in the embodiment, the surface roughness of the circuit layer can be lowered without affecting the thickness and line width of the circuit layer composed of the first metal layer and the second metal layer. Accordingly, the embodiment can further improve the electrical reliability and physical reliability of the circuit board.

[0037] Meanwhile, in the embodiment, an additional insulating layer is laminated on the circuit layer. At this time, the additional insulating layer contacts not only the first and second metal layers of the circuit layer but also the third metal layer. At this time, the first and second metal layers may contain copper, and the third metal layer may contain tin. At this time, the tin contains more hydroxyl groups than the copper. Furthermore, the additional insulating layer may have a higher adhesion to the third metal layer than to the first and second metal layers. In this case, the additional insulating layer in the comparative example contacts only the first and second metal layers of the circuit layer. Accordingly, in the comparative example, there is a limit to increasing the adhesion between the circuit layer and the additional insulating layer. In contrast, the additional insulating layer in the embodiment contacts not only the first and second metal layers of the circuit layer but also the third metal layer. Accordingly, the adhesion between the circuit layer and the additional insulating layer can be improved in the embodiment compared to the comparative example. Accordingly, the product reliability of the circuit board can be further improved in the embodiment.

[0038] Meanwhile, an undercut is formed on the lower side of the circuit layer of the comparative example. The undercut acts as a factor that reduces the reliability of the circuit layer. In this case, in the embodiment, the depth of the undercut can be reduced by the thickness of the third metal layer compared to the comparative example. Accordingly, the product reliability of the circuit board can be further improved in the embodiment. Brief explanation of the drawing

[0039] Figure 1 is a cross-sectional view of a circuit board according to a comparative example. Figure 2 is a drawing showing a circuit board according to an embodiment. FIG. 3 is a drawing for explaining the layer structure of a circuit layer according to a first embodiment. FIG. 4 is a drawing for explaining the layer structure of a circuit layer according to a second embodiment. FIG. 5 is a diagram showing a circuit layer according to the first embodiment. Figure 6 is a drawing showing the surface of a circuit layer prior to surface treatment according to an embodiment. Figure 7 is a drawing showing the surface of a circuit layer after surface treatment according to an embodiment. FIG. 8 is a diagram showing a circuit layer according to a second embodiment. FIG. 9 is a drawing illustrating the adhesion force between the circuit layer and the insulating layer according to an embodiment. Figure 10 is a diagram showing the undercut of the circuit layer of a comparative example. FIG. 11 is a drawing showing an undercut of a circuit layer according to an embodiment. FIG. 12 is a drawing showing a semiconductor package according to an embodiment. FIGS. 13 to 23 are drawings for explaining a method for manufacturing a circuit board according to an embodiment in process order. Specific details for implementing the invention

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0041] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0042] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “A and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0043] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0044] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0045] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0046] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0048] Before describing the embodiments, the circuit board of the comparative example will be described.

[0049] Figure 1 is a cross-sectional view of a circuit board according to a comparative example.

[0050] Referring to FIG. 1, the circuit board of the comparative example includes an insulating layer (10) and a circuit layer (20).

[0051] The circuit layer (20) is disposed on the surface of the insulating layer (10). For example, the circuit layer (20) is disposed on at least one of the upper and lower surfaces of the insulating layer (10).

[0052] The above circuit layer (20) includes a plurality of surfaces.

[0053] For example, the circuit layer (20) includes a first surface (20U), a second surface (20S1), and a third surface (20S2). The first surface (20U) may refer to the upper surface of the circuit layer (20). The second surface (20S1) may refer to the first side or left side of the circuit layer (20). The third surface (20S2) may refer to the second side or right side of the circuit layer (20). Additionally, the circuit layer (20) may include a fourth surface or lower surface that contacts the upper surface of the insulating layer (10).

[0054] At this time, the first surface (20U), second surface (20S1), and third surface (20S2) of the circuit layer (20) have a specific surface roughness.

[0055] The above surface roughness may be imparted during the manufacturing process of forming the circuit layer (20). For example, the circuit layer (20) has a plurality of layer structures. For example, the circuit layer (20) includes a first metal layer (not shown) and a second metal layer (not shown). The first metal layer may refer to a seed layer for electroplating the second metal layer. And, the second metal layer may be an electroplated layer formed by electroplating the first metal layer as a seed layer.

[0056] And the circuit layer (20) of the circuit board of the comparative example can be manufactured by forming the second metal layer on the first metal layer and removing by etching the area of ​​the entire area of ​​the first metal layer that does not overlap with the second metal layer in the thickness direction.

[0057] At this time, the first surface (20U), the second surface (20S1), and the third surface (20S2) of the circuit layer (20) may be given a specific surface roughness during the process of etching the first metal layer.

[0058] For example, the arithmetic mean roughness (Ra) of the first surface (20U), the second surface (20S1), and the third surface (20S2) of the circuit layer (20) of the comparative example exceeds 0.3 μm. For example, the ten-point average roughness (Rz) of the first surface (20U), the second surface (20S1), and the third surface (20S2) of the circuit layer (20) of the comparative example exceeds 3.5 μm.

[0059] Accordingly, the circuit layer (20) of the comparative example has a problem of relatively high signal transmission loss due to the arithmetic mean roughness and ten-point average roughness of the first surface (20U), the second surface (20S1), and the third surface (20S2). For example, the signal transmission loss increases in proportion to the surface roughness of the surface of the circuit layer (20). Furthermore, the circuit board of the comparative example has a problem of relatively high signal transmission loss due to the skin effect caused by the arithmetic mean roughness or ten-point average roughness of the first surface (20U), the second surface (20S1), and the third surface (20S2) of the circuit layer (20). Therefore, the circuit board of the comparative example has a problem of being difficult to apply to high-frequency applications.

[0060] In addition, in the comparative example, the surface of the circuit layer (20) is oxidized to reduce the surface roughness of the circuit layer (20).

[0061] For example, in a comparative example, the surface of the circuit layer (20) is oxidized to form an oxide layer, and the oxide layer is reduced to decrease the surface roughness of the circuit layer (20). However, the adhesion between the formed oxide layer and the circuit layer (20) is relatively low. Accordingly, in the process of forming the oxide layer, a portion of the oxide layer may be separated from the circuit layer (20). Furthermore, if the oxide layer is separated from the circuit layer (20), there is a problem in that the surface roughness in that portion appears relatively high. Additionally, in the process of reducing the oxide layer, a problem may occur in which the oxide layer is not partially reduced. Furthermore, if the oxide layer is not partially reduced, a problem may occur in which the electrical reliability of the circuit layer (20) is reduced.

[0062] Meanwhile, if the surface roughness of the circuit layer (20) is reduced indiscriminately, other problems may occur. For example, a circuit board is manufactured by performing a process of stacking multiple insulating layers. At this time, if the surface roughness of the circuit layer (20) is reduced, there is a problem in that the bonding strength between the circuit layer (20) and the additionally stacked insulating layer (not shown) is reduced. Accordingly, a problem may occur in which the additionally stacked insulating layer separates from the circuit layer (20).

[0064] Accordingly, the embodiment provides a circuit board with a novel structure capable of lowering the surface roughness of the circuit layer compared to the comparative example while improving the bonding strength between the circuit layer and the insulating layer, and a semiconductor package including the same. Accordingly, the embodiment provides a circuit board and a semiconductor package suitable for high-frequency applications.

[0066] -former device -

[0067] Before describing the embodiment, an electronic device including the semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to the semiconductor package of the embodiment. Various components may be mounted on the semiconductor package.

[0068] For example, the semiconductor package may be equipped with memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

[0069] For example, at least one of various types of passive and active components may be mounted on the semiconductor package.

[0070] At this time, the electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to these, and it is obvious that it may be any other electronic device that processes data in addition to these.

[0072] Hereinafter, a circuit board and a semiconductor package according to an embodiment will be described in detail. Here, the circuit board may refer to a substrate prior to the mounting of an electronic component. The semiconductor package may refer to a package in which an electronic component is mounted on the circuit board.

[0074] Figure 2 is a drawing showing a circuit board according to an embodiment.

[0075] Referring to FIG. 2, the circuit board may include an insulating layer, a circuit layer, a through electrode, and a protective layer. In this case, the circuit board is depicted in the drawing as having a three-layer structure based on the number of insulating layers, but it is not limited thereto. For example, the circuit board may have two or fewer layers based on the number of insulating layers, or it may have four or more layers.

[0076] The insulating layer may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). The first insulating layer (111) may refer to an insulating layer disposed on the inner side of the stacked structure of the circuit board. The second insulating layer (112) may refer to an insulating layer disposed on the upper side of the first insulating layer (111). The third insulating layer (113) may refer to an insulating layer disposed on the lower side of the first insulating layer (111).

[0077] At least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may include prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with epoxy resin or the like, and then performing heat pressing. However, the embodiments are not limited thereto, and the prepreg constituting at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0078] For example, at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be rigid or flexible.

[0079] At least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may have a thickness in the range of 10 μm to 60 μm. Preferably, at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may have a thickness in the range of 12 μm to 50 μm. More preferably, at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may have a thickness in the range of 15 μm to 40 μm.

[0080] If the thickness of at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) is less than 10 μm, the circuit layer included in the antenna substrate may not be reliably protected. If the thickness of at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) exceeds 60 μm, the thickness of the circuit board, the semiconductor package, and the electronic device including the same may increase. Additionally, if the thickness of at least one of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) exceeds 60 μm, the thickness of the circuit layer and the thickness of the through electrode may increase accordingly. Furthermore, if the thickness of the circuit layer and the thickness of the through electrode increase, the signal transmission loss may increase.

[0081] A circuit layer may be disposed on the surface of the above insulating layer.

[0082] The above circuit layer can be placed on the surface of the insulating layer for signal transmission on the circuit board.

[0083] For example, the circuit layer may be disposed on the respective surfaces of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113).

[0084] Specifically, the circuit layer may include a first circuit layer (121) disposed on the upper surface of the first insulating layer (111). Additionally, the circuit layer may include a first circuit layer (121) disposed on the lower surface of the first insulating layer (111). Furthermore, the circuit layer may include a third circuit layer (123) disposed on the upper surface of the second insulating layer (112). Additionally, the circuit layer may include a fourth circuit layer (124) disposed on the lower surface of the third insulating layer (113).

[0085] The first circuit layer (121), the second circuit layer (122), the third circuit layer (123), and the fourth circuit layer (124) may each have a thickness of 10 μm to 25 μm. Preferably, the first circuit layer (121), the second circuit layer (122), the third circuit layer (123), and the fourth circuit layer (124) may each have a thickness of 12 μm to 23 μm. More preferably, the first circuit layer (121), the second circuit layer (122), the third circuit layer (123), and the fourth circuit layer (124) may each have a thickness of 15 μm to 20 μm.

[0086] The first circuit layer (121), second circuit layer (122), third circuit layer (123), and fourth circuit layer (124) may include a conductive material. For example, the first circuit layer (121), second circuit layer (122), third circuit layer (123), and fourth circuit layer (124) may include at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit layer (121), second circuit layer (122), third circuit layer (123), and fourth circuit layer (124) may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0087] The first circuit layer (121), second circuit layer (122), third circuit layer (123), and fourth circuit layer (124) can be manufactured using conventional circuit board manufacturing processes such as the Additive Process, Subtractive Process, Modified Semi Additive Process (MSAP), and Semi Additive Process (SAP), and a detailed description is omitted here.

[0088] The circuit board includes a through electrode. For example, the circuit board includes a through electrode that penetrates the insulating layer and electrically connects circuit layers disposed on different layers.

[0089] For example, the through electrode includes a first through electrode (131) that penetrates the first insulating layer (111). The first through electrode (131) can electrically connect the first circuit layer (121) and the second circuit layer (122).

[0090] Additionally, the through electrode includes a second through electrode (132) that penetrates the second insulating layer (112). The second through electrode (132) can electrically connect the first circuit layer (121) and the third circuit layer (123).

[0091] Additionally, the through electrode includes a third through electrode (133) that penetrates the third insulating layer (113). The third through electrode (133) can electrically connect the second circuit layer (122) and the fourth circuit layer (124).

[0092] Additionally, the circuit board includes a protective layer. The protective layer may be disposed on the uppermost or lowermost side of the circuit board. The protective layer may protect the surface of a circuit layer or an insulating layer disposed on the uppermost or lowermost side of the circuit board.

[0093] Preferably, the protective layer may include a first protective layer (141) disposed on the upper surface of the second insulating layer (112). The first protective layer (141) may protect the upper surface of the second insulating layer (112) and the upper surface of the third circuit layer (123). Additionally, the first protective layer (141) may include a first opening (not shown) that overlaps in the thickness direction with at least a portion of the upper surface of the third circuit layer (123). The first opening may be formed to correspond to the mounting position of the electronic element.

[0094] Additionally, the protective layer may include a second protective layer (142) disposed on the lower surface of the third insulating layer (113). The second protective layer (142) may protect the lower surface of the third insulating layer (113) and the lower surface of the fourth circuit layer (124). Additionally, the second protective layer (142) may include a second opening (not shown) that overlaps in the thickness direction with at least a portion of the lower surface of the fourth circuit layer (124). The second opening may be formed to correspond to the mounting location of an electronic component or the connection location with an external substrate.

[0095] At this time, the first protective layer (141) and the second protective layer (142) may be solder resist, but are not limited thereto.

[0097] Below, the layer structure of the circuit layer and the surface roughness thereof according to the embodiment will be described in detail.

[0098] At this time, the layer structure of the circuit layer may vary depending on the manufacturing method of the circuit board. For example, the circuit layer may have different numbers of layers depending on the manufacturing method of the circuit board.

[0099] FIG. 3 is a drawing for explaining the layer structure of a circuit layer according to a first embodiment, and FIG. 4 is a drawing for explaining the layer structure of a circuit layer according to a second embodiment.

[0100] Hereinafter, the explanation will focus on one of the circuit layers from the first circuit layer (121) to the fourth circuit layer (124). For example, the layer structure of the first circuit layer (121) will be explained below. However, the layer structures of the second circuit layer (122), the third circuit layer (123), and the fourth circuit layer (124) may correspond to the layer structure of the first circuit layer (121) described below.

[0101] Accordingly, the first insulating layer (111) will be referred to as the insulating layer, the first circuit layer (121) as the circuit layer, and the first penetrating electrode (131) as the penetrating electrode for the following description.

[0102] Referring to FIG. 3, the circuit board of the first embodiment can be manufactured using the MSAP method.

[0103] Meanwhile, it was explained below that the circuit layer is composed of the first to third metal layers.

[0104] At this time, the circuit layer may include a first layer and a second layer.

[0105] Furthermore, the first layer of the circuit layer may refer to the first metal layer and the second metal layer described below. Furthermore, the second layer of the circuit layer may refer to the third metal layer described below.

[0106] Below, the explanation will focus on the first to third metal layers of the circuit layer.

[0107] Meanwhile, the circuit board includes an insulating layer (111), a circuit layer (121), and a through electrode (131).

[0108] The above circuit layer (121) may include a first metal layer (121-1) and a second metal layer (121-2).

[0109] The first metal layer (121-1) of the circuit layer (121) may be disposed on the upper surface of the insulating layer (111). The first metal layer (121-1) of the circuit layer (121) may represent a seed layer of the circuit layer (121).

[0110] At this time, the circuit layer (121) is manufactured by the MSAP process. Accordingly, the first metal layer (121-1) of the circuit layer (121) can be composed of multiple layers.

[0111] Preferably, the first metal layer (121-1) of the circuit layer (121) may include a first-1 metal layer (121-1a) and a first-2 metal layer (121-1b).

[0112] The first-1 metal layer (121-1a) of the first metal layer (121-1) of the circuit layer (121) may be disposed on the upper surface of the insulating layer (111). The first-1 metal layer (121-1a) of the first metal layer (121-1) of the circuit layer (121) may refer to a copper foil layer disposed on the upper surface of the insulating layer (111). For example, the first-1 metal layer (121-1a) of the first metal layer (121-1) of the circuit layer (121) may refer to a copper foil (Cu foil).

[0113] The first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) may be disposed on the first-first metal layer (121-1a). For example, the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) may be formed by performing electroless plating on the first-first metal layer (121-1a). Preferably, the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) may be a chemical copper plating layer.

[0114] The second metal layer (121-2) of the circuit layer (121) is disposed on the first metal layer (121-1) of the circuit layer (121). For example, the second metal layer (121-2) of the circuit layer (121) is disposed on the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121). For example, the second metal layer (121-2) of the circuit layer (121) may be an electroplated layer formed by electroplating the first-second metal layer (121-1b) as a seed layer.

[0115] Meanwhile, the penetrating electrode (131) can penetrate the insulating layer (111). For example, the penetrating electrode (131) can be formed by filling the inside of the penetrating hole penetrating the insulating layer (111) with a conductive material. At this time, the penetrating electrode (131) can be formed simultaneously during the formation process of the circuit layer (121).

[0116] Preferably, the through electrode (131) includes a first metal layer (131-1) corresponding to the first metal layer (121-1) of the circuit layer (121). Preferably, the first metal layer (131-1) of the through electrode (131) may correspond to the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121).

[0117] Specifically, the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) and the first metal layer (131-1) of the through electrode (131) may refer to a single layer formed by a chemical copper plating process. However, the first-second metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) and the first metal layer (131-1) of the through electrode (131) may be distinguished according to the placement position of the chemical copper plating layer.

[0118] For example, the first-2 metal layer (121-1b) of the first metal layer (121-1) of the circuit layer (121) may refer to a portion that contacts the first-1 metal layer (121-1a) of the first metal layer (121-1) of the circuit layer (121) in a single chemical copper plating layer.

[0119] For example, the first metal layer (131-1) of the through electrode (131) may refer to a portion in a chemical copper plating layer that contacts the inner wall of a through hole penetrating the insulating layer (111).

[0120] Meanwhile, the through electrode (131) may include a second metal layer (131-2). The second metal layer (131-2) of the through electrode (131) may correspond to the second metal layer (121-2) of the circuit layer (121).

[0121] Preferably, the through electrode (131) includes a second metal layer (131-2) corresponding to the second metal layer (121-2) of the circuit layer (121). That is, the second metal layer (121-2) of the circuit layer (121) and the second metal layer (131-2) of the through electrode (131) may refer to a single layer formed by performing electroplating on the chemical copper plating layer as a seed layer. However, the second metal layer (121-2) of the circuit layer (121) and the second metal layer (131-2) of the through electrode (131) may be distinguished according to the placement position of the electroplating layer.

[0122] For example, the second metal layer (131-2) of the through electrode (131) may refer to a portion disposed within the through hole of the insulating layer (111) in a single electroplating layer. For example, the second metal layer (121-2) of the circuit layer (121) may refer to a portion disposed outside the through hole in a single electroplating layer.

[0123] Meanwhile, the circuit layer of the circuit board of the second embodiment shown in FIG. 4 may have a different number of layers than the circuit layer of the circuit board of the first embodiment shown in FIG. 3.

[0124] For example, the through electrode of the circuit board of the second embodiment may have a structure substantially identical to the through electrode of the circuit board of the first embodiment.

[0125] However, the circuit layer (121) of the circuit board of the second embodiment may have a different number of layers than the circuit layer of the circuit board of the first embodiment.

[0126] For example, the circuit layer (121) of the circuit board of the second embodiment includes a first metal layer (121-1) and a second metal layer (121-2).

[0127] At this time, the first metal layer (121-1) of the circuit layer of the circuit board of the first embodiment included a first-1 metal layer (121-1a) and a first-2 metal layer (121-1b).

[0128] Alternatively, the first metal layer (121-1) of the circuit layer (121) of the circuit board of the second embodiment may be composed of a single layer. For example, the circuit layer (121) of the circuit board of the second embodiment may include only the first-2 metal layer (121-1b) of the first metal layer of the first embodiment.

[0129] That is, the circuit board of the second embodiment can be manufactured using the SAP method. In the process of forming the circuit layer using the SAP method, the copper foil layer or copper foil corresponding to the first-1 metal layer (121-1a) disposed on the surface of the insulating layer can be removed. Accordingly, the first metal layer corresponding to the seed layer in the circuit board of the second embodiment may include only the first-2 metal layer (121-1b) corresponding to the chemical copper plating layer. Furthermore, the first metal layer (121-1) corresponding to the first-2 metal layer (121-1b) in the second embodiment may be in direct contact with the upper surface of the insulating layer (111).

[0131] Meanwhile, the circuit layer (121) of the circuit board in FIGS. 3 and FIGS. 4 may represent a circuit layer prior to surface treatment according to an embodiment.

[0132] Hereinafter, the surface structure of the circuit layer (121) according to the embodiment will be described in detail. Specifically, the circuit layer (121) of the embodiment may form a surface treatment layer by performing surface treatment of the circuit layer of FIGS. 3 and FIGS. 4.

[0134] FIG. 5 is a drawing showing a circuit layer according to a first embodiment, FIG. 6 is a drawing showing the surface of a circuit layer before surface treatment according to an embodiment, FIG. 7 is a drawing showing the surface of a circuit layer after surface treatment according to an embodiment, and FIG. 8 is a drawing showing a circuit layer according to a second embodiment.

[0135] Referring to FIG. 5, the circuit layer (121) according to the first embodiment includes a surface. At this time, the surface of the circuit layer (121) may include a first surface (121U), a second surface (121S1), and a third surface (121S2).

[0136] At this time, the first surface (121U) of the circuit layer (121) may refer to the upper surface of the circuit layer (121). Also, the second surface (121S1) of the circuit layer (121) may refer to the first side or left side of the circuit layer (121). Additionally, the third surface (121S2) of the circuit layer (121) may refer to the second side or right side opposite to the first side of the circuit layer (121).

[0137] Specifically, the first surface (121U) of the circuit layer (121) may refer to the upper surface of the second metal layer (121-2) of the circuit layer (121). Additionally, the second surface (121S1) of the circuit layer (121) may refer to the left side of the first metal layer (121-1) and the left side of the second metal layer (121-2) of the circuit layer (121). For example, the second surface (121S1) of the circuit layer (121) may include a first portion corresponding to the left side or first side corresponding to the first metal layer (121-1) of the circuit layer (121), and a second portion corresponding to the left side or first side of the second metal layer (121-2). Additionally, the third surface (121S2) of the circuit layer (121) may refer to the right side of the first metal layer (121-1) of the circuit layer (121) and the right side of the second metal layer (121-2). For example, the third surface (121S2) of the circuit layer (121) may include a first portion corresponding to the right side or second side of the first metal layer (121-1) of the circuit layer (121), and a second portion corresponding to the right side or second side of the second metal layer (121-2).

[0138] At this time, the first surface (121U), the second surface (121S1), and the third surface (121S2) may refer to the surface of the circuit layer (121) prior to the surface treatment described below. Preferably, the first surface (121U), the second surface (121S1), and the third surface (121S2) may refer to a surface composed of the first metal layer (121-1) and the second metal layer (121-2) of the circuit layer (121).

[0139] And, the surfaces of the final circuit layer (121) further include a third metal layer (121-3) corresponding to the surface layer described below, in addition to the first metal layer (121-1) and the second metal layer (121-2). Accordingly, the surface of the final circuit layer (121) of the embodiment may have a structure including the third surface (121S2).

[0140] In the following description, the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121) are described as referring to the surface prior to surface treatment. However, the final surface of the circuit layer (121) may have a structure including the third metal layer (121-3) described below. This will be explained in more detail below.

[0141] Meanwhile, the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) may have a certain surface roughness. For example, at least one of the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) may have a surface roughness that the surface of the circuit layer (20) of the comparative example has.

[0142] For example, the arithmetic mean roughness (Ra) of the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) may exceed 0.3 μm. For example, the ten-point average roughness (Rz) of the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) may exceed 3.5 μm.

[0143] Meanwhile, the circuit board of the embodiment may include a surface layer (121-3) formed on at least one surface among the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121). For example, the circuit board of the embodiment may include a surface layer (121-3) formed on at least two surfaces among the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121).

[0144] Preferably, the surface layer (121-3) may be formed on the first surface (121U), the second surface (121S1), and the third surface (121U), respectively, of the circuit layer (121). At this time, the surface layer (121-3) may also be referred to as the third metal layer of the circuit layer (121). Hereinafter, the surface layer (121-3) will be described as the third metal layer (121-3).

[0145] The third metal layer (121-3) can be formed on the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121), respectively.

[0146] At this time, the third metal layer (121-3) may include a metal material different from the first metal layer (121-1) and the second metal layer (121-2) of the circuit layer (121). For example, the first metal layer (121-1) and the second metal layer (121-2) of the circuit layer (121) may include copper. And, the third metal layer (121-3) of the circuit layer (121) may include a metal material other than copper. For example, the third metal layer (121-3) of the circuit layer (121) may include tin (Sn).

[0147] Preferably, the circuit layer (121) of the embodiment may include a third metal layer (121-3) formed by electroless plating of tin (Sn) on the first surface (121U), the second surface (121S1), and the third surface (121S2).

[0148] At this time, the third metal layer (121-3) may be partially formed on the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121).

[0149] For example, the profile of the third metal layer (121-3) may differ from the profiles of the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121).

[0150] Specifically, the profiles of the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121) can correspond to the arithmetic mean roughness (Ra) and the ten-point average roughness (Rz).

[0151] For example, the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) include a plurality of peaks and valleys corresponding to the arithmetic mean roughness (Ra) and the ten-point average roughness (Rz). The peaks may refer to portions protruding outward from the circuit layer (121) on the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121). And the valleys may refer to portions recessed inward from the circuit layer (121) on the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121).

[0152] The profiles of the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121) may include peaks and valleys corresponding to the arithmetic mean roughness (Ra) and ten-point average roughness (Rz).

[0153] And the third metal layer (121-3) of the circuit layer (121) may have a different profile from the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121).

[0154] For example, in the case of a general electroless plating layer, the profile of the electroless plating layer can correspond to the profile of the underlying layer.

[0155] Alternatively, the third metal layer (121-3) in the embodiment may have a profile different from the profiles of the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121) which is the underlying layer.

[0156] This can be achieved by the composition of the plating solution for forming the third metal layer (121-3). Below, the composition of the plating solution for forming the third metal layer (121-3) will be described first.

[0157] The plating solution contains tin (Sn). For example, the plating solution may contain a first tin ion. For example, the plating solution may contain a first tin salt. Specifically, the plating solution may contain at least one first tin salt selected from the group consisting of tin methanesulfonate, tin sulfate, tin sulfamate, and tin pyrophosphate.

[0158] Additionally, the plating solution may include a complexing agent. The complexing agent may be added to the plating solution to enable copper substitution plating, which is theoretically impossible to perform due to surface electrode potential in electroless plating. For example, the complexing agent may include a thiourea derivative. Preferably, the complexing agent may be selected from the group consisting of 1,3-dimethylthiourea, trimethylthiourea, and diethylthiourea.

[0159] In addition, the plating solution may include a stabilizer. The stabilizer may be added to the plating solution to stabilize the tin plating solution or prevent decomposition. For example, the stabilizer may be selected from the group consisting of thiosulfates, sulfites, thioglycolic acid, and thioglycol polyethoxylates.

[0160] In addition, the plating solution may include an antioxidant. The antioxidant may be added to the plating solution to prevent first tin ions contained in the plating solution from being oxidized into second tin ions (e.g., tetravalent tin ions). For example, the antioxidant may be selected from the group consisting of resorcinol, prologlucinol, hydrazine, hypophosphorous acid, ascorbic acid, and cresolsulfonic acid.

[0161] In addition, the plating solution may include a surfactant. The surfactant may be added to the plating solution to improve the appearance, density, smoothness, and adhesion of the plating film. For example, the surfactant may include ethylene oxide or propylene oxide.

[0162] In addition, the plating solution may contain an additive. The additive may combine with tin ions contained in the plating solution to reduce the size of the crystal grains of the tin ions. For example, the additive may include benzotriazole or imidazole.

[0163] As described above, an additive that controls the crystal grains of the tin ions is added to the plating solution of the embodiment. The additive reduces the crystal grains of the tin ions so that plating can be performed such that the third metal layer (121-3) does not follow the profiles of the first surface (121U), second surface (121S1), and third surface (121S2) of the circuit layer (121).

[0164] For example, the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) include valleys and peaks. Furthermore, the third metal layer (121-3) may be formed by filling the valleys of the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) due to the additive. For example, the third metal layer (121-3) may be formed by filling a portion of the valleys on the surface of the circuit layer (121). Accordingly, in the embodiment, the surface roughness of the first surface (121U), the second surface (121S1), and the third surface (121S2) of the circuit layer (121) can be reduced in proportion to the thickness of the third metal layer (121-3). At this time, the third metal layer (121-3) can fill the grooves on the surface of the circuit layer (121) with a level of about 0.1 μm.

[0165] Accordingly, the surface of the final circuit layer (121) in the embodiment may include a first portion corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second portion corresponding to the third metal layer (121-3).

[0166] For example, the first surface (121U) of the circuit layer (121) may be divided into a plurality of parts. For example, the first surface (121U) of the circuit layer (121) may include a first part (121U1-1) corresponding to the second metal layer (121-2) and a second part (121U-2) corresponding to the third metal layer (121-3). For example, the first surface (121U) of the circuit layer (121) may include a first part (121U1-1) corresponding to a first metal material (e.g., copper) and a second part (121U-2) corresponding to a second metal material (e.g., tin) different from the first metal material.

[0167] For example, the second surface (121S1) of the circuit layer (121) may be divided into a plurality of parts. For example, the second surface (121S1) of the circuit layer (121) may include a first part (121S1-1) corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second part (121S1-2) corresponding to the third metal layer (121-3). For example, the second surface (121S1) of the circuit layer (121) may include a first part (121S1-1) corresponding to a first metal material (e.g., copper) and a second part (121S1-2) corresponding to a second metal material (e.g., tin) different from the first metal material.

[0168] For example, the third surface (121S2) of the circuit layer (121) may be divided into a plurality of parts. For example, the third surface (121S2) of the circuit layer (121) may include a first part (121S2-1) corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second part (121S2-2) corresponding to the third metal layer (121-3). For example, the third surface (121S2) of the circuit layer (121) may include a first part (121S2-1) corresponding to a first metal material (e.g., copper) and a second part (121S2-2) corresponding to a second metal material (e.g., tin) different from the first metal material.

[0169] As described above, in the embodiment, a surface layer is formed by performing a surface treatment using tin on the surface of the circuit layer (121). At this time, the surface layer may not be formed entirely on the surface of the circuit layer but may be formed partially. For example, the circuit layer may include a plurality of valleys and peaks corresponding to the surface roughness. Furthermore, the surface layer may be formed by partially filling the plurality of valleys on the surface of the circuit layer. In the embodiment, the surface roughness of the circuit layer may be reduced in proportion to the thickness of the surface layer filling the valleys.

[0170] Specifically, referring to FIGS. 6 and FIGS. 7, it was confirmed that the third metal layer (121-3) according to the embodiment is formed by filling a portion of the valley among the plurality of peaks and valleys on the surface of the circuit layer (121).

[0171] That is, FIG. 6(a) is a drawing (magnification: 10k) of the surface before the third metal layer (121-3) according to the embodiment is formed, and FIG. 6(b) is a drawing (magnification: 30k) of the surface of FIG. 6(a) tilted 40 degrees. Referring to FIG. 6(a) and (b), it was confirmed that prior to surface treatment (e.g., before the third metal layer (121-3) is formed), a certain level of surface roughness (e.g., peaks and valleys of a certain depth or height) is formed on the surface of the circuit layer (121).

[0172] That is, FIG. 7(a) is a drawing (magnification: 10k) of the surface of the circuit layer with the third metal layer (121-3) formed after surface treatment according to the embodiment, and FIG. 7(b) is a drawing (magnification: 30k) of the surface of FIG. 7(a) tilted 40 degrees. Referring to FIG. 7(a) and (b), it was confirmed that the surface of the circuit layer (121) after surface treatment has a lower surface roughness (e.g., low depth or low height peaks and valleys) than the surface of the circuit layer (121) before surface treatment.

[0174] Specifically, the embodiment can reduce the surface roughness of the circuit layer (121) by forming the third metal layer (121-3).

[0175] For example, the arithmetic mean roughness (Ra) of the surface of the circuit layer (121) of the embodiment may be 0.2 μm or less. For example, the arithmetic mean roughness (Ra) of the surface of the circuit layer (121) of the embodiment may be 0.1 μm or less.

[0176] Specifically, the arithmetic mean roughness (Ra) of the surface of the circuit layer (121) of the embodiment may have a range between 0.05 μm and 0.2 μm. Preferably, the arithmetic mean roughness (Ra) of the surface of the circuit layer (121) of the embodiment may have a range between 0.08 μm and 0.18 μm. More preferably, the arithmetic mean roughness (Ra) of the surface of the circuit layer (121) of the embodiment may have a range between 0.09 and 0.15 μm.

[0177] For example, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may be 1 μm or less. For example, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may be 0.8 μm or less. For example, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may be 0.6 μm or less.

[0178] Specifically, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may have a range between 0.1 μm and 1.0 μm. Preferably, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may have a range between 0.15 μm and 0.8 μm. More preferably, the ten-point average roughness (Rz) of the surface of the circuit layer (121) of the embodiment may have a range between 0.15 μm and 0.6 μm.

[0179] At this time, if the arithmetic mean roughness (Ra) or ten-point average roughness (Rz) of the surface of the circuit layer (121) is smaller than the range described above, the resistance of the circuit layer may increase. Additionally, if the arithmetic mean roughness (Ra) or ten-point average roughness (Rz) of the surface of the circuit layer (121) is smaller than the range described above, adhesion with the additionally stacked insulating layer may not be secured. Furthermore, if the arithmetic mean roughness (Ra) or ten-point average roughness (Rz) of the surface of the circuit layer (121) is larger than the range described above, signal transmission loss due to the skin effect may increase. For example, if the arithmetic mean roughness (Ra) or ten-point average roughness (Rz) of the surface of the circuit layer (121) is larger than the range described above, a circuit board suitable for high-frequency applications may not be provided.

[0181] Meanwhile, the results of testing the transmission loss of the circuit layer according to the embodiment are as shown in Table 1 below.

[0182] Transmission loss(dB / in), strip line 20GHz 30GHz 40GHz Example of implementation -1.49 -1.77 -2.04 Comparison Example -1.77 -2.12 -2.46

[0184] Referring to Table 1, it was confirmed that the signal transmission loss of the comparison example under conditions where a 20 GHz signal is transmitted was -1.77, and it was confirmed that the signal transmission loss of -1.49, which is lower than this, appeared in the example.

[0185] In addition, it was confirmed that the signal transmission loss of the comparison example under conditions where a 30 GHz signal is transmitted was -2.12, and it was confirmed that the signal transmission loss of -1.77, which is lower than this, appeared in the example.

[0186] In addition, it was confirmed that the signal transmission loss of the comparison example under conditions where a 40 GHz signal is transmitted was -2.46, and it was confirmed that the signal transmission loss of -2.04, which is lower than this, appeared in the example.

[0187] As described above, in the embodiment, plating is performed on the surface of the circuit layer (121) with a third metal layer (121-3). In addition, in the embodiment, the surface roughness of the circuit layer (121) is lower than that of the comparative example due to the third metal layer (121-3). Accordingly, in the embodiment, the signal transmission loss of the circuit layer (121) can be reduced, and the signal characteristics can be improved. Furthermore, in the embodiment, a circuit board suitable for high frequency applications can be provided.

[0188] Meanwhile, the third metal layer (121-3) according to the first embodiment in FIG. 5 is formed on the surface of the circuit layer (121) with a certain curvature. For example, the third metal layer (121-3) of the first embodiment may have a curved surface that is convex in the outward direction or a curved surface that is sunken in the inward direction.

[0189] In contrast, as illustrated in FIG. 8, the circuit layer (121a) of the second embodiment may have a shape different from that of the first embodiment.

[0190] For example, the surface of the circuit layer (121a) of the second embodiment may include a first surface (121Ua), a second surface (121S1a), and a third surface (121S2a).

[0191] The first surface (121Ua) of the circuit layer (121a) may be divided into a plurality of parts. For example, the first surface (121Ua) of the circuit layer (121a) may include a first part (121U1-1) corresponding to the second metal layer (121-2) and a second part (121U-2a) corresponding to the third metal layer (121-3a). For example, the first surface (121Ua) of the circuit layer (121a) may include a first part (121U1-1) corresponding to a first metal material (e.g., copper) and a second part (121U-2a) corresponding to a second metal material (e.g., tin) different from the first metal material. In this case, the first part (121U1-1) of the first surface (121Ua) may have a curve. And the second portion (121U-2a) of the first surface (121Ua) may be flat. At this time, the fact that the second portion (121U-2a) of the first surface (121Ua) is flat may mean that the difference between the maximum height and the minimum height of the upper surface of the second portion (121U-2a) is 0.05㎛ or less, or 0.03㎛ or less, or 0.02㎛ or less.

[0192] Additionally, the second surface (121S1a) of the circuit layer (121a) may include a first portion (121S1-1) corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second portion (121S1-2a) corresponding to the third metal layer (121-3a). For example, the second surface (121S1a) of the circuit layer (121a) may include a first portion (121S1-1) corresponding to a first metal material (e.g., copper) and a second portion (121S1-2a) corresponding to a second metal material different from the first metal material (e.g., tin). In this case, the first portion (121S1-1) of the second surface (121S1a) may have a certain curvature, and the second portion (121S1-2a) may be flat.

[0193] For example, the third surface (121S2a) of the circuit layer (121a) may be divided into a plurality of parts. For example, the third surface (121S2a) of the circuit layer (121a) may include a first part (121S2-1) corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second part (121S2-2a) corresponding to the third metal layer (121-3a). For example, the third surface (121S2a) of the circuit layer (121a) may include a first part (121S2-1) corresponding to a first metal material (e.g., copper) and a second part (121S2-2a) corresponding to a second metal material (e.g., tin) different from the first metal material. At this time, the first part (121S2-1) of the third surface (121S2a) may have a curve, and the second part (121S2-2a) may be flat.

[0195] Meanwhile, in the embodiment, the surface of the circuit layer (121) includes not only a first portion containing copper but also a second portion containing tin. Accordingly, in the embodiment, the adhesion between the circuit layer (121) and the second insulating layer (112) can be further improved.

[0196] FIG. 9 is a drawing illustrating the adhesion force between the circuit layer and the insulating layer according to an embodiment.

[0197] Referring to FIG. 9, the circuit board of the embodiment includes a first insulating layer (111), a circuit layer (121), and a second insulating layer (112).

[0198] At this time, the circuit layer (121) is placed on the first insulating layer (111). Then, the second insulating layer (112) is placed on the first insulating layer (111) to cover the circuit layer (121).

[0199] At this time, the surface of the circuit layer (121) is divided into a plurality of parts as described above. For example, the surface of the circuit layer (121) includes a first part containing copper corresponding to the first metal layer (121-1) and the second metal layer (121-2), and a second part containing tin corresponding to the third surface (121S2).

[0200] Accordingly, the lower surface of the second insulating layer (112) can be divided into a plurality of parts corresponding to the surface of the circuit layer (121).

[0201] For example, the lower surface of the second insulating layer (112) includes a first lower surface (112B1) that contacts the first metal layer (121-1) and the second metal layer (121-2) of the circuit layer (121). For example, the lower surface of the second insulating layer (112) includes a first lower surface (112B1) that contacts the first portion (121U-1) of the first surface (121U) of the circuit layer (121), the first portion (121S1-1) of the second surface (121S1), and the first portion (121S2-1) of the third surface (121S2).

[0202] Additionally, the lower surface of the second insulating layer (112) includes a second lower surface (112B2) that contacts the third metal layer (121-3) of the circuit layer (121). For example, the lower surface of the second insulating layer (112) includes a second lower surface (112B2) that contacts the second portion (121U-2) of the first surface (121U) of the circuit layer (121), the second portion (121S1-2) of the second surface (121S1), and the second portion (121S2-2) of the third surface (121S2).

[0203] Additionally, the lower surface of the second insulating layer (112) includes a third lower surface (112B3) that contacts the upper surface of the first insulating layer (111).

[0204] At this time, the second insulating layer in the comparative example included only the first and third lower surfaces among the lower surfaces of the second insulating layer of the embodiment.

[0205] Alternatively, the second insulating layer (112) of the embodiment further includes a second lower surface (112B2) in addition to the first lower surface (112B1) and the third lower surface (112B3). In the embodiment, by further including the second lower surface (112B2) in the second insulating layer (112), the adhesion between the second insulating layer (112) and the circuit layer (121) can be improved.

[0207] For example, the first portion of the surface of the circuit layer (121) contains copper. And the second portion of the circuit layer (121) contains tin. At this time, the isoelectric points for the respective oxides of copper and tin are as shown in Table 2 below. Here, the isoelectric point may represent the number of hydroxyl groups on the surface of the oxide of each material.

[0208] oxide IEPS CuO 9.5 SnO2 4.3

[0210] IEPS in Table 1 may be a unit representing the content of isoelectric point (IEP).

[0211] Referring to Table 1, it can be seen that the IEPS of copper oxide CuO is 9.5 and the IEPS of tin oxide SnO2 is 4.3.

[0212] In this case, a lower IEPS value indicates a higher number of hydroxyl groups on the surface of the oxide layer.

[0213] Here, the circuit layer of the comparative example consists solely of copper oxide with a relatively low hydroxyl content. Accordingly, there is a limit to increasing the adhesion between the circuit layer and the insulating layer of the comparative example.

[0214] In contrast, the surface of the circuit layer in the embodiment includes not only copper oxide but also tin oxide. Furthermore, the tin oxide contains a large number of hydroxyl groups compared to the copper oxide.

[0215] At this time, the number of hydroxyl groups is related to the adhesion force with the second insulating layer (112). For example, as the number of hydroxyl groups increases, the adhesion force with the second insulating layer (112), which is a dielectric layer, can be increased. In addition, in the embodiment, the second insulating layer (112) includes not only the first lower surface (112B1) but also the second lower surface (112B2). Accordingly, in the embodiment, the adhesion force between the circuit layer and the second insulating layer (112) can be further improved compared to the comparative example.

[0217] Meanwhile, in the embodiment, the depth of the undercut of the circuit layer (121) can be reduced compared to the comparative example by partially forming a third metal layer (121-3) on the surface of the circuit layer (121).

[0218] FIG. 10 is a drawing showing an undercut of a circuit layer of a comparative example, and FIG. 11 is a drawing showing an undercut of a circuit layer according to an embodiment.

[0219] Referring to FIG. 10, the circuit layer (20) includes a first metal layer (20-1) and a second metal layer (20-2). In the process of etching the first metal layer (20-1) of the circuit layer (20), a step may be formed between the side of the first metal layer (201) and the side of the second metal layer (20-2). The step may be an undercut formed on the lower side of the circuit layer (20). The depth of the undercut may refer to the horizontal distance between the outermost side of the circuit layer (20) and the innermost side of the circuit layer (20).

[0220] At this time, the depth (w1) of the undercut in the comparative example exceeded 5 μm. For example, the depth (w1) of the undercut in the comparative example exceeded 6 μm. In addition, the undercut can act as a factor that reduces the electrical reliability and physical reliability of the circuit layer. For example, as the depth of the undercut increases, the electrical reliability and physical reliability of the circuit layer may decrease.

[0221] Referring to FIG. 11, the circuit layer (121) of the embodiment includes a first metal layer (121-1), a second metal layer (121-2), and a third metal layer (121-3). The third metal layer (121-3) may be partially formed on the surface of the first metal layer (121-1) and the second metal layer (121-2).

[0222] At this time, the third metal layer (121-3) is also disposed on the side of the first metal layer (121-1). For example, the third metal layer (121-3) is formed by filling a portion of the groove on the side of the first metal layer (121-1). Accordingly, in the embodiment, the depth of the undercut of the circuit layer (121) can be reduced to correspond to the thickness of the third metal layer (121-3).

[0223] For example, the embodiment can reduce the depth (W1) of the undercut to 4 μm or less. For example, the embodiment can reduce the depth (W1) of the undercut to 3 μm or less. Accordingly, in the embodiment, the depth of the undercut of the circuit layer (121) can be reduced compared to the comparative example, and accordingly, the electrical reliability and physical reliability of the circuit layer (121) can be improved.

[0225] FIG. 12 is a drawing showing a semiconductor package according to an embodiment.

[0226] Referring to FIG. 12, the semiconductor package of the embodiment includes a circuit board described with reference to the previous drawings.

[0227] The circuit board includes a first protective layer (141) and a second protective layer (142). The first protective layer (141) and the second protective layer (142) each include an opening.

[0228] Meanwhile, the semiconductor package includes a first connection portion (210) disposed at an opening of the first protection layer (141). For example, the first connection portion (210) may be disposed on a third circuit layer (123) that is vertically superimposed on the opening of the first protection layer (141).

[0229] The first connection part (210) may include a spherical shape. For example, the cross-section of the first connection part (210) may include a circular shape or a semicircular shape. For example, the cross-section of the first connection part (210) may include a partially or entirely rounded shape. For example, the cross-sectional shape of the first connection part (210) may be flat on one side and curved on the other side. The first connection part (210) may be a solder ball, but is not limited thereto.

[0230] A component (220) may be disposed on the first connection portion (210). The component (220) may be a processor chip. For example, the component (220) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller. However, the embodiment is not limited thereto, and the component (220) may be various types of passive or active components other than a processor chip, such as a driver IC, a capacitor, an inductor, etc.

[0231] A terminal (225) is formed on the lower surface of the above element (220). The terminal (225) of the above element (220) is connected to the first connection part (210). Through this, the above element (220) can be electrically connected to the third circuit layer (123).

[0232] At this time, the drawing shows that one element is mounted on the circuit board, but it is not limited thereto. For example, the semiconductor package of the embodiment may include a first element and a second element arranged horizontally spaced apart from each other on a single circuit board.

[0233] For example, the first and second elements may be different types of application processors (APs).

[0234] At this time, the first element and the second element may be spaced apart at a certain distance in the horizontal direction on the circuit board. For example, the horizontal spacing between the first element and the second element may be 150 μm or less. For example, the horizontal spacing between the first element and the second element may be 120 μm or less. For example, the horizontal spacing between the first element and the second element may be 100 μm or less.

[0235] Preferably, the horizontal separation width between the first element and the second element may satisfy a range of 60 μm to 150 μm. More preferably, the horizontal separation width between the first element and the second element may satisfy a range between 70 μm and 120 μm. Even more preferably, the horizontal separation width between the first element and the second element may satisfy a range of 80 μm to 110 μm.

[0236] At this time, if the horizontal separation width between the first element and the second element is less than 60 μm, the mutual interference between the first element and the second element may cause problems with the operational reliability of the first element or the second element. Additionally, if the horizontal separation width between the first element and the second element is greater than 150 μm, the signal transmission distance between the first element and the second element increases, and the signal transmission loss may increase accordingly.

[0237] Meanwhile, the semiconductor package may include a molding layer (230). The molding layer (230) may be placed on the circuit board to mold the device (220). The molding layer (230) may function to protect the device (220). For example, the molding layer (230) may be an EMC (Epoxy Mold Compound), but is not limited thereto.

[0238] Meanwhile, the molding layer (230) may have a low dielectric constant. Accordingly, the molding layer (230) may have improved heat dissipation characteristics. To this end, the dielectric constant (Dk) of the molding layer (230) may be 0.2 to 10. Preferably, the dielectric constant of the molding layer (230) may be 0.5 to 5. More preferably, the dielectric constant of the molding layer (230) may be 0.8 to 5. Accordingly, in the embodiment, the molding layer (230) may have a low dielectric constant. By doing so, in the embodiment, the heat dissipation characteristics for heat generated in the device (220) can be improved.

[0239] Meanwhile, the semiconductor package further includes a second connection portion (240). The second connection portion (240) may be disposed at the bottom side of the circuit board. Preferably, the second protective layer (142) includes an opening. And, the second connection portion (240) may be disposed within the opening of the second protective layer (142). Preferably, at least a portion of the lower surface of the fourth circuit layer (124) overlaps with the opening of the second protective layer (142) in the thickness direction. And, the second connection portion (240) may be disposed on the lower surface of the fourth circuit layer (124) that overlaps with the opening of the second protective layer (142) in the thickness direction. The second connection portion (240) may be for connecting the semiconductor package and an external substrate (e.g., a main board of an electronic device).

[0241] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0242] FIGS. 13 to 23 are drawings for explaining a method for manufacturing a circuit board according to an embodiment in process order.

[0243] Referring to FIG. 13, the embodiment prepares a base material that serves as the basis for manufacturing a circuit board. For example, the base material may have a structure in which an insulating layer and a copper foil layer or copper foil is attached on the insulating layer.

[0244] Specifically, the base material of the embodiment may include a first insulating layer (111), a first-1 metal layer (121-1a) of a first circuit layer (121) disposed on the upper surface of the first insulating layer (111), and a first-1 metal layer (122-1a) of a second circuit layer (122) disposed on the lower surface of the first insulating layer (111).

[0245] Next, referring to FIG. 14, the embodiment may proceed with a process of forming a through hole (TH1) that penetrates the upper and lower surfaces of the prepared base material. At this time, FIG. 14 may represent a manufacturing method for manufacturing a circuit board using an MSAP process. Alternatively, when manufacturing a circuit board using an SAP process, a process of removing the first-1 metal layer (121-1a) of the first circuit layer (121) and the first-1 metal layer (122-1a) of the second circuit layer (122) may be performed.

[0246] The above through hole (TH1) can penetrate from the upper surface of the first-1 metal layer (121-1a) of the first circuit layer (121) to the lower surface of the first-1 metal layer (122-1a) of the second circuit layer (122).

[0247] Next, referring to FIG. 15, the embodiment may proceed with a process of forming a chemical copper plating layer by performing chemical copper plating.

[0248] At this time, the chemical copper plating layer is substantially formed as a single layer, but can be classified as follows depending on the location.

[0249] That is, the chemical copper plating layer may include a first-2 metal layer (121-1b) of the first circuit layer (121) formed on the upper surface of the first-1 metal layer (121-1a) of the first circuit layer (121), a first-2 metal layer (122-1b) of the second circuit layer (122) formed on the lower surface of the first-1 metal layer (122-1a) of the second circuit layer (122), and a first metal layer (131-1) of the first through electrode (131) formed on the inner wall of the through hole (TH1).

[0250] Next, as illustrated in FIG. 16, the embodiment may proceed with a process of forming a mask.

[0251] For example, the embodiment may proceed with a process of forming a first mask (M1) on the upper surface of the first-second metal layer (121-1b) of the first circuit layer (121). At this time, the first mask (M1) may include an open portion. For example, the first mask (M1) may include an open portion that overlaps in the thickness direction with the placement area of ​​the second metal layer (121-2) of the first circuit layer (121) and the placement area of ​​the first through electrode (131).

[0252] Additionally, the embodiment may proceed with a process of forming a second mask (M2) on the lower surface of the first-second metal layer (122-1b) of the second circuit layer (122). At this time, the second mask (M2) may include an open portion. For example, the second mask (M2) may include an open portion that overlaps in the thickness direction with the placement area of ​​the second metal layer (122-2) of the second circuit layer (122) and the placement area of ​​the first through electrode (131).

[0253] Next, as illustrated in FIG. 17, the embodiment can form an electroplating layer that fills the open portion of the first mask (M1), the open portion of the second mask (M2), and the through hole (TH1).

[0254] At this time, the electrolytic plating layer may refer to a single layer substantially connected to one another, but may be divided into multiple parts as follows depending on the location.

[0255] The electrolytic plating layer may include a second metal layer (121-2) of a first circuit layer (121) disposed in an open portion of the first mask (M1). Additionally, the electrolytic plating layer may include a second metal layer (122-2) of a second circuit layer (122) disposed in an open portion of the second mask (M2). Furthermore, the electrolytic plating layer may include a second metal layer (131-2) of a first through electrode (131) disposed within the through hole (TH1).

[0256] Next, as illustrated in FIG. 18, the embodiment may proceed with the process of removing the first mask (M1) and the second mask (M2).

[0257] At this time, as the first mask (M1) is removed, the non-placement area of ​​the second metal layer (121-2) of the first circuit layer (121) on the upper surface of the first-second metal layer (121-1b) of the first circuit layer (121) may be exposed to the outside.

[0258] Additionally, as the second mask (M2) is removed, the non-placement area of ​​the second metal layer (122-2) of the second circuit layer (122) on the lower surface of the first-second metal layer (122-1b) of the second circuit layer (122) may be exposed to the outside.

[0259] Next, referring to FIG. 19, in the embodiment, a process can be performed to remove by etching a region that does not overlap in the thickness direction with the second metal layer (121-2) of the first circuit layer (121) among the first metal layers (1-1 metal layer and 1-2 metal layer) of the first circuit layer (121).

[0260] In addition, in the embodiment, a process can be performed to remove by etching a region that does not overlap in the thickness direction with the second metal layer (122-2) of the second circuit layer (122) among the first metal layers (1-1 metal layer and 1-2 metal layer) of the second circuit layer (122).

[0261] At this time, the thickness of each of the first metal layers of the first circuit layer (121) and the second circuit layer (122) is approximately 3 μm. Accordingly, the etching process may mean a process of removing about 3 μm in the thickness direction.

[0262] Here, in the etching process of the first metal layer, the surfaces of the first circuit layer (121) and the second circuit layer (122) may have an arithmetic mean roughness (Ra) and a ten-point average roughness (Rz) as described above.

[0263] For example, the first metal layer (121-1) and the second metal layer (121-2) of the first circuit layer (121) may be pretreated in the etching process. Furthermore, the first metal layer (121-1) and the second metal layer (121-2) of the first circuit layer (121) may be given surface roughness of arithmetic mean roughness (Ra) and ten-point average roughness (Rz) as described above through the pretreatment.

[0264] Accordingly, the first metal layer (122-1) and the second metal layer (122-2) of the second circuit layer (122) may be pretreated in the etching process. Furthermore, the first metal layer (122-1) and the second metal layer (122-2) of the second circuit layer (122) may be given surface roughness of arithmetic mean roughness (Ra) and ten-point average roughness (Rz) as described above through the pretreatment.

[0265] Next, as illustrated in FIG. 20, in the embodiment, a process of forming a surface layer on the surface of the first circuit layer (121) and the surface of the second circuit layer (122) can be carried out. At this time, the surface layer may be partially formed on the surface of the first circuit layer (121) and the surface of the second circuit layer (122), respectively.

[0266] For example, the surface layer includes a first surface layer (121-3) disposed on the surface of the first circuit layer (121) or a third metal layer (121-3) of the first circuit layer (121). Furthermore, the third metal layer (121-3) of the first circuit layer (121) may be formed on the upper surface and side surface of the first circuit layer (121). At this time, the surface of the first circuit layer (121) includes a plurality of peaks and valleys corresponding to the surface roughness imparted in the pretreatment process. Furthermore, the third metal layer (121-3) may be formed by filling a portion of the valleys on the surface of the first circuit layer (121).

[0267] Accordingly, the surface layer includes a second surface layer (122-3) disposed on the surface of the second circuit layer (122) or a third metal layer (122-3) of the second circuit layer (122). Furthermore, the third metal layer (122-3) of the second circuit layer (122) may be formed on the lower surface and side surface of the second circuit layer (122). At this time, the surface of the second circuit layer (122) includes a plurality of peaks and valleys corresponding to the surface roughness imparted in the pretreatment process. Furthermore, the third metal layer (122-3) may be formed by filling a portion of the valleys on the surface of the second circuit layer (122). Accordingly, in the embodiment, the first circuit layer (121) is configured to include the third metal layer (121-3), thereby allowing the surface roughness of the surface of the first circuit layer (121) to be lowered compared to the comparative example. In addition, by including the third metal layer (122-3) of the second circuit layer (122), the surface roughness of the second circuit layer (122) can be lowered compared to the comparative example.

[0268] Next, as illustrated in FIG. 21, in the embodiment, a process of laminating a second insulating layer (112) on the upper surface of the first insulating layer (111) can be carried out. Additionally, in the embodiment, a process of laminating a third insulating layer (113) on the lower surface of the first insulating layer (111) can be carried out.

[0269] At this time, the second insulating layer (112) may include a first lower surface in contact with the first metal layer (121-1) and the second metal layer (121-2) of the first circuit layer (121), a second lower surface in contact with the third metal layer (121-3) of the first circuit layer (121), and a third lower surface in contact with the upper surface of the first insulating layer (111).

[0270] Additionally, the third insulating layer (113) may include a first upper surface in contact with the first metal layer (122-1) and the second metal layer (122-2) of the second circuit layer (122), a second upper surface in contact with the third metal layer (122-3) of the second circuit layer (122), and a third upper surface in contact with the lower surface of the first insulating layer (111).

[0271] Next, referring to FIG. 22, in the embodiment, a process may be carried out to form a second through electrode (132) penetrating the second insulating layer (112) and a third circuit layer (123) disposed on the upper surface of the second insulating layer (112). At this time, the process of forming the third circuit layer (123) may be the same as the process of forming the first circuit layer (121). Accordingly, the surface roughness of the third circuit layer (123) may correspond to the surface roughness of the first circuit layer (121). For example, the third circuit layer (123) may include first to third metal layers corresponding to the first circuit layer (121). To this end, in the process of laminating the second insulating layer (112), a copper foil layer (not shown) or a copper foil (not shown) may be disposed on the upper surface of the second insulating layer (112).

[0272] Additionally, in the embodiment, a process may be performed to form a third penetrating electrode (133) penetrating the third insulating layer (113) and a fourth circuit layer (124) disposed on the lower surface of the third insulating layer (1131). At this time, the process of forming the fourth circuit layer (124) may be the same as the process of forming the second circuit layer (122). Accordingly, the surface roughness of the fourth circuit layer (124) may correspond to the surface roughness of the second circuit layer (122). For example, the fourth circuit layer (124) may include first to third metal layers corresponding to the second circuit layer (122). To this end, in the process of laminating the third insulating layer (113), a copper foil layer (not shown) or a copper foil (not shown) may be disposed on the lower surface of the third insulating layer (112).

[0273] Next, as illustrated in FIG. 23, in the embodiment, a process of forming a first protective layer (141) on the upper surface of the second insulating layer (112) can be carried out. Additionally, in the embodiment, a process of forming a second protective layer (142) on the lower surface of the third insulating layer (113) can be carried out. Furthermore, in the embodiment, a process of forming a first opening on the first protective layer (141) that overlaps in the thickness direction with at least a portion of the upper surface of the third circuit layer (123). Additionally, in the embodiment, a process of forming a second opening on the second protective layer (142) that overlaps in the thickness direction with at least a portion of the lower surface of the fourth circuit layer (124) can be carried out.

[0275] The circuit board of the embodiment includes a circuit layer. The circuit layer includes a first metal layer corresponding to a seed layer and a second metal layer disposed on the first metal layer. At this time, the surface of the circuit layer may be imparted with a certain level of surface roughness during the etching process of the first metal layer. Furthermore, the imparted surface roughness may act as a factor that increases signal transmission loss. Consequently, it may be difficult to apply it for high-frequency applications.

[0276] Accordingly, the circuit layer of the embodiment includes a third metal layer. The third metal layer is selectively disposed on the surface of the first metal layer and the surface of the second metal layer. For example, the surface of the circuit layer includes a first surface corresponding to the upper surface of the second metal layer. And, the third metal layer is partially disposed on the first surface. Specifically, the first surface includes a plurality of valleys and peaks corresponding to the applied surface roughness. And, the third metal layer is formed by filling a portion of the valleys on the first surface through the control of the crystal grains of metal ions in the plating solution. Accordingly, in the embodiment, the surface roughness of the first surface can be lowered to correspond to the thickness of the third metal layer.

[0277] Accordingly, the surface of the circuit layer includes a second surface corresponding to the first side of the first metal layer and the first side of the second metal layer. Additionally, the surface of the circuit layer includes a third surface corresponding to the second side of the first metal layer and the second side of the second metal layer. Furthermore, the third metal layer is arranged to fill not only the first surface but also a portion of the grooves of the second surface and a portion of the grooves of the third surface. Accordingly, in the embodiment, the surface roughness of the second surface and the third surface of the circuit layer can be reduced.

[0278] Through this, the embodiment can reduce the signal transmission loss of the circuit layer compared to the comparative example. By doing so, the signal characteristics of the circuit board can be improved in the embodiment. Furthermore, the embodiment can provide a circuit board suitable for high frequency applications.

[0279] Meanwhile, in the embodiment, the third metal layer is arranged to fill only a portion of the grooves on the first to third surfaces. Accordingly, in the embodiment, the surface roughness of the circuit layer can be lowered without affecting the thickness and line width of the circuit layer composed of the first metal layer and the second metal layer. Accordingly, the embodiment can further improve the electrical reliability and physical reliability of the circuit board.

[0280] Meanwhile, in the embodiment, an additional insulating layer is laminated on the circuit layer. At this time, the additional insulating layer contacts the third metal layer in addition to the first and second metal layers of the circuit layer. At this time, the first and second metal layers may contain copper, and the third metal layer may contain tin. At this time, the tin contains more hydroxyl groups than the copper. Furthermore, the additional insulating layer may have a higher adhesion to the third metal layer than to the first and second metal layers. In this case, the additional insulating layer in the comparative example contacts only the first and second metal layers of the circuit layer. Accordingly, in the comparative example, there is a limit to increasing the adhesion between the circuit layer and the additional insulating layer. In contrast, the additional insulating layer in the embodiment contacts the third metal layer in addition to the first and second metal layers of the circuit layer. Accordingly, the adhesion between the circuit layer and the additional insulating layer can be improved in the embodiment compared to the comparative example. Accordingly, the product reliability of the circuit board can be further improved in the embodiment.

[0281] Meanwhile, an undercut is formed on the lower side of the circuit layer of the comparative example. The undercut acts as a factor that reduces the reliability of the circuit layer. In this case, in the embodiment, the depth of the undercut can be reduced by the thickness of the third metal layer compared to the comparative example. Accordingly, the product reliability of the circuit board can be further improved in the embodiment.

[0283] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the antenna board to which the invention is applied to achieve functional integration or technical interoperability.

[0284] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0285] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

Claims

Claim 1 A circuit board comprising: a first insulating layer; and a circuit layer disposed on the first insulating layer, wherein the circuit layer comprises: a first metal layer disposed on the first insulating layer; a second metal layer disposed on the first metal layer; and a third metal layer partially disposed on the second metal layer, wherein the upper surface of the second metal layer comprises a plurality of peaks and valleys, and the third metal layer is formed by filling at least one portion of the plurality of valleys on the upper surface of the second metal layer. Claim 2 In claim 1, the profile of the upper surface of the second metal layer is different from the profile of the upper surface of the third metal layer, circuit board. Claim 3 delete Claim 4 In claim 1, the third metal layer is disposed on the side of the first metal layer and on the side of the second metal layer, and the respective profiles of the side of the first metal layer and the side of the second metal layer are different from the profile of the side of the third metal layer, circuit board. Claim 5 A circuit board according to claim 4, wherein each of the sides of the first metal layer and the side of the second metal layer comprises a plurality of peaks and valleys, and the third metal layer fills at least one part of the plurality of valleys on each of the sides of the first and second metal layers. Claim 6 A circuit board according to claim 1, wherein the upper surface of the circuit layer comprises a first portion corresponding to the upper surface of the second metal layer and a second portion corresponding to the upper surface of the third metal layer. Claim 7 A circuit board according to claim 6, wherein the arithmetic mean roughness (Ra) of the upper surface of the circuit layer has a range between 0.05 μm and 0.2 μm, and the ten-point average roughness (Rz) of the upper surface of the circuit layer has a range between 0.1 μm and 1.0 μm. Claim 8 A circuit board according to claim 4 or 5, wherein the side of the circuit layer comprises a first portion corresponding to the side of the first and second metal layers and a second portion corresponding to the side of the third metal layer. Claim 9 A circuit board according to claim 8, wherein the arithmetic mean roughness (Ra) of the side of the circuit layer has a range between 0.05 μm and 0.2 μm, and the ten-point average roughness (Rz) of the side of the circuit layer has a range between 0.1 μm and 1.0 μm. Claim 10 A circuit board according to claim 1, comprising a second insulating layer disposed on the first insulating layer to cover the circuit layer, wherein the lower surface of the second insulating layer comprises a first lower surface in contact with the second metal layer of the circuit layer, a second lower surface in contact with the third metal layer of the circuit layer, and a third lower surface in contact with the first insulating layer. Claim 11 A circuit board according to claim 10, wherein the second metal layer of the circuit layer comprises a first metal material, and the third metal layer of the circuit layer comprises a second metal material different from the first metal material. Claim 12 A circuit board according to claim 11, wherein the first metal material comprises copper and the second metal material comprises tin. Claim 13 A circuit board according to claim 1, wherein the first metal layer comprises a first-1 metal layer and a first-2 metal layer disposed on the first-1 metal layer, and the second metal layer disposed on the first-2 metal layer. Claim 14 A circuit board comprising: an insulating layer; and a circuit layer disposed on the insulating layer; wherein the surface of the circuit layer comprises a first portion comprising a first metal material and a second portion comprising a second metal material different from the first metal material, wherein the first metal material comprises copper and the second metal material comprises tin, wherein the surface of the circuit layer comprises an upper surface, a left surface, a right surface, and a lower surface of the circuit layer, and the arithmetic mean roughness (Ra) of at least two surfaces among the upper surface, left surface, right surface, and lower surface of the circuit layer has a range between 0.05 μm and 0.2 μm. Claim 15 delete Claim 16 A circuit board according to claim 14, wherein the ten-point average roughness (Rz) of at least two surfaces among the upper surface, left side, right side, and lower surface of the circuit layer has a range between 0.1 μm and 1.0 μm. Claim 17 A semiconductor package comprising: a plurality of insulating layers; a plurality of circuit layers each disposed on the surface of the plurality of insulating layers; a first connection portion disposed on the uppermost circuit layer among the plurality of circuit layers; and a component disposed on the first connection portion, wherein at least one of the plurality of circuit layers, the first circuit layer comprises a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the first metal layer and the second metal layer, wherein the upper surface of the first circuit layer comprises a first upper surface corresponding to the second metal layer and a second upper surface corresponding to the third metal layer, and the side surface of the first circuit layer comprises a first side surface corresponding to the first metal layer and the second metal layer and a second side surface corresponding to the third metal layer, and at least one of the upper surface of the first circuit layer and the side surface of the first circuit layer has an arithmetic mean roughness (Ra) in the range of 0.05 μm to 0.2 μm and a ten-point average roughness (Rz) in the range of 0.1 μm to 1.0 μm.

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