Display device

Abstract

A display device comprises a substrate, an active pattern disposed on the substrate and including a first region, a second region, a first-1 channel region, a first-2 channel region, and a third region located between the first-1 channel region and the first-2 channel region, a first insulating layer disposed on the substrate and covering the active pattern, a second insulating layer disposed on the first insulating layer and having an opening that overlaps with the first-2 channel region, the second region, and the third region, a first gate electrode disposed on the first insulating layer and overlapping with the first-1 channel region and the first-2 channel region, respectively, and a high dielectric layer disposed on the first insulating layer and the second insulating layer, covering the first gate electrode and filling the opening.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device that provides visual information. Background Technology

[0002] As information technology develops, the importance of display devices, which serve as a medium of connection between users and information, is being highlighted. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs), and quantum dot display devices is increasing.

[0003] The display device includes a plurality of pixels, and each pixel includes a plurality of transistors and a storage capacitor. For example, the plurality of transistors include a switching transistor and a driving transistor.

[0004] Meanwhile, a display device can emit light using various signals. Current leakage may occur during the process of these signals being transmitted to the light-emitting element. In this case, the light-emitting performance of the display device may be degraded.

[0005] In addition, the driving transistor must have a wide driving range of gate voltage to control rich gradations by adjusting the magnitude of the driving transistor's gate voltage. The problem to be solved

[0006] The objective of the present invention is to provide a display device with improved display quality.

[0007] However, the purpose of the present invention is not limited to such purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0008] To achieve the aforementioned objectives of the present invention, a display device according to embodiments of the present invention may comprise a substrate, an active pattern disposed on the substrate and comprising a first region, a second region, a first-1 channel region, a first-2 channel region, and a third region located between the first-1 channel region and the first-2 channel region, a first insulating layer disposed on the substrate and covering the active pattern, a second insulating layer disposed on the first insulating layer and having an opening that overlaps with the first-2 channel region, the second region, and the third region, a first gate electrode disposed on the first insulating layer and overlapping with the first-1 channel region and the first-2 channel region, respectively, and a high dielectric layer disposed on the first insulating layer and the second insulating layer, covering the first gate electrode and filling the opening.

[0009] In one embodiment, the high dielectric layer may comprise at least one selected from the group consisting of aluminum oxide (Al2O3), zirconium oxide (ZrO), and hafnium oxide (HfO2).

[0010] In one embodiment, the first insulating layer and the second insulating layer may comprise different inorganic materials.

[0011] In one embodiment, the first insulating layer is silicon oxide (SiO₂). x ...including ), and the second insulating layer is silicon nitride (SiN x It may include ).

[0012] In one embodiment, the thickness of the first insulating layer may be different from the thickness of the second insulating layer.

[0013] In one embodiment, the thickness of the first insulating layer may be 800 Å to 1,400 Å, and the thickness of the second insulating layer may be 200 Å to 600 Å.

[0014] In one embodiment, the thickness of the high dielectric layer may be 300 Å to 1,000 Å.

[0015] In one embodiment, the first gate electrode may include a first portion disposed on the second insulating layer that overlaps with the first-1 channel region and overlaps with the first-2 channel region and a second portion disposed on the first insulating layer.

[0016] In one embodiment, the first portion of the first gate electrode may form a first-1 switching transistor together with the first region of the active pattern, the first-1 channel region, and a portion of the third region, and the second portion of the first gate electrode may form a first-2 switching transistor together with the second region of the active pattern, the first-2 channel region, and a portion of the third region.

[0017] In one embodiment, the display device may further include a third insulating layer disposed on the high dielectric layer and comprising at least one selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride, and a capacitor electrode disposed on the third insulating layer.

[0018] In one embodiment, the thickness of the third insulating layer may be 500 Å to 1,400 Å.

[0019] In one embodiment, the portion of the capacitor electrode that overlaps with the third region of the active pattern can form a node capacitor together with the third region of the active pattern.

[0020] In one embodiment, the active pattern may further include a fourth region, a fifth region, and a second channel region located between the fourth region and the fifth region.

[0021] In one embodiment, the display device further includes a second gate electrode disposed on the same layer as the first gate electrode, overlapping with the second channel region, and covered by the high dielectric layer, and the second gate electrode may form a driving transistor together with the fourth region, the fifth region, and the second channel region of the active pattern.

[0022] In one embodiment, the portion of the capacitor electrode that overlaps with the second gate electrode may form a storage capacitor together with the second gate electrode.

[0023] In one embodiment, the active pattern may include at least one selected from the group consisting of polysilicon and amorphous silicon.

[0024] To achieve the aforementioned objectives of the present invention, a display device according to embodiments of the present invention may comprise a substrate, an active pattern disposed on the substrate and comprising a first region, a second region, a first-1 channel region, a first-2 channel region, and a third region located between the first-1 channel region and the first-2 channel region, a first insulating layer disposed on the substrate and covering the active pattern, a second insulating layer disposed on the first insulating layer and having an opening that overlaps the first-2 channel region, the second region, and the third region, a capacitor electrode disposed on the first insulating layer and at least a portion of which forms a node capacitor together with the third region of the active pattern, and a high dielectric layer disposed between the first insulating layer and the capacitor electrode and filling the opening.

[0025] In one embodiment, the high dielectric layer may comprise at least one selected from the group consisting of aluminum oxide (Al2O3), zirconium oxide (ZrO), and hafnium oxide (HfO2).

[0026] In one embodiment, the display device may further include a gate electrode comprising a first portion disposed between the second insulating layer and the high dielectric layer and overlapping with the first-1 channel region, and a second portion disposed between the first insulating layer and the high dielectric layer and overlapping with the first-2 channel region.

[0027] In one embodiment, the first portion of the gate electrode may form a first-1 switching transistor together with the first region of the active pattern, the first-1 channel region, and a portion of the third region, and the second portion of the gate electrode may form a first-2 switching transistor together with the second region of the active pattern, the first-2 channel region, and a portion of the third region. Effects of the invention

[0028] A display device according to one embodiment of the present invention may include an insulating layer disposed on a substrate and having an opening that overlaps with a portion of an active pattern constituting a first-second switching transistor, and a high dielectric layer that fills the opening and includes a material with a high dielectric constant. Accordingly, a node capacitor composed of a capacitor electrode that overlaps with an active pattern and a portion of an active pattern constituting a first-second switching transistor may be increased. In this case, the leakage current flowing through the first-second switching transistor becomes greater than the leakage current flowing through the first-first switching transistor, thereby reducing the leakage current flowing through the first-first switching transistor. Additionally, a wide driving range of the driving transistor may be secured.

[0029] However, the effects of the present invention are not limited to the above effects, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0030] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing a pixel of the display device of Figure 1. Figure 3 is a cross-sectional view showing an example of the display device of Figure 1. Figure 4 is a layout diagram showing pixels included in the display device of Figure 1. FIGS. 5 to 11 are layouts showing the components illustrated in FIG. 4 layer by layer. Figure 12 is a cross-sectional view taken along line II' of Figure 9. Figure 13 is a cross-sectional view taken along the line II-II' of Figure 9. FIGS. 14 to 20 are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention. Specific details for implementing the invention

[0031] Hereinafter, a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings will be referred to by the same reference numerals, and redundant descriptions of identical components will be omitted.

[0032] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.

[0033] Referring to FIG. 1, a display device (DD) according to one embodiment of the present invention may include a display area (DA) and a peripheral area (PA). The display area (DA) may be defined as an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area (PA) may be defined as an area that does not display an image. Additionally, the peripheral area (PA) may surround at least a portion of the display area (DA). For example, the peripheral area (PA) may completely surround the display area (DA).

[0034] A plurality of pixels (PX) may be arranged in a display area (DA). For example, each of the pixels (PX) may include a driving element (e.g., a transistor, etc.) and a light-emitting element (e.g., a light-emitting diode, etc.) electrically connected to the driving element. The light-emitting element may emit light by receiving a signal from the driving element. In this way, the display device (DD) can display an image by the plurality of pixels (PX) emitting light.

[0035] A single pixel (PX) can display a single predetermined primary color. In other words, a single pixel (PX) can be the minimum unit capable of displaying a color independent of other pixels (PX). For example, a single pixel (PX) can display any one of red, green, and blue.

[0036] Pixels (PX) can be arranged in a matrix form along a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). For example, the first direction (DR1) and the second direction (DR2) can be orthogonal.

[0037] A driving unit for driving a plurality of pixels (PX) may be disposed in a peripheral area (PA). For example, the driving unit may include a data driving unit, a gate driving unit, a light emission driving unit, a power supply voltage generating unit, a timing controller, etc. The plurality of pixels (PX) may emit light based on signals received from the driving units.

[0038] Figure 2 is a circuit diagram showing a pixel of the display device of Figure 1.

[0039] Referring to FIGS. 1 and 2, each pixel (PX) may include a pixel circuit (PC) and a light-emitting element (EL). The pixel circuit (PC) may be connected to the light-emitting element (EL). The pixel circuit (PC) may include first to eighth transistors (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, T8), a storage capacitor (CST), a first node capacitor (CN1), and a second node capacitor (CN2).

[0040] The first transistor (T1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor (T1) may be connected to a first node (N1). The first electrode of the first transistor (T1) may be connected to a second node (N2). The second electrode of the first transistor (T1) may be connected to a third node (N3).

[0041] The first transistor (T1) can generate a driving current based on the difference between the data voltage (DATA) and the driving voltage (ELVDD). The first transistor (T1) can provide the driving current to the light-emitting element (EL).

[0042] The second transistor (T2) may include a gate electrode, a first electrode, and a second electrode. A data write signal (GW) may be applied to the gate electrode of the second transistor (T2). A data voltage (DATA) may be applied to the first electrode of the second transistor (T2). The second electrode of the second transistor (T2) may be connected to a second node (N2). The second transistor (T2) may provide the data voltage (DATA) to the second node (N2) in response to the data write signal (GW).

[0043] The third-1 transistor (T3-1) may include a gate electrode, a first electrode, and a second electrode. A compensation gate signal (GC) may be applied to the gate electrode of the third-1 transistor (T3-1). The first electrode of the third-1 transistor (T3-1) may be connected to a fourth node (N4). The second electrode of the third-1 transistor (T3-1) may be connected to a fifth node (N5).

[0044] The third-2 transistor (T3-2) may include a gate electrode, a first electrode, and a second electrode. A compensation gate signal (GC) may be applied to the gate electrode of the third-2 transistor (T3-2). The first electrode of the third-2 transistor (T3-2) may be connected to a fifth node (N5). The second electrode of the third-2 transistor (T3-2) may be connected to a third node (N3).

[0045] As the third transistor, comprising the third-1 transistor (T3-1) and the third-2 transistor (T3-2), is configured as a dual transistor, leakage current occurring in the pixel circuit (PC) can be prevented. The third transistor can compensate the threshold voltage of the first transistor (T1) by diode-connecting the first transistor (T1) in response to a compensation gate signal (GC).

[0046] The 4-1 transistor (T4-1) may include a gate electrode, a first electrode, and a second electrode. An initialization gate signal (GI) may be applied to the gate electrode of the 4-1 transistor (T4-1). The first electrode of the 4-1 transistor (T4-1) may be connected to the 4th node (N4). The second electrode of the 4-1 transistor (T4-1) may be connected to the 6th node (N6).

[0047] The 4-2 transistor (T4-2) may include a gate electrode, a first electrode, and a second electrode. An initialization gate signal (GI) may be applied to the gate electrode of the 4-2 transistor (T4-2). The first electrode of the 4-2 transistor (T4-2) may be connected to the 6th node (N6). An initialization voltage (VNIT) may be applied to the second electrode of the 4-2 transistor (T4-2).

[0048] The fourth transistor, comprising the fourth-1 transistor (T4-1) and the fourth-2 transistor (T4-2), may be configured as a dual transistor. The fourth transistor may provide an initialization voltage (VINT) to the gate electrode of the first transistor (T1) in response to an initialization gate signal (GI).

[0049] The fifth transistor (T5) may include a gate electrode, a first electrode, and a second electrode. A light emission control signal (EM) may be applied to the gate electrode of the fifth transistor (T5). A driving voltage (ELVDD) may be applied to the first electrode of the fifth transistor (T5). The second electrode of the fifth transistor (T5) may be connected to a second node (N2).

[0050] The sixth transistor (T6) may include a gate electrode, a first electrode, and a second electrode. A light emission control signal (EM) may be applied to the gate electrode of the sixth transistor (T6). The first electrode of the sixth transistor (T6) may be connected to the third node (N3). The second electrode of the sixth transistor (T6) may be connected to the seventh node (N7).

[0051] Each of the fifth transistor (T5) and the sixth transistor (T6) can provide the driving current generated in the first transistor (T1) to the light-emitting element (EL) in response to the light-emitting control signal (EM).

[0052] The seventh transistor (T7) may include a gate electrode, a first electrode, and a second electrode. A bias control signal (EB) may be applied to the gate electrode of the seventh transistor (T7). The first electrode of the seventh transistor (T7) may be connected to the seventh node (N7). An anode initialization voltage (AINT) may be applied to the second electrode of the seventh transistor (T7). The seventh transistor (T7) may provide the anode initialization voltage (AINT) to the anode electrode of the light-emitting element (EL) in response to the bypass control signal (EB).

[0053] The eighth transistor (T8) may include a gate electrode, a first electrode, and a second electrode. A bypass control signal (EB) may be applied to the gate electrode of the eighth transistor (T8). The first electrode of the eighth transistor (T8) may be connected to a second node (N2). A bias voltage (VBIAS) may be applied to the second electrode of the eighth transistor (T8). The eighth transistor (T8) may provide the bias voltage (VBIAS) to the second node (N2) in response to the bypass control signal (EB).

[0054] A storage capacitor (CST) may include a first electrode and a second electrode. A driving voltage (ELVDD) may be applied to the first electrode of the storage capacitor (CST). The second electrode of the storage capacitor (CST) may be connected to a first node (N1).

[0055] The first node capacitor (CN1) may include a first electrode and a second electrode. A driving voltage (ELVDD) may be applied to the first electrode of the first node capacitor (CN1). The second electrode of the first node capacitor (CN1) may be connected to a fifth node (N5) between the third transistors (T3-1, T3-2).

[0056] The second node capacitor (CN2) may include a first electrode and a second electrode. A driving voltage (ELVDD) may be applied to the first electrode of the second node capacitor (CN2). The second electrode of the second node capacitor may be connected to the sixth node (N6) between the fourth transistors (T4-1, T4-2).

[0057] The light-emitting element (EL) may include an anode electrode and a cathode electrode. The anode electrode of the light-emitting element (EL) may be connected to a seventh node (N7). A common voltage (ELVSS) may be applied to the cathode electrode of the light-emitting element (EL). The voltage level of the common voltage (ELVSS) may be lower than the voltage level of the driving voltage (ELVDD). The light-emitting element (EL) may emit light based on the driving current.

[0058] However, although it has been described that each pixel (PX) of the present invention comprises eight transistors, one storage capacitor, and two node capacitors, the configuration of the present invention is not limited thereto. For example, each pixel (PX) may have a configuration comprising at least one transistor, at least one storage capacitor, and at least one node capacitor.

[0059] FIG. 3 is a cross-sectional view showing an example of the display device of FIG. 1. For example, FIG. 3 schematically shows an example of a cross-section of a display area (DA).

[0060] Referring to FIG. 3, a display device (DD) according to one embodiment of the present invention may include a substrate (SUB), a circuit layer (CL), a light-emitting element (EL), a pixel defining film (PDL), and an encapsulation layer (TFE).

[0061] The substrate (SUB) may include a transparent or opaque material. The substrate (SUB) may be made of a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate. In this case, the polyimide substrate (SUB) may include a first organic layer, a first barrier layer, a second organic layer, etc. Optionally, the substrate (SUB) may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz (F-doped quartz) substrate, a sodalime glass substrate, a non-alkali glass substrate, etc. These may be used alone or in combination with each other.

[0062] A circuit layer (CL) may be disposed on a substrate (SUB). The circuit layer (CL) may provide signals and voltages to the light-emitting element (EL) for the light-emitting element (EL) to emit light. For example, the circuit layer (CL) may include a transistor, a conductive layer, an insulating layer, etc.

[0063] A pixel electrode (PE) may be disposed on the circuit layer (CL). The pixel electrode (PE) may receive the signals and voltages from the circuit layer (CL). For example, the pixel electrode (PE) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode (PE) may be an anode electrode. Optionally, the pixel electrode (PE) may be a cathode electrode.

[0064] A pixel defining film (PDL) may be disposed on a circuit layer (CL) and a pixel electrode (PE). The pixel defining film (PDL) may have an opening that exposes a portion of the pixel electrode (PE). By having the opening, the pixel defining film (PDL) may define each pixel (PX) that emits light. The pixel defining film (PDL) may include an organic material or an inorganic material. Examples of the organic material that can be used as the pixel defining film (PDL) include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0065] A light-emitting layer (EML) may be disposed on a pixel electrode (PE). Specifically, the light-emitting layer (EML) may be disposed within the opening of the pixel defining film (PDL). The light-emitting layer (EML) may include materials for emitting light. For example, the light-emitting layer (EML) may include an organic light-emitting material or an inorganic light-emitting material.

[0066] A common electrode (CE) may be disposed on the pixel defining layer (PDL) and the light-emitting layer (EML). For example, the common electrode (CE) may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode (CE) may be a cathode electrode. Optionally, the common electrode (CE) may be an anode electrode.

[0067] Accordingly, a light-emitting element (EL) including a pixel electrode (PE), a light-emitting layer (EML), and a common electrode (CE) can be disposed on a substrate (SUB).

[0068] An encapsulation layer (TFE) may be disposed on a common electrode (CE). The encapsulation layer (TFE) can protect the light-emitting element (EL) from external oxygen and moisture. The encapsulation layer (TFE) may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer (TFE) may include a first inorganic layer (TFE1) disposed on the common electrode (CE), an organic layer (TFE2) disposed on the first inorganic layer (TFE1), and a second inorganic layer (TFE3) disposed on the organic layer (TFE2).

[0069] FIG. 4 is a layout diagram showing pixels included in the display device of FIG. 1. For example, FIG. 4 may be an example of a plan view showing the circuit layer (CL) of FIG. 3. The light-emitting element (EL) of FIG. 3 may be placed on the layout diagram shown in FIG. 4.

[0070] Referring to FIGS. 1 and 4, a plurality of pixels (PX) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). For example, the first pixel (PX1) may emit green light, the second pixel (PX2) may emit red light, and the third pixel (PX3) may emit blue light. However, the color of the light emitted by each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) is not limited thereto. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include the same component.

[0071] In the following, since the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) have the same components, we will describe one pixel (e.g., the first pixel (PX1)) in detail.

[0072] FIGS. 5 through 11 are layouts showing the components illustrated in the layout of FIG. 4 in layers. For example, FIG. 5 is a layout showing the active layer (100) of FIG. 4. FIG. 6 is a layout showing the first conductive layer (200) of FIG. 4. FIG. 7 is a layout showing the active layer (100) and the first conductive layer (200) of FIG. 4. FIG. 8 is a layout showing the second conductive layer (300) of FIG. 4. FIG. 9 is a layout showing the active layer (100), the first conductive layer (200), and the second conductive layer (300) of FIG. 4. FIG. 10 is a layout showing the third conductive layer (400) of FIG. 4. FIG. 11 is a layout showing the fourth conductive layer (500) of FIG. 4.

[0073] Referring to FIGS. 3, 4, and 5, a display device (DD) according to one embodiment of the present invention may further include an active layer (100). The active layer (100) may be disposed on a substrate (SUB). Specifically, a buffer layer may be disposed on the substrate (SUB), and the active layer (100) may be disposed on the buffer layer.

[0074] The active layer (100) may include a first active pattern (101) and a second active pattern (102). The first active pattern (101) and the second active pattern (102) may be disposed on the same layer. The first active pattern (101) and the second active pattern (102) may have different shapes on a plane.

[0075] The first active pattern (101) may include a first-1 channel area (CA1-1), a first-2 channel area (CA1-2), a second channel area (CA2), a third-1 channel area (CA3-1), and a third-2 channel area (CA3-2) that are spaced apart from each other.

[0076] The first active pattern (101) may further include a first region (A1), a second region (A2), a third region (A3), a fourth region (A4), and a fifth region (A5) that are spaced apart from each other. The first region (A1) may be located adjacent to each of the first-1 channel region (CA1-1) and the third-1 channel region (CA3-1). The second region (A2) may be located adjacent to each of the first-2 channel region (CA1-2) and the second channel region (CA2). The third region (A3) may be located between the first-1 channel region (CA1-1) and the first-2 channel region (CA1-2). The fourth region (A4) may be located adjacent to the second channel region (CA2). The fifth region (A5) may be located adjacent to each of the second channel region (CA2) and the first-2 channel region (CA1-2).

[0077] The active layer (100) may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. In one embodiment, the active layer (100) may include an inorganic semiconductor.

[0078] Referring to FIGS. 3, 4, 6 and 7, a display device (DD) according to one embodiment of the present invention may further include a first conductive layer (200). The first conductive layer (200) may be disposed on an active layer (100). Specifically, a first insulating layer covering the active layer (100) may be disposed on the active layer (100), and the first conductive layer (200) may be disposed on the first insulating layer.

[0079] The first conductive layer (200) may include a first gate electrode (201), a second gate electrode (202), a third gate electrode (203), a fourth gate electrode (204), a light emission control wiring (205), and a bias control wiring (206). The first gate electrode (201), the second gate electrode (202), the third gate electrode (203), the fourth gate electrode (204), the light emission control wiring (205), and the bias control wiring (206) may be disposed on the same layer.

[0080] The first gate electrode (201) may include a first portion (201a) and a second portion (201b). The first portion (201a) of the first gate electrode (201) extends in a second direction (DR2), and the second portion (201b) of the first gate electrode (201) may extend in a first direction (DR2) that is orthogonal to the second direction (DR2).

[0081] A part of the first active pattern (101) (i.e., part of the first region (A1), the first-1 channel region (CA1-1), and the third region (A2)) and a first part (201a) of the first gate electrode (201) that overlaps with the first-1 channel region (CA1-1) of the first active pattern (101) may form a third-1 transistor (T3-1), and a second part (203b) of the first gate electrode (201) that overlaps with a part of the first active pattern (101) (i.e., part of the second region (A2), the first-2 channel region (CA1-2), and the third region (A3)) and the first-2 channel region (CA1-2) of the first active pattern (101) may form a third-2 transistor (T3-2). The source region of the third-1 transistor (T3-1) may be the first region (A1), and the drain region of the third-1 transistor (T3-1) may be the third region (A3). Additionally, the source region of the third-2 transistor (T3-2) may be the third region (A3), and the drain region of the third-2 transistor (T3-2) may be the second region (A2).

[0082] The second gate electrode (202) may have an island shape on a plane. A portion of the first active pattern (101) (i.e., the fourth region (A4), the second channel region (CA2), and the fifth region (A5)) and a portion of the second gate electrode (202) that overlaps with the second channel region (CA2) of the first active pattern (101) may form the first transistor (T1). The source region of the first transistor (T1) may be the fourth region (A4), and the drain region of the first transistor (T1) may be the fifth region (A5).

[0083] The third gate electrode (203) may include a first portion (203a), a second portion (203b), and a third portion (203c). The first portion (203a) of the third gate electrode (203) may extend in a second direction (DR2). The second portion (203b) and the third portion (203c) of the third gate electrode (203) may each extend in a first direction (DR1). The second portion (203b) and the third portion (203c) of the third gate electrode (203) may be spaced apart from each other.

[0084] A first part (203a) of a third gate electrode (203) that overlaps with the first active pattern (101) and the third-1 channel region (CA3-1) of the first active pattern (101) may form a fourth-1 transistor (T4-1), and a second part (203b) of a third gate electrode (203) that overlaps with the first active pattern (101) and the third-2 channel region (CA3-2) of the first active pattern (101) may form a fourth-2 transistor (T4-2).

[0085] The first active pattern (101) and the portion of the fourth gate electrode (204) that overlaps with the first active pattern (101) can form a second transistor (T2).

[0086] The light-emitting control wiring (205) may be extended in a first direction (DR1). A portion of the first active pattern (101) and a portion of the light-emitting control wiring (205) that overlaps with the first active pattern (101) (i.e., the gate electrode) may form a fifth transistor (T5). A portion of the first active pattern (101) and a portion of the light-emitting control wiring (205) that overlaps with the first active pattern (101) (i.e., the gate electrode) may form a sixth transistor (T6).

[0087] The bias control wiring (206) may be extended in a first direction (DR1). A portion of the first active pattern (101) and a portion of the bias control wiring (206) that overlaps with the first active pattern (101) (i.e., the gate electrode) may form a seventh transistor (T7). A portion of the second active pattern (102) and a portion of the bias control wiring (206) that overlaps with the second active pattern (102) (i.e., the gate electrode) may form an eighth transistor (T8).

[0088] The first conductive layer (200) may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0089] Here, the first transistor (T1) may be referred to as a driving transistor. Additionally, the third-1 transistor (T3-1) and the fourth-1 transistor (T4-1) may each be referred to as the first-1 switching transistor, and the third-2 transistor (T3-2) and the fourth-2 transistor (T4-2) may each be referred to as the first-2 switching transistor.

[0090] Referring to FIGS. 3, 4, 8 and 9, a display device (DD) according to one embodiment of the present invention may further include a second conductive layer (300). The second conductive layer (300) may be disposed on the first conductive layer (200). Specifically, an insulating layer may be disposed on the first conductive layer (200), and the second conductive layer (300) may be disposed on the insulating layer.

[0091] The second conductive layer (300) may include a capacitor electrode (301) and a repair wiring (302). The capacitor electrode (301) and the repair wiring (302) may be disposed on the same layer.

[0092] A hole (H) penetrating the capacitor electrode (301) may be formed in the capacitor electrode (301). The hole (H) may overlap with the second gate electrode (202). The third region (A3) of the first active pattern (101) and the portion of the capacitor electrode (301) that overlaps with the third region (A3) of the first active pattern (101) may form a first node capacitor (CN1). The portion of the first active pattern (101) and the portion of the capacitor electrode (301) that overlaps with the said portion of the first active pattern (101) may form a second node capacitor (CN2). Additionally, the second gate electrode (202) and the portion of the capacitor electrode (301) that overlaps with the second gate electrode (202) may form a storage capacitor (CST).

[0093] The repair wiring (302) can be extended in a first direction (DR1). The repair wiring (302) can increase the yield of the display device (DD). For example, if a defect occurs in some of the wirings during the process of manufacturing the display device (DD), the repair wiring (302) can replace said wirings.

[0094] The second conductive layer (300) may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0095] Referring to FIGS. 3, 4 and 10, a display device (DD) according to one embodiment of the present invention may further include a third conductive layer (400). The third conductive layer (400) may be disposed on the second conductive layer (300). Specifically, an insulating layer may be disposed on the second conductive layer (300), and the third conductive layer (400) may be disposed on the insulating layer.

[0096] The third conductive layer (400) may include a first connection pattern (401), a driving voltage connection pattern (402), a lower anode connection pattern (403), a second connection pattern (404), a data connection pattern (405), an initialization gate wiring (406), a data writing wiring (407), a compensation gate wiring (408), an extension wiring (409), an anode initialization connection wiring (410), and a bias voltage connection wiring (411).

[0097] The first connection pattern (401), the driving voltage connection pattern (402), the lower anode connection pattern (403), the second connection pattern (404), the data connection pattern (405), the initialization gate wiring (406), the data writing wiring (407), the compensation gate wiring (408), the extension wiring (409), the anode initialization connection wiring (410), and the bias voltage connection wiring (411) can be placed on the same layer.

[0098] The first connection pattern (401) can be extended in a second direction (DR2) that is orthogonal to the first direction (DR1). The first connection pattern (401) can be in contact with the first active pattern (101) and the second active pattern (102), respectively.

[0099] The driving voltage connection pattern (402) can be extended in a first direction (DR1). The driving voltage connection pattern (402) can provide a driving voltage (e.g., the driving voltage (ELVDD) of FIG. 2) to the first active pattern (101).

[0100] The lower anode connection pattern (403) can be extended in a first direction (DR1). The lower anode connection pattern (403) can come into contact with the first active pattern (101). Accordingly, the lower anode connection pattern (403) can connect the first active pattern (101) and the light-emitting element (EL).

[0101] The second connection pattern (404) can be extended in the second direction (DR2). The first connection pattern (404) can be in contact with the first active pattern (101) and the second gate electrode (202), respectively.

[0102] The data connection pattern (405) can come into contact with the first active pattern (101). The data connection pattern (405) can provide a data voltage (e.g., the data voltage (DATA) of FIG. 2) to the first active pattern (101).

[0103] The initialization gate wiring (406) may be extended in a first direction (DR1). The initialization gate wiring (406) may be in contact with a third gate electrode (203). The initialization gate wiring (406) may provide an initialization gate signal (e.g., the initialization gate signal (GI) of FIG. 2) to the third gate electrode (203).

[0104] The data writing wiring (407) may be extended in a first direction (DR1). The data writing wiring (407) may be in contact with the fourth gate electrode (204). The data writing wiring (407) may provide a data writing signal (e.g., the data writing signal (GW) of FIG. 2) to the fourth gate electrode (204).

[0105] The compensation gate wiring (408) can be extended in a first direction (DR1). The compensation gate wiring (408) can overlap with the first gate electrode (201). The compensation gate wiring (408) can provide a compensation gate signal (e.g., the compensation gate signal (GC) of FIG. 2) to the first gate electrode (201).

[0106] The extension wiring (409) can be extended in a first direction (DR1). The extension wiring (409) can be in contact with the bias control wiring (206).

[0107] The anode initialization connection wiring (410) may be extended in a first direction (DR1). The anode initialization connection wiring (410) may be in contact with a first active pattern (101). The anode initialization connection wiring (410) may provide an anode initialization voltage (e.g., the anode initialization voltage (AINT) of FIG. 2) to the first active pattern (101).

[0108] The bias voltage connection wiring (411) may be extended in a first direction (DR1). The bias voltage connection wiring (411) may be in contact with a second active pattern (102). The bias voltage connection wiring (411) may provide a bias voltage (e.g., the bias voltage (VBIAS) of FIG. 2) to the second active pattern (102).

[0109] The third conductive layer (400) may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. These may be used alone or in combination with each other.

[0110] Referring to FIGS. 3, 4 and 11, a display device (DD) according to one embodiment of the present invention may further include a fourth conductive layer (500). The fourth conductive layer (500) may be disposed on a third conductive layer (400). Specifically, an insulating layer may be disposed on the third conductive layer (400), and the fourth conductive layer (500) may be disposed on the insulating layer.

[0111] The fourth conductive layer (500) may include a data wiring (501), a common voltage wiring (502), an initialization voltage wiring (503), and an upper anode connection pattern (504). The data wiring (501), the driving voltage wiring (502), the anode initialization voltage wiring (503), and the upper anode connection pattern (504) may be placed on the same layer.

[0112] The data wiring (501) may extend in a second direction (DR2) orthogonal to the first direction (DR1). The data wiring (501) may come into contact with a data connection pattern (405). The data wiring (501) may provide a data voltage (e.g., the data voltage (DATA) of FIG. 2) to the first active pattern (101).

[0113] The driving voltage wiring (502) may be extended in a second direction (DR2). The driving voltage wiring (502) may be in contact with the driving voltage connection pattern (402). The driving voltage wiring (502) may provide a driving voltage (e.g., the driving voltage (ELVDD) of FIG. 2) to the first active pattern (101).

[0114] The anode initialization voltage wiring (503) may be extended in a second direction (DR2). The anode initialization voltage wiring (503) may be in contact with the anode initialization connection wiring (410). The initialization voltage wiring (503) may provide an anode initialization voltage (e.g., the anode initialization voltage (AINT) of FIG. 2) to the first active pattern (101).

[0115] The upper anode connection pattern (504) can come into contact with the lower anode connection pattern (403). Accordingly, the upper anode connection pattern (504) can connect the first active pattern (101) and the light-emitting element (EL).

[0116] The fourth conductive layer (500) may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0117] FIG. 12 is a cross-sectional view taken along line II' of FIG. 9. FIG. 13 is a cross-sectional view taken along line II-II' of FIG. 9. However, while FIG. 12 shows the cross-sectional structure of the 3-1 and 3-2 transistors (T3-1, T3-2), the present invention is not limited thereto. For example, the cross-sectional structure of the 4-1 and 4-2 transistors (T4-1, T4-2) of FIG. 2 and FIG. 7 may be substantially the same as the cross-sectional structure of the 3-1 and 3-2 transistors (T3-1, T3-2) shown in FIG. 12.

[0118] Referring to FIGS. 9, 12, and 13, a buffer layer (150) may be disposed on a substrate (SUB). The buffer layer (150) can prevent impurities from diffusing from the substrate to the active layer (100). Additionally, the buffer layer (150) can control the rate of heat transfer generated during the process of forming the active layer (100). Thus, the active layer (100) can be formed uniformly. For example, the buffer layer (150) may include an organic material or an inorganic material.

[0119] An active layer (100) may be disposed on a buffer layer (150). Specifically, a first active pattern (101) of the active layer (100) may be disposed on the buffer layer (150).

[0120] The first active pattern (101) may include a first region (A1), a second region (A2), a first-1 channel region (CA1-1), a first-2 channel region (CA1-2), and a third region (A3) located between the first-1 channel region (CA1-1) and the first-2 channel region (CA1-2). Additionally, the first active pattern (101) may further include a fourth region (A4), a fifth region (A5), and a second channel region (CA2) located between the fourth region (A4) and the fifth region (A5). Impurities may be doped into the first region (A1), the second region (A2), the third region (A3), the fourth region (A4), and the fifth region (A5).

[0121] A first insulating layer (250a) may be disposed on the buffer layer (150). The first insulating layer (250a) may sufficiently cover the first active pattern (101). The first insulating layer (250a) may include an inorganic material. For example, the first insulating layer (250a) may be silicon oxide (SiO₂). x ), silicon nitride (SiO₂ y ), silicon oxynitride (SiO₂ x N y These may include ) etc. These may be used alone or in combination with each other. In one embodiment, the first insulating layer (250a) may include silicon oxide.

[0122] A second insulating layer (250b) may be disposed on the first insulating layer (250a). The second insulating layer (250b) may include an inorganic material. For example, the second insulating layer (250b) may include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other. In one embodiment, the second insulating layer (250b) may include silicon nitride.

[0123] The second insulating layer (250b) may have an opening (OP) that overlaps with a part of the first active pattern (101). In one embodiment, the opening (OP) may overlap with the second region (A2), the first-second channel region (CA1-2), and the third region (A3) of the first active pattern (101). That is, the opening (OP) may not overlap with the first region (A1) and the first-first channel region (CA1-1) of the first active pattern (101).

[0124] The thickness of the first insulating layer (250a) may differ from the thickness of the second insulating layer (250b). For example, the thickness of the second insulating layer (250b) may be smaller than the thickness of the first insulating layer (250a). In one embodiment, the thickness of the first insulating layer (250a) may be about 800 Å to 1,400 Å, and the thickness of the second insulating layer (250b) may be about 200 Å to 600 Å.

[0125] A first gate electrode (201) may be disposed on the first insulating layer (250a). Additionally, a second gate electrode (202) may be disposed on the second insulating layer (250b). A first portion (201a) of the first gate electrode (201) may overlap with the first-1 channel region (CA1-1) and may be disposed on the second insulating layer (250b). A second portion (201b) of the first gate electrode (201) may overlap with the first-2 channel region (CA1-2) and may be disposed on the first insulating layer (250a). Specifically, the second portion (201b) of the first gate electrode (201) may be disposed inside the opening (OP) of the second insulating layer (250b).

[0126] In one embodiment, a high dielectric layer (350) may be disposed on the first insulating layer (250a) and the second insulating layer (250b). The high dielectric layer (350) may cover the first gate electrode (201) and the second gate electrode (202) and fill the opening (OP) of the second insulating layer (250b).

[0127] For example, the high dielectric layer (350) may include an inorganic material with a high dielectric constant. In one embodiment, the high dielectric layer (350) may include aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. These may be used alone or in combination with each other. However, the composition of the present invention is not limited thereto, and the high dielectric layer (350) may include other inorganic materials with a high dielectric constant.

[0128] In one embodiment, the thickness of the high dielectric layer (350) may be about 300 Å to about 1,000 Å.

[0129] A third insulating layer (250c) may be disposed on the high dielectric layer (350). The third insulating layer (250c) may include an inorganic material. For example, the third insulating layer (250c) may include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other. In one embodiment, the third insulating layer (250c) may include silicon nitride.

[0130] In one embodiment, the thickness of the third insulating layer (250c) may be about 500 Å to about 1,400 Å.

[0131] A capacitor electrode (301) may be disposed on the third insulating layer (250c). A portion of the capacitor electrode (301) may partially overlap with the third region (A3) of the first active pattern (101). Additionally, another portion of the capacitor electrode (301) may partially overlap with the second gate electrode (202).

[0132] In order to reduce the leakage current flowing through the switching transistors (e.g., the 3-1 and 3-2 transistors (T3-1, T3-2) or the 4-1 and 4-2 transistors (T4-1, T4-2) of FIG. 2 and 7), the first active pattern (101) must have few defects. Additionally, in order to secure a wide driving range of the driving transistor (e.g., the first transistor (T1) of FIG. 2), the first active pattern (101) must have many defects. That is, the leakage current flowing through the switching transistors and the driving range of the driving transistor may have a trade-off relationship. For example, if the first active pattern (101) has many defects, the leakage current flowing through the switching transistors increases, and a wide driving range of the driving transistor can be secured.

[0133] A display device (DD) according to one embodiment of the present invention may include a second insulating layer (250b) having an opening (OP) that overlaps with a portion of the first active pattern (101) constituting the first-second switching transistor (i.e., a portion of the second region (A2), the first-second channel region (CA1-2), and the third region (A3)) and a high dielectric layer (350) that fills the opening (OP) and includes a material with a high dielectric constant. Accordingly, the node capacitor (e.g., the first node capacitor (CN1) or the second node capacitor (CN2) of FIG. 9) may be increased. In this case, the leakage current flowing through the first-second switching transistor may be greater than the leakage current flowing through the first-first switching transistor, thereby reducing the leakage current flowing through the first-first switching transistor. Additionally, a wide driving range of the driving transistor may be secured. In other words, the leakage current flowing through the switching transistors is reduced, and at the same time, a wide driving range of the driving transistor can be secured.

[0134] FIGS. 14 to 20 are cross-sectional views illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0135] Referring to FIG. 14, a buffer layer (150) may be formed on a substrate (SUB) comprising a transparent material or an opaque material. For example, the buffer layer (150) may be formed using an organic material or an organic material.

[0136] A first active pattern (101) can be formed on the buffer layer (150). For example, the first active pattern (101) can be formed using polysilicon, amorphous silicon, etc.

[0137] A first insulating layer (250a) may be formed on the buffer layer (150). The first insulating layer (250a) may sufficiently cover the first active pattern (101). For example, the first insulating layer (250a) may be formed using silicon oxide, silicon nitride, silicon oxynitride, etc.

[0138] An insulating film (450) may be formed on the first insulating layer (250a). The insulating film (450) may be formed entirely on the first insulating layer (250a). The insulating film (450) may be formed using silicon oxide, silicon nitride, etc.

[0139] Referring to FIG. 15, a photoresist layer (550) may be formed on an insulating film (450). The photoresist layer (550) may be formed using photoresist. The photoresist layer (550) may have an opening that overlaps with a part of the first active pattern (101). The opening may overlap with a part of the first active pattern (101) that constitutes the third-second transistor (e.g., the third-second transistor (T3-2) of FIG. 7).

[0140] Referring to FIG. 16, a portion of the insulating film (450) can be removed using the photoresist layer (550) as a mask. Specifically, a portion of the insulating film (450) that overlaps with the opening of the photoresist layer (550) can be removed. In one embodiment, the portion of the insulating film (450) can be removed through a dry etch process or a wet etch process. Accordingly, a second insulating layer (250b) having an opening (OP) that overlaps with the opening of the photoresist layer (550) can be formed.

[0141] Referring to FIGS. 7, FIGS. 17 and FIGS. 18, the photoresist layer (550) can be removed.

[0142] A second gate electrode (202) may be formed on the second insulating layer (250b), and a first gate electrode (201) may be formed on the first insulating layer (250a). Specifically, a first portion (201a) of the first gate electrode (201) may be formed on the second insulating layer (250b), and a second portion (201b) of the first gate electrode (201) may be formed on the first insulating layer (250a). For example, the first gate electrode (201) and the second gate electrode (202) may each be formed using a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0143] Impurities can be doped into a portion of the first active pattern (101) using the first gate electrode (201) as a mask. Accordingly, a first-1 channel region (CA1-1), a first-2 channel region (CA1-2), a first region (A1), a second region (A2), and a third region (A3) can be formed in the first active pattern (101). A first portion (201a) of the first gate electrode (201) may overlap with the first-1 channel region (CA1-1), and a second portion (201b) of the first gate electrode (201) may overlap with the first-2 channel region (CA1-2). An opening (OP) of the second insulating layer (250b) may overlap with a portion of the second region (A2), the first-2 channel region (CA1-2), and the third region (A3) of the first active pattern (101).

[0144] At the same time, impurities may be doped into a portion of the first active pattern (101) using the second gate electrode (202) as a mask. Accordingly, a fourth region (A4), a fifth region (A5), and a second channel region (CA2) located between the fourth region (A4) and the fifth region (A5) may be formed in the first active pattern (101). The second gate electrode (202) may overlap with the second channel region (CA2).

[0145] Referring to FIG. 19, a high dielectric layer (350) may be formed on the second insulating layer (250b). The high dielectric layer (350) may sufficiently cover the first gate electrode (201) and the second gate electrode (202). For example, the high dielectric layer (350) may be formed using aluminum oxide, zirconium oxide, hafnium oxide, etc. A third insulating layer (250c) may be formed on the high dielectric layer (350). For example, the third insulating layer (250c) may be formed using silicon oxide, silicon nitride, silicon oxynitride, etc.

[0146] Referring to FIG. 20, a capacitor electrode (301) may be formed on a third insulating layer (250c). At least a portion of the capacitor electrode (301) may form a first node capacitor (CN1) together with the third region (A3) of the first active pattern (101). Additionally, a portion of the capacitor electrode (301) that overlaps with the second gate electrode (202) may form a storage capacitor (CST) together with the second gate electrode (202). For example, the capacitor electrode (301) may be formed using a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0147] Although the foregoing description refers to exemplary embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0148] The present invention can be applied to various display devices that may be equipped with a display device. For example, the present invention can be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc. Explanation of the symbols

[0149] DD: Display device SUB: Board A1, A2, A3, A4, A5: 1st to 5th regions CA1-1: Channel 1-1 area CA1-2: Channel 1-2 area CA2: 2nd channel area OP: Opening CST: Storage Capacitor CN1, CN2: 1st and 2nd node capacitors T1, T2, T3, T4: First to fourth thicknesses 101, 102: First and second active patterns 250a: First insulating layer 250b: Second insulating layer 250c: Third insulating layer 301: Capacitor electrode 350: High electric layer

Claims

Claim 1 A substrate; an active pattern disposed on the substrate and comprising a first region, a second region, a first-1 channel region adjacent to the first region, a first-2 channel region adjacent to the second region, and a third region located between the first-1 channel region and the first-2 channel region; a first insulating layer disposed on the substrate and covering the active pattern; a second insulating layer disposed on the first insulating layer and having an opening that overlaps with the first-2 channel region, the second region, and the third region; a first gate electrode disposed on the first insulating layer and overlapping with the first-1 channel region and the first-2 channel region, respectively; A display device comprising a high dielectric layer disposed on the first insulating layer and the second insulating layer, covering the first gate electrode and filling the opening, wherein the first-1 channel region is located between the first region and the third region, the first-2 channel region is located between the second region and the third region, the first insulating layer is in contact with the active pattern, the second insulating layer is disposed directly on the first insulating layer, and the entire upper surface of the third region is covered by the first insulating layer. Claim 2 A display device according to claim 1, wherein the high dielectric layer comprises at least one selected from the group consisting of aluminum oxide (Al2O3), zirconium oxide (ZrO), and hafnium oxide (HfO2). Claim 3 A display device according to claim 1, characterized in that the first insulating layer and the second insulating layer comprise different inorganic materials. Claim 4 In claim 3, the first insulating layer is silicon oxide (SiO₂ x ...including ), and the second insulating layer is silicon nitride (SiN x A display device characterized by including ). Claim 5 A display device according to claim 1, characterized in that the thickness of the first insulating layer is different from the thickness of the second insulating layer. Claim 6 A display device according to claim 5, characterized in that the thickness of the first insulating layer is 800 Å to 1,400 Å and the thickness of the second insulating layer is 200 Å to 600 Å. Claim 7 A display device according to claim 1, characterized in that the thickness of the high dielectric layer is 300 Å to 1,000 Å. Claim 8 A display device according to claim 1, wherein the first gate electrode comprises: a first portion that overlaps with the first-1 channel region and is disposed on the second insulating layer; and a second portion that overlaps with the first-2 channel region and is disposed on the first insulating layer. Claim 9 A display device according to claim 8, wherein the first portion of the first gate electrode forms a first-1 switching transistor together with the first region of the active pattern, the first-1 channel region, and a portion of the third region, and the second portion of the first gate electrode forms a first-2 switching transistor together with the second region of the active pattern, the first-2 channel region, and a portion of the third region. Claim 10 A display device according to claim 1, further comprising: a third insulating layer disposed on the high dielectric layer and comprising at least one selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride; and a capacitor electrode disposed on the third insulating layer. Claim 11 A display device according to claim 10, characterized in that the thickness of the third insulating layer is 500 Å to 1,400 Å. Claim 12 A display device according to claim 10, wherein the portion of the capacitor electrode overlapping with the third region of the active pattern forms a node capacitor together with the third region of the active pattern. Claim 13 A display device according to claim 10, wherein the active pattern further comprises a fourth region, a fifth region, and a second channel region located between the fourth region and the fifth region. Claim 14 A display device according to claim 13, further comprising a second gate electrode disposed on the same layer as the first gate electrode, overlapping with the second channel region, and covered by the high dielectric layer, wherein the second gate electrode constitutes a driving transistor together with the fourth region, the fifth region, and the second channel region of the active pattern. Claim 15 A display device according to claim 14, wherein the portion of the capacitor electrode overlapping with the second gate electrode forms a storage capacitor together with the second gate electrode. Claim 16 A display device according to claim 1, wherein the active pattern comprises at least one selected from the group consisting of polysilicon and amorphous silicon. Claim 17 A display device comprising: a substrate; an active pattern disposed on the substrate and including a first region, a second region, a first-1 channel region adjacent to the first region, a first-2 channel region adjacent to the second region, and a third region located between the first-1 channel region and the first-2 channel region; a first insulating layer disposed on the substrate and covering the active pattern; a second insulating layer disposed on the first insulating layer and having an opening that overlaps the first-2 channel region, the second region, and the third region; a capacitor electrode disposed on the first insulating layer, at least a portion of which forms a node capacitor together with the third region of the active pattern; and a high dielectric layer disposed on the first insulating layer and the second insulating layer between the first insulating layer and the capacitor electrode and filling the opening, wherein the first-1 channel region is located between the first region and the third region, and the first-2 channel region is located between the second region and the third region. Claim 18 A display device according to claim 17, wherein the high dielectric layer comprises at least one selected from the group consisting of aluminum oxide (Al2O3), zirconium oxide (ZrO), and hafnium oxide (HfO2). Claim 19 A display device according to claim 17, further comprising a gate electrode including a first portion disposed between the second insulating layer and the high dielectric layer and overlapping with the first-1 channel region, and a second portion disposed between the first insulating layer and the high dielectric layer and overlapping with the first-2 channel region. Claim 20 A display device according to claim 19, wherein the first portion of the gate electrode forms a first-1 switching transistor together with the first region of the active pattern, the first-1 channel region, and a portion of the third region, and the second portion of the gate electrode forms a first-2 switching transistor together with the second region of the active pattern, the first-2 channel region, and a portion of the third region.

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