Net-based wafer inspection

Abstract

A defect map can be generated by merging defects at locations on multiple dies containing copies of an integrated circuit (IC). Layout shapes or nets that overlap with the defects in the defect map can be determined. Next, connectivity between the layout shapes or nets can be determined. Then, the defects can be grouped into defect groups based on the connectivity between the layout shapes or nets, each defect group including defects that overlap with layout shapes or nets that are electrically connected to one another.

Description

Technology Field

[0001] <Related Application>

[0002] This application claims the benefit of U.S. provisional application serial number 62 / 952,758 filed on December 23, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0003] Technology Field

[0004] The present disclosure relates to the design and manufacture of integrated circuits (ICs). More specifically, the present disclosure relates to net-based wafer inspection. Background Technology

[0005] While the IC is being manufactured based on the IC design, defects (if any) in the IC can be detected using wafer inspection. Detected defects can be categorized as actual defects or false alarms. Actual defects are those that cause the IC to malfunction or fail to meet desired performance targets, whereas false alarms are defects that can be ignored because they do not affect the IC's function or performance in any meaningful way. The false alarm rate is the ratio of the number of false alarms to the total number of detected defects. It is desirable to have a low false alarm rate.

[0006] As device geometries continue to shrink, the total number of detected defects and the false alarm rate are increasing dramatically. When the number of detected defects is high and the false alarm rate is high, wafer inspection can require a significant amount of time and resources. Furthermore, since actual defects may be missed, yields can be lower and manufacturing costs may increase.

[0007] Some embodiments described herein may generate a defect map by merging defects at locations on multiple dies containing copies of the IC. Next, the embodiments may determine layout shapes that overlap with the defects in the defect map. Then, the embodiments may determine the connectivity between the layout shapes. Specifically, the connectivity between the layout shapes may be determined by tracking the electrical connectivity between the layout shapes across one or more layers of the IC. Next, the embodiments may group defects into defect groups based on the connectivity between the layout shapes, each defect group including defects that overlap with layout shapes that are electrically connected to one another.

[0008] Some embodiments may create a database that allows layout data, netlist data, or both layout data and netlist data of an IC design to be looked up based on the location of a defect in a die containing the IC. In these embodiments, for each defect in a defect map, the database may be used to look up the layout data, netlist data, or both layout data and netlist data based on the location of the defect. Then, the embodiments may group the defects into defect groups based on the associated layout data, netlist data, or both layout data and netlist data.

[0009] Some embodiments may prioritize and / or select defect groups based on the count of defects in defect groups, attributes of defects, layout data associated with defects, and / or netlist data associated with defects.

[0010] Specifically, some embodiments may select defect groups containing a number of defects greater than a critical number. Some embodiments may select defect groups having at least one defect having a size greater than a critical size. Some embodiments may select defect groups associated with critical nets. Some embodiments may select defect groups associated with nets having a width smaller than a critical width. Brief explanation of the drawing

[0011] The present disclosure may be understood based on the detailed description given below and the accompanying drawings. The drawings are for illustrative purposes only and do not limit the scope of the present disclosure. Additionally, the drawings are not necessarily drawn to scale. FIG. 1 illustrates a process for prioritizing and / or selecting defects according to some embodiments described herein. FIG. 2 illustrates a connectivity generator according to some embodiments disclosed in this specification. FIG. 3 illustrates a defect map according to some embodiments disclosed in this specification. FIG. 4 illustrates a grouping of defects according to some embodiments disclosed in this specification. FIG. 5 illustrates the selection of defects according to some embodiments disclosed in this specification. FIG. 6 illustrates the selection of defects using proximity boxes according to some embodiments disclosed herein. FIG. 7 illustrates the review and analysis of selected defects according to some embodiments disclosed in this specification. FIG. 8 illustrates an exemplary flow for the design, verification, and manufacture of an integrated circuit according to some embodiments described herein. FIG. 9 illustrates an exemplary machine of a computer system in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. Specific details for implementing the invention

[0012] Aspects of the present disclosure relate to net-based wafer inspection. The number of defects that must be detected and processed during wafer inspection has increased significantly. Furthermore, the false alarm rate has also increased.

[0013] In the present disclosure, the term "defect" may refer to a deviation (greater than the allowable tolerance) between a pattern printed on a wafer and the design intent, which is detected by a wafer inspection tool. During semiconductor manufacturing, a wafer undergoes a number of processing stages. Results after one or more processing stages may be inspected using wafer inspection tools. Wafer inspection tools may capture an image of the wafer using optical or electron beam techniques and then use image processing techniques to detect defects. During wafer inspection, a defect may be detected if the observed deviation between the printed feature and the corresponding design intent (describes the features intended to be printed on the wafer) is greater than the allowable tolerance. For example, if the design intent assumes that there is a space between two layout features and the wafer inspection tool detects that there is no space between the corresponding printed features, the wafer inspection tool may indicate that a defect exists in the location where the space is expected.

[0014] The increase in the number of defects and false alarm rates is due to the shrinking of the geometric structures and physical limitations of wafer inspection tools. For example, in the N22 process technology node, the false alarm rate was typically less than 50%, whereas in the N5 process technology node, it was found to be greater than 90%. Analyzing such a large number of defects and separating actual defects from false alarms is time-consuming and prone to errors. High false alarm rates increase the likelihood of actual and critical defects being missed. Optical wafer inspection errors at different semiconductor manufacturing stages can cause defective wafers to pass inspection, which can lead to lower yields and higher manufacturing costs.

[0015] The embodiments disclosed herein provide techniques and systems for using layout and netlist data associated with defects to identify defects that have a high likelihood of being actual defects. The identified defects, which may be a small fraction of the total number of defects, may be analyzed to further confirm that the defects are actual and to determine solutions (e.g., changes to the layout) to fix the defects. The advantages of the embodiments disclosed herein include, but are not limited to, (1) providing a system for using various layout and net-based attributes of an IC design to distinguish between actual defects and false alarms, and (2) significantly reducing the amount of time and resources required for wafer inspection by accurately separating actual defects from false alarms.

[0016] FIG. 1 illustrates a process for prioritizing and / or selecting defects according to some embodiments described herein.

[0017] The process may begin (in step (102)) by creating a database that allows layout and / or netlist data of the IC design to be looked up based on the location of defects in the die containing the IC. High-level technical details of the IC design can be converted into a netlist, and subsequently into a layout. The layout can then be used to generate photolithography masks used during manufacturing. The term "netlist" may refer to a network of cells (e.g., AND gates, OR gates, MUXs, etc.) that implement the desired function of the IC design. The term "cell" may refer to the actual part of the IC created when the IC design is manufactured. A netlist may refer to a list (or collection) of nets, where each "net" may refer to a set of routing shapes that electrically connect the inputs and outputs of the cells. The term "layout" may refer to the shapes to be manufactured. Specifically, the shapes of the layout can represent the physical structures that implement transistors and electrical connections in the IC.

[0018] FIG. 2 illustrates a connectivity generator according to some embodiments disclosed in this specification.

[0019] A connectivity generator (206) (which may be a software module executed by a processor) may receive layout data (202) and / or netlist data (204). Next, the connectivity generator (206) may determine connectivity between features of the layout data (202) and / or extract connectivity information from the netlist data (204). The connectivity generator (206) may store connectivity information between features and / or nets and the locations of the features and / or nets in a database (208) so that the database (208) may be used to perform lookups of layout features and / or nets based on the location of defects.

[0020] Next, referring to FIG. 1, the process can generate a defect map by merging defects from multiple dies containing copies of the IC (in step (104)). A semiconductor manufacturing process may be used to create multiple copies of the IC on a wafer, and each copy of the IC may be referred to as a "die." Each die may contain defects that may be caused by random or systematic processes. Random defects may occur due to random variations of physical and / or chemical processes used during manufacturing. Systematic defects may be caused by a specific arrangement of shapes in an IC design area that does not produce desired shapes on the wafer. It is desirable to identify systematic defects so that the layout shapes of the IC design can be modified to fix the systematic defects (e.g., by using resolution enhancement techniques such as optical proximity correction and / or assist feature placement).

[0021] FIG. 3 illustrates a defect map according to some embodiments disclosed in this specification.

[0022] A plurality of dies, for example, dies (302, 304, and 306) may include copies of an IC manufactured based on an IC design. Each die may include zero or more defects, for example, defects (308). Some embodiments disclosed herein may merge defects on a plurality of dies to generate a defect map (310) so that the defect map (310) includes defects from all dies.

[0023] Next, referring to FIG. 1, for each defect in the defect map, the process can look up layout and / or netlist data based on the location of the defect using a database (in step (106)). Then, the process can group the defects into defect groups based on the associated layout and / or netlist data (in step (108)).

[0024] FIG. 4 illustrates a grouping of defects according to some embodiments disclosed in this specification.

[0025] For each defect in the defect map (310), the embodiments disclosed herein may use the location of the defect to look up associated layout and / or netlist data from the database (208). For example, defects (402) include three distinct defects (which may have occurred on the same or different dies). When the location of each of these three defects is looked up using the database (208), the same net (net (404)) may be returned by the database lookup operation. Thus, the embodiments disclosed herein may associate three defects (402) with net (404), and the embodiments may create a defect group (406) containing three defects (402).

[0026] The following example illustrates how layout data can be processed by a connectivity generator (206) and how a database (208) can be used to group defects. It is assumed that the layout data (202) includes the following information: (1) a metal shape S1 is connected to a via V1, and (2) the via V1 is connected to a metal shape S2. Based on this information, the connectivity generator (206) can track the connectivity between layout shapes S1 and S2 through the via V1 and determine that layout shapes S1 and S2 are part of the same network because they are electrically connected to each other. The connectivity generator (206) can store this connectivity information in the database (208). It is assumed that defect D1 is detected at a location (X1,Y1) within the boundary of metal shape S1, and defect D2 is detected at a location (X2,Y2) within the boundary of metal shape S2. The embodiments disclosed herein may look up shapes corresponding to locations (X1,Y1) and (X2,Y2) and use connectivity information between metal shapes S1 and S2 stored in the database (208) to determine that defects D1 and D2 are associated with the same net. Thus, the embodiments disclosed herein may group defects D1 and D2 into the same defect group. In some embodiments, connectivity between different layout shapes may be tracked "on demand" or "on-the-fly," that is, after layout shapes overlapping with a set of defects are identified, electrical connectivity between layout shapes may be determined to group the defects.

[0027] Referring to FIG. 1, the process can then (at step (110)) prioritize and / or select defect groups based on the count of defects in the defect groups, the attributes of the defects, and / or layout and / or netlist data associated with the defects in the defect groups. Once the database (208) is created, the process can use rules to create defect groups and prioritize and / or select defect groups based on the layout and / or netlist data associated with the defects. Selected defect groups or higher priority defect groups can be examined by using analysis tools such as a scanning electron microscope (SEM) tool.

[0028] In some embodiments, the criticality of a net may be used to select and / or prioritize groups of faults. For example, if a set of faults is associated with a critical net, those faults may be assigned a higher priority than other faults associated with non-critical nets. The term "critical net" may refer to a net with timing slack close to zero.

[0029] FIG. 5 illustrates the selection of defects according to some embodiments disclosed in this specification.

[0030] The defect map (500) may include defects (502, 504, and 506). Some defects may be located in layout shapes, while others may not be located in any layout shapes, that is, these defects may be located in the space area between layout shapes. For example, defect shape (502) is located in layout shape (508), but defect shapes (504 and 506) are not located in any layout shape. Some embodiments disclosed herein may select defects located in layout shapes corresponding to functional parts of the IC and ignore defects located in non-functional parts of the IC (e.g., the space area between layout shapes). As illustrated in FIG. 5, selected defects (510) are located in layout shapes, and defects (504 and 506) are filtered out.

[0031] In other embodiments, the process can filter out defects that match a given criterion or criteria, that is, the process can select defects that do not match a given criterion or criteria. For example, in another embodiment, the process can select defects (504 and 506) that are not located in any layout shape and filter out other defects.

[0032] Some embodiments may allow the user to specify rules for selecting or prioritizing defects or groups of defects. For example, the user may decide to prioritize groups containing more than three defects (or, more generally, the user may prioritize groups containing more than a threshold number of defects). Similarly, the user may define rules for masking (or filtering) groups of defects sent to the review tool. For example, the user may define rules for filtering out defects located in a fill layer, which may refer to a layer of the IC design layout containing non-functional structures. User-defined rules for filtering these groups of defects can significantly improve inspection efficiency by shortening the review process.

[0033] Some embodiments may allow the user to define advanced rules including multiple nets, dimensions, and spatial characteristics of defects, generate multiple combinations of filters, and generate complex rules for assigning priorities. Specifically, in some embodiments, the rules used by the net-based inspection tool may be "SELECT" and "FILTER". These rules may be applied to defects based on criteria specified in the rules. The system may use a default set of criteria, and if the user provides a set of criteria, user-defined criteria may override the default criteria. A "SELECT" rule may return defects or groups of defects that match the criteria or criteria specified in the selection rule. A "FILTER" rule may return defects or groups of defects that do not match the criteria or criteria specified in the filter rule. Selection and filter rules may be combined and / or chained using logical operators (i.e., a sequence of selection and filter rules may be applied). Some examples of rules that can be used to select and / or filter defects and / or defect groups are discussed below.

[0034] Generally, rules can prioritize and / or select defects and / or defect groups based on criteria that include, but are not limited to, the count of defects in defect groups, the attributes of defects (e.g., size, width, and / or IC design layer), and / or layout and / or netlist data associated with the defects in defect groups. An example of selecting defect groups based on the count of defects in a defect group is "SELECT COUNT > 1," which selects defect groups that have two or more defects. An example of a rule using the attributes of defects is "SELECT DEFECT_SIZE > 0.1 micron," which selects defects with a size greater than 0.1 micron. A rule for selecting defects based on the layout and / or netlist data associated with defects is "FILTER NET=NULL," where the "NET=NULL" directive instructs a net-based inspection tool to filter out all defects that do not overlap with a net (thus, the "assigned" net is "NULL"). Another rule may select defects located in nets passing through multiple IC design layers. Another rule may select defects located in layout features where the width is smaller than a given threshold (e.g., "SELECT NET_WIDTH < 2 microns"). Examples of these rules are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0035] Optical wafer inspection tools may include calibration errors, and measurements may have error tolerances. Additionally, physical and chemical processes used during manufacturing may create variations in printed features. Some embodiments may use proximity boxes to account for these errors and variations. Specifically, some embodiments may place a proximity box around each defect and determine whether the defect overlaps with the layout feature or net based on whether the proximity box overlaps with the location of the layout feature or net.

[0036] FIG. 6 illustrates the selection of defects using proximity boxes according to some embodiments disclosed in this specification.

[0037] Proximity boxes are placed around each defect in FIG. 6. For example, a proximity box (602) is placed around defect (506). In these embodiments, the process can select defects where the proximity box overlaps with the layout shape. For example, a proximity box around defect (504) overlaps with the layout shape (508) and can therefore be selected by the process. An example of a rule for using proximity boxes may be "FILTER NET=NULL PBOX=0.1 micron", where the instruction "PBOX=0.1 micron" may instruct a net-based inspection tool to use a 0.1 micron proximity box around a defect to determine whether the defect overlaps with the layout shape or the net.

[0038] If a set of defects is prioritized or selected by the process illustrated in FIG. 1, the selected or prioritized defects can then be reviewed and / or analyzed using a scanning electron microscope (SEM) tool.

[0039] FIG. 7 illustrates the review and analysis of selected defects according to some embodiments disclosed in this specification.

[0040] The embodiments disclosed herein may select the defect (504) based on layout data and / or netlist data associated with the defect (504), and the area around the defect (504) may be further analyzed using an SEM tool (704). The analysis may indicate that, due to a systemic problem in this area, the layout features are short-circuited together (706), which is inconsistent with the IC design. Specifically, further analysis may reveal that the resolution enhancement techniques applied to this area of ​​the layout were insufficient to accurately print the layout features. Therefore, a specific area of ​​the layout may be modified to fix the problem.

[0041] FIG. 8 illustrates an exemplary flow (800) for designing, verifying, and manufacturing an integrated circuit according to some embodiments described in this specification.

[0042] EDA processes (812) (the acronym “EDA” stands for “Electronic Design Automation”) can be used to convert and verify design data and instructions representing integrated circuits. Each of these processes can be configured and activated as a number of modules or operations.

[0043] The flow (800) may begin by generating a product idea (810) with information provided by the designer, and this information is converted and verified using EDA processes (812). When the design is finalized, the design is tape-out (834), which is used to manufacture the integrated circuit when the artwork (e.g., geometric patterns) for the integrated circuit is transferred to a fabrication facility to manufacture a mask set. After tape-out, a semiconductor die is fabricated (836), and packaging and assembly (838) are performed to produce the manufactured IC chip (840).

[0044] Specifications for circuits or electronic structures can range from low-level transistor material layouts to high-level description languages. High-level abstractions can be used to design circuits and systems using hardware description languages ​​("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register transfer-level ("RTL") descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower level of abstraction, which is a less abstract description, adds more detail to the design description. Abstractions at lower levels, which are less abstract descriptions, can be generated by a computer, derived from design libraries, or created by other design automation processes. An example of a specification language at a lower level of abstraction for specifying more detailed descriptions is SPICE (meaning "Simulation Program with Integrated Circuit Emphasis"). The techniques of abstraction at each level include sufficient details for use by the corresponding tools of that layer (e.g., formal verification tools).

[0045] During system design (814), the function of the integrated circuit to be manufactured is specified. The design can be optimized to meet desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design may be partitioned into different types of modules or components.

[0046] During logic design and functional verification (816), modules or components of the circuit are specified in one or more technical languages, and the specifications are checked for functional accuracy. For example, components of the circuit may be verified to produce outputs that match the requirements of the specifications of the circuit or system under design. Functional verification may use other programs such as simulators and testbench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems of components referred to as "emulators" or "prototyping systems" are used to speed up functional verification.

[0047] During synthesis and design for testing (818), the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, where the edges of the graph structure represent components of the circuit and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical constructs that can be used by an EDA product to verify that the integrated circuit performs according to the specified design when it is manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specifications.

[0048] During netlist verification (820), the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning (822), a full plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0049] During layout or physical implementation (824), physical placement (location of circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) occur, and selection of cells from a library may be performed to enable specific logic functions. As used herein, the term 'cell' may designate a set of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (e.g., flip-flop or latch). As used herein, a circuit 'block' may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components, and may be both physical structures and simulations. Parameters, such as size, are assigned to selected cells (based on 'standard cells') and are accessible from a database for use by EDA products.

[0050] During analysis and extraction (826), circuit functions are verified at the layout level, which allows for refinement of the layout design. During physical verification (828), the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithography constraints, are accurate and that the circuit network functions match the HDL design specifications. During resolution enhancement (830), the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0051] During tape-out, data is generated to be used for the production of lithography masks (after lithography enhancements are applied, where appropriate). During mask data preparation (832), the 'tape-out' data is used to produce lithography masks used to produce finished integrated circuits.

[0052] A storage subsystem of a computer system (such as the computer system (900) of FIG. 9) may be used to store programs and data structures used by some or all of the products used for the development of cells for the EDA products and libraries described herein, and for the physical and logical design using the libraries.

[0053] FIG. 9 illustrates an exemplary machine of a computer system (900) in which a set of instructions for enabling the machine to perform any one or more of the methodologies discussed in this specification can be executed.

[0054] In alternative implementations, the machine may be connected to other machines on a LAN, intranet, extranet, and / or the Internet (e.g., it may be networked). The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0055] A machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or not) that specify actions to be taken by said machine. Additionally, although a single machine is exemplified, the term “machine” should also be taken to include any set of machines that execute a set of instructions (or multiple sets) individually or jointly to perform any one or more of the methodologies discussed herein.

[0056] An exemplary computer system (900) includes a processing device (902), main memory (904) (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), e.g., synchronous DRAM (SDRAM), static memory (906) (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device (918), which communicate with each other via a bus (930).

[0057] The processing device (902) represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device (902) may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device (902) may be configured to execute instructions (926) for performing the operations and steps described herein.

[0058] The computer system (900) may additionally include a network interface device (908) to communicate through a network (920). The computer system (900) may also include a video display unit (910) (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device (912) (e.g., a keyboard), a cursor control device (914) (e.g., a mouse), a graphics processing unit (922), a signal generation device (916) (e.g., a speaker), a graphics processing unit (922), a video processing unit (928), and an audio processing unit (932).

[0059] The data storage device (918) may include a machine-readable storage medium (924) (also known as a non-transient computer-readable medium) in which one or more sets of instructions (926) or software are stored that implement any one or more of the methodologies or functions described herein. The instructions (926) may also reside in the main memory (904) and / or the processing device (902) in whole or at least partially while being executed by the computer system (900), and the main memory (904) and the processing device (902) also constitute machine-readable storage media.

[0060] In some implementations, the instructions (926) include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium (924) is depicted as a single medium in an exemplary implementation, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term “machine-readable storage medium” should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and enabling the machine and processing device (902) to perform any one or more of the methodologies of the present disclosure. Accordingly, the term “machine-readable storage medium” should be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0061] Some parts of the previous detailed descriptions were presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by ordinary skilled practitioners in the field of data processing technology to most effectively convey the content of their work to other ordinary skilled practitioners in the same field. An algorithm may be a sequence of operations leading to a desired result. Operations are those that require the physical manipulation of physical quantities. These quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. These signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0062] However, it should be kept in mind that all such terms and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to such quantities. Unless explicitly stated otherwise in this disclosure, it should be understood that throughout the description, specific terms refer to actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

[0063] The present disclosure also relates to an apparatus for performing the operations of the present specification. The apparatus may be specifically configured for intended purposes or may include a computer that is selectively activated or reconfigured by a computer program stored in the computer. Such computer program may be stored on any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, but not limited to computer-readable storage media, each of which is coupled to a computer system bus.

[0064] The algorithms and displays presented herein are not inherently related to any specific computer or other device. Various other systems may be used with programs according to the teachings of this specification, or it may be found convenient to configure a more specialized device to perform the method. Furthermore, this disclosure is not described by reference to any specific programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described herein.

[0065] The present disclosure may be provided as a computer program product or software comprising a machine-readable medium storing instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium comprises any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0066] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made without departing from the scope of the embodiments of the present disclosure as set forth in the claims below. Where the disclosure refers to some elements in the singular tense, two or more elements may be depicted in the drawings, and similar elements are labeled with similar numbers. Accordingly, the present disclosure and drawings should be conceived in an exemplary sense rather than a restrictive sense.

Claims

Claim 1 A method performed by a processor comprising: generating a defect map by merging defects at locations on a plurality of dies comprising copies of an integrated circuit (IC); determining layout shapes that overlap with defects in the defect map; determining connectivity between the layout shapes; and grouping the defects into defect groups based on the connectivity between the layout shapes, wherein each defect group includes defects that overlap with layout shapes that are electrically connected to each other. Claim 2 A method according to claim 1, wherein the step of determining connectivity between the layout shapes includes the step of tracking electrical connectivity between the layout shapes across one or more layers of the IC. Claim 3 A method according to claim 1, comprising the step of selecting defect groups containing a number of defects greater than a critical number. Claim 4 A method according to claim 1, comprising the step of selecting defect groups based on the attributes of the defects. Claim 5 In claim 4, the step of selecting defect groups based on the attributes of the defects comprises the step of selecting defect groups having at least one defect having a size larger than a threshold size. Claim 6 A method according to claim 1, comprising the step of selecting defect groups based on associated layout data, netlist data, or both layout data and netlist data. Claim 7 In claim 6, the step of selecting fault groups based on the associated layout data, netlist data, or both layout data and netlist data comprises the step of selecting fault groups associated with critical nets. Claim 8 In claim 6, the step of selecting defect groups based on the associated layout data, netlist data, or both the layout data and the netlist data comprises the step of selecting defect groups associated with nets having a width smaller than a threshold width. Claim 9 A system comprising: a memory for storing instructions; and a processor coupled to said memory and executing said instructions, wherein, when the instructions are executed, the processor generates a defect map by merging defects from a plurality of dies comprising copies of an integrated circuit (IC), determines layout shapes that overlap with the defects of said defect map, determines connectivity between said layout shapes, and groups said defects into defect groups based on connectivity between said layout shapes, each defect group comprising defects that overlap with layout shapes that are electrically connected to each other. Claim 10 In claim 9, the above instructions, when executed, cause the processor to select defect groups based on the count of defects in the defect groups, a system. Claim 11 A system according to claim 10, wherein selecting defect groups based on the count of defects in the defect groups includes selecting defect groups containing a number of defects greater than a threshold number. Claim 12 In claim 9, the above instructions, when executed, cause the processor to select defect groups based on the attributes of the defects, a system. Claim 13 A system according to claim 12, wherein selecting defect groups based on the attributes of the defects includes selecting defect groups having at least one defect having a size greater than a threshold size. Claim 14 In claim 9, the above instructions, when executed, cause the processor to select fault groups based on associated layout data, netlist data, or both layout data and netlist data, in a system. Claim 15 A system according to claim 14, wherein selecting fault groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting fault groups associated with critical nets. Claim 16 A system according to claim 14, wherein selecting fault groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting fault groups associated with nets having a width smaller than a threshold width. Claim 17 A non-transient computer-readable medium comprising stored instructions, wherein, when executed by a processor, the instructions enable the processor to generate a database capable of looking up layout data, netlist data, or both layout data and netlist data of an integrated circuit (IC) design based on the location of a defect in a die comprising said IC, generate a defect map by merging defects from a plurality of dies comprising copies of said IC, and for each defect in said defect map, use said database to look up the layout data, netlist data, or both layout data and netlist data based on the location of said defect, and group said defects into defect groups based on the associated layout data, netlist data, or both layout data and netlist data. Claim 18 A non-transient computer-readable medium, wherein, in paragraph 17, the instructions, when executed, cause the processor to assign priorities to the fault groups based on the count of faults in the fault groups and to perform repeater insertion on the fault groups in the order of the assigned priorities. Claim 19 A non-transient computer-readable medium, wherein, in paragraph 17, the instructions, when executed, cause the processor to assign priorities to the fault groups based on the attributes of the faults and to perform repeater insertion for the fault groups in the order of the assigned priorities. Claim 20 A non-transient computer-readable medium, wherein, when executed, the instructions cause the processor to assign priorities to the fault groups based on associated layout data, netlist data, or both layout data and netlist data, and to perform repeater insertion for the fault groups in the order of the assigned priorities.

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