Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package comprises a core substrate having a cavity, a semiconductor chip having chip pads disposed within the cavity of the core substrate and provided on the front surface, a lower redistribution layer covering a first surface of the core substrate and electrically connected to the chip pads and including first redistributions, a sealing layer covering a second surface opposite to the first surface of the core substrate and filling the cavity, second redistributions disposed on the sealing layer and electrically connected to conductive structures of the core substrate, and a bonding pad formed on the redistribution pad of the second redistribution. The bonding pad includes a first plating pattern formed on the redistribution pad and having inclined sidewalls having a diameter that decreases toward the top, a second plating pattern formed on the second plating pattern, and a third plating pattern formed on the second plating pattern and having the same diameter as the second plating pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a fan-out semiconductor package and a method for manufacturing the same. Background Technology

[0002] In the manufacture of a fan-out package, a bonding pad for bonding with a solder bump can be formed through a plating process after forming a redistribution layer. However, the dry film resist used in the plating process has poor adhesion to the underlying redistribution pad, causing the dry film resist on the surrounding area of ​​the redistribution pad to lift and form a bird's beak-like space. Furthermore, due to the plating pattern that fills this space in the subsequent plating process, an undercut occurs on the redistribution pad due to galvanic corrosion during the subsequent etching process. Additionally, there is a problem in that voids occur when forming a passivation film that exposes the plating pattern, leading to defects caused by cracking later on. The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor package with improved reliability.

[0004] Another objective of the present invention is to provide a method for manufacturing the semiconductor package described above. means of solving the problem

[0005] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises a core substrate having a cavity, a semiconductor chip having chip pads disposed within the cavity of the core substrate and provided on the front surface, a lower redistribution layer covering a first surface of the core substrate and electrically connected to the chip pads and including first redistributions, a sealing layer covering a second surface opposite to the first surface of the core substrate and filling the cavity, second redistributions disposed on the sealing layer and electrically connected to conductive structures of the core substrate, and a bonding pad formed on the redistribution pad of the second redistribution. The bonding pad includes a first plating pattern formed on the redistribution pad and having inclined sidewalls having a diameter that decreases toward the top, a second plating pattern formed on the second plating pattern, and a third plating pattern formed on the second plating pattern and having the same diameter as the second plating pattern.

[0006] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises a lower redistribution layer including first redistributions, a semiconductor chip disposed on the lower redistribution layer and electrically connected to the first redistributions, a base substrate surrounding the semiconductor chip on the lower redistribution layer, a sealing layer disposed on the base substrate and covering the semiconductor chip, second redistributions electrically connected to conductive structures of the base substrate on the sealing layer, and an upper redistribution layer comprising a bonding pad formed on a redistribution pad of the second redistributions. The bonding pad comprises a first plating pattern formed on the redistribution pad and including a base portion having a first diameter smaller than the diameter of the redistribution pad and a rim portion protruding to surround the outer surface of the base portion and having a slanted sidewall having a diameter that decreases toward the top, a second plating pattern formed on the second plating pattern, and a third plating pattern formed on the second plating pattern.

[0007] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises a core substrate, at least one semiconductor chip disposed within the core substrate and having chip pads, a lower redistribution layer covering a first surface of the core substrate and electrically connected to the chip pads and including first redistributions, a sealing layer covering a second surface opposite to the first surface of the core substrate and covering the semiconductor chip, second redistributions electrically connected to conductive structures of the core substrate on the sealing layer, and an upper redistribution layer including a bonding pad formed on the redistribution pad of the second redistribution. The bonding pad includes a first plating pattern formed on the redistribution pad and including a base portion having a first diameter smaller than the diameter of the redistribution pad and a rim portion protruding to surround the outer surface of the base portion, a second plating pattern formed on the second plating pattern, and a third plating pattern formed on the second plating pattern. Effects of the invention

[0008] According to exemplary embodiments, the upper redistribution layer of a semiconductor package may include a bonding pad formed on a redistribution pad of the redistribution. The bonding pad may include first, second, and third plating patterns sequentially stacked on the redistribution pad. The diameter of the first plating pattern may decrease toward the top. The diameter of the lower portion of the first plating pattern may be larger than the diameter of the upper portion of the first plating pattern. The diameter of the lower portion of the first plating pattern may be equal to or smaller than the diameter of the redistribution pad. The lower portion of the first plating pattern may be formed to cover the entire upper surface of the redistribution pad.

[0009] Accordingly, the upper surface of the redistribution pad under the third plating pattern containing gold (Au) can be covered by the first plating pattern. Accordingly, undercutting can be prevented by galvanic corrosion of the redistribution pad during the etching process formed after the bonding pad is formed.

[0010] However, the effects of the present invention are not limited to the effects mentioned above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 2 is an enlarged cross-sectional view showing part A of Figure 1. Figure 3 is an enlarged cross-sectional view showing part A of Figure 1 according to a comparative example. FIGS. 4 to 17 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 18 is a cross-sectional view showing a bonding pad according to exemplary embodiments. FIG. 19 is a cross-sectional view showing a bonding pad according to exemplary embodiments. FIG. 20 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 21 is an enlarged cross-sectional view showing part C of FIG. 20. FIG. 22 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 23 is an enlarged cross-sectional view showing part D of FIG. 22. FIGS. 24 to 29 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

[0013] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 2 is an enlarged cross-sectional view showing portion A of FIG. 1.

[0014] Referring to FIGS. 1 and 2, a semiconductor package (10) may include a core substrate (100), at least one semiconductor chip (200) disposed within the core substrate (100), a lower redistribution layer (300) disposed on a lower surface (104) of the core substrate (100), and an upper redistribution layer (160) disposed on an upper surface (102) of the core substrate (100). Additionally, the semiconductor package (10) may further include external connection members (400) disposed on an outer surface of the lower redistribution layer (300).

[0015] In exemplary embodiments, the semiconductor package (10) may include a core substrate (100) provided as a base substrate surrounding the semiconductor chip (200). The core substrate (100) may serve as a frame surrounding the semiconductor chip (200). The core substrate (100) may include core connection wirings (120) as a conductive connection structure that serves as an electrical connection path with the semiconductor chip (200) in a fan-out area extending beyond the area where the semiconductor chip (200) is placed. Thus, the semiconductor package (10) may be provided as a fan-out package. Additionally, the semiconductor package (10) may be provided as a unit package on which a second package is stacked on top.

[0016] Additionally, the semiconductor package (10) may be provided as a System In Package (SIP). For example, one or more semiconductor chips may be disposed within a core substrate (100). The semiconductor chips may include a logic chip and / or a memory chip that includes a logic circuit. The logic chip may be a controller that controls the memory chips. The memory chip may include various types of memory circuits, such as DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM.

[0017] In exemplary embodiments, the core substrate (100) may have a first surface (upper surface) (102) and a second surface (lower surface) (104) facing each other. The core substrate (100) may have a cavity (106) in the center. The cavity (106) may extend from the first surface (102) of the core substrate (100) to the second surface (104).

[0018] The core substrate (100) may include a plurality of stacked insulating layers (110, 120) and core connecting wires (120) within the insulating layers. The plurality of core connecting wires (120) may be used for electrical connection with the semiconductor chip mounted in a fan-out area extending beyond the area where the semiconductor chip (die) is placed. The core connecting wires (120) may be vertical connecting structures penetrating the core substrate (100) from a first surface (102) to a second surface (104) of the core substrate (100).

[0019] For example, the core substrate (100) may include a first insulating layer (110) and a second insulating layer (112) laminated on the first insulating layer (110). The core connecting wiring (120) may include a first wiring (122), a first contact (123), a second wiring (124), a second contact (125), and a third wiring (126). The first wiring (122) is provided on the second surface (104) of the core substrate (100), i.e., the lower surface of the first insulating layer (110), and at least a portion of the first wiring (122) may be exposed from the second surface (104). The third wiring (126) is provided on the first surface (102) of the core substrate (100), i.e., the upper surface of the second insulating layer (112), and at least a portion of the third wiring (126) may be exposed from the first surface (102). It will be understood that the number and arrangement of the insulating layers and the core connecting wires of the core substrate (100) are provided as examples and that the present invention is not limited thereto.

[0020] In exemplary embodiments, the semiconductor chip (200) may be placed within the cavity (106) of the core substrate (110). The sidewall of the semiconductor chip (200) may be spaced apart from the inner wall of the cavity (106). Thus, a gap may be formed between the sidewall of the semiconductor chip (200) and the inner wall of the cavity (106).

[0021] A semiconductor chip (200) may include chip pads (210) on a substrate and on the front surface (202) of the substrate, i.e., the active surface. The front surface (202) on which the chip pads (210) of the semiconductor chip (200) are formed may be positioned so as to face downward. Thus, the chip pads (210) may be exposed through the second surface (104) of the core substrate (100). The front surface (202) of the semiconductor chip (200) may be located on the same plane as the second surface (104) of the core substrate (100). The rear surface (204) opposite to the front surface (202) of the semiconductor chip (200) may be located lower than the first surface (102) of the core substrate (100). The thickness of the semiconductor chip (200) may be smaller or larger than the thickness of the core substrate (100). The thickness of the semiconductor chip (200) is within the range of 60㎛ to 150㎛, and the thickness of the core substrate (100) may be within the range of 50㎛ to 140㎛.

[0022] In exemplary embodiments, the sealing layer (130) may be provided to expose the rear surface (204) of the semiconductor chip (200) while filling the cavity (106) on the first surface (102) of the core substrate (100). The sealing layer (130) may have openings that expose the third wiring (126) of the core connection wiring (120). The rear surface (204) of the semiconductor chip (200) may be located in the same plane as the upper surface (132) of the sealing layer (130).

[0023] The sealing layer (130) can be formed to fill the gap between the side wall of the semiconductor chip (200) and the inner wall of the cavity (106). Thus, the side wall of the semiconductor chip (200), the first surface (102) of the core substrate (100), and the inner wall of the cavity (106) can be covered by the sealing layer (130).

[0024] For example, the sealing layer (130) may include a resin containing reinforcing materials such as inorganic fillers, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, etc. Specifically, the sealing layer may include an insulating film such as ABF (Ajinomoto Build-up Film), a composite material such as FR-4, a resin such as BT (Bismaleimide Triazine), etc.

[0025] In exemplary embodiments, the lower redistribution layer (300) may have first redistributions (302) disposed on the front surface (202) of the semiconductor chip (200) and the second surface (104) of the core substrate (100), and connected to the chip pads (210) of the semiconductor chip (200) and the core connection wirings (120), respectively. The first redistributions (302) may be provided on the front surface (202) of the semiconductor chip (200) and the second surface (104) of the core substrate (100) to perform the role of front redistribution. Accordingly, the lower redistribution layer (300) may be a front redistribution wiring layer of a fan-out package.

[0026] Specifically, the lower redistribution layer (300) may include a first lower redistribution layer having first lower redistributions (312) disposed on the first lower insulating film (310).

[0027] A first lower insulating film (310) is provided on a second surface (104) of a core substrate (100) and may have first openings that expose the chip pads (210) of a semiconductor chip (200) and the first wirings (122) of the core connection wiring (120). The first lower wirings (312) are formed on the first lower insulating film (310) and at least a portion may come into direct contact with the chip pads (210) and the first wirings (122) through the first openings.

[0028] The lower redistribution layer (300) may include a second lower redistribution layer having second lower redistributions (322) disposed on the second lower insulating film (320).

[0029] A second lower insulating film (320) is provided on a first lower insulating film (310) and may have second openings that expose the first lower redistribution lines (312). The second lower redistribution lines (322) are formed on the second lower insulating film (320) and at least a portion may come into direct contact with the first lower redistribution lines (312) through the second openings.

[0030] The lower redistribution layer (300) may include a third lower redistribution layer having third lower redistributions (322) disposed on the third lower insulating film (330).

[0031] A third lower insulating film (330) is provided on a second lower insulating film (320) and may have third openings that expose second lower redistribution lines (322). The third lower redistribution lines (332) are formed on the third lower insulating film (330) and at least a portion may come into direct contact with the second lower redistribution lines (322) through the third openings.

[0032] The lower redistribution layer (300) may include a fourth lower insulating layer (340) provided on the third lower insulating layer (330) to expose portions of the third lower redistributions (332). The fourth lower insulating layer (340) may serve as a passivation layer. A bump pad (not shown), such as Under Bump Metallurgy (UBM), may be provided on the third lower redistributions (332) exposed by the fourth lower insulating layer (340). In this case, the exposed portion of the third lower redistributions (332) may serve as a landing pad, i.e., a package pad.

[0033] For example, the first to third lower insulating films may include polymers, dielectric films, etc. The first to third lower redistribution films may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof. The thickness of each of the first to third lower redistribution films may be within the range of 3 μm to 8 μm.

[0034] Accordingly, the lower redistribution layer (300) may have first redistributions (302) provided on the front surface (202) of the semiconductor chip (200) and the second surface (104) of the core substrate (100), which are respectively connected to chip pads (210) and core connection wires (122). The lower redistribution layer (300) may cover the second surface (104) of the core substrate (100) provided in the outer region (fan-out region) of the semiconductor chip (200). Some of the first redistributions (302) may electrically connect the core connection wires (120) of the semiconductor chip (200) and the core substrate (100). It will be understood that the number and arrangement of the lower insulating films of the redistribution layer and the lower redistributions are provided as examples and that the present invention is not limited thereto.

[0035] In exemplary embodiments, the upper redistribution layer (160) may include a sealing layer (130) on the back surface (204) of the semiconductor chip (200) and the first surface (102) of the core substrate (100), second redistributions (132) disposed on the sealing layer (130) and electrically connected to the core connection wirings (120), a bonding pad (140) disposed on the redistribution pad (135) of the second redistributions (132), and a solder resist film (150) exposing at least a portion of the bonding pad (140). The second redistributions (132) may be provided on the back surface (204) of the semiconductor chip (200) and the first surface (102) of the core substrate (100) to perform the role of backside redistribution. Thus, the upper redistribution layer (160) may be a backside redistribution wiring layer of a fan-out package.

[0036] The second redistribution wires (132) may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0037] In some embodiments, the upper redistribution layer (160) may include at least two layers of stacked first upper redistribution and second upper redistribution. In this case, the second redistributions (132) may correspond to the first upper redistribution, and although not shown in the drawing, the second upper redistribution may correspond to the uppermost second redistribution among the second redistributions. In this case, the bonding pad may be formed on the second upper redistribution.

[0038] The second redistribution (132) may include a redistribution via (133), a redistribution line (134, see FIG. 9), and a redistribution pad (135). The redistribution via (133) may be formed to penetrate the sealing layer (130). The redistribution line (134) may be provided on the sealing layer (130).

[0039] The redistribution pad (135) may have a first diameter (D1). For example, the first diameter (D1) of the redistribution pad (135) may be within the range of 300 μm to 350 μm. The redistribution pad (135) may have a first thickness (T1). The first thickness (T1) of the redistribution pad (135) may be within the range of 5 μm to 15 μm.

[0040] In exemplary embodiments, the bonding pad (140) may include first, second, and third plating patterns (142, 144, 146) sequentially stacked on the rewiring pad (135).

[0041] The diameter of the first plating pattern (142) may decrease towards the top. The diameter of the lower part of the first plating pattern (142) may be larger than the diameter of the upper part of the first plating pattern (142). The diameter of the lower part of the first plating pattern (142) may be equal to the diameter (D1) of the redistribution pad (135). The lower part of the first plating pattern (142) may be formed to cover the entire upper surface of the redistribution pad (135).

[0042] The first plating pattern (142) may include a base portion (142a) having a diameter (D2) smaller than the diameter (D1) of the redistribution pad (135) and a rim portion (142b) protruding to surround the outer surface of the base portion (142a). The rim portion (142b) may have a slanted side wall (S) having a diameter that decreases toward the top.

[0043] For example, the first plating pattern (142) may have a second thickness (T2). The second thickness (T2) of the first plating pattern (142) may be within the range of 0.5 μm to 4 μm. The width (L1) of the edge portion (142b) may be within the range of 10 μm to 20 μm. The height (L2) of the edge portion (142b) may be within the range of 0.5 μm to 2 μm. The first plating pattern (142) may include the same material as the redistribution pad (135). The first plating pattern (142) may include copper (Cu).

[0044] A second plating pattern (144) may be formed on the first plating pattern (142). The diameter of the second plating pattern (144) may be equal to the diameter of the upper part of the first plating pattern (142). For example, the second plating pattern (144) may include nickel (Ni).

[0045] The second plating pattern (144) may have a third thickness (T3) greater than the second thickness (T2). The third thickness (T3) of the second plating pattern (144) may be within the range of 3 µm to 7 µm. The diameter of the second plating pattern (144) may be within the range of 270 µm to 330 µm.

[0046] A third plating pattern (146) may be formed on the second plating pattern (144). The diameter of the third plating pattern (146) may be the same as the diameter of the second plating pattern (144). For example, the third plating pattern (146) may include gold (Au).

[0047] The third plating pattern (146) may have a fourth thickness (T4) that is smaller than the third thickness (T3). The fourth thickness (T4) of the third plating pattern (146) may be smaller than or equal to the second thickness (T2). The fourth thickness (T4) of the third plating pattern (146) may be within the range of 0.3 μm to 1 μm.

[0048] The solder resist film (150) may include an opening (152) that covers the second redistributions (132) on the sealing layer (130) and exposes at least a portion of the bonding pad (140). The solder resist film (150) may serve as a passivation film. For example, the solder resist film (150) may include an ABF insulating film, etc., identical to the sealing layer (130).

[0049] In exemplary embodiments, external connection members (400) may be disposed on the package pads on the outer surface of the lower redistribution layer (300). For example, the external connection member (400) may include a solder ball. The solder ball may have a diameter of 300 μm to 500 μm. The semiconductor package (10) may be mounted on a module substrate (not shown) via the solder balls to form a memory module.

[0050] As described above, the semiconductor package (10) as a fan-out panel level package may include a sealing layer (130) that covers the upper surface (102) of the core substrate (100) and covers the semiconductor chip (200), second redistribution layers (132) that are electrically connected to the conductive structures (120) of the core substrate (100) on the sealing layer (130), and a bonding pad (140) formed on the redistribution pad (135) of the second redistribution layer (132).

[0051] The bonding pad (140) may include first, second, and third plating patterns (142, 144, 146) sequentially stacked on the redistribution pad (135). The diameter of the first plating pattern (142) may decrease towards the top. The diameter of the lower part of the first plating pattern (142) may be larger than the diameter of the upper part of the first plating pattern (142). The diameter of the lower part of the first plating pattern (142) may be equal to the diameter (D1) of the redistribution pad (135). The lower part of the first plating pattern (142) may be formed to cover the entire upper surface of the redistribution pad (135).

[0052] Accordingly, the upper surface of the redistribution pad (135) under the third plating pattern (146) containing gold (Au) can be covered by the first plating pattern (142). Accordingly, undercutting due to galvanic corrosion of the redistribution pad (135) can be prevented during the etching process performed after forming the bonding pad.

[0053] Figure 3 is an enlarged cross-sectional view showing part A of Figure 1 according to a comparative example.

[0054] Referring to FIG. 3, the bonding pad (141) according to the comparative example may not have a first plating pattern (142) and may include second and third plating patterns (144, 146). The lower part of the second plating pattern (144) containing nickel may have a foot-like shape. That is, the edge portion (144b) of the second plating pattern (144) may have a slanted side wall (S) having a diameter that decreases toward the top. Since the lower part of the second plating pattern (144) is formed to cover the entire upper surface of the redistribution pad (135), the exposed area of ​​the redistribution pad (135) under the nickel foot is relatively reduced during the etching process performed after the bonding pad is formed, so that an undercut occurs in the redistribution pad (135) due to galvanic corrosion, and a void (V) may occur between the solder resist film (150) formed thereafter and the redistribution pad (135).

[0055] Below, a method for manufacturing the semiconductor package of FIG. 1 will be described.

[0056] FIGS. 4 through 17 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 4 is a plan view showing a panel having a plurality of core substrates formed thereon. FIGS. 5 through 8, FIG. 10, FIG. 16, and FIG. 17 are cross-sectional views cut along line II' of FIG. 4. FIGS. 11 and FIGS. 13 through 15 are enlarged cross-sectional views showing part B of FIG. 10.

[0057] Referring to FIGS. 4 to 7, first, a panel (P) having a plurality of core substrates (100) formed thereon is provided, and a semiconductor chip (200) is placed in a cavity (106) of the core substrate (100), and then a sealing layer (130) can be formed to cover the semiconductor chip (200).

[0058] In exemplary embodiments, the core substrate (100) may be used as a support frame or base substrate for electrical connection on which a semiconductor chip (200) is placed to form a semiconductor package of a fan-out panel level package structure.

[0059] As illustrated in FIG. 4, the panel (P) may include a frame region (FR) for the core substrate (100) and a scribe lane region surrounding the frame region (FR), i.e., a cutting region (CA). As described below, the panel (P) may be cut along the cutting region (CA) separating the frame region (FR) to be individualized into a core substrate (100).

[0060] The core substrate (100) may have a first surface (102) and a second surface (104) facing each other. The core substrate (100) may have a cavity (106) in the center. As described below, the cavity (106) may have a planar area for accommodating at least one semiconductor chip.

[0061] The core substrate (100) may include a plurality of stacked insulating layers (110, 112) and core connecting wires (120) as conductive connection structures provided in the insulating layers. The plurality of core connecting wires (120) are provided to penetrate the core substrate (100) from a first surface (102) to a second surface (104) of the core substrate (100) and can each serve as an electrical connection passage. That is, the core connecting wires (120) may be provided in a fan-out area extending beyond the area where the semiconductor chip (die) is placed and used for electrical connection. For example, the core connecting wires (120) may include a first wire (122), a first contact (123), a second wire (124), a second contact (125), and a third wire (126).

[0062] As shown in FIG. 5, after placing the panel (P) on the barrier tape (20), at least one semiconductor chip (200) can be placed in the cavity (106).

[0063] A second surface (104) of the core substrate (100) can be attached to a barrier tape (20). For example, hundreds to thousands of dies (chips) can be placed in each cavity (106) of the panel (P). As described below, a singulation process can be performed to cut the panel (P) along a cutting area (CA) to complete individual fan-out panel-level packages. Alternatively, multiple semiconductor chips (200) can be placed in a single cavity (106).

[0064] A semiconductor chip (200) may include a substrate and chip pads (210) provided on the front surface (202) of the substrate, i.e., the active surface. The front surface on which the chip pads (210) of the semiconductor chip (200) are formed may be positioned to face the barrier tape (20). The front surface (202) of the semiconductor chip (200) may be located in the same plane as the second surface (104) of the core substrate (100).

[0065] A semiconductor chip (200) can be placed within a cavity (106) of a core substrate (100). The sidewalls of the semiconductor chip (200) can be spaced apart from the inner wall of the cavity (106). Thus, a gap can be formed between the sidewalls of the semiconductor chip (200) and the inner wall of the cavity (106).

[0066] The thickness of the semiconductor chip (200) may be smaller than the thickness of the core substrate (100). Thus, the back surface (204) of the semiconductor chip (200) may be located lower than the first surface (102) of the core substrate (100). Alternatively, the thickness of the semiconductor chip (200) may be equal to or greater than the thickness of the core substrate (100). In this case, the back surface (204) of the semiconductor chip (200) may be located on the same plane as or higher than the first surface (102) of the core substrate (100).

[0067] As illustrated in FIG. 6, the sealing layer (130) may be formed to cover the semiconductor chip (200) on the first surface (102) of the core substrate (100). The sealing layer (130) may be formed to fill the gap between the side wall of the semiconductor chip (200) and the inner wall of the cavity (106). Thus, the rear surface (204) of the semiconductor chip (200), the first surface (102) of the core substrate (100), and the inner wall of the cavity (106) may be covered by the sealing layer (130).

[0068] For example, the sealing layer (130) may include an insulating film such as ABF, an insulating material such as epoxy resin (thermosetting dielectric material), a photosensitive insulating material (PID), etc. If the sealing layer (130) includes an insulating film such as ABF, the sealing layer (130) may be formed by a lamination process.

[0069] Referring to FIG. 7, a lower redistribution layer (300) can be formed on the second surface (104) of the core substrate (100) and the front surface (202) of the semiconductor chip (200). A lower redistribution layer (300) can be formed on the second surface (104) of the core substrate (100) and the front surface (202) of the semiconductor chip (200), having first redistributions (302) respectively connected to the chip pads (210) of the semiconductor chip (200) and the core connection wirings (122). The lower redistribution layer (300) may be a front redistribution wiring layer of a fan-out package.

[0070] Specifically, after removing the barrier tape (20), the structure of FIG. 6 can be inverted, and a sealing layer (130) can be attached on a first carrier substrate (not shown). Subsequently, a first lower insulating film (310) covering the second surface (104) of the core substrate (100) and the front surface (202) of the semiconductor chip (200) can be formed, and then the first lower insulating film (310) can be patterned to form openings that expose the chip pads (210) of the semiconductor chip (200) and the first wiring (122) of the core connection wiring (120), respectively.

[0071] For example, the first lower insulating film (310) may include a polymer, a dielectric film, etc. The first lower insulating film (310) may include a photosensitive insulating material (PID), an insulating film such as ABF, etc. The first lower insulating film may be formed by a spin coating process, a vapor deposition process, etc.

[0072] Next, first lower redistribution lines (312) can be formed on the first lower insulating film (310). The first lower redistribution lines (312) can directly contact the chip pads (210) and the first wires (122), respectively, through the openings.

[0073] The first lower redistribution can be formed by forming a seed film in a part of the first lower insulating film (310) and within the opening, and then patterning the seed film and performing an electroplating process. Accordingly, at least a part of the first lower redistributions (312) can come into direct contact with the chip pad (210) and the first wiring (122) through the openings.

[0074] For example, the first lower redistribution wire may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0075] Similarly, after forming a second lower insulating film (320) on a first lower insulating film (310), the second lower insulating film (320) can be patterned to form openings that expose each of the first lower redistribution lines (312). Subsequently, second lower redistribution lines (322) can be formed on the second lower insulating film (320) that are in direct contact with each of the first lower redistribution lines (312) through the openings.

[0076] Subsequently, a third lower insulating film (330) may be formed on the second lower insulating film (320), and then the third lower insulating film (330) may be patterned to form openings that expose the second lower redistribution lines (322). Subsequently, third lower redistribution lines (332) may be formed on the third lower insulating film (330) that are in direct contact with the second lower redistribution lines (322) through the openings. The third lower redistribution line (332) may be the uppermost first redistribution line among the first redistribution lines (302). Subsequently, a fourth lower insulating film (340) covering the third lower redistribution lines (332) may be included on the third lower insulating film (330).

[0077] The fourth lower insulating layer (340) can serve as a passivation layer. As described below, the fourth lower insulating layer (340) can be partially removed by a subsequent via formation process to expose parts of the third lower redistribution lines (332). Additionally, a bump pad, such as a UBM, can be formed on the third lower redistribution lines (332) exposed by the fourth lower insulating layer (340) by a subsequent plating process.

[0078] The above-mentioned fourth lower insulating film may include a photosensitive insulating material (PID), an insulating film such as ABF, etc. The above-mentioned fourth lower insulating film may include the same or different materials as the above-mentioned first to third lower insulating films.

[0079] Referring to FIGS. 8 and 9, second redistribution lines (132) can be formed on a sealing layer (130) on the first surface (102) of the core substrate (100) and the rear surface (204) of the semiconductor chip (200).

[0080] Specifically, after removing the first carrier substrate, a lower redistribution layer (300) can be attached on a second carrier substrate (not shown). Subsequently, a sealing layer (130) on the first surface (102) of the core substrate (100) can be partially removed to form openings that expose the third wiring (126) of the core connection wiring (120), and then second redistributions (132) can be formed on the sealing layer (130). The second redistributions (132) can be electrically connected to the core connection wiring (120) through the openings. For example, the second redistributions may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0081] Although not illustrated in the drawing, the openings can be formed by forming an insulating film on the sealing layer (130) and then partially removing the insulating film and the sealing layer (130). The insulating film may include an insulating film such as ABF, which is identical to the sealing layer (130). Accordingly, the second redistribution lines (132) can be formed more easily on the insulating film.

[0082] Additionally, the second redistribution lines (132) may include at least two layers of stacked first upper redistribution lines and second upper redistribution lines. In this case, the second redistribution lines (132) may correspond to the first upper redistribution lines, and although not shown in the drawing, the second upper redistribution line may correspond to the uppermost second redistribution line among the second redistribution lines. A bonding pad may be formed on the second upper redistribution line by a subsequent process.

[0083] As illustrated in FIG. 9, the second rewiring (132) may include a rewiring via (133, see FIG. 11), a rewiring line (134), and a rewiring pad (135). The rewiring via (133) may be formed to penetrate the sealing layer (130). The rewiring line (134) may be formed to extend over the sealing layer (130). The rewiring pad (135) may be formed at one end of the rewiring line (134).

[0084] The redistribution pad (135) may have a first diameter (D1). For example, the first diameter (D1) of the redistribution pad (135) may be within the range of 300 μm to 350 μm. The redistribution pad (135) may have a first thickness (T1, see FIG. 11). The first thickness (T1) of the redistribution pad (135) may be within the range of 5 μm to 15 μm.

[0085] Referring to FIGS. 10 to 15, a bonding pad (140) can be formed on a rewiring pad (135).

[0086] As shown in FIGS. 10 to 12, a photosensitive film (30) can be formed on the front surface of the sealing layer (130), and the photosensitive film (30) can be patterned to form an opening (32) that exposes the redistribution pad (135).

[0087] In exemplary embodiments, the photosensitive film (30) may include a dry film resist (DRF). The photosensitive film (30) may be formed by a lamination process. A mask pattern having an opening that exposes an area to form the bonding pad on the dry film resist film of the sealing layer (130) may be formed, and a portion of the dry film resist film may be removed by a development process to form an opening (32) that exposes the area.

[0088] The thickness of the photosensitive film (30) may be within the range of 40 µm to 60 µm. The diameter (D2) of the opening (32) may be within the range of 270 µm to 330 µm. The distance (L1) between the outer surface of the redistribution pad (135) and the opening (32) may be within the range of 15 to 20 µm.

[0089] At this time, the dry film resist film is relatively thick, and the adhesion to the redistribution pad (135) containing copper may be reduced. Accordingly, when the opening (32) is formed by the development process, the dry film resist on the surrounding area of ​​the redistribution pad (135) may be lifted, and a space (34) resembling a bird's beak may be formed. The width (L1) of the space (34) may be within the range of 15 to 20 μm. The height (L2) of the space (34) may be within the range of 0.5 μm to 2 μm.

[0090] As illustrated in FIG. 13, an electrolytic plating process can be performed to form a first plating pattern (142) within an opening (32) on a redistribution pad (135). The first plating pattern (142) can be formed to fill the space (34) of the opening (32). The first plating pattern (142) may have a shape corresponding to the shape of the space (34), such as a bird's beak. The diameter of the first plating pattern (142) may decrease towards the top. The diameter of the lower part of the first plating pattern (142) may be larger than the diameter of the upper part of the first plating pattern (142). The diameter of the lower part of the first plating pattern (142) may be equal to the diameter (D1) of the redistribution pad (135).

[0091] The first plating pattern (142) may include a base portion (142a) having a diameter (D2) smaller than the diameter (D1) of the redistribution pad (135) and a rim portion (142b) protruding to surround the outer surface of the base portion (142a). The rim portion (142b) may have a slanted side wall (S) having a diameter that decreases toward the top.

[0092] For example, the first plating pattern (142) may have a second thickness (T2). The second thickness (T2) of the first plating pattern (142) may be within the range of 0.5 μm to 4 μm. The width (L1) of the edge portion (142b) may be within the range of 10 μm to 20 μm. The height (L2) of the edge portion (142b) may be within the range of 0.5 μm to 2 μm.

[0093] The first plating pattern (142) may contain the same material as the redistribution pad (135). The first plating pattern (142) may contain copper (Cu). The lower portion of the first plating pattern (142) is formed to cover the entire upper surface of the redistribution pad (135), thereby serving as an undercut prevention pad that can prevent undercuts caused by galvanic corrosion of the redistribution pad (135) during a subsequent etching process.

[0094] Referring to FIG. 14, an electroplating process can be performed to form a second plating pattern (144) within an opening (32) on a first plating pattern (142). The second plating pattern (144) may include a material that acts as a diffusion barrier layer between the solder alloy and the redistribution pad (135) during a subsequent soldering process. For example, the second plating pattern (144) may include nickel (Ni).

[0095] The second plating pattern (144) may have a third thickness (T3) greater than the second thickness (T2). The third thickness (T3) of the second plating pattern (144) may be within the range of 3 µm to 7 µm. The diameter of the second plating pattern (144) may be within the range of 270 µm to 330 µm.

[0096] Referring to FIG. 15, an electroplating process can be performed to form a third plating pattern (146) within an opening (32) on a second plating pattern (144). The third plating pattern (146) may include a material for wetting with a solder material in a subsequent soldering process. For example, the third plating pattern (146) may include gold (Au).

[0097] The third plating pattern (146) may have a fourth thickness (T4) that is smaller than the third thickness (T3). The fourth thickness (T4) of the third plating pattern (146) may be smaller than or equal to the second thickness (T2). The fourth thickness (T4) of the third plating pattern (146) may be within the range of 0.3 μm to 1 μm.

[0098] Accordingly, a bonding pad (140) comprising first, second, and third plating patterns (142, 144, 146) sequentially stacked on the rewiring pad (135) of the second rewiring (132) can be formed.

[0099] Referring to FIG. 16, a photosensitive film (30) is removed from the sealing layer (130), and an etching process is performed on the sealing layer (130) on which the bonding pad (140) is formed, and a solder resist film (150) can be formed that covers the second redistributions (132) and exposes at least a portion of the bonding pad (140).

[0100] The above etching process may be performed to etch the seed layer used in the electroplating process or to remove the seed layer used to form bump pads, such as UBM, on the front redistribution layer. The upper surface of the redistribution pad (135) under the third plating pattern (146) containing gold (Au) may be covered by the first plating pattern (142). Accordingly, undercuts can be prevented by galvanic corrosion of the redistribution pad (135) during the etching process.

[0101] The solder resist film (150) can serve as a passivation film. For example, the solder resist film (150) may include an ABF insulating film, etc., identical to the sealing layer (130). The diameter of the opening (152) of the solder resist film (150) that exposes the bonding pad (140) may be within the range of 220 μm to 270 μm.

[0102] Accordingly, an upper redistribution layer can be formed that covers the first surface (102) of the core substrate and includes a sealing layer (130), second redistributions (132), bonding pads (140), and a solder resist film (150).

[0103] Referring to FIG. 17, external connection members (400) that are electrically connected to each of the first redistributions (302) can be formed on the outer surface of the lower redistribution layer (300).

[0104] For example, a solder ball can be formed as an external connection member on a part of the third lower redistribution (332). In this case, the part of the third lower redistribution (332) can function as a landing pad, i.e., a package pad. Accordingly, a semiconductor manufacturing process can be performed to form a lower redistribution layer (300) having fan-out type solder ball landing pads.

[0105] Afterwards, a fan-out panel level package can be completed by separating into individual core substrates (100) through a sawing process, the core substrate (100), a lower redistribution layer (300) formed on the lower surface of the core substrate (100), and an upper redistribution layer formed on the upper surface of the core substrate (100).

[0106] FIG. 18 is a cross-sectional view showing a bonding pad according to exemplary embodiments.

[0107] Referring to FIG. 18, the first plating pattern (142) of the bonding pad (140) may include a base portion (142a) having a diameter (D2) smaller than the diameter (D1) of the redistribution pad (135), a rim portion (S142b) having a protruding and inclined side wall to surround the outer surface of the base portion (142a), and a head portion (142c) provided on the base portion (142a) and having the same diameter as the diameter (D2) of the base portion (142a).

[0108] FIG. 19 is a cross-sectional view showing a bonding pad according to exemplary embodiments.

[0109] Referring to FIG. 19, the first plating pattern (142) of the bonding pad (140) may include a base portion (142a) having a diameter (D2) smaller than the diameter (D1) of the redistribution pad (135) and a rim portion (142b) protruding to surround the outer surface of the base portion (142a).

[0110] The outer diameter of the rim portion (142b) may be smaller than the diameter (D1) of the redistribution pad (135). The rim portion (142b) may have a rectangular or trapezoidal cross-sectional shape. A rim portion (142b) having a rectangular cross-sectional shape may have vertical side walls. A rim portion (142b) having a trapezoidal cross-sectional shape may have inclined side walls.

[0111] FIG. 20 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 21 is an enlarged cross-sectional view showing portion C of FIG. 20. The semiconductor package is substantially identical to the semiconductor package described with reference to FIG. 1, except for the additional configuration of the second package. Accordingly, identical components are denoted by identical reference numerals, and repeated descriptions of identical components are omitted.

[0112] Referring to FIGS. 20 and 21, the semiconductor package (11) may include a first package and a second package (600) stacked on the first package. The semiconductor package (11) may further include a heat sink (700) stacked on the second package (600). The first package may include a core substrate (100), a semiconductor chip (200), a redistribution layer (300), and an upper redistribution layer (160). The first package may be substantially the same or similar as the unit package described with reference to FIG. 1.

[0113] In exemplary embodiments, the second package (600) may be laminated on the first package via conductive connection members (650).

[0114] The second package (600) may include a second package substrate (610), second and third semiconductor chips (620, 630) mounted on the second package substrate (610), and a sealing member (642) covering the second and third semiconductor chips (620, 630) on the second package substrate (610).

[0115] The second package (600) may be laminated onto the first package via conductive connection members (650). For example, the conductive connection members (650) may include solder balls, conductive bumps, etc.

[0116] As illustrated in FIG. 21, a conductive connection member (650) may be disposed between the bonding pad (140) of the upper redistribution layer (160) and the second connection pad (614) of the second package substrate (610). Thus, the first package and the second package (600) may be electrically connected to each other by the conductive connection members (650).

[0117] The second and third semiconductor chips (620, 630) can be laminated onto the second package substrate (610) by means of adhesive members. Bonding wires (640) can connect the chip pads (622, 632) of the second and third semiconductor chips (620, 630) to the first connection pads (612) of the second package substrate (610). The second and third semiconductor chips (620, 630) can be electrically connected to the second package substrate (610) by means of the bonding wires (640).

[0118] It will be understood that the second package (600) includes two semiconductor chips mounted by a wire bonding method, but the number of semiconductor chips in the second package, the mounting method, etc., are not limited thereto.

[0119] In exemplary embodiments, a heat sink (700) may be provided on a second package (600) to release heat from the first and second packages to the outside. The heat sink (700) may be attached to the second package (600) by a thermal interface material (TIM) (710).

[0120] FIG. 22 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 23 is an enlarged cross-sectional view showing portion D of FIG. 22. The semiconductor package is substantially identical to the semiconductor package described with reference to FIG. 20, except for the configuration of the base substrate and the lower redistribution layer. Accordingly, identical components are indicated by identical reference numerals, and a repeated description of identical components is omitted.

[0121] Referring to FIGS. 22 and 23, the semiconductor package (12) may include a lower redistribution layer (300), at least one semiconductor chip (200) disposed on the lower redistribution layer (300), a sealing member (100) covering at least one semiconductor chip (200) on the lower redistribution layer (300), and an upper redistribution layer (198) disposed on the sealing member (100). Additionally, the semiconductor package (10) may further include external connection members (400) disposed on the outer surface of the lower redistribution layer (300).

[0122] In exemplary embodiments, the lower redistribution layer (300) may include a plurality of first redistributions (302). The first redistributions (302) may be electrically connected to the chip pads (210) of the semiconductor chip (200) and the conductive structures (120), respectively. The first redistributions (302) may be provided on the front surface (202) of the semiconductor chip (200) and the second surface (104) of the sealing member (100) to perform the role of front redistribution. Thus, the lower redistribution layer (300) may be a front redistribution wiring layer of a fan-out package.

[0123] For example, the lower redistribution layer (300) may include first to fifth lower insulating films (310, 320, 330, 340, 350) stacked sequentially. The first redistributions (302) may include first to fourth lower redistributions (312, 322, 332, 342) provided in the first to fifth lower insulating films (310, 320, 330, 340, 350).

[0124] The lower redistribution layer (300) may include a first bonding pad (360) formed on the fourth lower redistribution (342) as the uppermost first redistribution. For example, the first bonding pad (360) may have the same or similar structure as the first bonding pad (190) as described below.

[0125] The fifth lower insulating layer (350) may include an opening that covers the fourth lower redistributions (342) on the fourth lower insulating layer (340) and exposes at least a portion of the first bonding pad (190). The fifth lower insulating layer (350) may include a solder resist film that acts as a passivation film. Accordingly, the first bonding pads (360) may be exposed from the upper surface of the lower redistribution layer (300).

[0126] In exemplary embodiments, a semiconductor chip (200) may be disposed on a lower redistribution layer (300). The semiconductor chip (200) may be mounted on the lower redistribution layer (300) by a flip chip bonding method. In this case, the semiconductor chip (200) may be mounted on the lower redistribution layer (300) such that the active surface on which the chip pads (210) are formed faces the lower redistribution layer (300). The chip pads (210) of the semiconductor chip (200) may be electrically connected to the first bonding pads (360) of the lower redistribution layer (300) by conductive bumps (220) as conductive connecting members. For example, the conductive bumps (220) may include microbumps (uBump).

[0127] In this embodiment, a structure has been described in which the chip pads (210) of the semiconductor chip (200) are electrically connected to the first bonding pads (360) of the lower redistribution layer (300) by means of conductive bumps (220), but is not limited thereto. For example, the chip pads (210) of the semiconductor chip (200) may be directly connected to the first bonding pads (360) of the lower redistribution layer (300) without interposing the conductive bumps.

[0128] In exemplary embodiments, conductive structures (120) are each disposed on first bonding pads (360), and a sealing member (100) can cover a semiconductor chip (200) and conductive structures (120) on a lower redistribution layer (300). The sealing member (100) may include a plurality of through-openings extending from the conductive structures (120). Within the through-openings, one end of the conductive structure (120) may be connected to the first bonding pad (360) of the lower redistribution layer (300), and the other end of the conductive structure (120) may be exposed from the first surface (102) of the sealing member (100).

[0129] For example, the conductive structure (120) may include pillar shapes, bump shapes, etc. The conductive structure (120) may include nickel (Ni), antimony (Sb), bismuth (Bi), zinc (Zn), indium (In), palladium (Pd), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), gold (Au), silver (Ag), chromium (Cr), and tin (Sn).

[0130] In exemplary embodiments, the upper redistribution layer (198) may include second redistributions (132, 172, 182) disposed on the sealing member (100) and electrically connected to each of the conductive structures (120), a second bonding pad (190) disposed on the redistribution pad (185) of the uppermost second redistribution (182) among the second redistributions, and a solder resist film (180) exposing at least a portion of the second bonding pad (190). The second redistributions (132, 172, 182) may be provided on the back surface (204) of the semiconductor chip (200) and the first surface (102) of the sealing member (100) to serve as backside redistributions. Thus, the upper redistribution layer may be a backside redistribution wiring layer of a fan-out package.

[0131] The uppermost second redistribution (182) may include a redistribution via (183), a redistribution line, and a redistribution pad (185). The redistribution via (183) may be formed to penetrate the second upper insulating film (170). The redistribution line may be provided on the second upper insulating film (170).

[0132] The redistribution pad (185) may have a first diameter (D1). For example, the first diameter (D1) of the redistribution pad (185) may be within the range of 300 μm to 350 μm. The redistribution pad (185) may have a first thickness (T1). The first thickness (T1) of the redistribution pad (185) may be within the range of 5 μm to 15 μm.

[0133] As illustrated in FIG. 23, the second bonding pad (190) may include first, second, and third plating patterns (192, 194, 196) sequentially stacked on the rewiring pad (185).

[0134] The diameter of the first plating pattern (192) may decrease towards the top. The diameter of the lower part of the first plating pattern (192) may be larger than the diameter of the upper part of the first plating pattern (192). The diameter of the lower part of the first plating pattern (192) may be equal to the diameter (D1) of the redistribution pad (185). The lower part of the first plating pattern (192) may be formed to cover the entire upper surface of the redistribution pad (185).

[0135] The first plating pattern (192) may include a base portion (192a) having a diameter (D2) smaller than the diameter (D1) of the redistribution pad (185) and a rim portion (192b) protruding to surround the outer surface of the base portion (192a). The rim portion (192b) may have a slanted side wall (S) having a diameter that decreases toward the top.

[0136] The first, second, and third plating patterns (192, 194, 196) of the second bonding pad (190) may be substantially identical or similar to the detailed configurations of the bonding pad (140) of FIG. 2. Therefore, a detailed description thereof is omitted.

[0137] As described above, the semiconductor package (12) may include a fan-out wafer level package comprising a sealing member (100), a lower redistribution layer (300) formed on the lower surface of the sealing member (100), and an upper redistribution layer (198) formed on the upper surface of the sealing member (100).

[0138] In exemplary embodiments, the semiconductor package (12) may further include a second package (600) stacked on the first package as the fan-out wafer level package. The second package (600) may be stacked via the conductive connection members (650) of the upper redistribution layer (198) of the first package.

[0139] A conductive connection member (650) may be disposed between the second bonding pad (190) of the upper redistribution layer (198) and the second connection pad (614) of the second package substrate (610). Accordingly, the first package and the second package (600) may be electrically connected to each other by the conductive connection members (650).

[0140] The second package above may be substantially identical or similar to the second package described with reference to FIG. 20. Therefore, a detailed description thereof will be omitted.

[0141] Below, a method for manufacturing the semiconductor package of FIG. 22 will be described.

[0142] FIGS. 24 to 29 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

[0143] Referring to FIG. 24, a lower redistribution layer (300) having first redistributions (302) on a carrier substrate (C1) may be provided.

[0144] In exemplary embodiments, the carrier substrate (C1) may include a wafer substrate as a base substrate for arranging a plurality of semiconductor chips and forming a sealing member that covers them. The carrier substrate (C1) may have a shape corresponding to the wafer on which the semiconductor process is performed. For example, the carrier substrate (C1) may include a silicon substrate, a glass substrate, a non-metallic or metallic plate, etc.

[0145] The carrier substrate (C1) may include a package area on which the semiconductor chip is mounted and a cut area surrounding the mounting area. As described below, the lower redistribution layer (300) and the sealing member (100) formed on the carrier substrate (C1) may be cut along the cut area separating the plurality of package areas to be individualized.

[0146] As illustrated in FIG. 24, a plating process can be performed on a carrier substrate (C1) to form first lower redistribution lines (312). Although not illustrated in the drawings, a barrier metal layer, a seed layer, and a photoresist film can be sequentially formed on the carrier substrate (C1), and then an exposure process can be performed on the photoresist film to form a photoresist pattern having an opening that exposes the first lower redistribution region. Subsequently, the plating process can be performed on the seed layer to form the first lower redistribution lines. For example, the first lower redistribution lines may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0147] Next, a first lower insulating film (310) covering the first lower redistribution lines (312) is formed on the carrier substrate (C1), and then the first lower insulating film (310) can be patterned to form openings that expose each of the first lower redistribution lines (312).

[0148] For example, the first lower insulating film (310) may include a polymer, a dielectric film, etc. The first lower insulating film (310) may include a photosensitive insulating material (PID), an insulating film such as ABF, etc. The first lower insulating film may be formed by a spin coating process, a vapor deposition process, etc.

[0149] Next, a second lower insulating film (320) can be formed on the first lower insulating film (310), and then second lower redistribution lines (322) can be formed on the second lower insulating film (320).

[0150] For example, after forming a second lower insulating film (320) covering the first lower redistribution lines (312), the second lower insulating film (320) can be patterned to form openings that expose each of the first lower redistribution lines (312). After forming a seed film in part of the first lower redistribution lines (312) and within the openings, the seed film can be patterned and an electroplating process performed to form the second lower redistribution lines (322). Thus, at least part of the second lower redistribution lines (322) can come into direct contact with the first lower redistribution lines (312) through the openings.

[0151] Similarly, after forming a third lower insulating film (330) on a second lower insulating film (320), the third lower insulating film (330) can be patterned to form openings that expose the second lower redistribution lines (322). Subsequently, third lower redistribution lines (332) can be formed on the third lower insulating film (330) that are in direct contact with each of the second lower redistribution lines (322) through the openings.

[0152] Afterward, a fourth lower insulating film (340) can be formed on the third lower insulating film (330), and then the fourth lower insulating film (340) can be patterned to form openings that expose the third lower redistribution wires (332). Subsequently, fourth lower redistribution wires (342) can be formed on the fourth lower insulating film (340) that are in direct contact with each of the third lower redistribution wires (332) through the openings.

[0153] Next, first bonding pads (360) can be formed on each of the fourth lower redistribution lines (342).

[0154] For example, a first bonding pad (360) can be formed by performing a plating process on the rewiring pad of the fourth lower rewiring (342). A first bonding pad (360) can be formed on the rewiring pad of the fourth lower rewiring (342) by performing processes identical or similar to those described with reference to FIGS. 10 to 15. In this case, the first bonding pad (360) may include first, second, and third plating patterns sequentially stacked on the rewiring pad of the fourth lower rewiring (342). The diameter of the first plating pattern may decrease towards the top. The diameter of the lower part of the first plating pattern may be larger than the diameter of the upper part of the first plating pattern. The diameter of the lower part of the first plating pattern may be equal to or smaller than the diameter of the rewiring pad. The lower part of the first plating pattern may be formed to cover the entire upper surface of the rewiring pad.

[0155] Subsequently, a solder resist film (350) as a fifth lower insulating film can be formed on the fourth lower insulating film (340) to cover the fourth lower redistributions (342) and expose at least a portion of the first bonding pad (360). Accordingly, a lower redistribution layer (300) having the first to fifth lower insulating films (310, 320, 330, 340, 350) can be formed. The first bonding pads (360) can be exposed from the upper surface of the lower redistribution layer (300).

[0156] Referring to FIG. 25, a semiconductor chip (200) can be mounted on the lower redistribution layer (300).

[0157] For example, a semiconductor chip (200) can be mounted on a lower redistribution layer (300) by a flip chip bonding method. Chip pads (210) of the semiconductor chip (200) can be electrically connected to first bonding pads (360) of the lower redistribution layer (300) by conductive bumps (220). The conductive bumps (220) may include microbumps (uBump).

[0158] Referring to FIGS. 26 and 27, a sealing member (100) covering a semiconductor chip (200) can be formed on a carrier substrate (C1), and a plurality of conductive structures (120) electrically connected to first bonding pads (360) can be formed.

[0159] As illustrated in FIG. 26, a sealing member (100) covering a semiconductor chip (200) can be formed on a lower redistribution layer (300). For example, the sealing member (100) may include an insulating film such as an epoxy mold compound (EMC) or ABF. The sealing member (100) may be formed to cover the upper surface and the side surface of the semiconductor chip (200).

[0160] Next, through-holes are formed that penetrate the sealing member (100) in a vertical direction and expose the upper surfaces of the first bonding pads (360), and a plurality of conductive structures (120) can be formed within the through-holes. The conductive structures (120) can be formed on the first bonding pads (360). The upper surface of the conductive structures (120) can be exposed from the upper surface of the sealing member (100). For example, the conductive structures (120) can be formed by a plating process, an electroless plating process, a vapor deposition process, etc. The conductive structures (120) may include pillar shapes, bump shapes, etc.

[0161] Alternatively, after forming conductive structures (120) on each of the first bonding pads (360), a sealing member (100) covering the semiconductor chip (200) and the conductive structures (120) can be formed on the lower redistribution layer (300).

[0162] In the present embodiment, a method of forming a lower redistribution layer (300) on the wafer substrate and then forming a semiconductor chip (200) and a sealing member (100) on the lower redistribution layer (300) has been described, but is not limited thereto. For example, a semiconductor chip may be stacked on the wafer substrate and a sealing member covering the semiconductor chip may be formed, and then a lower redistribution layer having first redistributions electrically connected to the semiconductor chip may be formed on the sealing member.

[0163] Referring to FIGS. 28 and 29, an upper redistribution layer (198) can be formed having second redistributions (132, 172, 182) electrically connected to conductive structures (120) on a sealing member (100) and a second bonding pad (190) formed on a redistribution pad of the uppermost second redistribution (152).

[0164] As illustrated in FIG. 28, first upper redistributions (132) can be formed on the sealing member (100) and electrically connected to each of the conductive structures (120). The first upper redistributions can be formed by forming a seed film on the upper surface of the sealing member (100), then patterning the seed film and performing an electroplating process.

[0165] Next, after forming a first upper insulating film (130) on the sealing member (100), second upper redistributions (142) can be formed on the first upper insulating film (130).

[0166] For example, after forming a first upper insulating film (130) covering the first upper redistribution lines (132), the first upper insulating film (130) can be patterned to form openings that expose each of the first upper redistribution lines (132). After forming a seed film in part of the first upper redistribution lines (132) and within the openings, the seed film can be patterned and an electroplating process performed to form the second upper redistribution lines (142). Thus, at least part of the second upper redistribution lines (142) can come into direct contact with the first upper redistribution lines (132) through the openings.

[0167] Similarly, after forming a second upper insulating film (170) on a first upper insulating film (130), the second upper insulating film (170) can be patterned to form openings that expose second upper redistribution lines (172). Subsequently, third upper redistribution lines (182) can be formed on the second upper insulating film (170) that are in direct contact with each of the second upper redistribution lines (172) through the openings.

[0168] Accordingly, the second redistribution lines may include at least two layers of stacked first upper redistribution lines and second upper redistribution lines. In this case, the second redistribution lines include stacked first to third upper redistribution lines (132, 172, 182), and the third upper redistribution line (182) may correspond to the uppermost second redistribution line among the second redistribution lines.

[0169] As shown in FIG. 29, second bonding pads (190) can be formed on the third upper redistribution lines (182) as the uppermost second redistribution lines.

[0170] For example, a second bonding pad (190) can be formed on the rewiring pad of the third upper rewiring (182) by performing processes identical or similar to those described with reference to FIGS. 10 to 15. In this case, the second bonding pad (190) may include first, second, and third plating patterns sequentially stacked on the rewiring pad of the third upper rewiring (182). The diameter of the first plating pattern may decrease toward the top. The diameter of the lower part of the first plating pattern may be larger than the diameter of the upper part of the first plating pattern. The diameter of the lower part of the first plating pattern may be equal to or smaller than the diameter of the rewiring pad. The lower part of the first plating pattern may be formed to cover the entire upper surface of the rewiring pad.

[0171] Subsequently, a solder resist film (180) can be formed as a third upper insulating film that covers the third upper redistributions (182) on the second upper insulating film (170) and exposes at least a portion of the second bonding pad (190). Accordingly, an upper redistribution layer (198) having the second redistributions (132, 172, 182) and the second bonding pads (190) can be formed.

[0172] Next, external connection members (400, see FIG. 22) that are electrically connected to each of the first redistribution lines (302) can be formed on the outer surface of the lower redistribution layer (300).

[0173] Afterwards, a fan-out wafer level package can be completed by separating into individual lower redistribution layers (300) through a sawing process, comprising a sealing member (100) as a base substrate, a lower redistribution layer (300) formed on the lower surface of the sealing member (100), and an upper redistribution layer (198) formed on the upper surface of the sealing member (100).

[0174] Next, as illustrated in FIG. 22, a second package (600) can be laminated onto a first package as a fan-out wafer level package via conductive connection members (650). The conductive connection member (650) may be disposed between the second bonding pad (190) of the upper redistribution layer (198) and the second connection pad (614) of the second package substrate (610). Thus, the first package and the second package (600) may be electrically connected to each other by the conductive connection members (650). The aforementioned semiconductor package may include semiconductor devices such as logic devices or memory devices.

[0175] The above semiconductor package may include logic devices such as, for example, a central processing unit (CPU, MPU), an application processor (AP), volatile memory devices such as, for example, an SRAM device, a DRAM device, and non-volatile memory devices such as, for example, a flash memory device, a PRAM device, an MRAM device, an RRAM device, and so on.

[0176] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0177] 10, 11: Semiconductor package 100: Core substrate 106: Cavity 120: Core connection wiring, conductive structure 110: First insulating layer 112: Second insulating layer 122: 1st wiring 124: 2nd wiring 126: Third wiring 130: Sealing layer, first upper insulating film 132, 172, 182: 2nd rewire 133, 183: Rewire via 134: Rewiring line 135, 185: Rewiring pad 140, 190, 460: Bonding pads 142, 192: First plating pattern 144, 194: 2nd plating pattern 146, 196: 3rd plating pattern 150, 180: Solder resist film 170: Second upper insulating film 198: Upper redistribution layer 200: Semiconductor chip 210: Chip pad 300: Lower redistribution layer 302: 1st redistribution 310: 1st lower insulating film 312: 1st lower rewiring 320: 2nd lower insulating film 322: 2nd lower rewiring 330: 3rd lower insulating film 332: 3rd lower rewiring 340: 4th lower insulating film 342: 4th lower rewiring 350: 5th lower insulating film 400: Absence of external connection 600: Second package 610: Second package substrate 620: Second semiconductor chip 630: Third semiconductor chip 640: Bonding wire 642: Sealing component 700: Heat sink

Claims

Claim 1 A semiconductor package comprising: a core substrate having a cavity; a semiconductor chip disposed within the cavity of the core substrate and having chip pads provided on its front surface; a lower redistribution layer covering a first surface of the core substrate and electrically connected to the chip pads and including first redistributions; a sealing layer covering a second surface opposite to the first surface of the core substrate and filling the cavity; second redistributions disposed on the sealing layer and electrically connected to conductive structures of the core substrate; and a bonding pad formed on the redistribution pad of the second redistribution, wherein the bonding pad comprises: a first plating pattern formed on the redistribution pad and having inclined sidewalls having a diameter that decreases toward the top; a second plating pattern formed on the first plating pattern; and a third plating pattern formed on the second plating pattern and having the same diameter as the second plating pattern. Claim 2 In claim 1, the first plating pattern comprises a semiconductor package having the same material as the redistribution pad. Claim 3 In claim 2, the first plating pattern is a semiconductor package including copper. Claim 4 A semiconductor package according to claim 1, wherein the second plating pattern comprises nickel (Ni) and the third plating pattern comprises gold (Au). Claim 5 A semiconductor package according to claim 1, wherein the first plating pattern comprises: a base portion having a first diameter smaller than the diameter of the redistribution pad; and a rim portion protruding to surround the outer surface of the base portion and having the inclined sidewall. Claim 6 In claim 5, the semiconductor package further comprises a head portion having the same diameter as the first diameter, wherein the first plating pattern is formed on the base portion. Claim 7 In claim 5, the semiconductor package wherein the width of the edge portion is within the range of 10㎛ to 20㎛. Claim 8 In claim 5, the semiconductor package wherein the height of the rim portion is within the range of 0.5㎛ to 2㎛. Claim 9 A semiconductor package according to claim 1, wherein the first plating pattern has a first thickness, the second plating pattern has a second thickness greater than the first thickness, and the third plating pattern has a third thickness smaller than the second thickness. Claim 10 A semiconductor package according to claim 1, further comprising a solder resist film that covers the second rewirings and exposes at least a portion of the bonding pad.

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