Display device

Abstract

The display device may include a pixel circuit, a first wire disposed on the pixel circuit and extending in a first direction, a second wire disposed on the same layer as the first wire and spaced apart from the first wire and parallel to the first wire, a light-emitting element disposed on the first wire and the second wire, and a connection pattern disposed between the first wire and the second wire on the same layer as the first wire, connecting the pixel circuit and the light-emitting element, and having a polygonal shape including at least six sides. A first vertex of the connection pattern may be located at the shortest distance from the first wire to the connection pattern.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] A display device may include a plurality of pixels for displaying an image. The display device may include wiring that provides signals, power, etc. for driving the pixels.

[0003] Recently, due to the increase in the size and resolution of display devices, the number of pixels placed per unit area is increasing. Consequently, as the spacing between the wires providing signals, power, etc., to the pixels decreases, defects such as short circuits between the wires may occur. The problem to be solved

[0004] One objective of the present invention is to provide a display device that prevents short-circuit failures.

[0005] However, the objectives of the present invention are not limited to such objectives, and may be expanded in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0006] To achieve one objective of the present invention as described above, a display device according to embodiments may include a pixel circuit, a first wiring disposed on the pixel circuit and extending in a first direction, a second wiring disposed on the same layer as the first wiring and spaced apart from the first wiring and parallel to the first wiring, a light-emitting element disposed on the first wiring and the second wiring, and a connection pattern disposed between the first wiring and the second wiring on the same layer as the first wiring, connecting the pixel circuit and the light-emitting element, and having a polygonal shape including at least six sides. A first vertex of the connection pattern may be located at the shortest distance from the first wiring to the connection pattern.

[0007] In one embodiment, the second vertex of the connection pattern may be located at the shortest distance from the second wiring to the connection pattern.

[0008] In one embodiment, the connection pattern includes a first connection portion connected to the light-emitting element and a second connection portion connected to the pixel circuit, and the first connection portion may have a rhombus shape.

[0009] In one embodiment, the first vertex may be the vertex of the first connection part.

[0010] In one embodiment, the second vertex may be the vertex of the first connection part.

[0011] In one embodiment, the second connecting portion may have a rhombus shape.

[0012] In one embodiment, the second vertex may be the vertex of the second connection part.

[0013] In one embodiment, the second connecting part may have a rectangular shape.

[0014] In one embodiment, the first wiring may be a data line that supplies a data signal to the pixel circuit.

[0015] In one embodiment, the second wiring may be a power wiring that supplies a power voltage to the pixel circuit.

[0016] In one embodiment, the display device further includes a first pixel and a second pixel located in a second direction intersecting the first direction from the first pixel, and the first wiring is connected to the first pixel and the second wiring can be connected to the second pixel.

[0017] In one embodiment, the light-emitting element includes a first electrode, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer, and the connection pattern can be connected to the first electrode.

[0018] To achieve one objective of the present invention as described above, a display device according to embodiments may include a pixel circuit, a first wiring disposed on the pixel circuit and extending in a first direction, a second wiring disposed on the same layer as the first wiring and spaced apart from the first wiring and parallel to the first wiring, a light-emitting element disposed on the first wiring and the second wiring, and a connection pattern comprising a first connection portion disposed between the first wiring and the second wiring on the same layer as the first wiring and connected to the light-emitting element and a second connection portion connected to the pixel circuit. The first connection portion may have a rhombus shape.

[0019] In one embodiment, the vertex of the first connection part may be located at the shortest distance from the first wiring to the connection pattern.

[0020] In one embodiment, the vertex of the first connection part may be located at the shortest distance from the second wiring to the connection pattern.

[0021] In one embodiment, the second connecting portion may have a rhombus shape.

[0022] In one embodiment, the vertex of the second connection part may be located at the shortest distance from the second wiring to the connection pattern.

[0023] In one embodiment, the second connecting part may have a rectangular shape.

[0024] In one embodiment, the length of the first side extending in the first direction of the second connecting part may be smaller than the distance in the first direction between the second side extending in the second direction intersecting the first direction of the second connecting part and the vertex of the first connecting part.

[0025] In one embodiment, the length of the first side of the second connecting portion may be greater than the width in the first direction of the contact hole where the second connecting portion and the pixel circuit are connected. Effects of the invention

[0026] According to embodiments of the present invention, a connection pattern of a display device includes a first connection portion having a rhombus shape that is connected to a light-emitting element, and a first vertex of the connection pattern may be located at the shortest distance from the first wiring to the connection pattern. Accordingly, even if the distance between the first wiring and the connection pattern decreases due to the increase in the resolution of the display device, the first vertex of the connection pattern and the side of the first wiring face each other, so a short circuit defect between the first wiring and the connection pattern can be prevented.

[0027] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0028] FIG. 1 is a circuit diagram showing a pixel included in a display device according to one embodiment of the present invention. FIG. 2 is a plan view showing a first pixel and a second pixel included in a display device according to an embodiment of the present invention. FIGS. 3, FIGS. 4, FIGS. 5, FIGS. 6, and FIGS. 7 are plan views showing different layers of the first pixel and the second pixel shown in FIG. 2. Figure 8 is a cross-sectional view along line II' of Figure 2. FIG. 9 is a plan view showing a first wiring, a second wiring, and a connection pattern according to an embodiment of the present invention. FIG. 10 is a plan view showing a first wiring, a second wiring, and a connection pattern according to another embodiment of the present invention. FIG. 11 is a plan view showing a first wiring, a second wiring, and a connection pattern according to another embodiment of the present invention. Specific details for implementing the invention

[0029] Hereinafter, a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical or similar reference numerals are used for identical components in the attached drawings.

[0030] FIG. 1 is a circuit diagram showing a pixel included in a display device according to one embodiment of the present invention.

[0031] Referring to FIG. 1, a display device according to one embodiment of the present invention may include a plurality of pixels (PX). Each of the pixels (PX) emits light, and the display device may display an image formed by the light emitted from the pixels (PX). Each of the pixels (PX) may include a light-emitting element (EL) and a pixel circuit (PC).

[0032] The anode of the light-emitting element (EL) is connected to the pixel circuit (PC), and the cathode of the light-emitting element (EL) can receive a second voltage (ELVSS). The light-emitting element (EL) receives a current (I) supplied from the pixel circuit (PC). EL Light of a predetermined brightness can be generated corresponding to the size of ). Current (I) through a light-emitting element (EL) EL In order for the current to flow, the first voltage (ELVDD) supplied to the anode of the light-emitting element (LE) may be greater than the second voltage (ELVSS).

[0033] The pixel circuit (PC) has a current (I) flowing from a first power source that supplies a first voltage (ELVDD) in response to a data signal (DT) to a second power source that supplies a second voltage (ELVSS) via a light-emitting element (EL). EL The size of ) can be controlled. To this end, the pixel circuit (PC) may include a plurality of transistors and at least one capacitor.

[0034] In one embodiment, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a capacitor (CAP). However, the present invention is not limited thereto, and in another embodiment, the pixel circuit (PC) may include two to six or eight or more transistors and / or two or more capacitors.

[0035] The first transistor (T1) has a current (I) corresponding to the data signal (DT). EL It may be a driving transistor that provides ) to a light-emitting element (EL). In one embodiment, the first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3).

[0036] The second transistor (T2) may be a switching transistor that provides a data signal (DT) to the first transistor (T1) in response to a first gate signal (GW). In one embodiment, the second transistor (T2) may include a gate electrode that receives the first gate signal (GW), a first electrode that receives the data signal (DT), and a second electrode connected to a second node (N2).

[0037] The third transistor (T3) may be a compensation transistor that diode-connects the gate electrode of the first transistor (T1) and the second electrode in response to the first gate signal (GW). In one embodiment, the third transistor (T3) may include a gate electrode that receives the first gate signal (GW), a first electrode connected to the first node (N1), and a second electrode connected to the third node (N3).

[0038] The fourth transistor (T4) may be a first initialization transistor that provides an initialization voltage (VINT) to the first transistor (T1) in response to a second gate signal (GI). In one embodiment, the fourth transistor (T4) may include a gate electrode that receives the second gate signal (GI), a first electrode that receives the initialization voltage (VINT), and a second electrode connected to the first node (N1).

[0039] Each of the fifth transistor (T5) and the sixth transistor (T6) may be a light-emitting control transistor that provides a first voltage (ELVDD) to a light-emitting element (EL) in response to a light-emitting control signal (EM). In one embodiment, the fifth transistor (T5) may include a gate electrode that receives the light-emitting control signal (EM), a first electrode that receives the first voltage (ELVDD), and a second electrode connected to a second node (N2). Additionally, the sixth transistor (T6) may include a gate electrode that receives the light-emitting control signal (EM), a first electrode connected to a third node (N3), and a second electrode connected to the positive electrode of the light-emitting element (EL).

[0040] The seventh transistor (T7) may be a second initialization transistor that provides an initialization voltage (VINT) to a light-emitting element (EL) in response to a third gate signal (GB). In one embodiment, the seventh transistor (T7) may include a gate electrode that receives the third gate signal (GB), a first electrode that receives the initialization voltage (VINT), and a second electrode connected to the positive electrode of the light-emitting element (EL).

[0041] The capacitor (CAP) can store a voltage corresponding to the data signal (DT) and the threshold voltage of the first transistor (T1). In one embodiment, the capacitor (CAP) may include a first capacitor electrode connected to a first node (N1) and a second capacitor electrode receiving a first voltage (ELVDD).

[0042] In one embodiment, the first electrode of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) is either a source electrode or a drain electrode, and the second electrode of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be an electrode different from the first electrode. For example, the first electrode of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be a source electrode, and the second electrode of each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) may be a drain electrode.

[0043] FIG. 2 is a plan view showing a first pixel and a second pixel included in a display device according to an embodiment of the present invention. FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are plan views showing different layers of the first pixel and the second pixel shown in FIG. 2. FIG. 8 is a cross-sectional view along line II' of FIG. 2.

[0044] Referring to FIGS. 1, 2, 3, 4, 5, 6, 7, and 8, a display device according to one embodiment may include a plurality of pixels (PX), including a first pixel (PX1) and a second pixel (PX2). The plurality of pixels (PX) may be arranged in a substantial matrix form along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The first pixel (PX1) is any one of the plurality of pixels (PX), and the second pixel (PX2) may be located in the second direction (DR2) from the first pixel (PX1). Each of the first pixel (PX1) and the second pixel (PX2) may include a pixel circuit (PC) and a light-emitting element (EL).

[0045] An active layer (110), a first conductive layer (121, 122, 123, 124), a second conductive layer (131, 132, 133), a third conductive layer (141, 142, 143, 144, 145), a first electrode (150), a light-emitting layer (160), and a second electrode (170) may be arranged sequentially on a substrate (100). The active layer (110), the first conductive layer (121, 122, 123, 124), and the second conductive layer (131, 132, 133) may form a pixel circuit (PC) including first to seventh transistors (T1, T2, T3, T4, T5, T6, T7) and a capacitor (CAP). Additionally, the first electrode (150), the light-emitting layer (160), and the second electrode (170) can form a light-emitting element (EL).

[0046] The substrate (100) may include a transparent insulating substrate. For example, the substrate (100) may be formed of a glass substrate, a quartz substrate, a plastic substrate, etc. In one embodiment, the substrate (100) may include a structure in which an organic insulating layer and an inorganic insulating layer are alternately stacked. For example, the substrate (100) may be formed in a structure in which a first organic insulating layer comprising polyimide (PI), a first inorganic insulating layer comprising a silicon compound and / or amorphous silicon, a second organic insulating layer comprising polyimide, and a second inorganic insulating layer comprising a silicon compound are stacked.

[0047] An active layer (110) may be disposed on a substrate (100). Although not shown in the drawing, a buffer layer that insulates the substrate (100) and the active layer (110) may be interposed between them. The buffer layer prevents the diffusion of impurities from the substrate (100) and can control the rate of heat transfer during the crystallization process for forming the active layer (110). The buffer layer may include a silicon compound, a metal oxide, etc. The active layer (110) may include a source region, a drain region, and a channel region for each of the first to seventh transistors (T1, T2, T3, T4, T5, T6, T7).

[0048] In one embodiment, the active layer (110) may be formed of polycrystalline silicon. For example, a polycrystalline silicon layer may be formed by depositing amorphous silicon on the buffer layer and then crystallizing it. Then, the polycrystalline silicon layer may be patterned to form the active layer (110). However, the present invention is not limited thereto, and in another embodiment, the active layer (110) may be formed of an oxide semiconductor. For example, the active layer (110) may be formed by depositing an oxide semiconductor on the buffer layer and then patterning it.

[0049] A first conductive layer (121, 122, 123, 124) may be disposed on the active layer (110). A first insulating layer (101) that insulates them may be interposed between the active layer (110) and the first conductive layer (121, 122, 123, 124). The first insulating layer (101) may include a silicon compound, a metal oxide, etc.

[0050] The first conductive layer (121, 122, 123, 124) may include a first gate line (121), a second gate line (122), a light emission control line (123), and a first capacitor electrode (124). The first gate line (121), the second gate line (122), and the light emission control line (123) may be arranged along a first direction (DR1) and may extend to a second direction (DR2). In one embodiment, the first gate line (121) may supply a first gate signal (GW) to a pixel circuit (PC), the second gate line (122) may supply a second gate signal (GI) to a pixel circuit (PC), and the light emission control line (123) may supply a light emission control signal (EM) to a pixel circuit (PC). The first conductive layer (121, 122, 123, 124) can be formed of a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0051] A portion of the first gate line (121) overlapping with the active layer (110) can function as the gate electrode of the second transistor (T2), and another portion of the first gate line (121) overlapping with the active layer (110) can function as the gate electrode of the third transistor (T3). Accordingly, the active layer (110) and the first gate line (121) can form the second transistor (T2) and the third transistor (T3). A portion of the second gate line (122) overlapping with the active layer (110) can function as the gate electrode of the fourth transistor (T4). Accordingly, the active layer (110) and the second gate line (122) can form the fourth transistor (T4). One part of the light emission control line (123) overlapping with the active layer (110) functions as the gate electrode of the fifth transistor (T5), and another part of the light emission control line (123) overlapping with the active layer (110) functions as the gate electrode of the sixth transistor (T6). Accordingly, the active layer (110) and the light emission control line (123) can form the fifth transistor (T5) and the sixth transistor (T6).

[0052] A second conductive layer (131, 132, 133) may be disposed on the first conductive layer (121, 122, 123, 124). A second insulating layer (102) that insulates the first conductive layer (121, 122, 123, 124) and the second conductive layer (131, 132, 133) may be interposed between them. The second insulating layer (102) may include a silicon compound, a metal oxide, etc.

[0053] The second conductive layer (131, 132, 133) may include a third gate line (131), an initial voltage line (132), and a conductive pattern (133). The third gate line (131), the initial voltage line (132), and the conductive pattern (133) may be arranged along a first direction (DR1) and may extend to a second direction (DR2). In one embodiment, the third gate line (131) may supply a third gate signal (GB) to a pixel circuit (PC), and the initial voltage line (132) may supply an initial voltage (VINT) to the pixel circuit (PC). The second conductive layer (131, 132, 133) may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0054] A portion of the third gate line (131) overlapping with the active layer (110) can function as the gate electrode of the seventh transistor (T7). Accordingly, the active layer (110) and the third gate line (131) can form the seventh transistor (T7). A portion of the conductive pattern (133) overlapping with the first capacitor electrode (124) can function as the second capacitor electrode of the capacitor (CAP). Accordingly, the first capacitor electrode (124) and the conductive pattern (133) can form the capacitor (CAP).

[0055] A third conductive layer (141, 142, 143, 144, 145) may be disposed on the second conductive layer (131, 132, 133). A third insulating layer (103) that insulates them may be interposed between the second conductive layer (131, 132, 133) and the third conductive layer (141, 142, 143, 144, 145). The third insulating layer (103) may include a silicon compound, a metal oxide, etc.

[0056] The third conductive layer (141, 142, 143, 144, 145) may include a first wiring (141), a second wiring (142), a connection pattern (143), a gate connection pattern (144), and an initialization connection pattern (145). The first wiring (141) and the second wiring (142) may be arranged along a second direction (DR2) and may extend into a first direction (DR1). In one embodiment, the first wiring (141) may supply a data signal (DT) to a pixel circuit (PC), and the second wiring (142) may supply a power supply voltage to the pixel circuit (PC). For example, the power supply voltage may be a first voltage (ELVDD). The third conductive layer (141, 142, 143, 144, 145) may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0057] The first wiring (141) can be connected to the active layer (110) through a first contact hole (CH1) formed in the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The second wiring (142) can be connected to the conductive pattern (133) through a second contact hole (CH2) formed in the third insulating layer (103), and can be connected to the active layer (110) through a third contact hole (CH3) formed in the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The connection pattern (143) can be connected to the active layer (110) through a fourth contact hole (CH4) formed in the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The gate connection pattern (144) can be connected to the first capacitor electrode (124) through a fifth contact hole (CH5) formed in the second insulating layer (102) and the third insulating layer (103), and can be connected to the active layer (110) through a sixth contact hole (CH6) formed in the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103). The initialization connection pattern (145) can be connected to the active layer (110) through a seventh contact hole (CH7) and an eighth contact hole (CH8) formed in the first insulating layer (101), the second insulating layer (102), and the third insulating layer (103), and can be connected to the initialization voltage line (132) through a ninth contact hole (CH9) formed in the third insulating layer (103).

[0058] A first electrode (150) may be disposed on the third conductive layer (141, 142, 143, 144, 145). A fourth insulating layer (104) that insulates them may be interposed between the third conductive layer (141, 142, 143, 144, 145) and the first electrode (150). The fourth insulating layer (104) may include polyimide, etc.

[0059] The first electrode (150) may be formed of a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the first electrode (150) may include silver (Ag), indium tin oxide (ITO), etc. The first electrode (150) may be connected to a connection pattern (143) through a tenth contact hole (CH10) formed in the fourth insulating layer (104).

[0060] A fifth insulating layer (105) may be disposed on the first electrode (150). The fifth insulating layer (105) may cover the first electrode (150) and may be disposed on the fourth insulating layer (104). The fifth insulating layer (105) may have a pixel opening that exposes at least a portion of the first electrode (150). In one embodiment, the pixel opening may expose the central portion of the first electrode (150), and the fifth insulating layer (105) may cover the periphery of the first electrode (150). The fifth insulating layer (105) may be formed of polyimide or the like.

[0061] A light-emitting layer (160) may be disposed on the first electrode (150). The light-emitting layer (160) may be disposed on the first electrode (150) exposed by the pixel opening. The light-emitting layer (160) may include at least one of an organic light-emitting material and quantum dots.

[0062] In one embodiment, the organic light-emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. For example, the low molecular weight organic compound may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc., and the high molecular weight organic compound may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, etc.

[0063] In one embodiment, the quantum dot may include a core comprising a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In one embodiment, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core, and as a charging layer to impart electrophoretic properties to the quantum dot.

[0064] A second electrode (170) may be disposed on the light-emitting layer (160). In one embodiment, the second electrode (170) may also be disposed on the fifth insulating layer (105). The second electrode (170) may include a conductive material such as a metal, an alloy, a transparent conductive oxide, etc. For example, the second electrode (170) may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. The first electrode (150), the light-emitting layer (160), and the second electrode (170) may form a light-emitting element (EL).

[0065] FIG. 9 is a plan view showing a first wiring, a second wiring, and a connection pattern according to an embodiment of the present invention. For example, FIG. 9 may show an example of area II of FIG. 6.

[0066] Referring to FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 9, a first wiring (141), a second wiring (142), and a connection pattern (143) may be disposed between a pixel circuit (PC) and a light-emitting element (EL). The first wiring (141), the second wiring (142), and the connection pattern (143) may be disposed on the pixel circuit (PC), and the light-emitting element (EL) may be disposed on the first wiring (141), the second wiring (142), and the connection pattern (143). The second wiring (142) may be disposed on the same layer as the first wiring (141) and may be spaced apart from the first wiring (141) in a second direction (DR2) and parallel to the first wiring (141). The connection pattern (143) can be placed between the first wiring (141) and the second wiring (142) on the same layer as the first wiring (141) and the second wiring (142).

[0067] In one embodiment, the first wiring (141) may be connected to the first pixel (PX1), and the second wiring (142) may be connected to the second pixel (PX2). In this case, the connection pattern (143) may connect the pixel circuit (PC) of the second pixel (PX2) and the light-emitting element (EL).

[0068] The connection pattern (143) may have a polygonal shape including at least six sides in a plane. In one embodiment, the connection pattern (143) may have a hexagonal shape. In this case, the connection pattern (143) may have six vertices.

[0069] The connection pattern (143) may include a first connection part (143a) connected to a light-emitting element (EL) and a second connection part (143b) connected to a pixel circuit (PC). The first connection part (143a) is connected to the first electrode (150) of the light-emitting element (EL) through the 10th contact hole (CH10), and the second connection part (143b) can be connected to the active layer (110) of the pixel circuit (PC) through the 4th contact hole (CH4).

[0070] The first connecting part (143a) may have a planar rhombus shape. For example, the sides of the first connecting part (143a) extend in directions different from the first direction (DR1) and the second direction (DR2), and the vertices of the first connecting part (143a) may be located in the first direction (DR1) or the second direction (DR2) from the center of the first connecting part (143a).

[0071] In one embodiment, the 10th contact hole (CH10) may have a rhombus shape similar to the shape of the first connecting part (143a) on a planar surface. For example, the area of ​​the 10th contact hole (CH10) may be smaller than the area of ​​the first connecting part (143a).

[0072] The first vertex of the connection pattern (143) may be located at the shortest distance (DS1) from the first wiring (141) to the connection pattern (143). In other words, the point closest to the first wiring (141) among the edges of the connection pattern (143) may be the first vertex. In this case, the first vertex of the connection pattern (143) may face the side (141a) of the first wiring (141).

[0073] In one embodiment, the vertex (VX1) of the first connection part (143a) may be located at the shortest distance (DS1) from the first wiring (141) to the connection pattern (143). In other words, the vertex (VX1) of the first connection part (143a) may be the first vertex of the connection pattern (143).

[0074] In a comparative example of the prior art, the connection pattern may have a planar rectangular shape, and accordingly, the sides of the connection pattern extending in the first direction (DR1) may face the sides of the first wiring or the sides of the second wiring extending in the first direction (DR1). Meanwhile, as the resolution of the display device increases, the distance between the first wiring and the connection pattern and the distance between the second wiring and the connection pattern may decrease, and accordingly, the distance between the sides of the first wiring and the sides of the connection pattern facing each other and the distance between the sides of the second wiring and the sides of the connection pattern facing each other may decrease. In this case, a short circuit defect may occur between the first wiring and the connection pattern and / or between the second wiring and the connection pattern due to errors in the etching process, particles generated during the etching process, etc., during the process of forming the first wiring, the second wiring, and the connection pattern placed on the same layer.

[0075] However, in one embodiment of the present invention, the first connection portion (143a) of the connection pattern (143) has a planar rhombus shape, and the first vertex of the connection pattern (143) corresponding to the vertex (VX1) of the first connection portion (143a) may be located at the shortest distance (DS1) from the first wiring (141) to the connection pattern (143). Accordingly, even if the distance between the first wiring (141) and the connection pattern (143) decreases due to the high resolution of the display device, the first vertex of the connection pattern (143) and the side (141a) of the first wiring (141) face each other, so a short circuit defect between the first wiring (141) and the connection pattern (143) can be prevented.

[0076] FIG. 10 is a plan view showing a first wiring, a second wiring, and a connection pattern according to another embodiment of the present invention. For example, FIG. 10 may show another example of area II of FIG. 6.

[0077] Referring to FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 10, a first wiring (141), a second wiring (142), and a connection pattern (1143) may be arranged between a pixel circuit (PC) and a light-emitting element (EL). In the first wiring (141), the second wiring (142), and the connection pattern (1143) described with reference to FIG. 10, descriptions of contents that are substantially identical or similar to the first wiring (141), the second wiring (142), and the connection pattern (143) described with reference to FIG. 9 are omitted.

[0078] The connection pattern (1143) may have a polygonal shape including at least six sides in a plane. In one embodiment, the connection pattern (1143) may have a nonagonal shape. In this case, the connection pattern (1143) may have nine vertices.

[0079] The connection pattern (1143) may include a first connection part (1143a) connected to a light-emitting element (EL) and a second connection part (1143b) connected to a pixel circuit (PC).

[0080] The second connecting part (1143b) may have a planar rhombus shape. For example, the sides of the second connecting part (1143b) extend in directions different from the first direction (DR1) and the second direction (DR2), and the vertices of the second connecting part (1143b) may be located in the first direction (DR1) or the second direction (DR2) from the center of the second connecting part (1143b).

[0081] In one embodiment, the fourth contact hole (CH4) may have a rhombus shape similar to the shape of the second connecting part (1143b) on the plane. For example, the area of ​​the fourth contact hole (CH4) may be smaller than the area of ​​the second connecting part (1143b).

[0082] The second vertex of the connection pattern (1143) may be located at the shortest distance from the second wiring (142) to the connection pattern (1143). In other words, the point closest to the second wiring (142) among the edges of the connection pattern (1143) may be the second vertex. In this case, the second vertex of the connection pattern (1143) may face the side (142a) of the second wiring (142).

[0083] In one embodiment, the vertex (VX2) of the first connection part (1143a) may be located at the shortest distance (DS2) from the second wiring (142) to the connection pattern (1143). In other words, the vertex (VX2) of the first connection part (1143a) may be the second vertex of the connection pattern (1143).

[0084] In another embodiment, the vertex (VX3) of the second connection part (1143b) may be located at the shortest distance (DS3) from the second wiring (142) to the connection pattern (1143). In other words, the vertex (VX3) of the second connection part (1143b) may be the second vertex of the connection pattern (1143).

[0085] In one embodiment of the present invention, the second connection part (1143b) of the connection pattern (1143) has a planar rhombus shape, and the second vertex of the connection pattern (1143) corresponding to the vertex (VX2) of the first connection part (1143a) and / or the vertex (VX3) of the second connection part (1143b) may be located at the shortest distance from the second wiring (142) to the connection pattern (1143). Accordingly, even if the distance between the second wiring (142) and the connection pattern (1143) decreases due to the high resolution of the display device, the second vertex of the connection pattern (1143) and the side (142a) of the second wiring (142) face each other, so a short circuit defect between the second wiring (142) and the connection pattern (1143) can be prevented.

[0086] FIG. 11 is a plan view showing a first wiring, a second wiring, and a connection pattern according to another embodiment of the present invention. For example, FIG. 11 may show another example of area II of FIG. 6.

[0087] Referring to FIGS. 1, 2, 3, 4, 5, 6, 7, 8, and 11, a first wiring (141), a second wiring (142), and a connection pattern (2143) may be arranged between a pixel circuit (PC) and a light-emitting element (EL). In the first wiring (141), the second wiring (142), and the connection pattern (2143) described with reference to FIG. 11, descriptions of contents that are substantially identical or similar to the first wiring (141), the second wiring (142), and the connection pattern (143) described with reference to FIG. 9 are omitted.

[0088] The connection pattern (2143) may have a polygonal shape including at least six sides in a plane. In one embodiment, the connection pattern (2143) may have an 11-sided shape. In this case, the connection pattern (2143) may have 11 vertices.

[0089] The connection pattern (2143) may include a first connection part (2143a) connected to a light-emitting element (EL) and a second connection part (2143b) connected to a pixel circuit (PC).

[0090] The second connecting portion (2143b) may have a planar rectangular shape. For example, the second connecting portion (2143b) may have a first side (SD1) extending in a first direction (DR1) and a second side (SD2) extending in a second direction (DR2).

[0091] In one embodiment, the fourth contact hole (CH4) may have a rectangular shape similar to the shape of the second connecting part (2143b) in a planar shape. For example, the area of ​​the fourth contact hole (CH4) may be smaller than the area of ​​the second connecting part (2143b).

[0092] In one embodiment, the length (LT) of the first side (SD1) of the second connecting part (2143b) may be smaller than the distance (DS4) in the first direction (DR1) between the second side (SD2) of the second connecting part (2143b) and the vertex of the first connecting part (2143a). For example, the vertex of the first connecting part (2143a) may be the vertex (VX2) of the first connecting part (2143a) located in the second direction (DR2) from the center of the first connecting part (2143a).

[0093] In one embodiment, the length (LT) of the first side (SD1) of the second connecting part (2143b) may be greater than the width (WT) of the fourth contact hole (CH4) in the first direction (DR1). By forming the length (LT) of the first side (SD1) of the second connecting part (2143b) to be greater than the width (WT) of the fourth contact hole (CH4) in the first direction (DR1), the second connecting part (2143b) may fill the entire fourth contact hole (CH4).

[0094] In one embodiment of the present invention, the second connecting part (2143b) of the connecting pattern (2143) has a planar rectangular shape, and the length (LT) of the first side (SD1) of the second connecting part (2143b) may be smaller than the distance (DS4) in the first direction (DR1) between the second side (SD2) of the second connecting part (2143b) and the vertex of the first connecting part (2143a). Accordingly, even if the distance between the first wiring (141) and the connection pattern (2143) and the distance between the second wiring (142) and the connection pattern (2143) decreases due to the high resolution of the display device, the length (LT) of the first side (SD1) of the second connection part (2143b) facing the side (141a) of the first wiring (141) and the side (142a) of the second wiring (142) decreases, so it is possible to prevent short circuit failures from occurring between the first wiring (141) and the connection pattern (2143) and between the second wiring (142) and the connection pattern (2143). Industrial applicability

[0095] A display device according to exemplary embodiments of the present invention can be applied to a display device including a computer, laptop, mobile phone, smartphone, smartpad, PMP, PDA, MP3 player, etc.

[0096] Although display devices according to exemplary embodiments of the present invention have been described above with reference to the drawings, the described embodiments are exemplary and may be modified and changed by those skilled in the art without departing from the technical spirit of the present invention as described in the following claims. Explanation of the symbols

[0097] 141: First wiring 142: Second wiring 143, 1143, 2143: Connection pattern 143a, 1143a, 2143a: First connecting part 143b, 1143b, 2143b: Second connecting part EL: Light-emitting diode PC: Pixel circuit PX1: 1st pixel PX2: Second pixel

Claims

Claim 1 A display device comprising: a pixel circuit; a first wiring disposed on the pixel circuit and extending in a first direction; a second wiring disposed on the same layer as the first wiring and spaced apart from the first wiring and parallel to the first wiring; a light-emitting element disposed on the first wiring and the second wiring; and a connection pattern disposed between the first wiring and the second wiring on the same layer as the first wiring, connecting the pixel circuit and the light-emitting element, and having a polygonal shape including at least six sides, wherein one first vertex of the connection pattern is located at the shortest distance from the first wiring to the connection pattern, and other parts of the connection pattern excluding the first vertex are located further from the first wiring than the first vertex. Claim 2 A display device according to claim 1, wherein the second vertex of the connection pattern is located at the shortest distance from the second wiring to the connection pattern. Claim 3 A display device according to claim 2, wherein the connection pattern includes a first connection portion connected to the light-emitting element and a second connection portion connected to the pixel circuit, and the first connection portion has a rhombus shape. Claim 4 A display device according to claim 3, wherein the first vertex is the vertex of the first connecting part. Claim 5 A display device according to claim 3, wherein the second vertex is the vertex of the first connection part. Claim 6 In claim 3, the second connecting part has a rhombus shape, a display device. Claim 7 A display device according to claim 6, wherein the second vertex is the vertex of the second connecting part. Claim 8 In claim 3, the second connecting part is a display device having a rectangular shape. Claim 9 A display device according to claim 1, wherein the first wiring is a data line that supplies a data signal to the pixel circuit. Claim 10 A display device according to claim 1, wherein the second wiring is a power wiring that supplies power voltage to the pixel circuit. Claim 11 A display device according to claim 1, further comprising a first pixel and a second pixel located in a second direction intersecting the first direction from the first pixel, wherein the first wiring is connected to the first pixel and the second wiring is connected to the second pixel. Claim 12 A display device according to claim 1, wherein the light-emitting element comprises a first electrode, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer, and the connection pattern is connected to the first electrode. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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