Storage class memory, data processing methods, and processor systems

Abstract

A storage class memory, a data processing method, and a processor system are disclosed, relating to the computer field. A plurality of memory chips contained within the storage class memory are divided into at least one group. Each group includes a first-type memory chip and a second-type memory chip. The second-type memory chip is configured to store an operation error correction code, and the first-type memory chip is configured to store data and a retry error correction code. The operation error correction code is intended to perform a first-level memory error correction on data stored within the first-type memory chip in the same group. The retry error correction code is intended to perform a second-level memory error correction on data stored within the first-type memory chip when the first-level memory error correction fails. A two-level memory error correction mechanism is used to ensure high reliability of data stored within the storage class memory and to minimize access latency. Additionally, memory chips of storage class memory are arranged so that the bit width of the storage class memory satisfies the memory bit width specified by the DDR protocol, and the storage class memory is compatible with the DDR protocol.

Description

Technology Field

[0001] This application claims priority to Chinese patent application No. 202111513788.2, filed with the Chinese Intellectual Property Office on December 13, 2021, under the title "Data Transmission Method and Storage Apparatus," and Chinese patent application No. 202210114650.3, filed with the Chinese Intellectual Property Office on January 30, 2022, under the title "Storage Class Memory, Data Processing Method, and Processor System," which are incorporated herein by reference in their entirety.

[0002] This application relates to the field of computers, in particular, to storage class memory, data processing methods, and processor systems. Background Technology

[0003] Storage class memory (SCM) is a new type of storage medium whose storage capacity, access speed, and cost fall between main memory (e.g., Dynamic Random Access Memory (DRAM)) and hard disks (e.g., NAND flash). For example, compared to DRAM, SCM possesses persistence capabilities, prevents data loss after power failures, and offers larger storage capacity. Compared to NAND flash, SCM offers higher access speeds.

[0004] Currently, SCMs implement memory error correction based on embedded controllers. Since the storage medium within the controller can cache data, the access latency of the SCM is uncertain, the SCM may not be compatible with the Double Data Rate (DDR) protocol, and the versatility of the SCM is low. Therefore, how to improve the reliability of the SCM and minimize its access latency when the SCM is compatible with the DDR protocol is an urgent problem that needs to be solved.

[0005] This application provides a storage class memory, a data processing method, and a processor system, thereby improving the reliability of the SCM and minimizing the access latency of the SCM when the SCM is compatible with the DDR protocol.

[0006] According to a first aspect, a storage class memory is provided. A plurality of memory chips contained within the storage class memory are divided into at least one group, and each of the at least one group includes a first-type memory chip and a second-type memory chip. The second-type memory chip is configured to store a running error correction code, and the first-type memory chip is configured to store data and a retry error correction code. The running error correction code is intended to perform a first-level memory error correction on data stored within the first-type memory chip within the same group. The retry error correction code is intended to perform a second-level memory error correction on data stored within the first-type memory chip when the first-level memory error correction fails.

[0007] In this case, a two-level memory error correction mechanism is used to ensure high reliability of data stored within the storage class memory and to minimize access latency. In contrast to high-complexity error correction algorithms used by the built-in controller of the SCM to perform memory error correction that causes high access latency, a two-level memory error correction mechanism is used in this embodiment of this application. When the error rate of the storage class memory is low, high reliability of the data stored within the storage class memory can be ensured by using the first-level memory error correction, and access latency is effectively reduced. When the error rate of the storage class memory is high, high reliability of the data stored within the storage class memory can also be ensured by using the second-level memory error correction, and access latency is reduced in combination with the first-level memory error correction. Additionally, memory chips of the storage class memory are arranged so that the bit width of the storage class memory meets the memory bit width indicated by the Double Data Rate (DDR) protocol. In this case, the storage class memory is compatible with the DDR protocol, the storage class memory can be connected to more types of processors, and the versatility of the storage class memory is improved.

[0008] The quantity of Type 1 memory chips and the quantity of Type 2 memory chips within each group are determined based on the bit width of the Type 1 memory chips, the bit width of the Type 2 memory chips, and the memory bit width indicated by the DDR protocol.

[0009] For example, the memory bit width specified by the DDR protocol is 80 bits, and both the bit width of the first-type memory chip and the bit width of the second-type memory chip are 8 bits, and the 10 memory chips contained within the storage class memory are divided into two groups. Each group contains four first-type memory chips and one second-type memory chip. The sum of the bit widths of the four first-type memory chips and the second-type memory chip contained within each group is 40 bits, and the unit data access amount of each bit is 16 bytes or 32 bytes.

[0010] In a possible embodiment, the first-type memory chip includes M first-type banks and N second-type banks. The first-type banks are configured to store data. The second-type banks are configured to store retry error correction codes. Therefore, the memory controller or firmware (FW) may perform online switching or upgrading on the quantity of first-type banks and the quantity of second-type banks based on usage scenarios to improve flexibility for adapting to the reliability requirements of different systems.

[0011] In another possible embodiment, the unit data access amount of the first-type bank and the unit data access amount of the second-type bank are each a unit data access amount of one bit within the bit width of the first-type memory chip. Therefore, the unit data access amount of the storage class memory satisfies the length of the cache line of the processor connected to the storage class memory, thereby improving the versatility of the storage class memory.

[0012] In another possible embodiment, the first-type memory chip further includes a third-type bank. The third-type bank is configured to implement a bad block management function for the bank of the first-type memory chip. Therefore, space for the storage class memory is saved, the storage class memory is more easily compatible with memory (such as DRAM) that meets the DDR protocol, and the versatility of the storage class memory is improved.

[0013] According to a second aspect, a data processing method is provided. The method is executed by a controller, and the controller is connected to a storage class memory and a processor in the first aspect or any possible aspect of the first aspect. The method comprises: the controller performs a first-level memory error correction on data stored in a first-type memory chip within the same group in the storage class memory. When the first-level memory error correction fails, the controller acquires each first-type memory chip and performs a second-level memory error correction on data stored in the first-type memory chip.

[0014] For example, a controller performing first-level memory error correction on data stored in a first-type memory chip within the same group within storage class memory includes the following: the controller performs first-level memory error correction on data stored in a first-type memory chip within the same group within storage class memory by using a Hamming code or a block code. The controller performs first-level memory error correction on a single bit of 128 to 512 bytes of data stored in a first-type memory chip within the same group within storage class memory.

[0015] For example, the controller performing second-level memory error correction on data stored in a first-type memory chip includes the following: the controller performs second-level memory error correction on data stored in the first-type memory chip by using a block code or a low-density parity-check code. The controller performs second-level memory error correction on hundreds of bits of 2048 to 4096 bytes of data stored in the first-type memory chip.

[0016] In a possible implementation, the method further comprises: the controller converts instructions of the processor into instructions of the storage class memory and instructions of the storage class memory into instructions of the processor. Thus, the processor performs read / write operations on the storage class memory.

[0017] According to a third aspect, a processor system is provided. The processor system comprises a controller, a storage class memory in the first aspect or any possible aspect of the first aspect, and a processor. The controller is separately connected to the processor and at least one storage class memory. The controller is configured to perform a step of operation of a method in the second aspect or any possible aspect of the second aspect.

[0018] This application may also combine embodiments provided in the above aspects to provide more embodiments. Brief explanation of the drawing

[0019] FIG. 1 is a schematic diagram of the structure of a storage class memory according to an embodiment of this application. FIG. 2 is a schematic diagram of the physical partitioning of a storage class memory according to an embodiment of this application. FIG. 3 is a schematic diagram of the structure of a first-type memory chip according to an embodiment of this application. FIG. 4 is a schematic diagram of the generation of an operation error correction code and a retry error correction code according to an embodiment of this application. FIG. 5 is a schematic diagram of the structure of another storage class memory according to an embodiment of this application. FIG. 6 is a schematic diagram of the structure of another storage class memory according to an embodiment of this application. FIG. 7 is a schematic diagram of the structure of a processor system according to an embodiment of this application. FIG. 8 is a schematic diagram of the structure of another processor system according to an embodiment of this application. FIG. 9 is a schematic diagram of a data processing method according to an embodiment of this application. Specific details for implementing the invention

[0020] In digital circuits, the smallest unit of data is the bit, and the bit is also the smallest unit of data in memory (or main memory). The value of a single bit is either "0" or "1", and eight consecutive bits form a byte. In machine language, a byte represents a character or a number. The value of a single bit stored in memory can be altered by electric fields, magnetic fields, or even cosmic ray interference. If the value of a single bit in a byte critical to system operation is altered, a system error may occur, which can result in a system breakdown or other errors.

[0021] Error Correcting Code (ECC) is a technology capable of implementing error checking and error correction. Error-correcting code memory (ECC memory) is memory to which ECC technology is applied; in other words, it is memory capable of implementing error checking and error correction. Error-correcting code memory is widely used in servers and graphics workstations, thereby improving the stability and reliability of computer operations.

[0022] Embodiments of this application provide a storage class memory, and in particular, a storage class memory having high reliability and low latency. Specifically, a two-level memory error correction mechanism is utilized to ensure high reliability of data stored within the storage class memory and to minimize access latency. Additionally, memory chips of the storage class memory are arranged so that the bit width of the storage class memory meets the memory bit width specified by the Double Data Rate (DDR) protocol. In this case, the storage class memory is compatible with the DDR protocol, the storage class memory can be connected to more types of processors, and the versatility of the storage class memory is improved.

[0023] In an embodiment of this application, the memory chip may be a Phase Change Memory (PCM). A Phase Change Memory is a storage device that stores data by utilizing the difference in electrical conductivity that occurs when a special material (e.g., a chalcogenide) transitions between a crystalline state and an amorphous state. The memory bit width refers to the amount of data that can be transmitted by the memory at one time. A larger bit width indicates a larger amount of data that must be transmitted at one time. The memory bit width may also be referred to as the data bit width or simply as the bit width.

[0024] A plurality of memory chips contained within the storage class memory are divided into at least one group. Each of the at least one group includes a first-type memory chip and a second-type memory chip. It can be understood that the at least one group refers to at least one channel of DDR. The quantity of first-type memory chips and the quantity of second-type memory chips within each group are determined based on the bit width of the first-type memory chip, the bit width of the second-type memory chip, and the memory bit width indicated by the DDR protocol, so that the bit width of the storage class memory satisfies the memory bit width indicated by the DDR protocol.

[0025] The second-type memory chip is configured to store an operation error correction code. The operation error correction code is intended to perform first-level memory error correction on data stored within the first-type memory chip within the same group. It should be understood that the operation error correction code may be generated based on data stored within the first-type memory chip belonging to the same group. First-level memory error correction refers to performing memory error correction on data stored within the first-type memory chip belonging to the same group. For example, the operation error correction code stored within the second-type memory chip included in the first group is generated based on data stored within the first-type memory chip included in the first group. The operation error correction code stored within the second-type memory chip included in the first group is intended to perform first-level memory error correction on data stored within the first-type memory chip included in the first group.

[0026] The first-type memory chip is configured to store data and a retry error correction code. The retry error correction code is intended to perform second-level memory error correction on the data stored within the first-type memory chip when first-level memory error correction fails. It should be understood that the retry error correction code may be generated based on the data stored within the first-type memory chip. Second-level memory error correction refers to performing memory error correction on the data stored within each first-type memory chip. For example, the retry error correction code stored within the first-type memory chip included in the first group is generated based on the data stored within the same first-type memory chip. The retry error correction code stored within the first-type memory chip included in the first group is intended to perform second-level memory error correction on the data stored within the same first-type memory chip.

[0027] In an embodiment of this application, the operation error correction code may also be referred to as a first-level correction code, and the retry error correction code may also be referred to as a second-level correction code.

[0028] In some other embodiments, the first-type memory chip is also configured to implement a bad block management function on the first-type memory chip. Compared to placing a memory chip to implement bad block management on the storage class memory, placing a medium to implement bad block management on the first-type memory chip saves space in the storage class memory, thereby making the storage class memory more easily compatible with memory (such as DRAM) that meets the DDR protocol, and improving the versatility of the storage class memory.

[0029] Storage class memory can include another chip, such as a clock chip.

[0030] The following describes in detail the storage class memory provided in the embodiments of this application with reference to the attached drawings.

[0031] For example, the storage class memory is compatible with DDR5, which has a memory bit width of 80 bits. FIG. 1 is a schematic diagram of the structure of the storage class memory according to an embodiment of this application. The storage class memory (100) includes 10 memory chips (110), and the bit width of each memory chip (110) is 8 bits. The 10 memory chips (110) are divided into 2 groups, each group includes 5 memory chips (110), and the sum of the bit widths of the 5 memory chips (110) included in each group is 40 bits. When the sum of the bit widths of the 5 memory chips (110) included in the 2 groups is 80 bits, the storage class memory (100) is compatible with the memory bit width of DDR5. It can be understood that the 2 groups obtained by dividing the 10 memory chips (110) refer to 2 sub-channels of DDR5. This is compatible with the DDR5 dual-channel standard. The bit width of each sub-channel is 40 bits.

[0032] Each group includes four first-type memory chips (111) and one second-type memory chip (112). The unit data access amount of each bit within the bit width of the memory chip (110) is 16 bytes or 32 bytes, that is, whenever the storage class memory is accessed, 16B or 32B of data can be obtained after a specific latency. When four first-type memory chips (111) are accessed at once, 64B of data can be read or written. When eight first-type memory chips (111) are accessed at once, 128B of data can be read or written. 64B or 128B is the length of the processor's carry line (cache line), thereby improving the versatility of the storage class memory.

[0033] The second-type memory chip (112) is configured to store an operation error correction code. The first-type memory chip (111) is configured to store data and a retry error correction code. The length of the codeword of the operation error correction code is determined by the first-type memory chip (111) and the second-type memory chip (112) within the group. For example, when four first-type memory chips (111) are accessed at once, 64B of data may be read or written, and the length of the codeword of the operation error correction code is 64B + 16B. When eight first-type memory chips (111) are accessed at once, 128B of data may be read or written, and the length of the codeword of the operation error correction code is 128B + 32B. The length of the codeword of the retry error correction code may be autonomously set by the retry error correction code based on reliability requirements.

[0034] As illustrated in FIG. 2, it can be understood that the storage class memory (100) can be physically divided into ranks (120), memory chips (110), banks (130), and storage cells (140) in descending order of hierarchy. A rank (120) includes all memory chips (110) placed on the storage class memory (100). Each memory chip (110) includes a plurality of banks (130). Each bank (130) includes storage cells (140). Each storage cell (140) is determined by rows and columns.

[0035] In some embodiments, the medium used by the first-type memory chip (111) to store a retry error correction code may be part of a bank (130) among a plurality of banks (130) included within the first-type memory chip (111). For example, the first-type memory chip (111) includes M first-type banks (131) and N second-type banks (132). The first-type banks (131) are configured to store data. The second-type banks (132) are configured to store a retry error correction code. During actual application, the quantity M of the first-type banks (131) and the quantity N of the second-type banks (132) may be flexibly configured based on reliability requirements. When the reliability requirements are low and the amount of data for which second-level memory error correction is performed is small, fewer second-type banks (132) and more first-type banks (131) may be configured. When the reliability requirements are high and the amount of data for which second-level memory error correction is performed is large, more second-type banks (132) may be configured. The memory controller or firmware (FW) may switch or upgrade the quantity M of the first-type banks (131) and the quantity N of the second-type banks (132) online based on usage scenarios to improve flexibility for adapting to the reliability requirements of different systems.

[0036] For example, as illustrated in FIG. 3, the first-type memory chip (111) includes 16 banks (130) that can operate independently. The first through fourteenth banks (130) serve as first-type banks (131) and are configured to store data. The fifteenth bank (130) serves as a second-type bank (132) and is configured to perform second-level memory error correction. Optionally, the sixteenth bank (130) within the first-type memory chip (111) serves as a third-type bank (133) and is configured to implement the function of bad block management on the banks (130) of the first-type memory chip (111). When one of the banks from the 1st bank (130) to the 15th bank (130) has an error, the bank with the error (130) can be replaced with the 16th bank (130) to avoid errors in the storage class memory (100). For example, when some addresses of one of the banks from the 1st bank (130) to the 15th bank (130) are corrupted, the controller can remap the corresponding address of 16B to the reserved 16th bank (130), thereby enabling the function of bad block management.

[0037] When the bank (130) is accessed at once, 16B or 32B of data may be read or written. It is assumed that when the bank (130) is accessed at once, 16B of data may be read or written, and the length of the codeword of the retry error correction code may be 224B (16*14)+16B. Because the codeword of the retry error correction code is long, the error correction capability of the second-level memory error correction is also strong. This is only one of the ways to construct the codeword of the retry error correction code. In some other embodiments, the codeword of the retry error correction code may alternatively be constructed by using data stored within a portion of the first-type bank (131) among a plurality of first-type banks (131). During the second-level memory error correction, error checking and error correction are performed periodically on a bank (130) contained within the first-type memory chip (111).

[0038] For example, as illustrated in FIG. 4, data on which first-level memory error correction is performed and data on which second-level memory error correction is performed can form a two-dimensional matrix. The x-dimensional dimension represents four first-type memory chips (111) and one second-type memory chip (112), and the y-dimensional dimension represents the address of the smallest access unit 16B of the memory chip. The four first-type memory chips (111) store data and retry error correction codes, and the second-type memory chip (112) stores operation error correction codes. Each row forms a 64B+16B codeword of operation error correction codes. The entire two-dimensional matrix forms a 512B+208B codeword of retry error correction codes. After the decoding of the codeword of the operation error correction code within any row fails, the system reads the data of a two-dimensional matrix to perform second-level memory error correction, that is, performs second-level memory error correction on the data within each column. The system can perform horizontal decoding and vertical decoding in parallel to effectively reduce the error correction rate of the system.

[0039] In some embodiments, the data of the first-type memory chip (111) in each column of the two-dimensional matrix may be data of any eight banks (130) among the first bank (130) to the fourteenth bank (130), and the eight banks (130) may be consecutive. For example, the data of the first-type memory chip (111) in the first column may be data of the first bank (130) to the eighth bank (130), and the retry error correction code stored in the first-type memory chip (111) in the first column is generated based on the data of the first bank (130) to the eighth bank (130). The retry error correction code stored in the first-type memory chip (111) in the first column is intended to perform memory error correction on the data of the first bank (130) to the eighth bank (130).

[0040] As another example, the data of the first-type memory chip (111) in the second column may be the data of the third bank (130) through the tenth bank (130), and the retry error correction code stored in the first-type memory chip (111) in the second column is generated based on the data of the third bank (130) through the tenth bank (130). The retry error correction code stored in the first-type memory chip (111) in the second column is intended to perform memory error correction on the data of the third bank (130) through the tenth bank (130).

[0041] Additionally, data of the first-type memory chip (111) for generating retry error correction codes is selected based on reliability requirements. In other words, when reliability requirements are high, each column in the two-dimensional matrix contains data from more banks (130). When reliability requirements are low, each column in the two-dimensional matrix contains data from fewer banks (130). The second-type bank (132) in the first-type memory chip (111) can store retry error correction codes generated by different first-type banks (131). For example, a second-type bank (132) in a first-type memory chip (111) in a first column can store a retry error correction code generated based on data from the first bank (130) to the eighth bank (130), and a retry error correction code generated based on data from the third bank (130) to the tenth bank (130), so that the controller performs memory error correction on data of different first-type banks (131).

[0042] The error correction algorithm used for first-level memory error correction and second-level memory error correction provided in the embodiments of this application comprises any one of a parity-check code, a Hamming code, a block code, or an error correction code. The error correction algorithm used for first-level memory error correction and the error correction algorithm used for second-level memory error correction may be the same or different. This is not limited to this.

[0043] In the example, the error correction method of DDR5 can be reused in first-level memory error correction. For example, Hamming code or block code can be used in first-level memory error correction. The memory error correction method of DDR5 has low latency and error correction capabilities that can cover most error scenarios of storage class memory. Therefore, when the error rate of storage class memory is low, access latency can be effectively reduced under conditions of high reliability of data stored in storage class memory.

[0044] When first-level memory error correction cannot be performed or fails, second-level memory error correction may be performed by using a retry error correction code within a single or multiple first-type memory chips (111). For example, a block code or a low-density parity-check code may be used in second-level memory error correction. When the error rate of the storage class memory is high, second-level memory error correction can effectively reduce the error rate of the storage class memory, ensure high reliability of data stored in the storage class memory, and extend the service life of the storage class memory.

[0045] In the example above, the first-level memory error correction is set between the first-type memory chips (111), that is, the codeword of the operation error correction code is configured by using the data of the first-type memory chips (111) belonging to the same group (channel), and the second-level memory error correction is set in the first-type memory chips (111), that is, the codeword of the retry error correction code is configured by using the data of the first-type memory chips (111). During actual application, the second-level memory error correction of the storage class memory may alternatively be set in another way.

[0046] The above-described embodiment is explained by using an example in which the bit width of the memory chip is 8 bits. In another embodiment, the bit width of the memory chip used by the storage class memory may alternatively be 4 bits.

[0047] For example, as illustrated in FIG. 5, the storage class memory (500) comprises 20 memory chips (510), and the bit width of each memory chip (510) is 4 bits. The 20 memory chips (510) are divided into 4 groups, each group comprises 5 memory chips (510), and the sum of the bit widths of the 5 memory chips (510) included in each group is 20 bits. When the sum of the bit widths of the 20 memory chips (510) included in the 4 groups is 80 bits, the storage class memory (500) is compatible with the memory bit width of DDR5. Each group comprises 4 first-type memory chips (511) and 1 second-type memory chip (512).

[0048] Optionally, as illustrated in FIG. 6, the 20 memory chips (510) contained within the storage class memory (500) may alternatively be divided into two groups, each group containing 10 memory chips (510), and the sum of the bit widths of the 10 memory chips (510) contained within each group is 40 bits. When the sum of the bit widths of the 20 memory chips (510) contained within the two groups is 80 bits, the storage class memory (500) is compatible with the memory bit width of DDR5. Each group contains nine first-type memory chips (511) and one second-type memory chip (512).

[0049] For a detailed description of the first-type memory chip (511) and one second-type memory chip (512), refer to the above description of the first-type memory chip (111) and one second-type memory chip (112).

[0050] When storage class memory is used as main memory, the storage class memory can be placed on a computer device by using a Dual-Inline-Memory-Module (DIMM) interface, so that the processor of the computer device performs read / write operations on the storage class memory. The computer device may be an independent server or a computing device within a computing cluster.

[0051] A controller also needs to be placed between the storage class memory and the processor. The controller is configured to implement functions such as instruction translation, memory error correction, bad block management, and address mapping. Compared to solutions where an embedded controller in the storage class memory implements memory error correction and a DRAM connected to the controller caches data, causing uncertainty in the access latency of the SCM, the storage class memory provided in the embodiments of this application does not require an embedded controller or DRAM. A memory controller integrated within the processor connected to the storage class memory is used to control the storage class memory, or another external controller is connected between the processor and the storage class memory so that the storage class memory is controlled, deterministic latency for accessing the storage class memory is guaranteed, and compatibility with the DDR protocol is achieved.

[0052] FIG. 7 is a schematic diagram of a processor system according to an embodiment of this application. The processor system (700) includes a controller (710), a storage class memory (720), and a processor (730). The processor system (700) may be a computer device, a server, a computing device within a computing cluster, etc.

[0053] The processor (730) is the computing core and control core of the processor system (700). The processor (730) may be a very large scale integrated circuit. An operating system (731) and other software programs are placed within the processor (730) so that the processor (730) can access storage class memory (720) and various Peripheral Component Interconnect Express (PCIe) devices. The processor (730) includes one or more processor cores (732). The processor cores (732) within the processor (730) are, for example, a Central Processing Unit (CPU) or another Application-Specific Integrated Circuit (ASIC). The processor (730) may alternatively be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, an individual gate or transistor logic device, an individual hardware component, etc. During actual application, the processor system (700) may further include multiple processors.

[0054] In this embodiment of the application, the processor (730) is configured to write data to the storage class memory (720) or read data from the storage class memory (720).

[0055] The storage class memory (720) may be the main memory of the processor system (700). The storage class memory (720) is typically configured to store various types of software operating in the operating system (731), input and output data, information exchanged with external memory, etc. In order to increase the access speed of the processor (730), the storage class memory (720) needs to have the advantage of a high access speed. The processor (730) can access the storage class memory (720) at high speed by using the controller (710) and can perform read and write operations on any storage cell within the storage class memory (720).

[0056] The controller (710) is a bus circuit controller configured to control the storage class memory (720) inside the processor system (700) and to manage and plan the transmission of data from the storage class memory (720) to the processor core (732). By using the controller (710), data can be exchanged between the storage class memory (720) and the processor core (732).

[0057] The controller (710) may be integrated into the processor (730), built into the northbridge, or be an independent memory controller chip. The controller (710) may be a separate chip and is connected to the processor core (732) via a system bus. For example, the difference from the processor system illustrated in FIG. 7 is that, as illustrated in FIG. 8, the controller (710) may be an external controller connected between the storage class memory (720) and the processor (730). The external controller may be a centralized controller, and the controller may be connected to multiple storage class memories (720), thereby expanding the storage capacity of the main memory of the processor system and making the storage class memory more easily compatible with the DDR protocol to reduce the cost of the controller.

[0058] The specific location and form of existence of the memory controller in this embodiment of this application is not limited. During actual application, the controller (710) may control the logic necessary to write data to the storage class memory (720) or to read data from the storage class memory (720). The controller (710) may be a memory controller within a processor system such as a general-purpose processor, a dedicated accelerator, a GPU, an FPGA, or an embedded processor.

[0059] The processor system (700) further includes various input / output (I / O) devices (740). An I / O device (740) can be understood as hardware for transmitting data or as a device connected to an I / O interface. Common I / O devices include network adapters, printers, keyboards, mice, etc. All external memory, such as hard disks, floppy disks, and optical disks, can also be used as I / O devices.

[0060] The processor (730), storage class memory (720), controller (710), and I / O device (740) are connected via a bus (750). The bus (750) may include a path for transmitting information between the above components (e.g., the processor (730) and the storage class memory (720)). In addition to the data bus, the bus (750) may further include a power bus, a control bus, a status signal bus, etc. However, for clarity of description, various buses are referred to as bus (750) in the drawings. The bus (750) may be a PCIe bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL) bus, a cache coherent interconnect for accelerators (CCIX) bus, etc. For example, the processor (730) can access this I / O device (740) via a PCIe bus. The processor (730) is connected to the storage class memory (720) via a double data rate (DDR) bus. Here, different storage class memory (720) can communicate with the processor (730) via different data buses. Therefore, the DDR bus can be replaced with another type of bus. The type of bus is not limited in this embodiment of the application.

[0061] The processor system (700) further includes a DPU (760), and the DPU (760) may be connected to the processor (730) via a PCIe bus. The DPU (760) offloads applications related to artificial intelligence and storage that are operated by another chip of the processor system (700) (e.g., processor (730)), thereby improving the data processing performance of the processor system (700) and reducing the load on the processor system (700). The processor system (700) may further include another dedicated processor. The dedicated processor is a processor for a specific application or field, for example, a graphics processing unit (GPU) configured to process graphic data, or a DSP configured to process signals.

[0062] It should be noted that the processor system (700) may be referred to as a host. FIG. 7 is merely a schematic diagram. The processor system (700) may further include other components, for example, a hard disk, an optical drive, a power supply, a chassis, a heat dissipation system, and further include other input / output controllers and interfaces not shown in FIG. 7. The number of processors, storage class memory, and controllers included within the processor system (700) is not limited to this embodiment of the application.

[0063] Next, FIG. 9 is a schematic diagram of a data processing method according to an embodiment of this application. The structure illustrated in FIG. 7 is used as an example for illustrative purposes. It is assumed that the processor (730) writes data to a storage class memory (720) or reads data from a storage class memory (720). The data processing method provided in this embodiment of this application comprises the following steps.

[0064] In some embodiments, when the processor (730) writes data to the storage class memory (720), S910 to S930 are performed.

[0065] S910: The controller (710) performs command conversion, that is, the controller (710) converts a write command of the processor (730) into a write command that can be recognized by the storage class memory (720).

[0066] S920: The controller (710) generates an operation error correction code and a retry error correction code based on the data to be written.

[0067] The controller (710) determines the location where the data to be written is written into the first-type memory chip within the storage class memory (720). For example, the controller (710) performs address mapping, that is, converts a logical block address into a physical block address. A Logic Block Address (LBA) describes a virtual address of a block where data on a storage device is located, and is generally used in auxiliary memory devices such as hard disks. An LBA may refer to the address of a data block, or the data block pointed to by the address. A Physical Block Address (PBA) describes the physical address of a block where data on a storage device is located. There is a one-to-one mapping relationship between an LBA and a PBA, and the mapping relationship is typically stored in main memory. In this embodiment of the application, the mapping relationship between an LBA and a PBA may be stored in the storage class memory. When deciding to write data to the storage class memory (720), the controller (710) first determines a logical block address, and then determines a physical block address of the storage class memory (720) based on the logical block address and the mapping relationship between LBA and PBA in order to write data to the storage class memory (720) based on the physical block address.

[0068] Additionally, the controller (710) generates an operation error correction code based on an error correction algorithm (e.g., Hamming code or block code) by using data that is in the data to be written and is written into a first-type memory chip within the same group, and generates a retry error correction code based on an error correction algorithm (e.g., block code or low-density parity-check code) by using data that is written into a first-type memory chip within the same group.

[0069] S930: The controller (710) writes the operation error correction code, the retry error correction code, and the data to be written into the storage class memory (720).

[0070] The controller (710) writes the data to be written to a determined location of the first-type memory chip, writes the operation error correction code to the second-type memory chip, and writes the retry error correction code to the second-type bank of the first-type memory chip.

[0071] In some other embodiments, when the processor (730) reads data from the storage class memory (720), S940 to S970 are performed.

[0072] S940: The controller (710) performs command conversion, that is, the controller (710) converts a read command of the processor (730) into a read command that can be recognized by the storage class memory (720).

[0073] S950: The controller (710) reads data, operation error correction code, and retry error correction code from the storage class memory (720).

[0074] The controller (710) determines the storage location of data within the storage class memory (720), specifically, first, determines the logical block address, and then, in order to read data from the storage class memory (720) based on the physical block address, determines the physical block address of the storage class memory (720) based on the logical block address and the mapping relationship between the LBA and the PBA.

[0075] S960: The controller (710) performs first-level memory error correction on the read data, that is, checks the read data by using an operation error correction code.

[0076] In some embodiments, the controller (710) determines the storage location of the data, reads the data, and operates an error correction code based on the storage location. The controller (710) generates a temporary operating error correction code by using the read data based on an error correction algorithm (e.g., Hamming code or block code) and compares the temporary operating error correction code with the operating error correction code. If the temporary operating error correction code and the operating error correction code are the same, it indicates that the read data is correct. If the temporary operating error correction code and the operating error correction code are different, it indicates that there is an error in the read data. If the read data does not match the stored data, the bits with errors are determined, and then, the read data can be decoded using parity-check bits to correct the bits with errors.

[0077] Optionally, if the first-level memory error correction fails, S970 is performed. The controller (710) performs the second-level memory error correction, that is, checks the data of the first-type memory chip by using a retry error correction code. For example, the controller (710) performs the second-level memory error correction on the data stored in the first-type memory chip by using a block code or a low-density parity-check code and by using a retry error correction code.

[0078] In the data processing process, the controller (710) can continuously scan the data by using an algorithm (e.g., Hamming code) to check and correct memory errors in each bit.

[0079] The method for determining the location where the controller (710) writes data to the storage class memory (720) and the location where the controller (710) reads data from the storage class memory (720) is not limited to this embodiment of the application. For details, reference is made to the prior art. Additionally, the method for generating an operation error correction code and a retry error correction code, and the method for checking the read data using the operation error correction code and the retry error correction code, may also reuse the prior art.

[0080] It may be understood that, in order to implement the functions of the embodiments described above, the computing device includes corresponding hardware structures and / or software modules for performing the functions. A person skilled in the art should readily recognize that, by combining the bank and method steps of the examples described in the embodiments disclosed in this application, this application can be implemented using hardware, or a combination of hardware and computer software. Whether the functions are performed by hardware, or by hardware driven by computer software, depends on the specific application scenario and design constraints of the technical solution.

[0081] The method steps in this embodiment may be implemented in hardware or by executing software instructions by a processor. Software instructions may include corresponding software modules. Software modules may be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable hard disks, CD-ROMs, or any other form widely known in the art. For example, the storage medium may be coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Certainly, the storage medium may be a component of the processor. The processor and the storage medium may be placed within an ASIC. Additionally, the ASIC may be located within a computing device. Certainly, the processor and storage medium can alternatively exist as individual components within a network device or terminal device.

[0082] All or part of the above-described embodiments may be implemented by using software, hardware, firmware, or any combination thereof. When software is used to implement the embodiments, all or part of the embodiments may be implemented in the form of a computer program product. A computer program product comprises one or more computer programs and instructions. When a computer program or instruction is loaded and executed on a computer, all or part of the process or function in the embodiments of this application is executed. The computer may be a general-purpose computer, a dedicated computer, a computer network, a network device, a user device, or another programmable device. A computer program or instruction may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, a computer program or instruction may be transmitted via wired or wireless means from a website, computer, server, or data center to another website, computer, server, or data center. A computer-readable storage medium may be any available medium that can be accessed by a computer or data storage device, such as a server or data center, that integrates one or more available media. Available media may be magnetic media, for example, a floppy disk, a hard disk, or a magnetic tape; optical media, for example, a digital video disc (DVD); or semiconductor media, for example, a solid-state drive (SSD).

[0083] The foregoing description is merely a specific embodiment of this application, but is not intended to limit the scope of protection of this application. Any modification or substitution readily derived by a person skilled in the art within the technical scope disclosed in this application will fall within the scope of protection of this application. Therefore, the scope of protection of this application will be the scope of protection of the claims.

Claims

Claim 1 A storage class memory comprising a plurality of memory chips, wherein the plurality of memory chips are divided into at least one group, and each of the at least one group comprises a plurality of first-type memory chips and at least one second-type memory chip, wherein each first-type memory chip comprises a plurality of banks, and the second-type memory chip is configured to store a running error correction code, wherein the running error correction code is for performing first-level memory error correction on data stored in the plurality of first-type memory chips within the same group, and wherein each first-type memory chip is configured to store data and a retry error correction code, and wherein the retry error correction code is for performing second-level memory error correction on data stored in two or more of the plurality of banks included in each first-type memory chip when the first-level memory error correction fails. Claim 2 A storage class memory according to claim 1, wherein the plurality of banks comprises M first-type banks and N second-type banks, wherein the first-type banks are configured to store data and the second-type banks are configured to store the retry error correction code. Claim 3 A storage class memory according to paragraph 2, wherein the unit data access amount of the first-type bank and the unit data access amount of the second-type bank are each a unit data access amount of one bit within the bit width of the first-type memory chip. Claim 4 A storage class memory according to claim 1, wherein the plurality of banks further include a third-type bank, and the third-type bank is configured to implement a bad block management function on the bank of the first-type memory chip. Claim 5 In claim 1, the storage class memory, wherein the bit width of the storage class memory satisfies the memory bit width indicated by the double data rate (DDR) protocol. Claim 6 In paragraph 5, the quantity of first-type memory chips and the quantity of second-type memory chips within each group are determined based on the bit width of the first-type memory chips, the bit width of the second-type memory chips, and the memory bit width indicated by the DDR protocol, for a storage class memory. Claim 7 A storage class memory according to claim 6, wherein the memory bit width indicated by the DDR protocol is 80 bits, both the bit width of the first-type memory chip and the bit width of the second-type memory chip are 8 bits, the 10 memory chips included in the storage class memory are divided into two groups, each group includes four first-type memory chips and one second-type memory chip, the sum of the bit widths of the four first-type memory chips and the second-type memory chip included in each group is 40 bits, and the unit data access amount of each bit is 16 bytes or 32 bytes. Claim 8 A data processing method comprising: a step of performing a first-level memory error correction on data stored in a plurality of first-type memory chips within the same group within the storage class memory by the controller, wherein the data processing method is executed by a controller, and the controller is connected to a storage class memory and a processor; and a step of, when the first-level memory error correction fails, performing a second-level memory error correction on data stored in two or more banks among a plurality of banks included in each first-type memory chip by the controller, using a retry error correction code stored in each first-type memory chip. Claim 9 A data processing method according to claim 8, wherein the step of performing first-level memory error correction on data stored in a plurality of first-type memory chips within the same group within the storage class memory by means of the controller comprises the step of performing first-level memory error correction on data stored in the plurality of first-type memory chips within the same group within the storage class memory by means of the controller using a Hamming code and a block code, wherein the retry error correction code comprises the block code or a low-density parity-check code. Claim 10 A data processing method according to claim 8, wherein the step of performing a first-level memory error correction on data stored in a plurality of first-type memory chips within the same group within the storage class memory by the controller includes the step of performing a first-level memory error correction on a single bit among 128 bytes to 512 bytes of data stored in the plurality of first-type memory chips within the same group within the storage class memory by the controller, and the step of performing a second-level memory error correction on data stored in two or more banks among a plurality of banks included in each first-type memory chip by the controller includes the step of performing a second-level memory error correction on hundreds of bits among 2048 bytes to 4096 bytes of data stored in two or more banks among a plurality of banks included in each first-type memory chip by the controller. Claim 11 A data processing method according to claim 8, further comprising the step of converting instructions of the processor into instructions of the storage class memory by the controller, and converting instructions of the storage class memory into instructions of the processor. Claim 12 A processor system comprising a controller, at least one storage class memory according to any one of claims 1 to 7, and a processor, wherein the controller is separately connected to the processor and the at least one storage class memory.

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